Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33142

1

T1

6

T2

13

T3

22

auto[1]

258

1

T15

6

T139

11

T140

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33155	1			T1	6		T2	13		T3	22
auto[134217728:268435455]	7	1			T148	1		T317	2		T285	1
auto[268435456:402653183]	9	1			T247	1		T317	1		T309	1
auto[402653184:536870911]	6	1			T139	1		T155	2		T247	2
auto[536870912:671088639]	8	1			T144	1		T155	1		T243	1
auto[671088640:805306367]	7	1			T139	1		T144	1		T407	2
auto[805306368:939524095]	4	1			T148	1		T285	1		T337	1
auto[939524096:1073741823]	2	1			T247	1		T370	1		-	-
auto[1073741824:1207959551]	5	1			T139	1		T296	1		T408	2
auto[1207959552:1342177279]	5	1			T139	1		T144	2		T313	1
auto[1342177280:1476395007]	6	1			T247	2		T309	1		T409	1
auto[1476395008:1610612735]	11	1			T15	1		T155	1		T294	1
auto[1610612736:1744830463]	11	1			T140	1		T395	1		T370	1
auto[1744830464:1879048191]	9	1			T15	2		T294	1		T247	1
auto[1879048192:2013265919]	10	1			T294	1		T317	1		T309	1
auto[2013265920:2147483647]	11	1			T148	1		T317	1		T369	1
auto[2147483648:2281701375]	9	1			T139	1		T144	1		T317	1
auto[2281701376:2415919103]	9	1			T139	1		T294	1		T317	1
auto[2415919104:2550136831]	4	1			T139	1		T243	1		T370	1
auto[2550136832:2684354559]	8	1			T144	1		T155	1		T387	1
auto[2684354560:2818572287]	9	1			T155	1		T369	1		T309	1
auto[2818572288:2952790015]	5	1			T15	1		T155	1		T147	1
auto[2952790016:3087007743]	7	1			T139	1		T309	2		T370	1
auto[3087007744:3221225471]	11	1			T155	1		T247	1		T309	1
auto[3221225472:3355443199]	12	1			T144	1		T294	2		T317	1
auto[3355443200:3489660927]	7	1			T139	1		T294	2		T317	1
auto[3489660928:3623878655]	11	1			T139	1		T144	1		T148	2
auto[3623878656:3758096383]	5	1			T155	1		T394	1		T410	1
auto[3758096384:3892314111]	12	1			T15	1		T144	1		T294	1
auto[3892314112:4026531839]	10	1			T247	1		T395	1		T317	1
auto[4026531840:4160749567]	6	1			T247	1		T408	1		T411	1
auto[4160749568:4294967295]	9	1			T140	1		T155	1		T309	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33142	1			T1	6		T2	13		T3	22
auto[0:134217727]	auto[1]	13	1			T15	1		T139	1		T294	1
auto[134217728:268435455]	auto[1]	7	1			T148	1		T317	2		T285	1
auto[268435456:402653183]	auto[1]	9	1			T247	1		T317	1		T309	1
auto[402653184:536870911]	auto[1]	6	1			T139	1		T155	2		T247	2
auto[536870912:671088639]	auto[1]	8	1			T144	1		T155	1		T243	1
auto[671088640:805306367]	auto[1]	7	1			T139	1		T144	1		T407	2
auto[805306368:939524095]	auto[1]	4	1			T148	1		T285	1		T337	1
auto[939524096:1073741823]	auto[1]	2	1			T247	1		T370	1		-	-
auto[1073741824:1207959551]	auto[1]	5	1			T139	1		T296	1		T408	2
auto[1207959552:1342177279]	auto[1]	5	1			T139	1		T144	2		T313	1
auto[1342177280:1476395007]	auto[1]	6	1			T247	2		T309	1		T409	1
auto[1476395008:1610612735]	auto[1]	11	1			T15	1		T155	1		T294	1
auto[1610612736:1744830463]	auto[1]	11	1			T140	1		T395	1		T370	1
auto[1744830464:1879048191]	auto[1]	9	1			T15	2		T294	1		T247	1
auto[1879048192:2013265919]	auto[1]	10	1			T294	1		T317	1		T309	1
auto[2013265920:2147483647]	auto[1]	11	1			T148	1		T317	1		T369	1
auto[2147483648:2281701375]	auto[1]	9	1			T139	1		T144	1		T317	1
auto[2281701376:2415919103]	auto[1]	9	1			T139	1		T294	1		T317	1
auto[2415919104:2550136831]	auto[1]	4	1			T139	1		T243	1		T370	1
auto[2550136832:2684354559]	auto[1]	8	1			T144	1		T155	1		T387	1
auto[2684354560:2818572287]	auto[1]	9	1			T155	1		T369	1		T309	1
auto[2818572288:2952790015]	auto[1]	5	1			T15	1		T155	1		T147	1
auto[2952790016:3087007743]	auto[1]	7	1			T139	1		T309	2		T370	1
auto[3087007744:3221225471]	auto[1]	11	1			T155	1		T247	1		T309	1
auto[3221225472:3355443199]	auto[1]	12	1			T144	1		T294	2		T317	1
auto[3355443200:3489660927]	auto[1]	7	1			T139	1		T294	2		T317	1
auto[3489660928:3623878655]	auto[1]	11	1			T139	1		T144	1		T148	2
auto[3623878656:3758096383]	auto[1]	5	1			T155	1		T394	1		T410	1
auto[3758096384:3892314111]	auto[1]	12	1			T15	1		T144	1		T294	1
auto[3892314112:4026531839]	auto[1]	10	1			T247	1		T395	1		T317	1
auto[4026531840:4160749567]	auto[1]	6	1			T247	1		T408	1		T411	1
auto[4160749568:4294967295]	auto[1]	9	1			T140	1		T155	1		T309	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1682

1

T2

1

T5

10

T12

3

auto[1]

1809

1

T1

1

T2

1

T5

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T2	1		T5	1		T12	1
auto[134217728:268435455]	109	1			T39	1		T50	1		T91	1
auto[268435456:402653183]	106	1			T12	1		T24	1		T43	1
auto[402653184:536870911]	99	1			T5	1		T44	1		T40	2
auto[536870912:671088639]	108	1			T5	2		T6	3		T57	1
auto[671088640:805306367]	113	1			T16	1		T39	1		T48	1
auto[805306368:939524095]	108	1			T5	2		T23	1		T24	1
auto[939524096:1073741823]	106	1			T48	1		T42	1		T111	2
auto[1073741824:1207959551]	108	1			T140	1		T50	1		T40	1
auto[1207959552:1342177279]	101	1			T1	1		T5	2		T12	2
auto[1342177280:1476395007]	122	1			T5	1		T139	1		T36	1
auto[1476395008:1610612735]	119	1			T12	1		T48	1		T49	1
auto[1610612736:1744830463]	99	1			T48	1		T42	1		T49	1
auto[1744830464:1879048191]	102	1			T23	1		T43	1		T108	1
auto[1879048192:2013265919]	131	1			T23	1		T50	1		T110	1
auto[2013265920:2147483647]	104	1			T5	1		T110	1		T36	1
auto[2147483648:2281701375]	87	1			T23	1		T43	1		T94	1
auto[2281701376:2415919103]	97	1			T24	1		T49	1		T29	1
auto[2415919104:2550136831]	115	1			T5	1		T139	1		T40	1
auto[2550136832:2684354559]	117	1			T5	1		T15	1		T44	1
auto[2684354560:2818572287]	95	1			T23	2		T196	1		T144	1
auto[2818572288:2952790015]	114	1			T15	2		T94	1		T111	1
auto[2952790016:3087007743]	121	1			T48	2		T44	1		T36	1
auto[3087007744:3221225471]	120	1			T14	1		T36	1		T196	1
auto[3221225472:3355443199]	123	1			T5	1		T48	1		T139	1
auto[3355443200:3489660927]	126	1			T5	1		T43	2		T91	1
auto[3489660928:3623878655]	113	1			T2	1		T5	1		T43	1
auto[3623878656:3758096383]	101	1			T15	1		T39	1		T140	1
auto[3758096384:3892314111]	105	1			T40	1		T41	1		T6	1
auto[3892314112:4026531839]	106	1			T5	1		T40	4		T36	1
auto[4026531840:4160749567]	100	1			T5	1		T48	1		T43	1
auto[4160749568:4294967295]	121	1			T5	1		T39	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T2	1		T43	1		T51	1
auto[0:134217727]	auto[1]	54	1			T5	1		T12	1		T24	1
auto[134217728:268435455]	auto[0]	51	1			T97	1		T6	1		T252	1
auto[134217728:268435455]	auto[1]	58	1			T39	1		T50	1		T91	1
auto[268435456:402653183]	auto[0]	44	1			T12	1		T24	1		T43	1
auto[268435456:402653183]	auto[1]	62	1			T40	1		T51	1		T144	1
auto[402653184:536870911]	auto[0]	48	1			T5	1		T44	1		T40	1
auto[402653184:536870911]	auto[1]	51	1			T40	1		T109	1		T6	1
auto[536870912:671088639]	auto[0]	61	1			T5	1		T6	1		T53	3
auto[536870912:671088639]	auto[1]	47	1			T5	1		T6	2		T57	1
auto[671088640:805306367]	auto[0]	60	1			T16	1		T20	1		T156	1
auto[671088640:805306367]	auto[1]	53	1			T39	1		T48	1		T209	1
auto[805306368:939524095]	auto[0]	52	1			T5	2		T43	1		T40	1
auto[805306368:939524095]	auto[1]	56	1			T23	1		T24	1		T94	1
auto[939524096:1073741823]	auto[0]	52	1			T48	1		T42	1		T111	2
auto[939524096:1073741823]	auto[1]	54	1			T40	2		T196	1		T6	1
auto[1073741824:1207959551]	auto[0]	48	1			T40	1		T198	1		T66	1
auto[1073741824:1207959551]	auto[1]	60	1			T140	1		T50	1		T30	1
auto[1207959552:1342177279]	auto[0]	54	1			T5	2		T12	2		T50	1
auto[1207959552:1342177279]	auto[1]	47	1			T1	1		T13	1		T44	1
auto[1342177280:1476395007]	auto[0]	57	1			T36	1		T108	1		T41	1
auto[1342177280:1476395007]	auto[1]	65	1			T5	1		T139	1		T155	1
auto[1476395008:1610612735]	auto[0]	63	1			T91	1		T41	1		T145	1
auto[1476395008:1610612735]	auto[1]	56	1			T12	1		T48	1		T49	1
auto[1610612736:1744830463]	auto[0]	46	1			T48	1		T198	1		T109	1
auto[1610612736:1744830463]	auto[1]	53	1			T42	1		T49	1		T40	2
auto[1744830464:1879048191]	auto[0]	52	1			T23	1		T43	1		T108	1
auto[1744830464:1879048191]	auto[1]	50	1			T57	1		T252	1		T53	2
auto[1879048192:2013265919]	auto[0]	64	1			T50	1		T97	1		T53	1
auto[1879048192:2013265919]	auto[1]	67	1			T23	1		T110	1		T40	1
auto[2013265920:2147483647]	auto[0]	43	1			T5	1		T53	1		T66	1
auto[2013265920:2147483647]	auto[1]	61	1			T110	1		T36	1		T108	2
auto[2147483648:2281701375]	auto[0]	43	1			T23	1		T43	1		T40	1
auto[2147483648:2281701375]	auto[1]	44	1			T94	1		T140	1		T96	1
auto[2281701376:2415919103]	auto[0]	44	1			T49	1		T198	1		T155	1
auto[2281701376:2415919103]	auto[1]	53	1			T24	1		T29	1		T50	1
auto[2415919104:2550136831]	auto[0]	59	1			T5	1		T109	1		T255	1
auto[2415919104:2550136831]	auto[1]	56	1			T139	1		T40	1		T57	1
auto[2550136832:2684354559]	auto[0]	60	1			T44	1		T40	1		T196	1
auto[2550136832:2684354559]	auto[1]	57	1			T5	1		T15	1		T40	1
auto[2684354560:2818572287]	auto[0]	53	1			T23	1		T144	1		T6	1
auto[2684354560:2818572287]	auto[1]	42	1			T23	1		T196	1		T6	1
auto[2818572288:2952790015]	auto[0]	59	1			T15	1		T94	1		T147	1
auto[2818572288:2952790015]	auto[1]	55	1			T15	1		T111	1		T36	1
auto[2952790016:3087007743]	auto[0]	53	1			T48	1		T44	1		T36	1
auto[2952790016:3087007743]	auto[1]	68	1			T48	1		T57	1		T145	1
auto[3087007744:3221225471]	auto[0]	59	1			T36	1		T6	2		T53	1
auto[3087007744:3221225471]	auto[1]	61	1			T14	1		T196	1		T96	1
auto[3221225472:3355443199]	auto[0]	60	1			T111	2		T40	1		T20	1
auto[3221225472:3355443199]	auto[1]	63	1			T5	1		T48	1		T139	1
auto[3355443200:3489660927]	auto[0]	49	1			T5	1		T43	1		T193	1
auto[3355443200:3489660927]	auto[1]	77	1			T43	1		T91	1		T52	1
auto[3489660928:3623878655]	auto[0]	63	1			T5	1		T43	1		T50	1
auto[3489660928:3623878655]	auto[1]	50	1			T2	1		T144	1		T108	1
auto[3623878656:3758096383]	auto[0]	45	1			T96	1		T25	1		T156	1
auto[3623878656:3758096383]	auto[1]	56	1			T15	1		T39	1		T140	1
auto[3758096384:3892314111]	auto[0]	51	1			T41	1		T6	1		T53	1
auto[3758096384:3892314111]	auto[1]	54	1			T40	1		T53	2		T202	1
auto[3892314112:4026531839]	auto[0]	45	1			T40	1		T36	1		T108	1
auto[3892314112:4026531839]	auto[1]	61	1			T5	1		T40	3		T198	2
auto[4026531840:4160749567]	auto[0]	41	1			T43	1		T50	1		T65	1
auto[4026531840:4160749567]	auto[1]	59	1			T5	1		T48	1		T91	1
auto[4160749568:4294967295]	auto[0]	62	1			T48	1		T144	1		T6	2
auto[4160749568:4294967295]	auto[1]	59	1			T5	1		T39	1		T42	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1644

1

T2

2

T5

8

T12

3

auto[1]

1847

1

T1

1

T5

10

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T5	3		T43	1		T50	1
auto[134217728:268435455]	103	1			T39	1		T24	1		T42	1
auto[268435456:402653183]	100	1			T12	1		T39	1		T40	1
auto[402653184:536870911]	115	1			T48	1		T49	1		T44	1
auto[536870912:671088639]	103	1			T5	1		T139	1		T36	1
auto[671088640:805306367]	93	1			T12	1		T48	1		T40	1
auto[805306368:939524095]	126	1			T1	1		T5	1		T15	1
auto[939524096:1073741823]	93	1			T5	1		T23	1		T43	1
auto[1073741824:1207959551]	109	1			T13	1		T110	1		T96	1
auto[1207959552:1342177279]	123	1			T43	1		T198	1		T109	1
auto[1342177280:1476395007]	122	1			T5	1		T43	1		T140	1
auto[1476395008:1610612735]	115	1			T43	1		T140	1		T91	2
auto[1610612736:1744830463]	112	1			T48	1		T111	1		T57	1
auto[1744830464:1879048191]	106	1			T5	1		T12	1		T48	1
auto[1879048192:2013265919]	119	1			T5	1		T39	1		T43	2
auto[2013265920:2147483647]	117	1			T12	1		T42	1		T94	1
auto[2147483648:2281701375]	105	1			T5	1		T39	1		T23	2
auto[2281701376:2415919103]	115	1			T14	1		T48	2		T139	1
auto[2415919104:2550136831]	91	1			T40	2		T36	1		T108	1
auto[2550136832:2684354559]	98	1			T2	1		T144	1		T65	1
auto[2684354560:2818572287]	101	1			T5	1		T50	1		T97	1
auto[2818572288:2952790015]	116	1			T48	1		T94	1		T40	2
auto[2952790016:3087007743]	100	1			T5	1		T139	1		T40	1
auto[3087007744:3221225471]	102	1			T5	1		T23	1		T43	1
auto[3221225472:3355443199]	121	1			T5	1		T24	1		T42	1
auto[3355443200:3489660927]	100	1			T5	1		T15	1		T94	1
auto[3489660928:3623878655]	121	1			T5	1		T15	1		T49	1
auto[3623878656:3758096383]	114	1			T43	1		T111	1		T25	1
auto[3758096384:3892314111]	118	1			T15	1		T48	1		T111	1
auto[3892314112:4026531839]	110	1			T2	1		T5	1		T12	1
auto[4026531840:4160749567]	107	1			T23	1		T111	1		T40	1
auto[4160749568:4294967295]	108	1			T5	1		T24	1		T140	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T5	1		T43	1		T50	1
auto[0:134217727]	auto[1]	60	1			T5	2		T40	1		T36	1
auto[134217728:268435455]	auto[0]	45	1			T198	1		T246	2		T405	1
auto[134217728:268435455]	auto[1]	58	1			T39	1		T24	1		T42	1
auto[268435456:402653183]	auto[0]	49	1			T12	1		T109	1		T6	2
auto[268435456:402653183]	auto[1]	51	1			T39	1		T40	1		T6	1
auto[402653184:536870911]	auto[0]	58	1			T49	1		T44	1		T36	1
auto[402653184:536870911]	auto[1]	57	1			T48	1		T146	1		T53	2
auto[536870912:671088639]	auto[0]	45	1			T5	1		T36	1		T108	1
auto[536870912:671088639]	auto[1]	58	1			T139	1		T57	2		T89	1
auto[671088640:805306367]	auto[0]	39	1			T51	1		T255	1		T66	1
auto[671088640:805306367]	auto[1]	54	1			T12	1		T48	1		T40	1
auto[805306368:939524095]	auto[0]	59	1			T16	1		T48	1		T44	1
auto[805306368:939524095]	auto[1]	67	1			T1	1		T5	1		T15	1
auto[939524096:1073741823]	auto[0]	49	1			T40	1		T155	1		T53	1
auto[939524096:1073741823]	auto[1]	44	1			T5	1		T23	1		T43	1
auto[1073741824:1207959551]	auto[0]	58	1			T53	1		T246	1		T7	1
auto[1073741824:1207959551]	auto[1]	51	1			T13	1		T110	1		T96	1
auto[1207959552:1342177279]	auto[0]	58	1			T43	1		T198	1		T109	1
auto[1207959552:1342177279]	auto[1]	65	1			T30	2		T6	3		T57	1
auto[1342177280:1476395007]	auto[0]	51	1			T43	1		T40	1		T41	1
auto[1342177280:1476395007]	auto[1]	71	1			T5	1		T140	1		T144	1
auto[1476395008:1610612735]	auto[0]	56	1			T43	1		T91	1		T6	1
auto[1476395008:1610612735]	auto[1]	59	1			T140	1		T91	1		T20	1
auto[1610612736:1744830463]	auto[0]	46	1			T57	1		T156	1		T89	1
auto[1610612736:1744830463]	auto[1]	66	1			T48	1		T111	1		T53	1
auto[1744830464:1879048191]	auto[0]	60	1			T12	1		T48	1		T24	1
auto[1744830464:1879048191]	auto[1]	46	1			T5	1		T23	1		T49	1
auto[1879048192:2013265919]	auto[0]	51	1			T5	1		T43	1		T50	1
auto[1879048192:2013265919]	auto[1]	68	1			T39	1		T43	1		T40	1
auto[2013265920:2147483647]	auto[0]	53	1			T12	1		T20	2		T156	1
auto[2013265920:2147483647]	auto[1]	64	1			T42	1		T94	1		T91	1
auto[2147483648:2281701375]	auto[0]	36	1			T23	1		T198	1		T6	1
auto[2147483648:2281701375]	auto[1]	69	1			T5	1		T39	1		T23	1
auto[2281701376:2415919103]	auto[0]	62	1			T48	1		T51	1		T25	1
auto[2281701376:2415919103]	auto[1]	53	1			T14	1		T48	1		T139	1
auto[2415919104:2550136831]	auto[0]	40	1			T40	1		T36	1		T97	1
auto[2415919104:2550136831]	auto[1]	51	1			T40	1		T108	1		T20	1
auto[2550136832:2684354559]	auto[0]	50	1			T2	1		T144	1		T193	1
auto[2550136832:2684354559]	auto[1]	48	1			T65	1		T6	2		T57	1
auto[2684354560:2818572287]	auto[0]	51	1			T50	1		T97	1		T6	1
auto[2684354560:2818572287]	auto[1]	50	1			T5	1		T57	1		T53	1
auto[2818572288:2952790015]	auto[0]	57	1			T48	1		T6	1		T57	2
auto[2818572288:2952790015]	auto[1]	59	1			T94	1		T40	2		T52	1
auto[2952790016:3087007743]	auto[0]	52	1			T40	1		T97	1		T65	1
auto[2952790016:3087007743]	auto[1]	48	1			T5	1		T139	1		T6	1
auto[3087007744:3221225471]	auto[0]	54	1			T5	1		T23	1		T43	1
auto[3087007744:3221225471]	auto[1]	48	1			T40	1		T51	1		T96	2
auto[3221225472:3355443199]	auto[0]	44	1			T5	1		T44	1		T108	1
auto[3221225472:3355443199]	auto[1]	77	1			T24	1		T42	1		T110	1
auto[3355443200:3489660927]	auto[0]	47	1			T15	1		T94	1		T40	1
auto[3355443200:3489660927]	auto[1]	53	1			T5	1		T144	1		T147	1
auto[3489660928:3623878655]	auto[0]	61	1			T5	1		T40	1		T196	1
auto[3489660928:3623878655]	auto[1]	60	1			T15	1		T49	1		T50	1
auto[3623878656:3758096383]	auto[0]	58	1			T43	1		T111	1		T25	1
auto[3623878656:3758096383]	auto[1]	56	1			T53	1		T202	1		T258	1
auto[3758096384:3892314111]	auto[0]	55	1			T48	1		T111	1		T36	1
auto[3758096384:3892314111]	auto[1]	63	1			T15	1		T36	1		T198	1
auto[3892314112:4026531839]	auto[0]	44	1			T2	1		T5	1		T44	1
auto[3892314112:4026531839]	auto[1]	66	1			T12	1		T50	1		T44	1
auto[4026531840:4160749567]	auto[0]	52	1			T23	1		T111	1		T255	1
auto[4026531840:4160749567]	auto[1]	55	1			T40	1		T6	1		T220	1
auto[4160749568:4294967295]	auto[0]	56	1			T5	1		T50	1		T40	1
auto[4160749568:4294967295]	auto[1]	52	1			T24	1		T140	1		T50	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1671

1

T2

2

T5

7

T12

3

auto[1]

1820

1

T1

1

T5

11

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	138	1			T39	1		T48	1		T111	1
auto[134217728:268435455]	94	1			T1	1		T49	1		T109	1
auto[268435456:402653183]	109	1			T5	1		T39	1		T24	1
auto[402653184:536870911]	109	1			T5	1		T144	1		T198	1
auto[536870912:671088639]	107	1			T5	1		T44	1		T198	1
auto[671088640:805306367]	113	1			T43	1		T94	1		T57	1
auto[805306368:939524095]	102	1			T23	1		T42	1		T49	1
auto[939524096:1073741823]	122	1			T12	1		T48	1		T23	1
auto[1073741824:1207959551]	127	1			T5	1		T12	2		T24	1
auto[1207959552:1342177279]	103	1			T5	1		T139	1		T40	1
auto[1342177280:1476395007]	113	1			T43	1		T40	1		T30	1
auto[1476395008:1610612735]	99	1			T91	2		T109	1		T6	2
auto[1610612736:1744830463]	89	1			T23	1		T198	1		T108	1
auto[1744830464:1879048191]	99	1			T5	1		T39	1		T110	1
auto[1879048192:2013265919]	110	1			T48	1		T110	1		T40	1
auto[2013265920:2147483647]	107	1			T5	2		T15	1		T50	1
auto[2147483648:2281701375]	102	1			T15	1		T23	2		T40	1
auto[2281701376:2415919103]	106	1			T5	1		T49	1		T139	1
auto[2415919104:2550136831]	108	1			T14	1		T16	1		T43	1
auto[2550136832:2684354559]	106	1			T48	1		T43	1		T29	1
auto[2684354560:2818572287]	126	1			T15	1		T43	1		T111	1
auto[2818572288:2952790015]	125	1			T2	1		T48	1		T43	1
auto[2952790016:3087007743]	104	1			T5	2		T40	1		T36	1
auto[3087007744:3221225471]	104	1			T13	1		T48	1		T44	1
auto[3221225472:3355443199]	131	1			T5	2		T24	1		T42	1
auto[3355443200:3489660927]	111	1			T5	1		T48	1		T43	1
auto[3489660928:3623878655]	116	1			T5	1		T48	1		T23	1
auto[3623878656:3758096383]	110	1			T2	1		T43	1		T108	1
auto[3758096384:3892314111]	105	1			T5	2		T12	1		T43	1
auto[3892314112:4026531839]	105	1			T12	1		T15	1		T39	1
auto[4026531840:4160749567]	93	1			T5	1		T48	1		T50	1
auto[4160749568:4294967295]	98	1			T40	1		T255	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	65	1			T48	1		T111	1		T198	1
auto[0:134217727]	auto[1]	73	1			T39	1		T91	1		T40	1
auto[134217728:268435455]	auto[0]	52	1			T49	1		T109	1		T255	1
auto[134217728:268435455]	auto[1]	42	1			T1	1		T209	1		T53	1
auto[268435456:402653183]	auto[0]	55	1			T42	1		T44	1		T156	1
auto[268435456:402653183]	auto[1]	54	1			T5	1		T39	1		T24	1
auto[402653184:536870911]	auto[0]	58	1			T108	1		T20	1		T245	1
auto[402653184:536870911]	auto[1]	51	1			T5	1		T144	1		T198	1
auto[536870912:671088639]	auto[0]	57	1			T44	1		T198	1		T6	1
auto[536870912:671088639]	auto[1]	50	1			T5	1		T6	1		T20	1
auto[671088640:805306367]	auto[0]	58	1			T43	1		T57	1		T149	1
auto[671088640:805306367]	auto[1]	55	1			T94	1		T89	1		T146	1
auto[805306368:939524095]	auto[0]	51	1			T23	1		T51	1		T6	1
auto[805306368:939524095]	auto[1]	51	1			T42	1		T49	1		T140	1
auto[939524096:1073741823]	auto[0]	57	1			T12	1		T50	1		T40	1
auto[939524096:1073741823]	auto[1]	65	1			T48	1		T23	1		T24	1
auto[1073741824:1207959551]	auto[0]	56	1			T12	1		T50	1		T36	1
auto[1073741824:1207959551]	auto[1]	71	1			T5	1		T12	1		T24	1
auto[1207959552:1342177279]	auto[0]	53	1			T41	1		T6	1		T53	1
auto[1207959552:1342177279]	auto[1]	50	1			T5	1		T139	1		T40	1
auto[1342177280:1476395007]	auto[0]	47	1			T43	1		T6	1		T57	1
auto[1342177280:1476395007]	auto[1]	66	1			T40	1		T30	1		T26	1
auto[1476395008:1610612735]	auto[0]	40	1			T109	1		T147	1		T136	1
auto[1476395008:1610612735]	auto[1]	59	1			T91	2		T6	2		T145	1
auto[1610612736:1744830463]	auto[0]	42	1			T23	1		T198	1		T41	1
auto[1610612736:1744830463]	auto[1]	47	1			T108	1		T53	1		T76	1
auto[1744830464:1879048191]	auto[0]	44	1			T5	1		T40	1		T41	1
auto[1744830464:1879048191]	auto[1]	55	1			T39	1		T110	1		T65	1
auto[1879048192:2013265919]	auto[0]	53	1			T48	1		T110	1		T40	1
auto[1879048192:2013265919]	auto[1]	57	1			T196	1		T30	1		T6	1
auto[2013265920:2147483647]	auto[0]	55	1			T5	1		T50	1		T198	1
auto[2013265920:2147483647]	auto[1]	52	1			T5	1		T15	1		T198	1
auto[2147483648:2281701375]	auto[0]	41	1			T97	1		T41	1		T6	2
auto[2147483648:2281701375]	auto[1]	61	1			T15	1		T23	2		T40	1
auto[2281701376:2415919103]	auto[0]	49	1			T111	1		T40	1		T97	1
auto[2281701376:2415919103]	auto[1]	57	1			T5	1		T49	1		T139	1
auto[2415919104:2550136831]	auto[0]	48	1			T43	1		T40	1		T36	1
auto[2415919104:2550136831]	auto[1]	60	1			T14	1		T16	1		T193	1
auto[2550136832:2684354559]	auto[0]	41	1			T48	1		T43	1		T111	1
auto[2550136832:2684354559]	auto[1]	65	1			T29	1		T111	1		T91	1
auto[2684354560:2818572287]	auto[0]	60	1			T15	1		T111	1		T40	1
auto[2684354560:2818572287]	auto[1]	66	1			T43	1		T40	1		T198	1
auto[2818572288:2952790015]	auto[0]	61	1			T2	1		T43	1		T65	1
auto[2818572288:2952790015]	auto[1]	64	1			T48	1		T40	1		T57	1
auto[2952790016:3087007743]	auto[0]	54	1			T5	2		T40	1		T36	1
auto[2952790016:3087007743]	auto[1]	50	1			T196	1		T108	1		T57	1
auto[3087007744:3221225471]	auto[0]	40	1			T48	1		T44	1		T89	1
auto[3087007744:3221225471]	auto[1]	64	1			T13	1		T40	2		T108	1
auto[3221225472:3355443199]	auto[0]	63	1			T24	1		T94	2		T36	1
auto[3221225472:3355443199]	auto[1]	68	1			T5	2		T42	1		T139	1
auto[3355443200:3489660927]	auto[0]	54	1			T5	1		T43	1		T51	1
auto[3355443200:3489660927]	auto[1]	57	1			T48	1		T140	1		T50	1
auto[3489660928:3623878655]	auto[0]	54	1			T23	1		T36	1		T6	1
auto[3489660928:3623878655]	auto[1]	62	1			T5	1		T48	1		T108	1
auto[3623878656:3758096383]	auto[0]	61	1			T2	1		T43	1		T108	1
auto[3623878656:3758096383]	auto[1]	49	1			T6	1		T57	2		T209	1
auto[3758096384:3892314111]	auto[0]	53	1			T5	1		T12	1		T43	1
auto[3758096384:3892314111]	auto[1]	52	1			T5	1		T144	1		T57	2
auto[3892314112:4026531839]	auto[0]	42	1			T44	2		T156	1		T252	1
auto[3892314112:4026531839]	auto[1]	63	1			T12	1		T15	1		T39	1
auto[4026531840:4160749567]	auto[0]	55	1			T5	1		T40	1		T196	1
auto[4026531840:4160749567]	auto[1]	38	1			T48	1		T50	1		T64	1
auto[4160749568:4294967295]	auto[0]	52	1			T6	1		T57	1		T25	1
auto[4160749568:4294967295]	auto[1]	46	1			T40	1		T255	1		T57	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1642

1

T2

2

T5

10

T12

2

auto[1]

1849

1

T1

1

T5

8

T12

3