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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4740 1 T2 2 T5 26 T12 8
auto[1] 2242 1 T1 2 T2 2 T5 10



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 212 1 T2 4 T5 4 T43 2
auto[134217728:268435455] 226 1 T40 2 T108 2 T6 2
auto[268435456:402653183] 220 1 T5 4 T14 2 T139 2
auto[402653184:536870911] 200 1 T15 2 T16 2 T24 2
auto[536870912:671088639] 180 1 T5 2 T43 2 T50 2
auto[671088640:805306367] 226 1 T39 2 T43 2 T44 2
auto[805306368:939524095] 192 1 T5 2 T15 4 T39 2
auto[939524096:1073741823] 224 1 T12 2 T139 2 T43 2
auto[1073741824:1207959551] 196 1 T5 2 T43 2 T40 2
auto[1207959552:1342177279] 220 1 T5 2 T48 2 T6 4
auto[1342177280:1476395007] 226 1 T111 2 T40 2 T108 2
auto[1476395008:1610612735] 218 1 T5 2 T23 2 T40 2
auto[1610612736:1744830463] 194 1 T12 2 T49 2 T51 2
auto[1744830464:1879048191] 216 1 T5 2 T23 2 T91 2
auto[1879048192:2013265919] 206 1 T39 2 T24 2 T42 2
auto[2013265920:2147483647] 230 1 T5 2 T48 2 T23 2
auto[2147483648:2281701375] 222 1 T48 2 T24 2 T91 2
auto[2281701376:2415919103] 212 1 T5 6 T12 2 T140 2
auto[2415919104:2550136831] 226 1 T48 2 T41 2 T6 2
auto[2550136832:2684354559] 196 1 T15 2 T39 2 T23 4
auto[2684354560:2818572287] 224 1 T12 2 T50 2 T40 2
auto[2818572288:2952790015] 246 1 T5 2 T43 2 T50 2
auto[2952790016:3087007743] 252 1 T13 2 T48 2 T50 2
auto[3087007744:3221225471] 226 1 T48 2 T49 2 T139 2
auto[3221225472:3355443199] 236 1 T94 2 T40 2 T36 2
auto[3355443200:3489660927] 232 1 T5 2 T44 2 T40 4
auto[3489660928:3623878655] 202 1 T12 2 T50 2 T40 2
auto[3623878656:3758096383] 176 1 T5 4 T50 2 T40 2
auto[3758096384:3892314111] 238 1 T23 2 T44 2 T198 2
auto[3892314112:4026531839] 220 1 T1 2 T49 2 T50 2
auto[4026531840:4160749567] 250 1 T48 4 T42 2 T29 2
auto[4160749568:4294967295] 238 1 T48 2 T42 2 T43 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 152 1 T2 2 T5 4 T43 2
auto[0:134217727] auto[1] 60 1 T2 2 T65 2 T6 2
auto[134217728:268435455] auto[0] 146 1 T6 2 T252 2 T244 2
auto[134217728:268435455] auto[1] 80 1 T40 2 T108 2 T209 2
auto[268435456:402653183] auto[0] 140 1 T5 2 T139 2 T140 4
auto[268435456:402653183] auto[1] 80 1 T5 2 T14 2 T196 2
auto[402653184:536870911] auto[0] 122 1 T16 2 T24 2 T110 2
auto[402653184:536870911] auto[1] 78 1 T15 2 T40 2 T145 2
auto[536870912:671088639] auto[0] 120 1 T5 2 T43 2 T50 2
auto[536870912:671088639] auto[1] 60 1 T111 2 T37 2 T45 2
auto[671088640:805306367] auto[0] 154 1 T39 2 T43 2 T44 2
auto[671088640:805306367] auto[1] 72 1 T196 2 T57 4 T25 2
auto[805306368:939524095] auto[0] 116 1 T15 2 T39 2 T36 2
auto[805306368:939524095] auto[1] 76 1 T5 2 T15 2 T110 2
auto[939524096:1073741823] auto[0] 166 1 T12 2 T139 2 T43 2
auto[939524096:1073741823] auto[1] 58 1 T6 2 T57 2 T156 2
auto[1073741824:1207959551] auto[0] 124 1 T5 2 T43 2 T40 2
auto[1073741824:1207959551] auto[1] 72 1 T145 2 T53 2 T7 2
auto[1207959552:1342177279] auto[0] 150 1 T5 2 T48 2 T6 2
auto[1207959552:1342177279] auto[1] 70 1 T6 2 T57 4 T211 2
auto[1342177280:1476395007] auto[0] 160 1 T111 2 T40 2 T97 2
auto[1342177280:1476395007] auto[1] 66 1 T108 2 T7 2 T270 2
auto[1476395008:1610612735] auto[0] 150 1 T23 2 T40 2 T6 2
auto[1476395008:1610612735] auto[1] 68 1 T5 2 T220 2 T211 2
auto[1610612736:1744830463] auto[0] 142 1 T12 2 T49 2 T51 2
auto[1610612736:1744830463] auto[1] 52 1 T6 2 T66 2 T317 2
auto[1744830464:1879048191] auto[0] 148 1 T5 2 T23 2 T91 2
auto[1744830464:1879048191] auto[1] 68 1 T145 2 T53 2 T66 2
auto[1879048192:2013265919] auto[0] 146 1 T39 2 T24 2 T43 2
auto[1879048192:2013265919] auto[1] 60 1 T42 2 T40 2 T417 2
auto[2013265920:2147483647] auto[0] 166 1 T48 2 T23 2 T51 2
auto[2013265920:2147483647] auto[1] 64 1 T5 2 T65 2 T156 2
auto[2147483648:2281701375] auto[0] 150 1 T24 2 T91 2 T36 2
auto[2147483648:2281701375] auto[1] 72 1 T48 2 T6 2 T135 2
auto[2281701376:2415919103] auto[0] 130 1 T5 6 T12 2 T40 4
auto[2281701376:2415919103] auto[1] 82 1 T140 2 T6 2 T209 2
auto[2415919104:2550136831] auto[0] 152 1 T48 2 T41 2 T6 2
auto[2415919104:2550136831] auto[1] 74 1 T57 2 T66 2 T293 2
auto[2550136832:2684354559] auto[0] 138 1 T15 2 T23 4 T24 2
auto[2550136832:2684354559] auto[1] 58 1 T39 2 T66 2 T45 2
auto[2684354560:2818572287] auto[0] 154 1 T50 2 T40 2 T52 2
auto[2684354560:2818572287] auto[1] 70 1 T12 2 T57 2 T25 2
auto[2818572288:2952790015] auto[0] 180 1 T5 2 T43 2 T50 2
auto[2818572288:2952790015] auto[1] 66 1 T57 2 T25 2 T396 2
auto[2952790016:3087007743] auto[0] 168 1 T48 2 T50 2 T40 2
auto[2952790016:3087007743] auto[1] 84 1 T13 2 T40 2 T108 2
auto[3087007744:3221225471] auto[0] 146 1 T48 2 T49 2 T139 2
auto[3087007744:3221225471] auto[1] 80 1 T94 2 T111 2 T40 4
auto[3221225472:3355443199] auto[0] 168 1 T94 2 T40 2 T36 2
auto[3221225472:3355443199] auto[1] 68 1 T196 2 T211 2 T246 2
auto[3355443200:3489660927] auto[0] 144 1 T5 2 T44 2 T40 2
auto[3355443200:3489660927] auto[1] 88 1 T40 2 T198 2 T89 2
auto[3489660928:3623878655] auto[0] 138 1 T12 2 T50 2 T40 2
auto[3489660928:3623878655] auto[1] 64 1 T144 2 T148 2 T37 2
auto[3623878656:3758096383] auto[0] 122 1 T5 2 T50 2 T40 2
auto[3623878656:3758096383] auto[1] 54 1 T5 2 T6 2 T145 2
auto[3758096384:3892314111] auto[0] 156 1 T23 2 T44 2 T198 2
auto[3758096384:3892314111] auto[1] 82 1 T57 2 T7 2 T202 2
auto[3892314112:4026531839] auto[0] 156 1 T50 2 T20 2 T57 2
auto[3892314112:4026531839] auto[1] 64 1 T1 2 T49 2 T111 2
auto[4026531840:4160749567] auto[0] 162 1 T48 2 T42 2 T40 4
auto[4026531840:4160749567] auto[1] 88 1 T48 2 T29 2 T44 2
auto[4160749568:4294967295] auto[0] 174 1 T48 2 T43 2 T94 2
auto[4160749568:4294967295] auto[1] 64 1 T42 2 T6 4 T66 4

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