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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3077 1 T1 1 T2 2 T5 14
auto[1] 248 1 T15 4 T139 5 T140 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 84 1 T5 1 T15 1 T36 1
auto[134217728:268435455] 95 1 T39 1 T48 1 T24 1
auto[268435456:402653183] 106 1 T48 1 T40 1 T36 1
auto[402653184:536870911] 109 1 T2 1 T12 1 T44 1
auto[536870912:671088639] 103 1 T15 1 T48 2 T94 1
auto[671088640:805306367] 112 1 T5 1 T110 1 T40 1
auto[805306368:939524095] 90 1 T49 1 T50 1 T144 1
auto[939524096:1073741823] 96 1 T5 1 T144 2 T198 1
auto[1073741824:1207959551] 107 1 T15 1 T23 1 T139 1
auto[1207959552:1342177279] 103 1 T39 1 T23 1 T110 1
auto[1342177280:1476395007] 103 1 T15 1 T24 1 T49 1
auto[1476395008:1610612735] 115 1 T12 1 T16 1 T48 1
auto[1610612736:1744830463] 95 1 T43 1 T111 1 T40 3
auto[1744830464:1879048191] 104 1 T24 1 T44 1 T52 1
auto[1879048192:2013265919] 82 1 T23 1 T139 1 T111 1
auto[2013265920:2147483647] 112 1 T5 1 T42 1 T139 1
auto[2147483648:2281701375] 120 1 T48 1 T139 1 T29 1
auto[2281701376:2415919103] 95 1 T43 2 T94 1 T196 1
auto[2415919104:2550136831] 104 1 T15 1 T43 1 T65 1
auto[2550136832:2684354559] 118 1 T2 1 T39 1 T91 1
auto[2684354560:2818572287] 106 1 T13 1 T139 3 T111 1
auto[2818572288:2952790015] 100 1 T5 1 T97 1 T6 1
auto[2952790016:3087007743] 90 1 T5 1 T36 1 T51 1
auto[3087007744:3221225471] 130 1 T49 1 T140 1 T36 1
auto[3221225472:3355443199] 105 1 T42 1 T43 1 T6 1
auto[3355443200:3489660927] 125 1 T1 1 T5 1 T12 1
auto[3489660928:3623878655] 102 1 T5 3 T140 1 T96 2
auto[3623878656:3758096383] 103 1 T5 1 T12 1 T23 1
auto[3758096384:3892314111] 97 1 T5 1 T39 1 T23 1
auto[3892314112:4026531839] 103 1 T15 1 T42 1 T94 1
auto[4026531840:4160749567] 120 1 T5 2 T12 1 T15 1
auto[4160749568:4294967295] 91 1 T43 1 T40 1 T198 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 75 1 T5 1 T36 1 T6 1
auto[0:134217727] auto[1] 9 1 T15 1 T155 1 T317 1
auto[134217728:268435455] auto[0] 86 1 T39 1 T48 1 T24 1
auto[134217728:268435455] auto[1] 9 1 T294 1 T247 1 T296 1
auto[268435456:402653183] auto[0] 98 1 T48 1 T40 1 T36 1
auto[268435456:402653183] auto[1] 8 1 T309 1 T416 1 T408 1
auto[402653184:536870911] auto[0] 103 1 T2 1 T12 1 T44 1
auto[402653184:536870911] auto[1] 6 1 T155 1 T247 1 T395 1
auto[536870912:671088639] auto[0] 95 1 T15 1 T48 2 T94 1
auto[536870912:671088639] auto[1] 8 1 T148 1 T387 1 T347 1
auto[671088640:805306367] auto[0] 102 1 T5 1 T110 1 T40 1
auto[671088640:805306367] auto[1] 10 1 T341 1 T247 1 T347 1
auto[805306368:939524095] auto[0] 86 1 T49 1 T50 1 T144 1
auto[805306368:939524095] auto[1] 4 1 T294 1 T370 1 T426 1
auto[939524096:1073741823] auto[0] 84 1 T5 1 T198 1 T108 1
auto[939524096:1073741823] auto[1] 12 1 T144 2 T146 1 T310 2
auto[1073741824:1207959551] auto[0] 97 1 T23 1 T43 1 T36 1
auto[1073741824:1207959551] auto[1] 10 1 T15 1 T139 1 T155 2
auto[1207959552:1342177279] auto[0] 96 1 T39 1 T23 1 T110 1
auto[1207959552:1342177279] auto[1] 7 1 T247 2 T310 1 T409 1
auto[1342177280:1476395007] auto[0] 99 1 T24 1 T49 1 T40 1
auto[1342177280:1476395007] auto[1] 4 1 T15 1 T415 1 T424 1
auto[1476395008:1610612735] auto[0] 104 1 T12 1 T16 1 T48 1
auto[1476395008:1610612735] auto[1] 11 1 T139 1 T149 1 T347 2
auto[1610612736:1744830463] auto[0] 87 1 T43 1 T111 1 T40 3
auto[1610612736:1744830463] auto[1] 8 1 T294 1 T317 1 T296 1
auto[1744830464:1879048191] auto[0] 97 1 T24 1 T44 1 T52 1
auto[1744830464:1879048191] auto[1] 7 1 T155 1 T149 1 T309 1
auto[1879048192:2013265919] auto[0] 80 1 T23 1 T139 1 T111 1
auto[1879048192:2013265919] auto[1] 2 1 T317 1 T415 1 - -
auto[2013265920:2147483647] auto[0] 104 1 T5 1 T42 1 T91 1
auto[2013265920:2147483647] auto[1] 8 1 T139 1 T294 1 T347 1
auto[2147483648:2281701375] auto[0] 110 1 T48 1 T29 1 T111 1
auto[2147483648:2281701375] auto[1] 10 1 T139 1 T155 1 T148 1
auto[2281701376:2415919103] auto[0] 89 1 T43 2 T94 1 T196 1
auto[2281701376:2415919103] auto[1] 6 1 T341 1 T243 1 T371 1
auto[2415919104:2550136831] auto[0] 101 1 T15 1 T43 1 T65 1
auto[2415919104:2550136831] auto[1] 3 1 T247 2 T423 1 - -
auto[2550136832:2684354559] auto[0] 111 1 T2 1 T39 1 T91 1
auto[2550136832:2684354559] auto[1] 7 1 T146 1 T370 1 T347 1
auto[2684354560:2818572287] auto[0] 102 1 T13 1 T139 2 T111 1
auto[2684354560:2818572287] auto[1] 4 1 T139 1 T371 1 T310 1
auto[2818572288:2952790015] auto[0] 90 1 T5 1 T97 1 T6 1
auto[2818572288:2952790015] auto[1] 10 1 T294 1 T247 1 T317 1
auto[2952790016:3087007743] auto[0] 80 1 T5 1 T36 1 T51 1
auto[2952790016:3087007743] auto[1] 10 1 T155 1 T247 3 T243 1
auto[3087007744:3221225471] auto[0] 121 1 T49 1 T36 1 T198 2
auto[3087007744:3221225471] auto[1] 9 1 T140 1 T317 2 T309 1
auto[3221225472:3355443199] auto[0] 96 1 T42 1 T43 1 T6 1
auto[3221225472:3355443199] auto[1] 9 1 T247 1 T317 1 T387 1
auto[3355443200:3489660927] auto[0] 112 1 T1 1 T5 1 T12 1
auto[3355443200:3489660927] auto[1] 13 1 T15 1 T148 1 T387 1
auto[3489660928:3623878655] auto[0] 97 1 T5 3 T140 1 T96 2
auto[3489660928:3623878655] auto[1] 5 1 T155 1 T370 1 T416 1
auto[3623878656:3758096383] auto[0] 97 1 T5 1 T12 1 T23 1
auto[3623878656:3758096383] auto[1] 6 1 T148 1 T387 1 T296 1
auto[3758096384:3892314111] auto[0] 92 1 T5 1 T39 1 T23 1
auto[3758096384:3892314111] auto[1] 5 1 T148 1 T247 1 T415 1
auto[3892314112:4026531839] auto[0] 95 1 T15 1 T42 1 T94 1
auto[3892314112:4026531839] auto[1] 8 1 T144 1 T294 1 T371 1
auto[4026531840:4160749567] auto[0] 109 1 T5 2 T12 1 T15 1
auto[4026531840:4160749567] auto[1] 11 1 T144 1 T149 1 T395 1
auto[4160749568:4294967295] auto[0] 82 1 T43 1 T40 1 T198 1
auto[4160749568:4294967295] auto[1] 9 1 T317 1 T296 2 T310 1

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