Unified Coverage Report :: Group Instance : sealing_sw_binding_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1630

1

T2

2

T5

9

T12

2

auto[1]

1861

1

T1

1

T5

9

T12

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T5	1		T42	1		T40	2
auto[134217728:268435455]	104	1			T5	1		T39	1		T29	1
auto[268435456:402653183]	107	1			T5	1		T139	1		T44	3
auto[402653184:536870911]	87	1			T40	1		T196	1		T198	1
auto[536870912:671088639]	118	1			T15	1		T24	1		T40	1
auto[671088640:805306367]	122	1			T12	1		T42	1		T36	2
auto[805306368:939524095]	119	1			T5	1		T139	1		T43	1
auto[939524096:1073741823]	92	1			T2	1		T42	1		T91	1
auto[1073741824:1207959551]	127	1			T48	1		T43	1		T44	1
auto[1207959552:1342177279]	106	1			T5	1		T39	1		T94	1
auto[1342177280:1476395007]	102	1			T12	1		T48	3		T40	1
auto[1476395008:1610612735]	99	1			T5	1		T12	1		T15	1
auto[1610612736:1744830463]	99	1			T5	1		T198	1		T97	1
auto[1744830464:1879048191]	117	1			T5	1		T23	1		T43	1
auto[1879048192:2013265919]	102	1			T5	2		T12	1		T50	1
auto[2013265920:2147483647]	94	1			T13	1		T48	1		T139	1
auto[2147483648:2281701375]	110	1			T49	1		T43	1		T198	1
auto[2281701376:2415919103]	120	1			T1	1		T48	1		T49	1
auto[2415919104:2550136831]	113	1			T39	1		T40	2		T65	1
auto[2550136832:2684354559]	94	1			T43	1		T50	1		T40	2
auto[2684354560:2818572287]	111	1			T5	1		T12	1		T15	1
auto[2818572288:2952790015]	118	1			T5	1		T23	2		T110	1
auto[2952790016:3087007743]	104	1			T24	1		T43	2		T91	1
auto[3087007744:3221225471]	105	1			T5	2		T23	1		T49	1
auto[3221225472:3355443199]	130	1			T15	1		T39	1		T50	1
auto[3355443200:3489660927]	123	1			T16	1		T23	1		T91	1
auto[3489660928:3623878655]	115	1			T5	1		T24	1		T43	1
auto[3623878656:3758096383]	110	1			T5	1		T50	1		T144	1
auto[3758096384:3892314111]	97	1			T5	1		T23	1		T44	1
auto[3892314112:4026531839]	120	1			T14	1		T36	1		T108	1
auto[4026531840:4160749567]	102	1			T40	1		T65	1		T155	1
auto[4160749568:4294967295]	117	1			T2	1		T5	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T42	1		T41	1		T53	1
auto[0:134217727]	auto[1]	58	1			T5	1		T40	2		T6	1
auto[134217728:268435455]	auto[0]	50	1			T5	1		T50	1		T36	1
auto[134217728:268435455]	auto[1]	54	1			T39	1		T29	1		T57	1
auto[268435456:402653183]	auto[0]	51	1			T44	2		T6	1		T57	1
auto[268435456:402653183]	auto[1]	56	1			T5	1		T139	1		T44	1
auto[402653184:536870911]	auto[0]	34	1			T196	1		T198	1		T26	1
auto[402653184:536870911]	auto[1]	53	1			T40	1		T96	1		T220	1
auto[536870912:671088639]	auto[0]	60	1			T40	1		T109	1		T41	1
auto[536870912:671088639]	auto[1]	58	1			T15	1		T24	1		T20	1
auto[671088640:805306367]	auto[0]	50	1			T36	2		T108	1		T6	2
auto[671088640:805306367]	auto[1]	72	1			T12	1		T42	1		T6	1
auto[805306368:939524095]	auto[0]	48	1			T43	1		T111	1		T66	1
auto[805306368:939524095]	auto[1]	71	1			T5	1		T139	1		T111	1
auto[939524096:1073741823]	auto[0]	44	1			T2	1		T91	1		T6	1
auto[939524096:1073741823]	auto[1]	48	1			T42	1		T255	1		T89	1
auto[1073741824:1207959551]	auto[0]	60	1			T43	1		T44	1		T198	1
auto[1073741824:1207959551]	auto[1]	67	1			T48	1		T36	1		T51	1
auto[1207959552:1342177279]	auto[0]	49	1			T5	1		T94	1		T97	1
auto[1207959552:1342177279]	auto[1]	57	1			T39	1		T140	1		T110	1
auto[1342177280:1476395007]	auto[0]	47	1			T48	2		T144	1		T97	1
auto[1342177280:1476395007]	auto[1]	55	1			T12	1		T48	1		T40	1
auto[1476395008:1610612735]	auto[0]	51	1			T5	1		T12	1		T15	1
auto[1476395008:1610612735]	auto[1]	48	1			T48	1		T24	1		T50	1
auto[1610612736:1744830463]	auto[0]	50	1			T5	1		T198	1		T97	1
auto[1610612736:1744830463]	auto[1]	49	1			T53	3		T76	1		T286	1
auto[1744830464:1879048191]	auto[0]	50	1			T43	1		T50	1		T6	1
auto[1744830464:1879048191]	auto[1]	67	1			T5	1		T23	1		T94	1
auto[1879048192:2013265919]	auto[0]	42	1			T5	1		T12	1		T50	1
auto[1879048192:2013265919]	auto[1]	60	1			T5	1		T40	1		T30	1
auto[2013265920:2147483647]	auto[0]	40	1			T40	1		T53	1		T246	1
auto[2013265920:2147483647]	auto[1]	54	1			T13	1		T48	1		T139	1
auto[2147483648:2281701375]	auto[0]	60	1			T49	1		T43	1		T108	1
auto[2147483648:2281701375]	auto[1]	50	1			T198	1		T255	1		T30	1
auto[2281701376:2415919103]	auto[0]	53	1			T48	1		T43	1		T50	1
auto[2281701376:2415919103]	auto[1]	67	1			T1	1		T49	1		T108	1
auto[2415919104:2550136831]	auto[0]	48	1			T40	1		T57	1		T53	1
auto[2415919104:2550136831]	auto[1]	65	1			T39	1		T40	1		T65	1
auto[2550136832:2684354559]	auto[0]	45	1			T43	1		T40	1		T41	1
auto[2550136832:2684354559]	auto[1]	49	1			T50	1		T40	1		T255	1
auto[2684354560:2818572287]	auto[0]	48	1			T5	1		T109	1		T66	1
auto[2684354560:2818572287]	auto[1]	63	1			T12	1		T15	1		T140	1
auto[2818572288:2952790015]	auto[0]	58	1			T5	1		T23	2		T110	1
auto[2818572288:2952790015]	auto[1]	60	1			T40	1		T108	1		T57	1
auto[2952790016:3087007743]	auto[0]	52	1			T43	1		T41	1		T6	1
auto[2952790016:3087007743]	auto[1]	52	1			T24	1		T43	1		T91	1
auto[3087007744:3221225471]	auto[0]	50	1			T5	1		T23	1		T65	1
auto[3087007744:3221225471]	auto[1]	55	1			T5	1		T49	1		T140	1
auto[3221225472:3355443199]	auto[0]	64	1			T50	1		T111	1		T51	1
auto[3221225472:3355443199]	auto[1]	66	1			T15	1		T39	1		T40	1
auto[3355443200:3489660927]	auto[0]	52	1			T109	1		T255	1		T6	1
auto[3355443200:3489660927]	auto[1]	71	1			T16	1		T23	1		T91	1
auto[3489660928:3623878655]	auto[0]	58	1			T43	1		T36	1		T41	1
auto[3489660928:3623878655]	auto[1]	57	1			T5	1		T24	1		T94	1
auto[3623878656:3758096383]	auto[0]	55	1			T6	2		T252	1		T244	2
auto[3623878656:3758096383]	auto[1]	55	1			T5	1		T50	1		T144	1
auto[3758096384:3892314111]	auto[0]	47	1			T5	1		T44	1		T41	1
auto[3758096384:3892314111]	auto[1]	50	1			T23	1		T40	1		T108	1
auto[3892314112:4026531839]	auto[0]	55	1			T89	1		T53	1		T396	1
auto[3892314112:4026531839]	auto[1]	65	1			T14	1		T36	1		T108	1
auto[4026531840:4160749567]	auto[0]	53	1			T65	1		T155	1		T26	2
auto[4026531840:4160749567]	auto[1]	49	1			T40	1		T57	1		T89	1
auto[4160749568:4294967295]	auto[0]	57	1			T2	1		T40	1		T6	1
auto[4160749568:4294967295]	auto[1]	60	1			T5	1		T48	1		T40	2