Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7205

1

T1

2

T2

4

T5

37

auto[1]

265

1

T15

1

T139

11

T140

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3016	1			T1	1		T2	2		T5	17
auto[134217728:268435455]	187	1			T15	1		T139	1		T94	1
auto[268435456:402653183]	171	1			T23	1		T139	1		T40	1
auto[402653184:536870911]	142	1			T48	1		T24	1		T6	2
auto[536870912:671088639]	142	1			T12	1		T139	2		T94	1
auto[671088640:805306367]	157	1			T5	1		T43	1		T140	1
auto[805306368:939524095]	136	1			T48	1		T24	1		T49	1
auto[939524096:1073741823]	155	1			T5	2		T139	1		T40	1
auto[1073741824:1207959551]	162	1			T5	1		T12	1		T39	1
auto[1207959552:1342177279]	149	1			T5	1		T12	1		T23	1
auto[1342177280:1476395007]	141	1			T5	1		T48	1		T24	1
auto[1476395008:1610612735]	143	1			T24	1		T49	1		T139	1
auto[1610612736:1744830463]	148	1			T5	3		T12	1		T16	1
auto[1744830464:1879048191]	136	1			T5	1		T48	1		T42	1
auto[1879048192:2013265919]	132	1			T5	1		T15	1		T139	1
auto[2013265920:2147483647]	127	1			T5	1		T23	1		T24	1
auto[2147483648:2281701375]	145	1			T23	1		T139	1		T255	1
auto[2281701376:2415919103]	132	1			T94	1		T140	1		T29	1
auto[2415919104:2550136831]	135	1			T48	1		T24	2		T139	1
auto[2550136832:2684354559]	133	1			T15	1		T39	1		T48	1
auto[2684354560:2818572287]	141	1			T2	1		T5	1		T139	1
auto[2818572288:2952790015]	133	1			T12	1		T23	1		T144	2
auto[2952790016:3087007743]	126	1			T15	1		T43	3		T140	1
auto[3087007744:3221225471]	146	1			T15	1		T39	1		T40	1
auto[3221225472:3355443199]	130	1			T5	1		T13	1		T14	1
auto[3355443200:3489660927]	148	1			T2	1		T5	1		T15	1
auto[3489660928:3623878655]	132	1			T1	1		T5	2		T48	1
auto[3623878656:3758096383]	132	1			T5	1		T24	1		T43	1
auto[3758096384:3892314111]	136	1			T43	1		T140	1		T198	2
auto[3892314112:4026531839]	134	1			T139	1		T140	1		T110	1
auto[4026531840:4160749567]	158	1			T5	2		T41	1		T20	1
auto[4160749568:4294967295]	165	1			T42	1		T196	1		T144	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3009	1			T1	1		T2	2		T5	17
auto[0:134217727]	auto[1]	7	1			T147	1		T387	1		T409	1
auto[134217728:268435455]	auto[0]	179	1			T15	1		T94	1		T44	1
auto[134217728:268435455]	auto[1]	8	1			T139	1		T146	1		T147	1
auto[268435456:402653183]	auto[0]	164	1			T23	1		T40	1		T198	2
auto[268435456:402653183]	auto[1]	7	1			T139	1		T294	1		T317	1
auto[402653184:536870911]	auto[0]	136	1			T48	1		T24	1		T6	2
auto[402653184:536870911]	auto[1]	6	1			T317	2		T285	1		T415	1
auto[536870912:671088639]	auto[0]	128	1			T12	1		T94	1		T198	1
auto[536870912:671088639]	auto[1]	14	1			T139	2		T294	1		T387	1
auto[671088640:805306367]	auto[0]	146	1			T5	1		T43	1		T140	1
auto[671088640:805306367]	auto[1]	11	1			T294	1		T247	2		T317	1
auto[805306368:939524095]	auto[0]	129	1			T48	1		T24	1		T49	1
auto[805306368:939524095]	auto[1]	7	1			T155	1		T309	1		T416	1
auto[939524096:1073741823]	auto[0]	145	1			T5	2		T40	1		T52	1
auto[939524096:1073741823]	auto[1]	10	1			T139	1		T148	1		T294	2
auto[1073741824:1207959551]	auto[0]	151	1			T5	1		T12	1		T39	1
auto[1073741824:1207959551]	auto[1]	11	1			T395	2		T387	1		T309	1
auto[1207959552:1342177279]	auto[0]	141	1			T5	1		T12	1		T23	1
auto[1207959552:1342177279]	auto[1]	8	1			T139	1		T309	1		T347	1
auto[1342177280:1476395007]	auto[0]	134	1			T5	1		T48	1		T24	1
auto[1342177280:1476395007]	auto[1]	7	1			T395	1		T370	1		T296	1
auto[1476395008:1610612735]	auto[0]	134	1			T24	1		T49	1		T94	2
auto[1476395008:1610612735]	auto[1]	9	1			T139	1		T247	1		T309	2
auto[1610612736:1744830463]	auto[0]	137	1			T5	3		T12	1		T16	1
auto[1610612736:1744830463]	auto[1]	11	1			T247	1		T309	2		T371	1
auto[1744830464:1879048191]	auto[0]	129	1			T5	1		T48	1		T42	1
auto[1744830464:1879048191]	auto[1]	7	1			T148	1		T387	1		T347	1
auto[1879048192:2013265919]	auto[0]	130	1			T5	1		T15	1		T40	2
auto[1879048192:2013265919]	auto[1]	2	1			T139	1		T294	1		-	-
auto[2013265920:2147483647]	auto[0]	121	1			T5	1		T23	1		T24	1
auto[2013265920:2147483647]	auto[1]	6	1			T146	1		T148	1		T415	1
auto[2147483648:2281701375]	auto[0]	136	1			T23	1		T255	1		T97	1
auto[2147483648:2281701375]	auto[1]	9	1			T139	1		T155	1		T317	2
auto[2281701376:2415919103]	auto[0]	123	1			T94	1		T140	1		T29	1
auto[2281701376:2415919103]	auto[1]	9	1			T144	1		T155	1		T247	1
auto[2415919104:2550136831]	auto[0]	128	1			T48	1		T24	2		T139	1
auto[2415919104:2550136831]	auto[1]	7	1			T317	1		T371	1		T409	2
auto[2550136832:2684354559]	auto[0]	123	1			T15	1		T39	1		T48	1
auto[2550136832:2684354559]	auto[1]	10	1			T139	1		T294	1		T247	1
auto[2684354560:2818572287]	auto[0]	132	1			T2	1		T5	1		T139	1
auto[2684354560:2818572287]	auto[1]	9	1			T140	1		T144	1		T294	2
auto[2818572288:2952790015]	auto[0]	119	1			T12	1		T23	1		T109	1
auto[2818572288:2952790015]	auto[1]	14	1			T144	2		T148	2		T317	1
auto[2952790016:3087007743]	auto[0]	120	1			T15	1		T43	3		T140	1
auto[2952790016:3087007743]	auto[1]	6	1			T144	1		T155	1		T294	1
auto[3087007744:3221225471]	auto[0]	136	1			T15	1		T39	1		T40	1
auto[3087007744:3221225471]	auto[1]	10	1			T144	1		T147	1		T148	1
auto[3221225472:3355443199]	auto[0]	127	1			T5	1		T13	1		T14	1
auto[3221225472:3355443199]	auto[1]	3	1			T317	1		T416	1		T411	1
auto[3355443200:3489660927]	auto[0]	139	1			T2	1		T5	1		T40	2
auto[3355443200:3489660927]	auto[1]	9	1			T15	1		T294	1		T387	1
auto[3489660928:3623878655]	auto[0]	126	1			T1	1		T5	2		T48	1
auto[3489660928:3623878655]	auto[1]	6	1			T317	1		T313	1		T337	1
auto[3623878656:3758096383]	auto[0]	126	1			T5	1		T24	1		T43	1
auto[3623878656:3758096383]	auto[1]	6	1			T147	1		T296	1		T374	1
auto[3758096384:3892314111]	auto[0]	126	1			T43	1		T198	2		T255	1
auto[3758096384:3892314111]	auto[1]	10	1			T140	1		T294	1		T395	1
auto[3892314112:4026531839]	auto[0]	126	1			T140	1		T110	1		T44	1
auto[3892314112:4026531839]	auto[1]	8	1			T139	1		T146	1		T341	1
auto[4026531840:4160749567]	auto[0]	147	1			T5	2		T41	1		T20	1
auto[4026531840:4160749567]	auto[1]	11	1			T294	1		T317	1		T387	1
auto[4160749568:4294967295]	auto[0]	158	1			T42	1		T196	1		T108	1
auto[4160749568:4294967295]	auto[1]	7	1			T144	1		T347	1		T416	1