Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4712

1

T1

2

T2

2

T5

26

auto[1]

2270

1

T2

2

T5

10

T12

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	224	1			T48	2		T23	2		T29	2
auto[134217728:268435455]	196	1			T5	2		T39	2		T24	2
auto[268435456:402653183]	222	1			T13	2		T42	2		T43	2
auto[402653184:536870911]	228	1			T2	2		T16	2		T23	2
auto[536870912:671088639]	204	1			T5	4		T15	2		T49	2
auto[671088640:805306367]	246	1			T48	2		T49	2		T44	2
auto[805306368:939524095]	214	1			T15	2		T42	2		T50	2
auto[939524096:1073741823]	192	1			T1	2		T15	2		T23	2
auto[1073741824:1207959551]	206	1			T14	2		T198	2		T109	2
auto[1207959552:1342177279]	202	1			T23	2		T40	2		T109	2
auto[1342177280:1476395007]	212	1			T49	2		T40	4		T36	2
auto[1476395008:1610612735]	220	1			T12	2		T23	2		T24	2
auto[1610612736:1744830463]	202	1			T12	2		T24	2		T43	2
auto[1744830464:1879048191]	258	1			T5	2		T43	2		T94	2
auto[1879048192:2013265919]	214	1			T5	2		T139	2		T43	2
auto[2013265920:2147483647]	228	1			T5	2		T48	2		T111	2
auto[2147483648:2281701375]	254	1			T5	2		T140	2		T111	2
auto[2281701376:2415919103]	180	1			T5	2		T48	4		T30	2
auto[2415919104:2550136831]	204	1			T2	2		T5	4		T48	2
auto[2550136832:2684354559]	228	1			T5	2		T48	2		T139	2
auto[2684354560:2818572287]	204	1			T12	2		T48	2		T50	2
auto[2818572288:2952790015]	234	1			T23	2		T110	2		T111	2
auto[2952790016:3087007743]	216	1			T5	2		T15	2		T50	2
auto[3087007744:3221225471]	198	1			T12	2		T39	2		T44	2
auto[3221225472:3355443199]	204	1			T5	2		T44	2		T40	2
auto[3355443200:3489660927]	234	1			T43	2		T40	2		T6	4
auto[3489660928:3623878655]	232	1			T5	4		T43	2		T108	2
auto[3623878656:3758096383]	240	1			T5	2		T40	4		T255	4
auto[3758096384:3892314111]	218	1			T5	2		T39	2		T48	2
auto[3892314112:4026531839]	226	1			T12	2		T39	2		T50	4
auto[4026531840:4160749567]	216	1			T51	2		T96	2		T30	2
auto[4160749568:4294967295]	226	1			T5	2		T139	2		T94	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	144	1			T23	2		T29	2		T108	2
auto[0:134217727]	auto[1]	80	1			T48	2		T89	2		T209	2
auto[134217728:268435455]	auto[0]	134	1			T39	2		T50	2		T36	2
auto[134217728:268435455]	auto[1]	62	1			T5	2		T24	2		T193	2
auto[268435456:402653183]	auto[0]	142	1			T43	2		T51	2		T144	4
auto[268435456:402653183]	auto[1]	80	1			T13	2		T42	2		T6	2
auto[402653184:536870911]	auto[0]	150	1			T2	2		T23	2		T140	2
auto[402653184:536870911]	auto[1]	78	1			T16	2		T50	2		T91	2
auto[536870912:671088639]	auto[0]	130	1			T5	4		T15	2		T40	2
auto[536870912:671088639]	auto[1]	74	1			T49	2		T108	2		T57	2
auto[671088640:805306367]	auto[0]	180	1			T48	2		T49	2		T44	2
auto[671088640:805306367]	auto[1]	66	1			T6	2		T202	4		T414	2
auto[805306368:939524095]	auto[0]	172	1			T42	2		T50	2		T44	2
auto[805306368:939524095]	auto[1]	42	1			T15	2		T417	2		T58	4
auto[939524096:1073741823]	auto[0]	122	1			T1	2		T23	2		T24	2
auto[939524096:1073741823]	auto[1]	70	1			T15	2		T110	2		T52	2
auto[1073741824:1207959551]	auto[0]	144	1			T198	2		T109	2		T41	2
auto[1073741824:1207959551]	auto[1]	62	1			T14	2		T57	2		T145	2
auto[1207959552:1342177279]	auto[0]	142	1			T23	2		T40	2		T211	2
auto[1207959552:1342177279]	auto[1]	60	1			T109	2		T6	2		T57	4
auto[1342177280:1476395007]	auto[0]	146	1			T49	2		T40	4		T36	2
auto[1342177280:1476395007]	auto[1]	66	1			T108	2		T53	4		T412	2
auto[1476395008:1610612735]	auto[0]	152	1			T24	2		T43	2		T91	2
auto[1476395008:1610612735]	auto[1]	68	1			T12	2		T23	2		T41	2
auto[1610612736:1744830463]	auto[0]	138	1			T12	2		T24	2		T43	2
auto[1610612736:1744830463]	auto[1]	64	1			T97	2		T7	2		T202	2
auto[1744830464:1879048191]	auto[0]	182	1			T5	2		T140	2		T91	2
auto[1744830464:1879048191]	auto[1]	76	1			T43	2		T94	2		T111	4
auto[1879048192:2013265919]	auto[0]	134	1			T43	2		T40	4		T57	2
auto[1879048192:2013265919]	auto[1]	80	1			T5	2		T139	2		T40	2
auto[2013265920:2147483647]	auto[0]	156	1			T5	2		T48	2		T156	4
auto[2013265920:2147483647]	auto[1]	72	1			T111	2		T40	2		T6	2
auto[2147483648:2281701375]	auto[0]	170	1			T5	2		T140	2		T40	2
auto[2147483648:2281701375]	auto[1]	84	1			T111	2		T6	2		T155	2
auto[2281701376:2415919103]	auto[0]	122	1			T5	2		T30	2		T6	4
auto[2281701376:2415919103]	auto[1]	58	1			T48	4		T211	2		T249	2
auto[2415919104:2550136831]	auto[0]	134	1			T5	2		T156	2		T146	2
auto[2415919104:2550136831]	auto[1]	70	1			T2	2		T5	2		T48	2
auto[2550136832:2684354559]	auto[0]	152	1			T5	2		T48	2		T40	2
auto[2550136832:2684354559]	auto[1]	76	1			T139	2		T40	2		T252	2
auto[2684354560:2818572287]	auto[0]	130	1			T12	2		T48	2		T50	2
auto[2684354560:2818572287]	auto[1]	74	1			T108	2		T244	2		T53	2
auto[2818572288:2952790015]	auto[0]	158	1			T23	2		T111	2		T244	2
auto[2818572288:2952790015]	auto[1]	76	1			T110	2		T36	2		T147	2
auto[2952790016:3087007743]	auto[0]	154	1			T5	2		T15	2		T50	2
auto[2952790016:3087007743]	auto[1]	62	1			T6	2		T25	2		T53	2
auto[3087007744:3221225471]	auto[0]	138	1			T12	2		T39	2		T51	2
auto[3087007744:3221225471]	auto[1]	60	1			T44	2		T40	2		T53	2
auto[3221225472:3355443199]	auto[0]	142	1			T5	2		T44	2		T40	2
auto[3221225472:3355443199]	auto[1]	62	1			T57	2		T53	2		T405	2
auto[3355443200:3489660927]	auto[0]	166	1			T43	2		T40	2		T6	2
auto[3355443200:3489660927]	auto[1]	68	1			T6	2		T53	2		T286	2
auto[3489660928:3623878655]	auto[0]	162	1			T5	2		T43	2		T108	2
auto[3489660928:3623878655]	auto[1]	70	1			T5	2		T66	2		T412	2
auto[3623878656:3758096383]	auto[0]	160	1			T40	2		T255	4		T41	2
auto[3623878656:3758096383]	auto[1]	80	1			T5	2		T40	2		T6	2
auto[3758096384:3892314111]	auto[0]	132	1			T5	2		T48	2		T43	4
auto[3758096384:3892314111]	auto[1]	86	1			T39	2		T42	2		T97	2
auto[3892314112:4026531839]	auto[0]	156	1			T39	2		T50	4		T36	2
auto[3892314112:4026531839]	auto[1]	70	1			T12	2		T40	2		T41	2
auto[4026531840:4160749567]	auto[0]	136	1			T30	2		T6	2		T145	2
auto[4026531840:4160749567]	auto[1]	80	1			T51	2		T96	2		T41	2
auto[4160749568:4294967295]	auto[0]	132	1			T5	2		T40	2		T155	2
auto[4160749568:4294967295]	auto[1]	94	1			T139	2		T94	4		T198	2