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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.04 97.87 98.35 100.00 99.02 98.41 91.17


Total test records in report: 1085
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T1009 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3365753387 Aug 11 05:57:15 PM PDT 24 Aug 11 05:57:17 PM PDT 24 192420390 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1531186825 Aug 11 05:56:21 PM PDT 24 Aug 11 05:56:26 PM PDT 24 89264946 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1377232533 Aug 11 05:56:57 PM PDT 24 Aug 11 05:56:59 PM PDT 24 226229527 ps
T1012 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3294388292 Aug 11 05:57:34 PM PDT 24 Aug 11 05:57:35 PM PDT 24 17142422 ps
T1013 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1702838791 Aug 11 05:57:01 PM PDT 24 Aug 11 05:57:03 PM PDT 24 16222519 ps
T1014 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1899003297 Aug 11 05:56:56 PM PDT 24 Aug 11 05:57:00 PM PDT 24 692025430 ps
T1015 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1034806451 Aug 11 05:56:07 PM PDT 24 Aug 11 05:56:09 PM PDT 24 21312545 ps
T393 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2944981942 Aug 11 05:57:02 PM PDT 24 Aug 11 05:57:10 PM PDT 24 941646238 ps
T1016 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.905902735 Aug 11 05:56:26 PM PDT 24 Aug 11 05:56:28 PM PDT 24 90233269 ps
T165 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2433075775 Aug 11 05:57:29 PM PDT 24 Aug 11 05:57:32 PM PDT 24 125075719 ps
T1017 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3478530973 Aug 11 05:56:19 PM PDT 24 Aug 11 05:56:20 PM PDT 24 34190685 ps
T1018 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3353434746 Aug 11 05:56:40 PM PDT 24 Aug 11 05:56:45 PM PDT 24 445070151 ps
T1019 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1861494747 Aug 11 05:56:49 PM PDT 24 Aug 11 05:56:54 PM PDT 24 212168954 ps
T1020 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3537380193 Aug 11 05:57:38 PM PDT 24 Aug 11 05:57:38 PM PDT 24 25743901 ps
T1021 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2068623248 Aug 11 05:57:07 PM PDT 24 Aug 11 05:57:22 PM PDT 24 422466029 ps
T174 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1125718037 Aug 11 05:57:09 PM PDT 24 Aug 11 05:57:12 PM PDT 24 531152203 ps
T1022 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3809289551 Aug 11 05:57:40 PM PDT 24 Aug 11 05:57:41 PM PDT 24 9912111 ps
T1023 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2751137680 Aug 11 05:57:02 PM PDT 24 Aug 11 05:57:04 PM PDT 24 302672364 ps
T160 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3008857376 Aug 11 05:56:59 PM PDT 24 Aug 11 05:57:07 PM PDT 24 884040512 ps
T1024 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1289151517 Aug 11 05:57:00 PM PDT 24 Aug 11 05:57:06 PM PDT 24 650264876 ps
T1025 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4209862052 Aug 11 05:56:04 PM PDT 24 Aug 11 05:56:05 PM PDT 24 59856938 ps
T161 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1852910128 Aug 11 05:57:23 PM PDT 24 Aug 11 05:57:27 PM PDT 24 536309259 ps
T1026 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4012691131 Aug 11 05:56:26 PM PDT 24 Aug 11 05:56:29 PM PDT 24 150781383 ps
T1027 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3640859477 Aug 11 05:56:55 PM PDT 24 Aug 11 05:56:56 PM PDT 24 97567818 ps
T171 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3447106257 Aug 11 05:56:33 PM PDT 24 Aug 11 05:56:39 PM PDT 24 93920532 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.319947805 Aug 11 05:56:58 PM PDT 24 Aug 11 05:57:00 PM PDT 24 66778651 ps
T1029 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3090548424 Aug 11 05:56:57 PM PDT 24 Aug 11 05:57:11 PM PDT 24 398861637 ps
T1030 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.71713749 Aug 11 05:57:21 PM PDT 24 Aug 11 05:57:23 PM PDT 24 32269609 ps
T1031 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2867960558 Aug 11 05:57:23 PM PDT 24 Aug 11 05:57:27 PM PDT 24 209124014 ps
T1032 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3925461332 Aug 11 05:56:33 PM PDT 24 Aug 11 05:56:34 PM PDT 24 14911289 ps
T1033 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.803427085 Aug 11 05:55:24 PM PDT 24 Aug 11 05:55:27 PM PDT 24 180500501 ps
T1034 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1489974890 Aug 11 05:56:31 PM PDT 24 Aug 11 05:56:33 PM PDT 24 309479530 ps
T1035 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3478400645 Aug 11 05:56:43 PM PDT 24 Aug 11 05:56:47 PM PDT 24 289832759 ps
T1036 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3852212510 Aug 11 05:56:33 PM PDT 24 Aug 11 05:56:37 PM PDT 24 79560492 ps
T1037 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1504397972 Aug 11 05:57:11 PM PDT 24 Aug 11 05:57:13 PM PDT 24 661559805 ps
T1038 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2184315961 Aug 11 05:57:17 PM PDT 24 Aug 11 05:57:18 PM PDT 24 14572976 ps
T1039 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2514225499 Aug 11 05:57:35 PM PDT 24 Aug 11 05:57:36 PM PDT 24 14288410 ps
T1040 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.634526176 Aug 11 05:57:38 PM PDT 24 Aug 11 05:57:39 PM PDT 24 11388988 ps
T169 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1300306011 Aug 11 05:56:40 PM PDT 24 Aug 11 05:56:47 PM PDT 24 303055242 ps
T1041 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2717457689 Aug 11 05:56:57 PM PDT 24 Aug 11 05:56:58 PM PDT 24 38657986 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1062453043 Aug 11 05:56:17 PM PDT 24 Aug 11 05:56:22 PM PDT 24 670230386 ps
T1043 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3742336653 Aug 11 05:57:35 PM PDT 24 Aug 11 05:57:36 PM PDT 24 9651721 ps
T1044 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4029687802 Aug 11 05:57:20 PM PDT 24 Aug 11 05:57:21 PM PDT 24 94962805 ps
T176 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1920669368 Aug 11 05:57:16 PM PDT 24 Aug 11 05:57:21 PM PDT 24 117820730 ps
T1045 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2040894063 Aug 11 05:56:56 PM PDT 24 Aug 11 05:56:58 PM PDT 24 532107654 ps
T1046 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.766365300 Aug 11 05:57:09 PM PDT 24 Aug 11 05:57:11 PM PDT 24 158192505 ps
T1047 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1788816064 Aug 11 05:56:56 PM PDT 24 Aug 11 05:56:56 PM PDT 24 43501202 ps
T1048 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2139085737 Aug 11 05:56:43 PM PDT 24 Aug 11 05:56:45 PM PDT 24 130288136 ps
T1049 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2418658241 Aug 11 05:57:09 PM PDT 24 Aug 11 05:57:14 PM PDT 24 479373300 ps
T1050 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.351117706 Aug 11 05:57:31 PM PDT 24 Aug 11 05:57:32 PM PDT 24 10422017 ps
T1051 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.770328645 Aug 11 05:57:30 PM PDT 24 Aug 11 05:57:31 PM PDT 24 35305322 ps
T1052 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1837002060 Aug 11 05:57:16 PM PDT 24 Aug 11 05:57:24 PM PDT 24 756710699 ps
T1053 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1951886367 Aug 11 05:57:34 PM PDT 24 Aug 11 05:57:35 PM PDT 24 46872280 ps
T1054 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3527990963 Aug 11 05:56:28 PM PDT 24 Aug 11 05:56:44 PM PDT 24 1842039308 ps
T1055 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4275043736 Aug 11 05:57:38 PM PDT 24 Aug 11 05:57:40 PM PDT 24 36185294 ps
T1056 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3278591307 Aug 11 05:57:02 PM PDT 24 Aug 11 05:57:04 PM PDT 24 386217657 ps
T1057 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1450309993 Aug 11 05:55:18 PM PDT 24 Aug 11 05:55:31 PM PDT 24 2041516548 ps
T1058 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.10664984 Aug 11 05:57:02 PM PDT 24 Aug 11 05:57:03 PM PDT 24 30145920 ps
T1059 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4248169633 Aug 11 05:57:40 PM PDT 24 Aug 11 05:57:41 PM PDT 24 109336175 ps
T1060 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.509412204 Aug 11 05:56:50 PM PDT 24 Aug 11 05:56:52 PM PDT 24 263323862 ps
T1061 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3960239317 Aug 11 05:57:25 PM PDT 24 Aug 11 05:57:28 PM PDT 24 635399895 ps
T1062 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3432930036 Aug 11 05:56:17 PM PDT 24 Aug 11 05:56:19 PM PDT 24 193770986 ps
T1063 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1094473429 Aug 11 05:56:25 PM PDT 24 Aug 11 05:56:26 PM PDT 24 18307355 ps
T1064 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2029761051 Aug 11 05:56:31 PM PDT 24 Aug 11 05:56:33 PM PDT 24 203268177 ps
T1065 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1633050511 Aug 11 05:56:15 PM PDT 24 Aug 11 05:56:18 PM PDT 24 452646098 ps
T1066 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.78326637 Aug 11 05:56:39 PM PDT 24 Aug 11 05:56:40 PM PDT 24 83030472 ps
T1067 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2406002666 Aug 11 05:56:43 PM PDT 24 Aug 11 05:56:44 PM PDT 24 21197600 ps
T1068 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2712696367 Aug 11 05:56:19 PM PDT 24 Aug 11 05:56:26 PM PDT 24 2609874726 ps
T1069 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.881197973 Aug 11 05:57:02 PM PDT 24 Aug 11 05:57:04 PM PDT 24 25358967 ps
T1070 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.218451960 Aug 11 05:57:39 PM PDT 24 Aug 11 05:57:40 PM PDT 24 30500198 ps
T1071 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2321422249 Aug 11 05:57:12 PM PDT 24 Aug 11 05:57:12 PM PDT 24 9276125 ps
T1072 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.292303955 Aug 11 05:56:57 PM PDT 24 Aug 11 05:56:58 PM PDT 24 413739455 ps
T1073 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3460593412 Aug 11 05:57:12 PM PDT 24 Aug 11 05:57:13 PM PDT 24 32100748 ps
T1074 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3201426226 Aug 11 05:57:20 PM PDT 24 Aug 11 05:57:23 PM PDT 24 304929087 ps
T1075 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.918078542 Aug 11 05:57:32 PM PDT 24 Aug 11 05:57:35 PM PDT 24 115896739 ps
T1076 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3554962636 Aug 11 05:56:02 PM PDT 24 Aug 11 05:56:03 PM PDT 24 11818948 ps
T1077 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.818547038 Aug 11 05:56:56 PM PDT 24 Aug 11 05:56:58 PM PDT 24 140942098 ps
T1078 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2574422808 Aug 11 05:55:40 PM PDT 24 Aug 11 05:55:42 PM PDT 24 34093660 ps
T1079 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3582267259 Aug 11 05:57:22 PM PDT 24 Aug 11 05:57:23 PM PDT 24 7909908 ps
T1080 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2988143230 Aug 11 05:56:38 PM PDT 24 Aug 11 05:56:39 PM PDT 24 32182806 ps
T1081 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2543976540 Aug 11 05:56:18 PM PDT 24 Aug 11 05:56:19 PM PDT 24 21466828 ps
T1082 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3053460174 Aug 11 05:57:30 PM PDT 24 Aug 11 05:57:31 PM PDT 24 12884597 ps
T1083 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.599939511 Aug 11 05:57:28 PM PDT 24 Aug 11 05:57:30 PM PDT 24 39891933 ps
T1084 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1759273290 Aug 11 05:56:52 PM PDT 24 Aug 11 05:57:07 PM PDT 24 416776777 ps
T1085 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.8411901 Aug 11 05:57:33 PM PDT 24 Aug 11 05:57:34 PM PDT 24 38682203 ps

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.427287061
Short name T5
Test name
Test status
Simulation time 2147210518 ps
CPU time 26.57 seconds
Started Aug 11 06:05:53 PM PDT 24
Finished Aug 11 06:06:20 PM PDT 24
Peak memory 222304 kb
Host smart-652e1aab-d790-4e0d-be8c-d89103cff21c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427287061 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.427287061
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.4256255023
Short name T6
Test name
Test status
Simulation time 705244744 ps
CPU time 28.6 seconds
Started Aug 11 06:05:44 PM PDT 24
Finished Aug 11 06:06:12 PM PDT 24
Peak memory 222372 kb
Host smart-ffcbe596-f2d7-46b2-8037-f99c307c0378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256255023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.4256255023
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4207286491
Short name T53
Test name
Test status
Simulation time 1093663494 ps
CPU time 39.47 seconds
Started Aug 11 06:06:06 PM PDT 24
Finished Aug 11 06:06:45 PM PDT 24
Peak memory 215424 kb
Host smart-7aa73629-bac1-4165-a093-c7ae22b9159b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207286491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4207286491
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.84028986
Short name T10
Test name
Test status
Simulation time 571339734 ps
CPU time 12.8 seconds
Started Aug 11 06:04:36 PM PDT 24
Finished Aug 11 06:04:49 PM PDT 24
Peak memory 238368 kb
Host smart-d373ee91-af67-4543-ba68-68fefc454e0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84028986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.84028986
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1068234721
Short name T48
Test name
Test status
Simulation time 267886193 ps
CPU time 16.03 seconds
Started Aug 11 06:06:15 PM PDT 24
Finished Aug 11 06:06:32 PM PDT 24
Peak memory 220024 kb
Host smart-bd844d7e-9e6c-4036-ba2b-6d531254395c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068234721 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1068234721
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4070191293
Short name T144
Test name
Test status
Simulation time 561660631 ps
CPU time 7.97 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:15 PM PDT 24
Peak memory 214440 kb
Host smart-5171aba4-55ab-4c76-a6c9-9a0ae9d999cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070191293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4070191293
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2955146538
Short name T43
Test name
Test status
Simulation time 341576659 ps
CPU time 4.63 seconds
Started Aug 11 06:06:01 PM PDT 24
Finished Aug 11 06:06:05 PM PDT 24
Peak memory 214352 kb
Host smart-e2914733-abca-4d37-9f13-44cd76b93b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955146538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2955146538
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.448709646
Short name T126
Test name
Test status
Simulation time 587727171 ps
CPU time 6.63 seconds
Started Aug 11 05:57:18 PM PDT 24
Finished Aug 11 05:57:25 PM PDT 24
Peak memory 214556 kb
Host smart-ff80a788-765a-44f4-acfc-b4749b53b639
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448709646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.448709646
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.698021421
Short name T28
Test name
Test status
Simulation time 39663720 ps
CPU time 2.76 seconds
Started Aug 11 06:05:41 PM PDT 24
Finished Aug 11 06:05:44 PM PDT 24
Peak memory 221668 kb
Host smart-2ffa6d01-9763-44a5-8944-23d2065afb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698021421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.698021421
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.511545849
Short name T8
Test name
Test status
Simulation time 311233266 ps
CPU time 4.21 seconds
Started Aug 11 06:04:49 PM PDT 24
Finished Aug 11 06:04:54 PM PDT 24
Peak memory 210392 kb
Host smart-0ccc4883-c7ea-43cd-b034-14e25cefe9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511545849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.511545849
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1526248162
Short name T57
Test name
Test status
Simulation time 768766606 ps
CPU time 15.31 seconds
Started Aug 11 06:06:44 PM PDT 24
Finished Aug 11 06:06:59 PM PDT 24
Peak memory 222616 kb
Host smart-dd1e9b70-2858-40f9-8001-631b5b40ca0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526248162 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1526248162
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4124080380
Short name T155
Test name
Test status
Simulation time 1108114847 ps
CPU time 32.42 seconds
Started Aug 11 06:06:29 PM PDT 24
Finished Aug 11 06:07:01 PM PDT 24
Peak memory 214204 kb
Host smart-64a81d21-ac4c-40ff-9ff7-a9f7a50fc43b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124080380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4124080380
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3901049226
Short name T1
Test name
Test status
Simulation time 308179259 ps
CPU time 2.16 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:45 PM PDT 24
Peak memory 214248 kb
Host smart-5d3f427b-fafe-4f89-a74c-ece0c43af675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901049226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3901049226
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1216473503
Short name T285
Test name
Test status
Simulation time 5909308716 ps
CPU time 78.43 seconds
Started Aug 11 06:06:13 PM PDT 24
Finished Aug 11 06:07:31 PM PDT 24
Peak memory 215912 kb
Host smart-38f88400-e374-4915-90f3-5bf2bf5c35d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216473503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1216473503
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1011421218
Short name T45
Test name
Test status
Simulation time 8956429037 ps
CPU time 46.58 seconds
Started Aug 11 06:04:49 PM PDT 24
Finished Aug 11 06:05:35 PM PDT 24
Peak memory 216476 kb
Host smart-c89d7526-a851-46fa-adac-8cd7051d6cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011421218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1011421218
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2740975589
Short name T20
Test name
Test status
Simulation time 125985658 ps
CPU time 5.7 seconds
Started Aug 11 06:07:06 PM PDT 24
Finished Aug 11 06:07:12 PM PDT 24
Peak memory 222344 kb
Host smart-0bbb17ca-6bf8-4230-b066-20c29f894b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740975589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2740975589
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.152274470
Short name T313
Test name
Test status
Simulation time 924519012 ps
CPU time 12.92 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:05:35 PM PDT 24
Peak memory 215076 kb
Host smart-e1683cde-b42e-4b01-8205-6acaab755ebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152274470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.152274470
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3217010365
Short name T34
Test name
Test status
Simulation time 265890508 ps
CPU time 2.9 seconds
Started Aug 11 06:05:53 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 209616 kb
Host smart-1760bc05-aad7-4d7a-850a-6c2fbe60d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217010365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3217010365
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1728101539
Short name T7
Test name
Test status
Simulation time 5171554526 ps
CPU time 154.18 seconds
Started Aug 11 06:04:11 PM PDT 24
Finished Aug 11 06:06:46 PM PDT 24
Peak memory 221940 kb
Host smart-cf6a4e0b-e873-4ad8-9b97-b105e33ad94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728101539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1728101539
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.138487654
Short name T139
Test name
Test status
Simulation time 1084317302 ps
CPU time 15 seconds
Started Aug 11 06:05:47 PM PDT 24
Finished Aug 11 06:06:02 PM PDT 24
Peak memory 214840 kb
Host smart-8b56377f-0f9f-4e05-ae15-019d629aef6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138487654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.138487654
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3795470820
Short name T415
Test name
Test status
Simulation time 685438565 ps
CPU time 7.91 seconds
Started Aug 11 06:04:46 PM PDT 24
Finished Aug 11 06:04:54 PM PDT 24
Peak memory 214260 kb
Host smart-c6a1e5b4-b618-4a47-8487-10475428d5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795470820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3795470820
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.582549319
Short name T58
Test name
Test status
Simulation time 1068362661 ps
CPU time 15.68 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 215240 kb
Host smart-0008e0ce-3079-4e51-989f-0acab51d9ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582549319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.582549319
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1670789515
Short name T98
Test name
Test status
Simulation time 1649566794 ps
CPU time 38.22 seconds
Started Aug 11 06:05:45 PM PDT 24
Finished Aug 11 06:06:23 PM PDT 24
Peak memory 210608 kb
Host smart-43c700ea-57c9-4eaa-9597-be18f6c81eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670789515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1670789515
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3813703991
Short name T122
Test name
Test status
Simulation time 155185227 ps
CPU time 4.18 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:12 PM PDT 24
Peak memory 218728 kb
Host smart-f3f254c4-0b53-4d7b-a49d-42dd31861b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813703991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3813703991
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.355007641
Short name T183
Test name
Test status
Simulation time 77784143 ps
CPU time 3.71 seconds
Started Aug 11 06:05:51 PM PDT 24
Finished Aug 11 06:05:55 PM PDT 24
Peak memory 220352 kb
Host smart-0ede920a-6a13-4b18-b416-a910e6be5983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355007641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.355007641
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1881228397
Short name T29
Test name
Test status
Simulation time 180289254 ps
CPU time 3.5 seconds
Started Aug 11 06:04:29 PM PDT 24
Finished Aug 11 06:04:33 PM PDT 24
Peak memory 220396 kb
Host smart-f073ccba-e865-4248-88b8-98caf9f98852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881228397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1881228397
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3723388879
Short name T135
Test name
Test status
Simulation time 2048311767 ps
CPU time 26.03 seconds
Started Aug 11 06:06:35 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 222796 kb
Host smart-db80830a-2cc1-416d-bf07-905c60fce2f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723388879 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3723388879
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1886394755
Short name T351
Test name
Test status
Simulation time 66376755 ps
CPU time 4.88 seconds
Started Aug 11 06:05:42 PM PDT 24
Finished Aug 11 06:05:47 PM PDT 24
Peak memory 214872 kb
Host smart-dfdd890c-b140-46f3-b533-c68d09bdbba9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886394755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1886394755
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1089861633
Short name T223
Test name
Test status
Simulation time 4748316303 ps
CPU time 90.37 seconds
Started Aug 11 06:07:10 PM PDT 24
Finished Aug 11 06:08:41 PM PDT 24
Peak memory 217188 kb
Host smart-e1f5dd0d-d04d-4b1b-8374-e29be1eefff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089861633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1089861633
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2682688649
Short name T40
Test name
Test status
Simulation time 2257539834 ps
CPU time 24.17 seconds
Started Aug 11 06:04:51 PM PDT 24
Finished Aug 11 06:05:15 PM PDT 24
Peak memory 221156 kb
Host smart-13dc4710-7a81-469f-9c77-cbc6b145e9e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682688649 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2682688649
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.844194593
Short name T101
Test name
Test status
Simulation time 82062446 ps
CPU time 3.32 seconds
Started Aug 11 06:05:52 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 222432 kb
Host smart-f74fba9f-bb44-46c2-b8f0-f51e6c32c757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844194593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.844194593
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2673101
Short name T140
Test name
Test status
Simulation time 97591643 ps
CPU time 2.61 seconds
Started Aug 11 06:05:52 PM PDT 24
Finished Aug 11 06:05:54 PM PDT 24
Peak memory 214292 kb
Host smart-1d91c028-120b-4706-8026-110abdbee3ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2673101
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.688461124
Short name T309
Test name
Test status
Simulation time 232981597 ps
CPU time 11.14 seconds
Started Aug 11 06:06:40 PM PDT 24
Finished Aug 11 06:06:52 PM PDT 24
Peak memory 214400 kb
Host smart-e30b52a6-fbb2-433b-8c1d-686be0eff09b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688461124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.688461124
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.157952623
Short name T928
Test name
Test status
Simulation time 408798018 ps
CPU time 3.27 seconds
Started Aug 11 05:57:01 PM PDT 24
Finished Aug 11 05:57:05 PM PDT 24
Peak memory 214608 kb
Host smart-d7419e7c-b6e8-4069-aadf-bc5035d8011c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157952623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.157952623
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.395719083
Short name T456
Test name
Test status
Simulation time 21295553 ps
CPU time 0.82 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:23 PM PDT 24
Peak memory 205880 kb
Host smart-131ebc74-7b3b-4275-abab-fb136e794d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395719083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.395719083
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1922177593
Short name T25
Test name
Test status
Simulation time 710946657 ps
CPU time 20.01 seconds
Started Aug 11 06:06:20 PM PDT 24
Finished Aug 11 06:06:40 PM PDT 24
Peak memory 221688 kb
Host smart-5bcb200c-1890-424c-bb7a-65c8ce0a16c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922177593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1922177593
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.68070804
Short name T66
Test name
Test status
Simulation time 1390411424 ps
CPU time 22.91 seconds
Started Aug 11 06:04:38 PM PDT 24
Finished Aug 11 06:05:01 PM PDT 24
Peak memory 222496 kb
Host smart-db3e8636-8a1b-4223-b345-13d41a88610c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68070804 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.68070804
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.4289150394
Short name T256
Test name
Test status
Simulation time 69357372 ps
CPU time 2.89 seconds
Started Aug 11 06:05:08 PM PDT 24
Finished Aug 11 06:05:11 PM PDT 24
Peak memory 222272 kb
Host smart-615f64ac-3f5b-4505-a802-daea0b3086c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289150394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4289150394
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2222404238
Short name T231
Test name
Test status
Simulation time 955890848 ps
CPU time 19.2 seconds
Started Aug 11 06:05:00 PM PDT 24
Finished Aug 11 06:05:19 PM PDT 24
Peak memory 220796 kb
Host smart-02a66bed-43ed-4419-8a4b-65df66397a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222404238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2222404238
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1379698111
Short name T180
Test name
Test status
Simulation time 1362538857 ps
CPU time 10.85 seconds
Started Aug 11 05:55:57 PM PDT 24
Finished Aug 11 05:56:08 PM PDT 24
Peak memory 214224 kb
Host smart-0978234a-39e1-4efb-af1c-fad8f139b233
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379698111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1379698111
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3788240872
Short name T212
Test name
Test status
Simulation time 10943441082 ps
CPU time 61.24 seconds
Started Aug 11 06:06:23 PM PDT 24
Finished Aug 11 06:07:25 PM PDT 24
Peak memory 208096 kb
Host smart-4ff71011-fb0e-4d09-a2f6-47278a80da4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788240872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3788240872
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2758650482
Short name T289
Test name
Test status
Simulation time 560727656 ps
CPU time 4.8 seconds
Started Aug 11 06:04:36 PM PDT 24
Finished Aug 11 06:04:41 PM PDT 24
Peak memory 222428 kb
Host smart-cbedee95-34e1-46f3-b335-b09db904d245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758650482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2758650482
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3401386766
Short name T123
Test name
Test status
Simulation time 100228599 ps
CPU time 4.41 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:21 PM PDT 24
Peak memory 217580 kb
Host smart-59b2e749-35f7-4bd5-9399-f8f6584f3072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401386766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3401386766
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1972510462
Short name T370
Test name
Test status
Simulation time 95835056 ps
CPU time 5.77 seconds
Started Aug 11 06:05:30 PM PDT 24
Finished Aug 11 06:05:35 PM PDT 24
Peak memory 214472 kb
Host smart-02385317-a6b0-41d6-8be1-e36ba031c6b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972510462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1972510462
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1024309739
Short name T108
Test name
Test status
Simulation time 475490284 ps
CPU time 13.53 seconds
Started Aug 11 06:04:27 PM PDT 24
Finished Aug 11 06:04:40 PM PDT 24
Peak memory 219640 kb
Host smart-2e2d4b0a-37e9-4257-a029-03e88b6addc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024309739 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1024309739
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3737373245
Short name T147
Test name
Test status
Simulation time 242183058 ps
CPU time 3.26 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:37 PM PDT 24
Peak memory 222472 kb
Host smart-23787a8f-85bd-43f6-83b3-9277917d6c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737373245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3737373245
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4284560624
Short name T159
Test name
Test status
Simulation time 276965269 ps
CPU time 11.09 seconds
Started Aug 11 05:55:30 PM PDT 24
Finished Aug 11 05:55:41 PM PDT 24
Peak memory 214272 kb
Host smart-e7850599-49e1-4b03-9752-13ef7ab00a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284560624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4284560624
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1288001626
Short name T175
Test name
Test status
Simulation time 54177739 ps
CPU time 2.92 seconds
Started Aug 11 05:57:00 PM PDT 24
Finished Aug 11 05:57:03 PM PDT 24
Peak memory 206052 kb
Host smart-baa73b2c-0c84-4d3b-91b7-97cac26b2463
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288001626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1288001626
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2195907713
Short name T321
Test name
Test status
Simulation time 121242170 ps
CPU time 2.38 seconds
Started Aug 11 06:04:32 PM PDT 24
Finished Aug 11 06:04:34 PM PDT 24
Peak memory 220816 kb
Host smart-27d508cc-611c-427a-b4ac-b84b8421d7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195907713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2195907713
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3642859000
Short name T583
Test name
Test status
Simulation time 131804770 ps
CPU time 2.68 seconds
Started Aug 11 06:06:09 PM PDT 24
Finished Aug 11 06:06:12 PM PDT 24
Peak memory 214456 kb
Host smart-aad4a001-b54f-4494-91b8-a2acd2fccb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642859000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3642859000
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2540455261
Short name T90
Test name
Test status
Simulation time 387806688 ps
CPU time 4.1 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:22 PM PDT 24
Peak memory 222472 kb
Host smart-82f54972-60b7-4aa7-9530-7a92f713c139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540455261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2540455261
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2088490638
Short name T121
Test name
Test status
Simulation time 32367821 ps
CPU time 1.8 seconds
Started Aug 11 06:06:33 PM PDT 24
Finished Aug 11 06:06:35 PM PDT 24
Peak memory 215272 kb
Host smart-fbaf216c-3fac-4304-90ef-122cb1132bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088490638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2088490638
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.919693973
Short name T59
Test name
Test status
Simulation time 129967119 ps
CPU time 2.61 seconds
Started Aug 11 06:06:53 PM PDT 24
Finished Aug 11 06:06:55 PM PDT 24
Peak memory 210124 kb
Host smart-65fa8000-e924-4a76-b42a-9260953dee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919693973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.919693973
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1091829997
Short name T166
Test name
Test status
Simulation time 1393667117 ps
CPU time 11.24 seconds
Started Aug 11 05:56:21 PM PDT 24
Finished Aug 11 05:56:32 PM PDT 24
Peak memory 214348 kb
Host smart-17af1f2f-f341-48c0-a59f-f56c008ee56b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091829997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1091829997
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3447106257
Short name T171
Test name
Test status
Simulation time 93920532 ps
CPU time 5.31 seconds
Started Aug 11 05:56:33 PM PDT 24
Finished Aug 11 05:56:39 PM PDT 24
Peak memory 214236 kb
Host smart-a6aff3e7-cdf6-40ed-b6fa-a5bb893f2735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447106257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3447106257
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1300306011
Short name T169
Test name
Test status
Simulation time 303055242 ps
CPU time 6.53 seconds
Started Aug 11 05:56:40 PM PDT 24
Finished Aug 11 05:56:47 PM PDT 24
Peak memory 214256 kb
Host smart-e6bd98ae-8af9-4705-a372-e4aa616e5c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300306011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1300306011
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3408704291
Short name T15
Test name
Test status
Simulation time 198637387 ps
CPU time 3.57 seconds
Started Aug 11 06:05:13 PM PDT 24
Finished Aug 11 06:05:17 PM PDT 24
Peak memory 214416 kb
Host smart-51766e1b-66e1-42d2-9afb-b923a57084d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408704291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3408704291
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1885638419
Short name T383
Test name
Test status
Simulation time 110963016 ps
CPU time 4.66 seconds
Started Aug 11 06:05:45 PM PDT 24
Finished Aug 11 06:05:50 PM PDT 24
Peak memory 215236 kb
Host smart-f8f4a30c-84b1-4810-850a-2d471f8ffb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885638419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1885638419
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1805761759
Short name T369
Test name
Test status
Simulation time 138183100 ps
CPU time 2.98 seconds
Started Aug 11 06:05:55 PM PDT 24
Finished Aug 11 06:05:58 PM PDT 24
Peak memory 215200 kb
Host smart-8e74b5bf-bdf5-4dce-9643-bad3843e8e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805761759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1805761759
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3940698066
Short name T286
Test name
Test status
Simulation time 496071282 ps
CPU time 5.85 seconds
Started Aug 11 06:05:56 PM PDT 24
Finished Aug 11 06:06:02 PM PDT 24
Peak memory 218416 kb
Host smart-1efea8eb-5db3-4ea3-adfb-090e86430d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940698066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3940698066
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.374764197
Short name T227
Test name
Test status
Simulation time 819143480 ps
CPU time 41.2 seconds
Started Aug 11 06:06:33 PM PDT 24
Finished Aug 11 06:07:15 PM PDT 24
Peak memory 217080 kb
Host smart-b2088d49-d4d8-48d6-ba59-ff28d4c83d31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374764197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.374764197
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2638408681
Short name T411
Test name
Test status
Simulation time 125944395 ps
CPU time 6.08 seconds
Started Aug 11 06:06:44 PM PDT 24
Finished Aug 11 06:06:50 PM PDT 24
Peak memory 215740 kb
Host smart-99a2aecb-c9b2-4bcc-a760-73ffdb44d157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638408681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2638408681
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3825086832
Short name T148
Test name
Test status
Simulation time 797724064 ps
CPU time 39.36 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:37 PM PDT 24
Peak memory 214512 kb
Host smart-dece1143-18e2-4624-8fe3-7a8c073ec5ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825086832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3825086832
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3402649268
Short name T94
Test name
Test status
Simulation time 100895615 ps
CPU time 4.78 seconds
Started Aug 11 06:05:41 PM PDT 24
Finished Aug 11 06:05:46 PM PDT 24
Peak memory 208888 kb
Host smart-93b77af0-91a5-4de9-9f7a-4c80441e868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402649268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3402649268
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3626931820
Short name T177
Test name
Test status
Simulation time 84122544 ps
CPU time 3.01 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:06:49 PM PDT 24
Peak memory 210320 kb
Host smart-1e43e455-a316-4302-b414-59fd16a31834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626931820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3626931820
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3664472123
Short name T124
Test name
Test status
Simulation time 651764327 ps
CPU time 3.37 seconds
Started Aug 11 06:07:27 PM PDT 24
Finished Aug 11 06:07:30 PM PDT 24
Peak memory 217104 kb
Host smart-dfaa6821-ce45-47ca-846f-a21f623775e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664472123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3664472123
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3967464541
Short name T272
Test name
Test status
Simulation time 445755470 ps
CPU time 4.63 seconds
Started Aug 11 06:05:16 PM PDT 24
Finished Aug 11 06:05:20 PM PDT 24
Peak memory 214964 kb
Host smart-99ef5545-ecfe-44f2-b220-b9f0a54c755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967464541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3967464541
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_random.2824076654
Short name T378
Test name
Test status
Simulation time 310218454 ps
CPU time 5.16 seconds
Started Aug 11 06:05:17 PM PDT 24
Finished Aug 11 06:05:23 PM PDT 24
Peak memory 214280 kb
Host smart-524bc5c7-fe06-437f-855a-3d0a29c80013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824076654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2824076654
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_random.801270177
Short name T365
Test name
Test status
Simulation time 26988119290 ps
CPU time 62.5 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:06:24 PM PDT 24
Peak memory 221812 kb
Host smart-a05d3a12-7834-4f5d-9b93-c85d47ac1a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801270177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.801270177
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3318812240
Short name T501
Test name
Test status
Simulation time 70305211 ps
CPU time 3.63 seconds
Started Aug 11 06:05:49 PM PDT 24
Finished Aug 11 06:05:53 PM PDT 24
Peak memory 208640 kb
Host smart-cc23e0c2-8a10-4286-b548-94e8c28504ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318812240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3318812240
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.420868501
Short name T329
Test name
Test status
Simulation time 2481409425 ps
CPU time 23.1 seconds
Started Aug 11 06:06:53 PM PDT 24
Finished Aug 11 06:07:17 PM PDT 24
Peak memory 215728 kb
Host smart-4d51fbf5-7aa3-4dfa-b47d-cc2e2ae7853f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420868501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.420868501
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3062619157
Short name T337
Test name
Test status
Simulation time 122871210 ps
CPU time 4.36 seconds
Started Aug 11 06:04:36 PM PDT 24
Finished Aug 11 06:04:41 PM PDT 24
Peak memory 215444 kb
Host smart-36bc24c4-3c21-44ad-beba-f26de72b2e56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3062619157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3062619157
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.939996709
Short name T252
Test name
Test status
Simulation time 71039135 ps
CPU time 2.65 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:01 PM PDT 24
Peak memory 214152 kb
Host smart-712f9afb-576c-4d55-ad2b-7e7f93bb4e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939996709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.939996709
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.758685211
Short name T357
Test name
Test status
Simulation time 41363085672 ps
CPU time 82.35 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:08:36 PM PDT 24
Peak memory 216584 kb
Host smart-2c59d255-290d-4471-a10c-f20d26891eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758685211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.758685211
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3358319043
Short name T217
Test name
Test status
Simulation time 106574076 ps
CPU time 4.79 seconds
Started Aug 11 06:07:16 PM PDT 24
Finished Aug 11 06:07:21 PM PDT 24
Peak memory 209672 kb
Host smart-cb5e4aac-a136-4a11-af1e-5871a1979c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358319043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3358319043
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1210179286
Short name T240
Test name
Test status
Simulation time 18674070581 ps
CPU time 96.12 seconds
Started Aug 11 06:07:21 PM PDT 24
Finished Aug 11 06:08:57 PM PDT 24
Peak memory 222584 kb
Host smart-e8b7319f-0f9d-49bc-84d1-5103121bb07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210179286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1210179286
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3008857376
Short name T160
Test name
Test status
Simulation time 884040512 ps
CPU time 8.7 seconds
Started Aug 11 05:56:59 PM PDT 24
Finished Aug 11 05:57:07 PM PDT 24
Peak memory 214196 kb
Host smart-b7838d9b-27d9-42a5-b2f1-0cbb61116a18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008857376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3008857376
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4089141898
Short name T163
Test name
Test status
Simulation time 116056223 ps
CPU time 3.49 seconds
Started Aug 11 05:57:08 PM PDT 24
Finished Aug 11 05:57:12 PM PDT 24
Peak memory 214280 kb
Host smart-c0ee857e-02b2-45d3-bbaf-6bc5afdf29e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089141898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.4089141898
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1125718037
Short name T174
Test name
Test status
Simulation time 531152203 ps
CPU time 2.61 seconds
Started Aug 11 05:57:09 PM PDT 24
Finished Aug 11 05:57:12 PM PDT 24
Peak memory 214216 kb
Host smart-2606a8e7-0c05-4eb5-bd99-c061f4c6e99b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125718037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1125718037
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3723147585
Short name T181
Test name
Test status
Simulation time 53882905 ps
CPU time 1.63 seconds
Started Aug 11 06:05:08 PM PDT 24
Finished Aug 11 06:05:10 PM PDT 24
Peak memory 209556 kb
Host smart-b649cafb-ab72-435a-86c2-20a14a7f7760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723147585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3723147585
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2222031628
Short name T363
Test name
Test status
Simulation time 113123086 ps
CPU time 2.05 seconds
Started Aug 11 06:06:26 PM PDT 24
Finished Aug 11 06:06:28 PM PDT 24
Peak memory 221412 kb
Host smart-6fef800e-e422-4995-b5db-64d88e2fdd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222031628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2222031628
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.492672938
Short name T64
Test name
Test status
Simulation time 58375350 ps
CPU time 3.9 seconds
Started Aug 11 06:05:31 PM PDT 24
Finished Aug 11 06:05:35 PM PDT 24
Peak memory 222564 kb
Host smart-8ba9f114-8e14-46c6-bd36-9b2736e83cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492672938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.492672938
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1184691864
Short name T125
Test name
Test status
Simulation time 42199473 ps
CPU time 2.34 seconds
Started Aug 11 06:05:00 PM PDT 24
Finished Aug 11 06:05:02 PM PDT 24
Peak memory 217040 kb
Host smart-3e8bf9ba-c28e-48be-8d88-914b49805625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184691864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1184691864
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.691372626
Short name T36
Test name
Test status
Simulation time 59586784 ps
CPU time 4.1 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:26 PM PDT 24
Peak memory 214292 kb
Host smart-a594f9e1-7dcf-43f6-8704-e2bc0882ae83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691372626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.691372626
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.711798953
Short name T659
Test name
Test status
Simulation time 165699676 ps
CPU time 1.86 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:25 PM PDT 24
Peak memory 210192 kb
Host smart-693b1327-2b8c-4612-ba07-3e543eb2a76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711798953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.711798953
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.4091329813
Short name T107
Test name
Test status
Simulation time 94254854 ps
CPU time 3.05 seconds
Started Aug 11 06:05:11 PM PDT 24
Finished Aug 11 06:05:15 PM PDT 24
Peak memory 217728 kb
Host smart-a285fae0-9197-4dc4-bed8-ea2a43ce7b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091329813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4091329813
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3804670841
Short name T49
Test name
Test status
Simulation time 347275418 ps
CPU time 2.79 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:17 PM PDT 24
Peak memory 214324 kb
Host smart-f6ba3dc2-8019-48bf-9b76-be68880999e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804670841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3804670841
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.840586520
Short name T586
Test name
Test status
Simulation time 199867752 ps
CPU time 2.55 seconds
Started Aug 11 06:05:23 PM PDT 24
Finished Aug 11 06:05:25 PM PDT 24
Peak memory 208780 kb
Host smart-65d5f3e9-6908-4f65-9a4d-0870d1868e7b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840586520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.840586520
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1560146188
Short name T418
Test name
Test status
Simulation time 178114382 ps
CPU time 5.18 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:05:27 PM PDT 24
Peak memory 215056 kb
Host smart-b39cdcab-a7af-46c0-8781-bb797c1ee69a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560146188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1560146188
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.4231659129
Short name T243
Test name
Test status
Simulation time 64323347 ps
CPU time 2.56 seconds
Started Aug 11 06:05:36 PM PDT 24
Finished Aug 11 06:05:39 PM PDT 24
Peak memory 215296 kb
Host smart-de9a6c59-2807-44f9-9ee7-3de6b2c0641b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231659129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.4231659129
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3624186911
Short name T333
Test name
Test status
Simulation time 69557352 ps
CPU time 2.71 seconds
Started Aug 11 06:04:24 PM PDT 24
Finished Aug 11 06:04:27 PM PDT 24
Peak memory 214368 kb
Host smart-372b7ba6-bfa0-4947-8c34-f9580e4bff6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624186911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3624186911
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1570952862
Short name T225
Test name
Test status
Simulation time 80066514 ps
CPU time 2.63 seconds
Started Aug 11 06:05:42 PM PDT 24
Finished Aug 11 06:05:45 PM PDT 24
Peak memory 214288 kb
Host smart-e3a3f9ee-a53a-44e4-b82f-71c708f0d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570952862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1570952862
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.888520098
Short name T232
Test name
Test status
Simulation time 6443278621 ps
CPU time 31.32 seconds
Started Aug 11 06:06:31 PM PDT 24
Finished Aug 11 06:07:03 PM PDT 24
Peak memory 214572 kb
Host smart-6eeed096-f9ce-48f4-b290-f65e2f704eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888520098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.888520098
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1078840746
Short name T325
Test name
Test status
Simulation time 242054767 ps
CPU time 6.3 seconds
Started Aug 11 06:06:41 PM PDT 24
Finished Aug 11 06:06:48 PM PDT 24
Peak memory 210300 kb
Host smart-79acf041-33d0-4950-aff9-122c97a803c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078840746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1078840746
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3550412923
Short name T247
Test name
Test status
Simulation time 547386982 ps
CPU time 7.36 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:06 PM PDT 24
Peak memory 214520 kb
Host smart-1732bb2e-c484-474f-92ac-d5ba586802ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3550412923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3550412923
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.528136119
Short name T233
Test name
Test status
Simulation time 2534410678 ps
CPU time 49.46 seconds
Started Aug 11 06:04:42 PM PDT 24
Finished Aug 11 06:05:32 PM PDT 24
Peak memory 222508 kb
Host smart-1108ba8c-82db-4e35-a909-7d7059e8534e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528136119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.528136119
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1591021091
Short name T150
Test name
Test status
Simulation time 89338699 ps
CPU time 3.69 seconds
Started Aug 11 05:55:43 PM PDT 24
Finished Aug 11 05:55:46 PM PDT 24
Peak memory 206136 kb
Host smart-eca84c53-4c2e-4cd4-be12-7c56dcc3b380
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591021091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
591021091
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4202517144
Short name T158
Test name
Test status
Simulation time 3885163688 ps
CPU time 15.23 seconds
Started Aug 11 05:55:41 PM PDT 24
Finished Aug 11 05:55:57 PM PDT 24
Peak memory 206116 kb
Host smart-a7a5b4e4-88c2-427d-b59d-2b28ed7531de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202517144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4
202517144
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1995693160
Short name T162
Test name
Test status
Simulation time 15860861 ps
CPU time 1 seconds
Started Aug 11 05:55:40 PM PDT 24
Finished Aug 11 05:55:41 PM PDT 24
Peak memory 206088 kb
Host smart-1bc05b83-05af-4a9f-9b7c-2156da46f39e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995693160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
995693160
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1606969410
Short name T984
Test name
Test status
Simulation time 38548006 ps
CPU time 1.3 seconds
Started Aug 11 05:55:48 PM PDT 24
Finished Aug 11 05:55:50 PM PDT 24
Peak memory 214348 kb
Host smart-acb47f98-bf80-40ea-8f48-1ea65e1957fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606969410 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1606969410
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2574422808
Short name T1078
Test name
Test status
Simulation time 34093660 ps
CPU time 1.64 seconds
Started Aug 11 05:55:40 PM PDT 24
Finished Aug 11 05:55:42 PM PDT 24
Peak memory 206152 kb
Host smart-d8eb3521-339a-45d4-b956-97d61d1b50c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574422808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2574422808
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4110052708
Short name T956
Test name
Test status
Simulation time 15781591 ps
CPU time 0.8 seconds
Started Aug 11 05:55:31 PM PDT 24
Finished Aug 11 05:55:32 PM PDT 24
Peak memory 205888 kb
Host smart-e10e400a-78bd-42e5-b3cc-2db40c78a262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110052708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.4110052708
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3283353683
Short name T154
Test name
Test status
Simulation time 67432164 ps
CPU time 2.31 seconds
Started Aug 11 05:55:48 PM PDT 24
Finished Aug 11 05:55:51 PM PDT 24
Peak memory 206164 kb
Host smart-94fd8d38-533e-48ee-b906-b37e52931e6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283353683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3283353683
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2079968778
Short name T981
Test name
Test status
Simulation time 55968446 ps
CPU time 1.57 seconds
Started Aug 11 05:55:20 PM PDT 24
Finished Aug 11 05:55:22 PM PDT 24
Peak memory 214628 kb
Host smart-2136da04-48db-42a9-85d6-420028ec9f4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079968778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2079968778
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1450309993
Short name T1057
Test name
Test status
Simulation time 2041516548 ps
CPU time 13.16 seconds
Started Aug 11 05:55:18 PM PDT 24
Finished Aug 11 05:55:31 PM PDT 24
Peak memory 220576 kb
Host smart-6a25970e-14cc-4634-a717-3e58f46fd46b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450309993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1450309993
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.803427085
Short name T1033
Test name
Test status
Simulation time 180500501 ps
CPU time 2.71 seconds
Started Aug 11 05:55:24 PM PDT 24
Finished Aug 11 05:55:27 PM PDT 24
Peak memory 214408 kb
Host smart-c5cd05f5-5a19-4f83-bc94-158d5cb3323d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803427085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.803427085
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1237541017
Short name T933
Test name
Test status
Simulation time 387351340 ps
CPU time 11.45 seconds
Started Aug 11 05:56:09 PM PDT 24
Finished Aug 11 05:56:20 PM PDT 24
Peak memory 206136 kb
Host smart-c430a190-f57c-4844-80fd-05a5fcc9b7eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237541017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
237541017
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4201047012
Short name T989
Test name
Test status
Simulation time 1341511948 ps
CPU time 16.75 seconds
Started Aug 11 05:56:03 PM PDT 24
Finished Aug 11 05:56:20 PM PDT 24
Peak memory 206116 kb
Host smart-55b4ecdf-b5b1-4e62-afc2-9f56fcfcfbea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201047012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4
201047012
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4209862052
Short name T1025
Test name
Test status
Simulation time 59856938 ps
CPU time 0.91 seconds
Started Aug 11 05:56:04 PM PDT 24
Finished Aug 11 05:56:05 PM PDT 24
Peak memory 205984 kb
Host smart-e5cfcf94-f2cc-4894-8899-ea51220c2f99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209862052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.4
209862052
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1153694209
Short name T987
Test name
Test status
Simulation time 35090960 ps
CPU time 1.86 seconds
Started Aug 11 05:56:08 PM PDT 24
Finished Aug 11 05:56:10 PM PDT 24
Peak memory 214428 kb
Host smart-e0a8b1c2-f867-4de1-b573-3770f73d895c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153694209 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1153694209
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3554962636
Short name T1076
Test name
Test status
Simulation time 11818948 ps
CPU time 0.87 seconds
Started Aug 11 05:56:02 PM PDT 24
Finished Aug 11 05:56:03 PM PDT 24
Peak memory 205940 kb
Host smart-d3b93d7d-a3e4-48ff-ac29-a5179f584cd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554962636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3554962636
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3173942606
Short name T980
Test name
Test status
Simulation time 10934657 ps
CPU time 0.89 seconds
Started Aug 11 05:56:01 PM PDT 24
Finished Aug 11 05:56:02 PM PDT 24
Peak memory 205924 kb
Host smart-4cd9ae8e-0bff-4ab3-aa29-67b5a8f2b555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173942606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3173942606
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1034806451
Short name T1015
Test name
Test status
Simulation time 21312545 ps
CPU time 1.67 seconds
Started Aug 11 05:56:07 PM PDT 24
Finished Aug 11 05:56:09 PM PDT 24
Peak memory 206048 kb
Host smart-ab83f299-061b-4804-9cf8-831c87fbf13d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034806451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1034806451
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3914892168
Short name T946
Test name
Test status
Simulation time 117809636 ps
CPU time 3.47 seconds
Started Aug 11 05:55:45 PM PDT 24
Finished Aug 11 05:55:49 PM PDT 24
Peak memory 214592 kb
Host smart-0b640507-9f88-4825-8a1f-10b54d671de1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914892168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3914892168
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2717522224
Short name T977
Test name
Test status
Simulation time 181193876 ps
CPU time 6.91 seconds
Started Aug 11 05:55:51 PM PDT 24
Finished Aug 11 05:55:58 PM PDT 24
Peak memory 214624 kb
Host smart-b970a020-10e4-448c-8645-41076a2ea04f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717522224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2717522224
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4049108382
Short name T983
Test name
Test status
Simulation time 300244364 ps
CPU time 1.92 seconds
Started Aug 11 05:55:59 PM PDT 24
Finished Aug 11 05:56:01 PM PDT 24
Peak memory 214320 kb
Host smart-aa36491f-328f-4f62-8afb-5e659e9a4462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049108382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4049108382
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2107030456
Short name T942
Test name
Test status
Simulation time 31201332 ps
CPU time 2.22 seconds
Started Aug 11 05:56:57 PM PDT 24
Finished Aug 11 05:56:59 PM PDT 24
Peak memory 214328 kb
Host smart-b258f3b9-4b27-40cc-bc50-a723566e0e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107030456 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2107030456
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3717697942
Short name T151
Test name
Test status
Simulation time 25860816 ps
CPU time 0.91 seconds
Started Aug 11 05:56:58 PM PDT 24
Finished Aug 11 05:56:59 PM PDT 24
Peak memory 206100 kb
Host smart-f4076563-b8f5-4ac9-a229-3748fec56b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717697942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3717697942
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.657544992
Short name T974
Test name
Test status
Simulation time 36119193 ps
CPU time 0.72 seconds
Started Aug 11 05:56:54 PM PDT 24
Finished Aug 11 05:56:55 PM PDT 24
Peak memory 205812 kb
Host smart-e3e1a8ff-dc57-4985-9a5e-8478bda2f794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657544992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.657544992
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3496750039
Short name T947
Test name
Test status
Simulation time 102170730 ps
CPU time 2.69 seconds
Started Aug 11 05:56:58 PM PDT 24
Finished Aug 11 05:57:01 PM PDT 24
Peak memory 206080 kb
Host smart-5a1cfe01-bd7d-492b-83d3-8544deffbb83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496750039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3496750039
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1823623693
Short name T949
Test name
Test status
Simulation time 57260875 ps
CPU time 2.2 seconds
Started Aug 11 05:56:56 PM PDT 24
Finished Aug 11 05:56:58 PM PDT 24
Peak memory 214560 kb
Host smart-698d6a18-b35b-4c68-89c6-1bc9f2f30063
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823623693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1823623693
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2731554326
Short name T131
Test name
Test status
Simulation time 559537472 ps
CPU time 10.74 seconds
Started Aug 11 05:56:57 PM PDT 24
Finished Aug 11 05:57:08 PM PDT 24
Peak memory 214624 kb
Host smart-0cc88395-592d-4518-bffb-a2304f3241bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731554326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2731554326
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1899003297
Short name T1014
Test name
Test status
Simulation time 692025430 ps
CPU time 3.82 seconds
Started Aug 11 05:56:56 PM PDT 24
Finished Aug 11 05:57:00 PM PDT 24
Peak memory 214412 kb
Host smart-5bfc3404-e13b-416f-a36c-6eceb7a92664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899003297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1899003297
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3920677744
Short name T188
Test name
Test status
Simulation time 250687281 ps
CPU time 2.06 seconds
Started Aug 11 05:57:01 PM PDT 24
Finished Aug 11 05:57:03 PM PDT 24
Peak memory 214464 kb
Host smart-da00a019-0f6d-44dd-9703-28453e8529ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920677744 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3920677744
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1702838791
Short name T1013
Test name
Test status
Simulation time 16222519 ps
CPU time 1.21 seconds
Started Aug 11 05:57:01 PM PDT 24
Finished Aug 11 05:57:03 PM PDT 24
Peak memory 206156 kb
Host smart-8173496d-c282-4368-9f7f-3215dac90b29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702838791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1702838791
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3472811281
Short name T957
Test name
Test status
Simulation time 20070648 ps
CPU time 0.73 seconds
Started Aug 11 05:57:03 PM PDT 24
Finished Aug 11 05:57:03 PM PDT 24
Peak memory 205852 kb
Host smart-c3d13dc1-a68a-4e4e-bbbc-45ac9f922ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472811281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3472811281
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2809514623
Short name T994
Test name
Test status
Simulation time 22043378 ps
CPU time 1.71 seconds
Started Aug 11 05:57:00 PM PDT 24
Finished Aug 11 05:57:02 PM PDT 24
Peak memory 206068 kb
Host smart-72d886a6-9b8d-4a05-b749-aa58dd629fc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809514623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2809514623
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2040894063
Short name T1045
Test name
Test status
Simulation time 532107654 ps
CPU time 2.02 seconds
Started Aug 11 05:56:56 PM PDT 24
Finished Aug 11 05:56:58 PM PDT 24
Peak memory 214588 kb
Host smart-b57ba633-980e-4f6d-a158-cbe765cfa027
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040894063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2040894063
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3090548424
Short name T1029
Test name
Test status
Simulation time 398861637 ps
CPU time 13.33 seconds
Started Aug 11 05:56:57 PM PDT 24
Finished Aug 11 05:57:11 PM PDT 24
Peak memory 220900 kb
Host smart-b25632a1-85a1-483c-a49f-a4b5cad233a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090548424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3090548424
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2751137680
Short name T1023
Test name
Test status
Simulation time 302672364 ps
CPU time 2.17 seconds
Started Aug 11 05:57:02 PM PDT 24
Finished Aug 11 05:57:04 PM PDT 24
Peak memory 214372 kb
Host smart-c6aeb920-0a1f-4747-95d5-800b2d706651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751137680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2751137680
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2944981942
Short name T393
Test name
Test status
Simulation time 941646238 ps
CPU time 8.77 seconds
Started Aug 11 05:57:02 PM PDT 24
Finished Aug 11 05:57:10 PM PDT 24
Peak memory 214192 kb
Host smart-fc066ce1-fc7c-4c2e-8def-57a090a74248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944981942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2944981942
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.10664984
Short name T1058
Test name
Test status
Simulation time 30145920 ps
CPU time 1.35 seconds
Started Aug 11 05:57:02 PM PDT 24
Finished Aug 11 05:57:03 PM PDT 24
Peak memory 214376 kb
Host smart-ac3f6366-549c-477e-863a-3c1fb06cf397
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10664984 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.10664984
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.659036003
Short name T972
Test name
Test status
Simulation time 14143009 ps
CPU time 1.01 seconds
Started Aug 11 05:57:00 PM PDT 24
Finished Aug 11 05:57:01 PM PDT 24
Peak memory 205972 kb
Host smart-d0948c8c-37d1-45e7-a0f9-bc283c65a47b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659036003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.659036003
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3080611668
Short name T959
Test name
Test status
Simulation time 10727053 ps
CPU time 0.75 seconds
Started Aug 11 05:57:02 PM PDT 24
Finished Aug 11 05:57:02 PM PDT 24
Peak memory 205792 kb
Host smart-dff78b24-1264-4c43-bcc5-f5d61602f25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080611668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3080611668
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.881197973
Short name T1069
Test name
Test status
Simulation time 25358967 ps
CPU time 1.39 seconds
Started Aug 11 05:57:02 PM PDT 24
Finished Aug 11 05:57:04 PM PDT 24
Peak memory 206008 kb
Host smart-8677e104-e8b4-47bf-ae66-6236b93e4cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881197973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.881197973
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1289151517
Short name T1024
Test name
Test status
Simulation time 650264876 ps
CPU time 5.24 seconds
Started Aug 11 05:57:00 PM PDT 24
Finished Aug 11 05:57:06 PM PDT 24
Peak memory 214648 kb
Host smart-e43daec5-29fd-4e67-8ee7-1766dadb702c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289151517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1289151517
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2204808905
Short name T939
Test name
Test status
Simulation time 266057352 ps
CPU time 2.63 seconds
Started Aug 11 05:57:02 PM PDT 24
Finished Aug 11 05:57:05 PM PDT 24
Peak memory 214260 kb
Host smart-06640f9c-3889-4c68-b29f-1cd198578fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204808905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2204808905
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1229544872
Short name T941
Test name
Test status
Simulation time 346183025 ps
CPU time 1.67 seconds
Started Aug 11 05:57:07 PM PDT 24
Finished Aug 11 05:57:08 PM PDT 24
Peak memory 214316 kb
Host smart-74324f9c-bff5-4ec1-8334-8a1ca2d91214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229544872 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1229544872
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4020759511
Short name T1000
Test name
Test status
Simulation time 73447548 ps
CPU time 1.06 seconds
Started Aug 11 05:57:07 PM PDT 24
Finished Aug 11 05:57:08 PM PDT 24
Peak memory 206136 kb
Host smart-7d92ddf2-c06b-4533-8e97-916583ca1002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020759511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4020759511
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3031647532
Short name T920
Test name
Test status
Simulation time 11232617 ps
CPU time 0.85 seconds
Started Aug 11 05:57:12 PM PDT 24
Finished Aug 11 05:57:12 PM PDT 24
Peak memory 205892 kb
Host smart-b937aae0-b2e5-4566-8a10-eb45e337a232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031647532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3031647532
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.505161802
Short name T152
Test name
Test status
Simulation time 119855596 ps
CPU time 2.92 seconds
Started Aug 11 05:57:07 PM PDT 24
Finished Aug 11 05:57:10 PM PDT 24
Peak memory 206072 kb
Host smart-3b7c6946-1123-4588-a5e2-8d11eeb738ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505161802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.505161802
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3278591307
Short name T1056
Test name
Test status
Simulation time 386217657 ps
CPU time 2.28 seconds
Started Aug 11 05:57:02 PM PDT 24
Finished Aug 11 05:57:04 PM PDT 24
Peak memory 214628 kb
Host smart-76b04410-20db-42ea-ba8c-05204d58e3a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278591307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3278591307
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2068623248
Short name T1021
Test name
Test status
Simulation time 422466029 ps
CPU time 14.72 seconds
Started Aug 11 05:57:07 PM PDT 24
Finished Aug 11 05:57:22 PM PDT 24
Peak memory 214616 kb
Host smart-b81f2a7e-80dc-4869-9acd-62d1cc0d19c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068623248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2068623248
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.780475629
Short name T991
Test name
Test status
Simulation time 336323849 ps
CPU time 2.97 seconds
Started Aug 11 05:57:08 PM PDT 24
Finished Aug 11 05:57:11 PM PDT 24
Peak memory 214284 kb
Host smart-4c368050-eb9a-4a59-bd29-17d276d8c5fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780475629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.780475629
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.766365300
Short name T1046
Test name
Test status
Simulation time 158192505 ps
CPU time 1.94 seconds
Started Aug 11 05:57:09 PM PDT 24
Finished Aug 11 05:57:11 PM PDT 24
Peak memory 214272 kb
Host smart-74b7722f-c8e1-44e8-9eea-6c55f2a228bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766365300 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.766365300
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3460593412
Short name T1073
Test name
Test status
Simulation time 32100748 ps
CPU time 1.22 seconds
Started Aug 11 05:57:12 PM PDT 24
Finished Aug 11 05:57:13 PM PDT 24
Peak memory 206208 kb
Host smart-3eb2943f-ad3a-483e-83c9-85ee265a68bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460593412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3460593412
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2321422249
Short name T1071
Test name
Test status
Simulation time 9276125 ps
CPU time 0.72 seconds
Started Aug 11 05:57:12 PM PDT 24
Finished Aug 11 05:57:12 PM PDT 24
Peak memory 205892 kb
Host smart-14ec2f88-cf42-4ba7-b23d-30c255c034e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321422249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2321422249
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2839091721
Short name T153
Test name
Test status
Simulation time 320935156 ps
CPU time 3.06 seconds
Started Aug 11 05:57:08 PM PDT 24
Finished Aug 11 05:57:11 PM PDT 24
Peak memory 206072 kb
Host smart-9b73c02d-abfa-4558-a2e9-2623204239bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839091721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2839091721
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1504397972
Short name T1037
Test name
Test status
Simulation time 661559805 ps
CPU time 1.68 seconds
Started Aug 11 05:57:11 PM PDT 24
Finished Aug 11 05:57:13 PM PDT 24
Peak memory 214684 kb
Host smart-91652545-90f0-4dfc-b77b-81263e84e172
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504397972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1504397972
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2418658241
Short name T1049
Test name
Test status
Simulation time 479373300 ps
CPU time 5.16 seconds
Started Aug 11 05:57:09 PM PDT 24
Finished Aug 11 05:57:14 PM PDT 24
Peak memory 214596 kb
Host smart-1cbf0ebf-bf6a-4ce4-903e-39aeeadddc18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418658241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2418658241
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1414868632
Short name T940
Test name
Test status
Simulation time 27938057 ps
CPU time 2.11 seconds
Started Aug 11 05:57:09 PM PDT 24
Finished Aug 11 05:57:11 PM PDT 24
Peak memory 217440 kb
Host smart-23170e76-29bf-4652-9ba0-b325449ce8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414868632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1414868632
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3365753387
Short name T1009
Test name
Test status
Simulation time 192420390 ps
CPU time 1.76 seconds
Started Aug 11 05:57:15 PM PDT 24
Finished Aug 11 05:57:17 PM PDT 24
Peak memory 214276 kb
Host smart-2e3a8111-a3cc-4c7b-b8c2-a007e4748d07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365753387 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3365753387
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2184315961
Short name T1038
Test name
Test status
Simulation time 14572976 ps
CPU time 1.07 seconds
Started Aug 11 05:57:17 PM PDT 24
Finished Aug 11 05:57:18 PM PDT 24
Peak memory 206040 kb
Host smart-c680b2e4-63c8-479b-b099-97984e63b82a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184315961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2184315961
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1279675776
Short name T924
Test name
Test status
Simulation time 28123482 ps
CPU time 0.78 seconds
Started Aug 11 05:57:14 PM PDT 24
Finished Aug 11 05:57:15 PM PDT 24
Peak memory 205840 kb
Host smart-09bd4696-1060-48e7-9b4b-60dd97f75afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279675776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1279675776
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3393521238
Short name T969
Test name
Test status
Simulation time 34025244 ps
CPU time 1.9 seconds
Started Aug 11 05:57:16 PM PDT 24
Finished Aug 11 05:57:18 PM PDT 24
Peak memory 206092 kb
Host smart-93ca3f80-d349-4572-a836-89d6669535e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393521238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3393521238
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2071194182
Short name T982
Test name
Test status
Simulation time 47120616 ps
CPU time 2.06 seconds
Started Aug 11 05:57:16 PM PDT 24
Finished Aug 11 05:57:18 PM PDT 24
Peak memory 214604 kb
Host smart-b06a1181-6bce-46bf-a3b6-daaf14c8b494
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071194182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2071194182
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3077041973
Short name T189
Test name
Test status
Simulation time 65720843 ps
CPU time 2.38 seconds
Started Aug 11 05:57:16 PM PDT 24
Finished Aug 11 05:57:19 PM PDT 24
Peak memory 214332 kb
Host smart-f2151247-f4d3-4731-8655-f7b28585a6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077041973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3077041973
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1982173767
Short name T164
Test name
Test status
Simulation time 416777239 ps
CPU time 4.86 seconds
Started Aug 11 05:57:15 PM PDT 24
Finished Aug 11 05:57:20 PM PDT 24
Peak memory 206100 kb
Host smart-35e5a677-eed1-413d-b28a-24c2f4eabb95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982173767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1982173767
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1674472725
Short name T963
Test name
Test status
Simulation time 58447257 ps
CPU time 2.02 seconds
Started Aug 11 05:57:21 PM PDT 24
Finished Aug 11 05:57:24 PM PDT 24
Peak memory 214356 kb
Host smart-ffb9a113-2685-4a9b-9702-b53a6f3b6494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674472725 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1674472725
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4029687802
Short name T1044
Test name
Test status
Simulation time 94962805 ps
CPU time 1.22 seconds
Started Aug 11 05:57:20 PM PDT 24
Finished Aug 11 05:57:21 PM PDT 24
Peak memory 205992 kb
Host smart-3c86a6a3-b4c9-47ea-8401-ac1081035227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029687802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4029687802
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2488970193
Short name T955
Test name
Test status
Simulation time 14176471 ps
CPU time 0.71 seconds
Started Aug 11 05:57:25 PM PDT 24
Finished Aug 11 05:57:25 PM PDT 24
Peak memory 205908 kb
Host smart-0732b499-6c23-4ffd-acf7-5c64622563b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488970193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2488970193
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.945730782
Short name T952
Test name
Test status
Simulation time 95023944 ps
CPU time 1.46 seconds
Started Aug 11 05:57:20 PM PDT 24
Finished Aug 11 05:57:22 PM PDT 24
Peak memory 206036 kb
Host smart-8aca18e6-856a-4e69-8957-c9412d31ab59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945730782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.945730782
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3135779843
Short name T129
Test name
Test status
Simulation time 231526956 ps
CPU time 1.96 seconds
Started Aug 11 05:57:16 PM PDT 24
Finished Aug 11 05:57:18 PM PDT 24
Peak memory 206648 kb
Host smart-7a2ea117-03fa-4b49-ad28-adfb54604f54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135779843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3135779843
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1837002060
Short name T1052
Test name
Test status
Simulation time 756710699 ps
CPU time 7.93 seconds
Started Aug 11 05:57:16 PM PDT 24
Finished Aug 11 05:57:24 PM PDT 24
Peak memory 214636 kb
Host smart-fb78f2ff-c57e-4664-ba91-8e57e76db9a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837002060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1837002060
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3916201740
Short name T187
Test name
Test status
Simulation time 337129285 ps
CPU time 2.31 seconds
Started Aug 11 05:57:18 PM PDT 24
Finished Aug 11 05:57:20 PM PDT 24
Peak memory 214440 kb
Host smart-40e99a59-9a26-4d25-b738-c0e97a1ed5a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916201740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3916201740
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1920669368
Short name T176
Test name
Test status
Simulation time 117820730 ps
CPU time 5.22 seconds
Started Aug 11 05:57:16 PM PDT 24
Finished Aug 11 05:57:21 PM PDT 24
Peak memory 214264 kb
Host smart-249a7f21-2ccf-49b5-8e4f-3f009d183343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920669368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1920669368
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.71713749
Short name T1030
Test name
Test status
Simulation time 32269609 ps
CPU time 1.96 seconds
Started Aug 11 05:57:21 PM PDT 24
Finished Aug 11 05:57:23 PM PDT 24
Peak memory 214324 kb
Host smart-d9b2fad3-2f00-4dbb-ba19-7465080b88ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71713749 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.71713749
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2179791247
Short name T961
Test name
Test status
Simulation time 137075044 ps
CPU time 1.15 seconds
Started Aug 11 05:57:23 PM PDT 24
Finished Aug 11 05:57:24 PM PDT 24
Peak memory 206024 kb
Host smart-ccbb19ca-8e9b-4f05-bd8d-8728c42e05a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179791247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2179791247
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1521683232
Short name T925
Test name
Test status
Simulation time 10922208 ps
CPU time 0.71 seconds
Started Aug 11 05:57:22 PM PDT 24
Finished Aug 11 05:57:22 PM PDT 24
Peak memory 205868 kb
Host smart-08735887-a39a-443f-b6d7-b89d54ead0b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521683232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1521683232
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1575316635
Short name T943
Test name
Test status
Simulation time 112949385 ps
CPU time 4.83 seconds
Started Aug 11 05:57:24 PM PDT 24
Finished Aug 11 05:57:29 PM PDT 24
Peak memory 206096 kb
Host smart-6c7a05c4-c035-411f-b836-ae8b9b84ddc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575316635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1575316635
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3960239317
Short name T1061
Test name
Test status
Simulation time 635399895 ps
CPU time 3.05 seconds
Started Aug 11 05:57:25 PM PDT 24
Finished Aug 11 05:57:28 PM PDT 24
Peak memory 214608 kb
Host smart-cded7fbc-1666-4d3b-a042-3e2efce670ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960239317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3960239317
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2867960558
Short name T1031
Test name
Test status
Simulation time 209124014 ps
CPU time 3.25 seconds
Started Aug 11 05:57:23 PM PDT 24
Finished Aug 11 05:57:27 PM PDT 24
Peak memory 220840 kb
Host smart-eaebc594-f50b-477a-a4ac-4a0ad06384b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867960558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2867960558
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3333513741
Short name T966
Test name
Test status
Simulation time 134750205 ps
CPU time 2.72 seconds
Started Aug 11 05:57:22 PM PDT 24
Finished Aug 11 05:57:25 PM PDT 24
Peak memory 216404 kb
Host smart-32d55ea4-fb2a-4f4f-911d-3b0af796ab71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333513741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3333513741
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1852910128
Short name T161
Test name
Test status
Simulation time 536309259 ps
CPU time 3.88 seconds
Started Aug 11 05:57:23 PM PDT 24
Finished Aug 11 05:57:27 PM PDT 24
Peak memory 214208 kb
Host smart-02e85dff-a33d-4b98-815f-57993354951c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852910128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1852910128
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.12025651
Short name T948
Test name
Test status
Simulation time 195026642 ps
CPU time 1.56 seconds
Started Aug 11 05:57:26 PM PDT 24
Finished Aug 11 05:57:27 PM PDT 24
Peak memory 214280 kb
Host smart-6a7d0d07-2ddd-4d4f-b489-4b39aedbb1eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12025651 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.12025651
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1160938260
Short name T1008
Test name
Test status
Simulation time 103993365 ps
CPU time 1.27 seconds
Started Aug 11 05:57:25 PM PDT 24
Finished Aug 11 05:57:26 PM PDT 24
Peak memory 206048 kb
Host smart-b22662a8-b967-447d-b356-df92e793c917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160938260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1160938260
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3582267259
Short name T1079
Test name
Test status
Simulation time 7909908 ps
CPU time 0.71 seconds
Started Aug 11 05:57:22 PM PDT 24
Finished Aug 11 05:57:23 PM PDT 24
Peak memory 205760 kb
Host smart-f74fd5f6-ab54-4ad4-9ac0-e8bbcecb90e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582267259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3582267259
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2699299037
Short name T999
Test name
Test status
Simulation time 91939758 ps
CPU time 1.63 seconds
Started Aug 11 05:57:25 PM PDT 24
Finished Aug 11 05:57:26 PM PDT 24
Peak memory 206172 kb
Host smart-0ac5ad3e-786b-40a0-b5d3-e1be9d576668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699299037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2699299037
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2627913169
Short name T130
Test name
Test status
Simulation time 212380781 ps
CPU time 3.67 seconds
Started Aug 11 05:57:23 PM PDT 24
Finished Aug 11 05:57:26 PM PDT 24
Peak memory 214540 kb
Host smart-f85700dc-65ad-4d9c-b4b7-dffabe4d892d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627913169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2627913169
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3314796879
Short name T132
Test name
Test status
Simulation time 1947200881 ps
CPU time 9.3 seconds
Started Aug 11 05:57:21 PM PDT 24
Finished Aug 11 05:57:31 PM PDT 24
Peak memory 214656 kb
Host smart-83c88b53-4bc5-4e07-92a7-2e94cac050e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314796879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3314796879
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3361913327
Short name T921
Test name
Test status
Simulation time 110475140 ps
CPU time 2.2 seconds
Started Aug 11 05:57:21 PM PDT 24
Finished Aug 11 05:57:23 PM PDT 24
Peak memory 214352 kb
Host smart-4a627988-4f2d-4914-bd52-30c17cb54df2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361913327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3361913327
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.425937185
Short name T179
Test name
Test status
Simulation time 728509635 ps
CPU time 5.48 seconds
Started Aug 11 05:57:22 PM PDT 24
Finished Aug 11 05:57:27 PM PDT 24
Peak memory 206344 kb
Host smart-c1cff952-a0e5-437b-ab37-1397e1b83690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425937185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.425937185
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4239648939
Short name T953
Test name
Test status
Simulation time 34572802 ps
CPU time 1.56 seconds
Started Aug 11 05:57:31 PM PDT 24
Finished Aug 11 05:57:33 PM PDT 24
Peak memory 206144 kb
Host smart-acd5b535-f282-41f3-ba2b-efd7b17945fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239648939 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.4239648939
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.770328645
Short name T1051
Test name
Test status
Simulation time 35305322 ps
CPU time 1.08 seconds
Started Aug 11 05:57:30 PM PDT 24
Finished Aug 11 05:57:31 PM PDT 24
Peak memory 206112 kb
Host smart-877aa31b-ed90-4028-9c45-86f2d228cd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770328645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.770328645
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3264909761
Short name T1001
Test name
Test status
Simulation time 25585652 ps
CPU time 0.82 seconds
Started Aug 11 05:57:28 PM PDT 24
Finished Aug 11 05:57:29 PM PDT 24
Peak memory 205840 kb
Host smart-3956caf7-5ab5-4695-9dfd-0868deac2cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264909761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3264909761
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.918078542
Short name T1075
Test name
Test status
Simulation time 115896739 ps
CPU time 2.71 seconds
Started Aug 11 05:57:32 PM PDT 24
Finished Aug 11 05:57:35 PM PDT 24
Peak memory 206000 kb
Host smart-8e6b2599-0c53-405c-b4f7-14639c53b5b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918078542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.918078542
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3201426226
Short name T1074
Test name
Test status
Simulation time 304929087 ps
CPU time 2.37 seconds
Started Aug 11 05:57:20 PM PDT 24
Finished Aug 11 05:57:23 PM PDT 24
Peak memory 214476 kb
Host smart-45819bf9-9329-40bd-88b6-81ef835608df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201426226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3201426226
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1247151639
Short name T978
Test name
Test status
Simulation time 2204821425 ps
CPU time 10.17 seconds
Started Aug 11 05:57:21 PM PDT 24
Finished Aug 11 05:57:32 PM PDT 24
Peak memory 214760 kb
Host smart-5abfd39a-aaa8-4a1e-b9e0-c450dd33ff09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247151639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1247151639
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.599939511
Short name T1083
Test name
Test status
Simulation time 39891933 ps
CPU time 1.63 seconds
Started Aug 11 05:57:28 PM PDT 24
Finished Aug 11 05:57:30 PM PDT 24
Peak memory 214264 kb
Host smart-719b2470-e4f0-40b9-8a15-1e3168f9872d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599939511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.599939511
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2433075775
Short name T165
Test name
Test status
Simulation time 125075719 ps
CPU time 2.7 seconds
Started Aug 11 05:57:29 PM PDT 24
Finished Aug 11 05:57:32 PM PDT 24
Peak memory 214316 kb
Host smart-82048467-9f36-4796-9cbe-3449f913706c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433075775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2433075775
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.493837052
Short name T986
Test name
Test status
Simulation time 141423351 ps
CPU time 7.35 seconds
Started Aug 11 05:56:18 PM PDT 24
Finished Aug 11 05:56:25 PM PDT 24
Peak memory 206004 kb
Host smart-89722a8e-d70f-4775-9d78-aadd2ca92398
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493837052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.493837052
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.270983835
Short name T954
Test name
Test status
Simulation time 2235071572 ps
CPU time 16.53 seconds
Started Aug 11 05:56:16 PM PDT 24
Finished Aug 11 05:56:33 PM PDT 24
Peak memory 206068 kb
Host smart-8b010f6b-e64b-424d-907a-0359888b4e25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270983835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.270983835
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1163911717
Short name T976
Test name
Test status
Simulation time 160890998 ps
CPU time 0.93 seconds
Started Aug 11 05:56:16 PM PDT 24
Finished Aug 11 05:56:17 PM PDT 24
Peak memory 205964 kb
Host smart-c0616c67-696c-493f-bb8c-9766a773c8d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163911717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
163911717
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2067774838
Short name T973
Test name
Test status
Simulation time 265252292 ps
CPU time 1.47 seconds
Started Aug 11 05:56:15 PM PDT 24
Finished Aug 11 05:56:16 PM PDT 24
Peak memory 214668 kb
Host smart-a609dc3c-ab0c-414a-bc2b-eb40e7bcfe7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067774838 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2067774838
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3478530973
Short name T1017
Test name
Test status
Simulation time 34190685 ps
CPU time 1.3 seconds
Started Aug 11 05:56:19 PM PDT 24
Finished Aug 11 05:56:20 PM PDT 24
Peak memory 206052 kb
Host smart-aa8d2f35-3e68-43d0-89e9-3d1b67ee36f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478530973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3478530973
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2543976540
Short name T1081
Test name
Test status
Simulation time 21466828 ps
CPU time 0.82 seconds
Started Aug 11 05:56:18 PM PDT 24
Finished Aug 11 05:56:19 PM PDT 24
Peak memory 205852 kb
Host smart-5f37b38a-5785-4b3b-a1b1-2060870c55ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543976540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2543976540
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3432930036
Short name T1062
Test name
Test status
Simulation time 193770986 ps
CPU time 2.22 seconds
Started Aug 11 05:56:17 PM PDT 24
Finished Aug 11 05:56:19 PM PDT 24
Peak memory 206056 kb
Host smart-6936e22f-c948-442d-b8a9-f6396b3986c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432930036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3432930036
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3801911635
Short name T997
Test name
Test status
Simulation time 76172832 ps
CPU time 2.44 seconds
Started Aug 11 05:56:06 PM PDT 24
Finished Aug 11 05:56:09 PM PDT 24
Peak memory 214528 kb
Host smart-60077044-2c41-467e-a26b-de49ca75ce18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801911635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3801911635
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1062453043
Short name T1042
Test name
Test status
Simulation time 670230386 ps
CPU time 4.62 seconds
Started Aug 11 05:56:17 PM PDT 24
Finished Aug 11 05:56:22 PM PDT 24
Peak memory 214584 kb
Host smart-fb0a890f-efec-4c1c-a2cb-ce680d5346fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062453043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1062453043
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1381587105
Short name T967
Test name
Test status
Simulation time 99164922 ps
CPU time 2.93 seconds
Started Aug 11 05:56:12 PM PDT 24
Finished Aug 11 05:56:15 PM PDT 24
Peak memory 217516 kb
Host smart-f0f083f6-bb8e-4103-a728-d5d2f1e378da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381587105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1381587105
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1025874782
Short name T173
Test name
Test status
Simulation time 1645441149 ps
CPU time 4.89 seconds
Started Aug 11 05:56:15 PM PDT 24
Finished Aug 11 05:56:20 PM PDT 24
Peak memory 214268 kb
Host smart-b049672b-8597-403b-bf67-2be31e39f941
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025874782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1025874782
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1174952266
Short name T932
Test name
Test status
Simulation time 7551664 ps
CPU time 0.72 seconds
Started Aug 11 05:57:27 PM PDT 24
Finished Aug 11 05:57:28 PM PDT 24
Peak memory 205924 kb
Host smart-8503b88b-fb92-4be6-b387-30235e3e40ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174952266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1174952266
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.784657047
Short name T968
Test name
Test status
Simulation time 25449729 ps
CPU time 0.75 seconds
Started Aug 11 05:57:28 PM PDT 24
Finished Aug 11 05:57:29 PM PDT 24
Peak memory 205816 kb
Host smart-8963b195-af56-4f95-9065-b47f449a8de0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784657047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.784657047
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.351117706
Short name T1050
Test name
Test status
Simulation time 10422017 ps
CPU time 0.71 seconds
Started Aug 11 05:57:31 PM PDT 24
Finished Aug 11 05:57:32 PM PDT 24
Peak memory 205776 kb
Host smart-02fea30d-3313-450e-a5ee-94cb82f2eed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351117706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.351117706
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1771091241
Short name T996
Test name
Test status
Simulation time 24045870 ps
CPU time 0.77 seconds
Started Aug 11 05:57:28 PM PDT 24
Finished Aug 11 05:57:29 PM PDT 24
Peak memory 205884 kb
Host smart-eb04dedc-b2ed-4e92-84d4-a01cd6b34d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771091241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1771091241
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3053460174
Short name T1082
Test name
Test status
Simulation time 12884597 ps
CPU time 0.77 seconds
Started Aug 11 05:57:30 PM PDT 24
Finished Aug 11 05:57:31 PM PDT 24
Peak memory 206108 kb
Host smart-9450e78c-c2de-4662-baa5-fb202c09ddc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053460174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3053460174
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1433448022
Short name T923
Test name
Test status
Simulation time 29995806 ps
CPU time 0.77 seconds
Started Aug 11 05:57:30 PM PDT 24
Finished Aug 11 05:57:31 PM PDT 24
Peak memory 205788 kb
Host smart-867c060d-dfc1-49fe-aaea-96019b1a4dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433448022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1433448022
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3567933336
Short name T936
Test name
Test status
Simulation time 16994843 ps
CPU time 0.74 seconds
Started Aug 11 05:57:33 PM PDT 24
Finished Aug 11 05:57:34 PM PDT 24
Peak memory 205816 kb
Host smart-402eba59-d854-425b-94c8-6823713218b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567933336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3567933336
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.218451960
Short name T1070
Test name
Test status
Simulation time 30500198 ps
CPU time 0.81 seconds
Started Aug 11 05:57:39 PM PDT 24
Finished Aug 11 05:57:40 PM PDT 24
Peak memory 205916 kb
Host smart-d1723059-1cca-4579-aa5e-cde892edafcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218451960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.218451960
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4275043736
Short name T1055
Test name
Test status
Simulation time 36185294 ps
CPU time 0.84 seconds
Started Aug 11 05:57:38 PM PDT 24
Finished Aug 11 05:57:40 PM PDT 24
Peak memory 205844 kb
Host smart-265c68f6-9af5-488e-b811-0e314bc7517b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275043736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.4275043736
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3742336653
Short name T1043
Test name
Test status
Simulation time 9651721 ps
CPU time 0.77 seconds
Started Aug 11 05:57:35 PM PDT 24
Finished Aug 11 05:57:36 PM PDT 24
Peak memory 205876 kb
Host smart-f522a5b4-c003-40be-ac83-6c7e5ccf8a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742336653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3742336653
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3527990963
Short name T1054
Test name
Test status
Simulation time 1842039308 ps
CPU time 16.29 seconds
Started Aug 11 05:56:28 PM PDT 24
Finished Aug 11 05:56:44 PM PDT 24
Peak memory 205980 kb
Host smart-9a3db0ec-dd67-4922-8116-6a6b791114bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527990963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
527990963
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2712696367
Short name T1068
Test name
Test status
Simulation time 2609874726 ps
CPU time 7.6 seconds
Started Aug 11 05:56:19 PM PDT 24
Finished Aug 11 05:56:26 PM PDT 24
Peak memory 206148 kb
Host smart-e3ba905c-1a35-43f4-bbff-dc51e31bc3df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712696367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
712696367
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2956598379
Short name T965
Test name
Test status
Simulation time 57188396 ps
CPU time 1.14 seconds
Started Aug 11 05:56:20 PM PDT 24
Finished Aug 11 05:56:21 PM PDT 24
Peak memory 206176 kb
Host smart-132d9a13-b72c-4b0d-9af6-6efd8178342b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956598379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
956598379
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.905902735
Short name T1016
Test name
Test status
Simulation time 90233269 ps
CPU time 1.85 seconds
Started Aug 11 05:56:26 PM PDT 24
Finished Aug 11 05:56:28 PM PDT 24
Peak memory 214420 kb
Host smart-ac984ce1-001b-46de-ae8c-7915bd35b273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905902735 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.905902735
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.473957092
Short name T950
Test name
Test status
Simulation time 109828703 ps
CPU time 1.5 seconds
Started Aug 11 05:56:20 PM PDT 24
Finished Aug 11 05:56:22 PM PDT 24
Peak memory 206168 kb
Host smart-1d1db926-35be-41cc-b41b-a6969fc2a547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473957092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.473957092
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1181274539
Short name T919
Test name
Test status
Simulation time 40338041 ps
CPU time 0.78 seconds
Started Aug 11 05:56:21 PM PDT 24
Finished Aug 11 05:56:22 PM PDT 24
Peak memory 205820 kb
Host smart-85250225-c9e8-4149-8217-f4d78292c9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181274539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1181274539
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4012691131
Short name T1026
Test name
Test status
Simulation time 150781383 ps
CPU time 2.48 seconds
Started Aug 11 05:56:26 PM PDT 24
Finished Aug 11 05:56:29 PM PDT 24
Peak memory 206080 kb
Host smart-08ed51e9-b936-4dac-a30b-16650117e31d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012691131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4012691131
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1633050511
Short name T1065
Test name
Test status
Simulation time 452646098 ps
CPU time 2.24 seconds
Started Aug 11 05:56:15 PM PDT 24
Finished Aug 11 05:56:18 PM PDT 24
Peak memory 214528 kb
Host smart-84c8a3c1-c7c9-4f3d-b6d3-ec0eaf141479
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633050511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1633050511
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1531186825
Short name T1010
Test name
Test status
Simulation time 89264946 ps
CPU time 5.15 seconds
Started Aug 11 05:56:21 PM PDT 24
Finished Aug 11 05:56:26 PM PDT 24
Peak memory 214600 kb
Host smart-58e24d2b-1bd6-4d8a-be28-d9980333e0bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531186825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1531186825
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2448795316
Short name T971
Test name
Test status
Simulation time 259007250 ps
CPU time 2.76 seconds
Started Aug 11 05:56:21 PM PDT 24
Finished Aug 11 05:56:24 PM PDT 24
Peak memory 217632 kb
Host smart-e3c7e222-ced4-479d-b2b2-b6633a7f88de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448795316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2448795316
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.321317588
Short name T922
Test name
Test status
Simulation time 18390237 ps
CPU time 0.84 seconds
Started Aug 11 05:57:36 PM PDT 24
Finished Aug 11 05:57:37 PM PDT 24
Peak memory 205900 kb
Host smart-f8f4903a-e229-4dda-b372-39ccc385bdd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321317588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.321317588
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.345968039
Short name T951
Test name
Test status
Simulation time 14290688 ps
CPU time 0.71 seconds
Started Aug 11 05:57:36 PM PDT 24
Finished Aug 11 05:57:37 PM PDT 24
Peak memory 205824 kb
Host smart-ad1a9e28-2df6-4f3b-bcee-5dc7a3891e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345968039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.345968039
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.8411901
Short name T1085
Test name
Test status
Simulation time 38682203 ps
CPU time 0.7 seconds
Started Aug 11 05:57:33 PM PDT 24
Finished Aug 11 05:57:34 PM PDT 24
Peak memory 205876 kb
Host smart-28a417c9-221c-4fb6-9ff3-4c5b45f54327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8411901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.8411901
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.190909428
Short name T962
Test name
Test status
Simulation time 20989396 ps
CPU time 0.73 seconds
Started Aug 11 05:57:44 PM PDT 24
Finished Aug 11 05:57:45 PM PDT 24
Peak memory 205860 kb
Host smart-778bd7d1-3c36-4855-8a27-2145e0022936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190909428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.190909428
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2502457084
Short name T993
Test name
Test status
Simulation time 37195792 ps
CPU time 0.77 seconds
Started Aug 11 05:57:34 PM PDT 24
Finished Aug 11 05:57:35 PM PDT 24
Peak memory 205912 kb
Host smart-14cd26f7-b049-4c22-828f-be2d4b5973af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502457084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2502457084
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2161184892
Short name T992
Test name
Test status
Simulation time 76659264 ps
CPU time 0.71 seconds
Started Aug 11 05:57:35 PM PDT 24
Finished Aug 11 05:57:36 PM PDT 24
Peak memory 205784 kb
Host smart-13f139e4-c385-4610-88dc-0b53a9f81a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161184892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2161184892
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.634526176
Short name T1040
Test name
Test status
Simulation time 11388988 ps
CPU time 0.7 seconds
Started Aug 11 05:57:38 PM PDT 24
Finished Aug 11 05:57:39 PM PDT 24
Peak memory 205920 kb
Host smart-ef19c756-3757-46b5-8c88-b89eb6c8a77a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634526176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.634526176
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1951886367
Short name T1053
Test name
Test status
Simulation time 46872280 ps
CPU time 0.72 seconds
Started Aug 11 05:57:34 PM PDT 24
Finished Aug 11 05:57:35 PM PDT 24
Peak memory 205816 kb
Host smart-33285fd9-2ea4-473f-b3ca-c332fe6d2bc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951886367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1951886367
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2236276846
Short name T985
Test name
Test status
Simulation time 13603184 ps
CPU time 0.78 seconds
Started Aug 11 05:57:35 PM PDT 24
Finished Aug 11 05:57:36 PM PDT 24
Peak memory 205852 kb
Host smart-978142cc-e859-4092-81ef-a179aa088a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236276846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2236276846
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3537380193
Short name T1020
Test name
Test status
Simulation time 25743901 ps
CPU time 0.69 seconds
Started Aug 11 05:57:38 PM PDT 24
Finished Aug 11 05:57:38 PM PDT 24
Peak memory 205920 kb
Host smart-f2eb22b7-d1ed-4694-bf26-63920a14ccec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537380193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3537380193
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3852212510
Short name T1036
Test name
Test status
Simulation time 79560492 ps
CPU time 4.22 seconds
Started Aug 11 05:56:33 PM PDT 24
Finished Aug 11 05:56:37 PM PDT 24
Peak memory 206188 kb
Host smart-6ca03301-a35b-4dab-83cd-7086724dde0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852212510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
852212510
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.473152603
Short name T944
Test name
Test status
Simulation time 510715664 ps
CPU time 12.74 seconds
Started Aug 11 05:56:25 PM PDT 24
Finished Aug 11 05:56:38 PM PDT 24
Peak memory 206104 kb
Host smart-349c789d-9fb1-4160-a994-e52147a3cdf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473152603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.473152603
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1038390208
Short name T934
Test name
Test status
Simulation time 33117725 ps
CPU time 1.11 seconds
Started Aug 11 05:56:28 PM PDT 24
Finished Aug 11 05:56:29 PM PDT 24
Peak memory 206244 kb
Host smart-16e2828a-400b-4d58-b195-8acaac294249
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038390208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
038390208
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.19978719
Short name T182
Test name
Test status
Simulation time 146381663 ps
CPU time 1.21 seconds
Started Aug 11 05:56:35 PM PDT 24
Finished Aug 11 05:56:36 PM PDT 24
Peak memory 206216 kb
Host smart-f83b129d-0de3-4a0b-9184-c3115f88f2bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19978719 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.19978719
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1094473429
Short name T1063
Test name
Test status
Simulation time 18307355 ps
CPU time 0.95 seconds
Started Aug 11 05:56:25 PM PDT 24
Finished Aug 11 05:56:26 PM PDT 24
Peak memory 205900 kb
Host smart-304cb1e0-03ef-4006-aff3-86781c242a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094473429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1094473429
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1703844189
Short name T929
Test name
Test status
Simulation time 43991531 ps
CPU time 0.73 seconds
Started Aug 11 05:56:26 PM PDT 24
Finished Aug 11 05:56:26 PM PDT 24
Peak memory 205708 kb
Host smart-f0aebf24-9ec5-4525-8477-5a6398bb2a92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703844189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1703844189
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3785515769
Short name T979
Test name
Test status
Simulation time 175298617 ps
CPU time 3.1 seconds
Started Aug 11 05:56:33 PM PDT 24
Finished Aug 11 05:56:36 PM PDT 24
Peak memory 206184 kb
Host smart-774034f2-08e6-4a87-997c-05c571e91c24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785515769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3785515769
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3364764945
Short name T935
Test name
Test status
Simulation time 72037186 ps
CPU time 1.37 seconds
Started Aug 11 05:56:27 PM PDT 24
Finished Aug 11 05:56:28 PM PDT 24
Peak memory 206392 kb
Host smart-0138b0fb-0c04-43c3-85b2-93726f791817
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364764945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3364764945
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2508515813
Short name T128
Test name
Test status
Simulation time 183722546 ps
CPU time 5.13 seconds
Started Aug 11 05:56:27 PM PDT 24
Finished Aug 11 05:56:32 PM PDT 24
Peak memory 220612 kb
Host smart-8a2442cb-2b86-42a2-9fe2-14d173d33472
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508515813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2508515813
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3698711555
Short name T970
Test name
Test status
Simulation time 245230107 ps
CPU time 3.8 seconds
Started Aug 11 05:56:29 PM PDT 24
Finished Aug 11 05:56:33 PM PDT 24
Peak memory 214404 kb
Host smart-20815e93-a2f1-4736-8669-304c7868908e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698711555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3698711555
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2358986220
Short name T958
Test name
Test status
Simulation time 179856660 ps
CPU time 2.5 seconds
Started Aug 11 05:56:27 PM PDT 24
Finished Aug 11 05:56:29 PM PDT 24
Peak memory 215328 kb
Host smart-b32eb802-bcc2-41bc-bc8f-25e4e1fae99e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358986220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2358986220
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.744286008
Short name T930
Test name
Test status
Simulation time 16061789 ps
CPU time 0.71 seconds
Started Aug 11 05:57:36 PM PDT 24
Finished Aug 11 05:57:37 PM PDT 24
Peak memory 206108 kb
Host smart-e68c0948-c36e-44d2-a9e2-d27ee93b8d11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744286008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.744286008
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.4167328371
Short name T1004
Test name
Test status
Simulation time 48648262 ps
CPU time 0.74 seconds
Started Aug 11 05:57:35 PM PDT 24
Finished Aug 11 05:57:36 PM PDT 24
Peak memory 205852 kb
Host smart-f21eecba-1575-4a66-8567-9cbdafb686a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167328371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.4167328371
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2514225499
Short name T1039
Test name
Test status
Simulation time 14288410 ps
CPU time 0.9 seconds
Started Aug 11 05:57:35 PM PDT 24
Finished Aug 11 05:57:36 PM PDT 24
Peak memory 206020 kb
Host smart-8c27c392-5455-4f27-bc64-986b791f0623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514225499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2514225499
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3294388292
Short name T1012
Test name
Test status
Simulation time 17142422 ps
CPU time 0.82 seconds
Started Aug 11 05:57:34 PM PDT 24
Finished Aug 11 05:57:35 PM PDT 24
Peak memory 205764 kb
Host smart-e75300fe-fde1-43f4-bee1-7e1ad211c382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294388292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3294388292
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.986078875
Short name T995
Test name
Test status
Simulation time 50276949 ps
CPU time 0.89 seconds
Started Aug 11 05:57:36 PM PDT 24
Finished Aug 11 05:57:37 PM PDT 24
Peak memory 205764 kb
Host smart-1aeb0d23-c93b-4d33-ad2b-54bd46e93165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986078875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.986078875
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2950470440
Short name T926
Test name
Test status
Simulation time 36747668 ps
CPU time 0.72 seconds
Started Aug 11 05:57:34 PM PDT 24
Finished Aug 11 05:57:35 PM PDT 24
Peak memory 205852 kb
Host smart-91b8e04f-2032-4d62-bcb2-b9510198f3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950470440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2950470440
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4248169633
Short name T1059
Test name
Test status
Simulation time 109336175 ps
CPU time 0.75 seconds
Started Aug 11 05:57:40 PM PDT 24
Finished Aug 11 05:57:41 PM PDT 24
Peak memory 205784 kb
Host smart-01b023d0-9349-4e56-8ea2-2d90130a414a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248169633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4248169633
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.205614474
Short name T964
Test name
Test status
Simulation time 49654630 ps
CPU time 0.8 seconds
Started Aug 11 05:57:39 PM PDT 24
Finished Aug 11 05:57:40 PM PDT 24
Peak memory 205856 kb
Host smart-80953b1a-e324-474f-bcbf-3ecfa7c5deb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205614474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.205614474
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3699828771
Short name T1003
Test name
Test status
Simulation time 21029675 ps
CPU time 0.7 seconds
Started Aug 11 05:57:37 PM PDT 24
Finished Aug 11 05:57:38 PM PDT 24
Peak memory 205776 kb
Host smart-a52228b4-cdfc-4394-aec0-ea2b09ddc179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699828771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3699828771
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3809289551
Short name T1022
Test name
Test status
Simulation time 9912111 ps
CPU time 0.84 seconds
Started Aug 11 05:57:40 PM PDT 24
Finished Aug 11 05:57:41 PM PDT 24
Peak memory 205784 kb
Host smart-9957ac91-5244-4241-b4c0-cf83282482c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809289551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3809289551
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2029761051
Short name T1064
Test name
Test status
Simulation time 203268177 ps
CPU time 1.77 seconds
Started Aug 11 05:56:31 PM PDT 24
Finished Aug 11 05:56:33 PM PDT 24
Peak memory 214364 kb
Host smart-7f4439fe-3e2c-482a-80c4-953e43f10c72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029761051 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2029761051
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1833332881
Short name T157
Test name
Test status
Simulation time 80531109 ps
CPU time 1.01 seconds
Started Aug 11 05:56:33 PM PDT 24
Finished Aug 11 05:56:35 PM PDT 24
Peak memory 205820 kb
Host smart-027ff9f0-c164-4421-9fa7-2d261d1c5610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833332881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1833332881
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3925461332
Short name T1032
Test name
Test status
Simulation time 14911289 ps
CPU time 0.79 seconds
Started Aug 11 05:56:33 PM PDT 24
Finished Aug 11 05:56:34 PM PDT 24
Peak memory 205784 kb
Host smart-953168d6-bb6a-4dc3-850d-2479f8ee63b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925461332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3925461332
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1489974890
Short name T1034
Test name
Test status
Simulation time 309479530 ps
CPU time 1.7 seconds
Started Aug 11 05:56:31 PM PDT 24
Finished Aug 11 05:56:33 PM PDT 24
Peak memory 206228 kb
Host smart-eaef7da3-bfbe-4c38-8825-217d8a587e90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489974890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1489974890
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.819791224
Short name T988
Test name
Test status
Simulation time 383523404 ps
CPU time 2.71 seconds
Started Aug 11 05:56:31 PM PDT 24
Finished Aug 11 05:56:34 PM PDT 24
Peak memory 214668 kb
Host smart-67781c08-a08a-4d89-81ba-db0b6da6c1dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819791224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.819791224
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4033930523
Short name T1007
Test name
Test status
Simulation time 482628385 ps
CPU time 9.07 seconds
Started Aug 11 05:56:34 PM PDT 24
Finished Aug 11 05:56:43 PM PDT 24
Peak memory 214708 kb
Host smart-4b490ba7-14ce-4731-98fe-835a3b726f7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033930523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.4033930523
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3268818766
Short name T990
Test name
Test status
Simulation time 42222436 ps
CPU time 2.99 seconds
Started Aug 11 05:56:33 PM PDT 24
Finished Aug 11 05:56:36 PM PDT 24
Peak memory 214428 kb
Host smart-06b0f156-acf8-4fff-946a-554d15cbe93c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268818766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3268818766
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3248478604
Short name T938
Test name
Test status
Simulation time 213995959 ps
CPU time 2.12 seconds
Started Aug 11 05:56:45 PM PDT 24
Finished Aug 11 05:56:47 PM PDT 24
Peak memory 214280 kb
Host smart-2fda2372-6e40-4d1e-81bb-ebb88bfe0a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248478604 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3248478604
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.78326637
Short name T1066
Test name
Test status
Simulation time 83030472 ps
CPU time 1.21 seconds
Started Aug 11 05:56:39 PM PDT 24
Finished Aug 11 05:56:40 PM PDT 24
Peak memory 206064 kb
Host smart-e3ffbb6e-9058-4691-b6d4-dd62a4d0cd9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78326637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.78326637
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2988143230
Short name T1080
Test name
Test status
Simulation time 32182806 ps
CPU time 0.76 seconds
Started Aug 11 05:56:38 PM PDT 24
Finished Aug 11 05:56:39 PM PDT 24
Peak memory 205844 kb
Host smart-5dad1f26-c7f2-4fbb-b2a6-a8758a0d3b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988143230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2988143230
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3353434746
Short name T1018
Test name
Test status
Simulation time 445070151 ps
CPU time 4.4 seconds
Started Aug 11 05:56:40 PM PDT 24
Finished Aug 11 05:56:45 PM PDT 24
Peak memory 206000 kb
Host smart-ab870c46-408c-436b-ad67-035074d3942e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353434746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3353434746
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.419268727
Short name T1005
Test name
Test status
Simulation time 604343009 ps
CPU time 4.51 seconds
Started Aug 11 05:56:39 PM PDT 24
Finished Aug 11 05:56:44 PM PDT 24
Peak memory 214580 kb
Host smart-405e98eb-eee4-4afe-a4b6-48752565ad0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419268727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.419268727
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1914852939
Short name T1006
Test name
Test status
Simulation time 225920268 ps
CPU time 4.08 seconds
Started Aug 11 05:56:38 PM PDT 24
Finished Aug 11 05:56:42 PM PDT 24
Peak memory 214688 kb
Host smart-378fc218-e2c1-4c6e-8e84-3008a599e98b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914852939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1914852939
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1122776070
Short name T937
Test name
Test status
Simulation time 22635966 ps
CPU time 1.59 seconds
Started Aug 11 05:56:37 PM PDT 24
Finished Aug 11 05:56:39 PM PDT 24
Peak memory 214376 kb
Host smart-672f2ad1-4380-4f38-ad3d-91b14124129d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122776070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1122776070
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1272267188
Short name T945
Test name
Test status
Simulation time 18140208 ps
CPU time 1.5 seconds
Started Aug 11 05:56:51 PM PDT 24
Finished Aug 11 05:56:53 PM PDT 24
Peak memory 214664 kb
Host smart-18607345-ddaf-4455-9a41-5a54bb28bd99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272267188 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1272267188
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1190197777
Short name T960
Test name
Test status
Simulation time 44788306 ps
CPU time 1.14 seconds
Started Aug 11 05:56:46 PM PDT 24
Finished Aug 11 05:56:47 PM PDT 24
Peak memory 206000 kb
Host smart-d709dfc6-73b1-4c13-9bb6-f218966588e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190197777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1190197777
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2406002666
Short name T1067
Test name
Test status
Simulation time 21197600 ps
CPU time 0.7 seconds
Started Aug 11 05:56:43 PM PDT 24
Finished Aug 11 05:56:44 PM PDT 24
Peak memory 205852 kb
Host smart-cde899bc-303a-4742-a8fb-fcbb7550a8d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406002666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2406002666
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.509412204
Short name T1060
Test name
Test status
Simulation time 263323862 ps
CPU time 1.88 seconds
Started Aug 11 05:56:50 PM PDT 24
Finished Aug 11 05:56:52 PM PDT 24
Peak memory 206156 kb
Host smart-5ffd6ed8-3541-49d2-b6e2-92d4063391df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509412204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.509412204
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2139085737
Short name T1048
Test name
Test status
Simulation time 130288136 ps
CPU time 1.89 seconds
Started Aug 11 05:56:43 PM PDT 24
Finished Aug 11 05:56:45 PM PDT 24
Peak memory 214540 kb
Host smart-2ec3033b-5f18-4f17-af34-af34b1e34965
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139085737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2139085737
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2176063921
Short name T998
Test name
Test status
Simulation time 165942925 ps
CPU time 8.42 seconds
Started Aug 11 05:56:45 PM PDT 24
Finished Aug 11 05:56:54 PM PDT 24
Peak memory 214576 kb
Host smart-def528f2-6dc9-4dfe-b4ce-6a3ea612f36f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176063921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2176063921
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3806523311
Short name T975
Test name
Test status
Simulation time 28715817 ps
CPU time 1.92 seconds
Started Aug 11 05:56:46 PM PDT 24
Finished Aug 11 05:56:48 PM PDT 24
Peak memory 216676 kb
Host smart-3278528e-5844-407b-9387-710fa50e79b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806523311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3806523311
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3478400645
Short name T1035
Test name
Test status
Simulation time 289832759 ps
CPU time 4.02 seconds
Started Aug 11 05:56:43 PM PDT 24
Finished Aug 11 05:56:47 PM PDT 24
Peak memory 214204 kb
Host smart-d2f55893-d2de-4b2f-aa17-82d030169fee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478400645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3478400645
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.818547038
Short name T1077
Test name
Test status
Simulation time 140942098 ps
CPU time 1.46 seconds
Started Aug 11 05:56:56 PM PDT 24
Finished Aug 11 05:56:58 PM PDT 24
Peak memory 214308 kb
Host smart-ee3ebbef-ef6e-4244-acd5-563e7a7a2615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818547038 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.818547038
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3640859477
Short name T1027
Test name
Test status
Simulation time 97567818 ps
CPU time 0.97 seconds
Started Aug 11 05:56:55 PM PDT 24
Finished Aug 11 05:56:56 PM PDT 24
Peak memory 205860 kb
Host smart-87c22ac4-eeee-42e5-917f-360614ef2dfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640859477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3640859477
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1788816064
Short name T1047
Test name
Test status
Simulation time 43501202 ps
CPU time 0.72 seconds
Started Aug 11 05:56:56 PM PDT 24
Finished Aug 11 05:56:56 PM PDT 24
Peak memory 205796 kb
Host smart-4aae47cc-2f27-4124-befd-15bcab04f32f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788816064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1788816064
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1377232533
Short name T1011
Test name
Test status
Simulation time 226229527 ps
CPU time 2.52 seconds
Started Aug 11 05:56:57 PM PDT 24
Finished Aug 11 05:56:59 PM PDT 24
Peak memory 206024 kb
Host smart-9b465414-aa65-4f36-96eb-c5e9dff1d2c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377232533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1377232533
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1861494747
Short name T1019
Test name
Test status
Simulation time 212168954 ps
CPU time 4.7 seconds
Started Aug 11 05:56:49 PM PDT 24
Finished Aug 11 05:56:54 PM PDT 24
Peak memory 214596 kb
Host smart-3d4a30c3-83b6-4e9c-bcc8-2a306bce39bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861494747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1861494747
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1759273290
Short name T1084
Test name
Test status
Simulation time 416776777 ps
CPU time 14.82 seconds
Started Aug 11 05:56:52 PM PDT 24
Finished Aug 11 05:57:07 PM PDT 24
Peak memory 214576 kb
Host smart-6550dadc-17a0-475b-96f6-ee912e5ad310
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759273290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1759273290
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2188067647
Short name T927
Test name
Test status
Simulation time 122996305 ps
CPU time 3.37 seconds
Started Aug 11 05:56:56 PM PDT 24
Finished Aug 11 05:57:00 PM PDT 24
Peak memory 214304 kb
Host smart-7c2ad710-726a-489e-83dc-5b623dd508b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188067647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2188067647
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2102628194
Short name T1002
Test name
Test status
Simulation time 110493465 ps
CPU time 3.43 seconds
Started Aug 11 05:56:53 PM PDT 24
Finished Aug 11 05:56:57 PM PDT 24
Peak memory 205996 kb
Host smart-bc54af1a-6f5c-430c-a597-73dc14d7188a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102628194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2102628194
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.21570623
Short name T931
Test name
Test status
Simulation time 106315948 ps
CPU time 1.57 seconds
Started Aug 11 05:56:56 PM PDT 24
Finished Aug 11 05:56:58 PM PDT 24
Peak memory 214464 kb
Host smart-40c5dfde-595b-488d-97cb-f7d9f94c7ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21570623 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.21570623
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.319947805
Short name T1028
Test name
Test status
Simulation time 66778651 ps
CPU time 1.05 seconds
Started Aug 11 05:56:58 PM PDT 24
Finished Aug 11 05:57:00 PM PDT 24
Peak memory 205996 kb
Host smart-f1b48ed6-3e1d-47f3-a6b8-4730f36197af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319947805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.319947805
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2717457689
Short name T1041
Test name
Test status
Simulation time 38657986 ps
CPU time 0.78 seconds
Started Aug 11 05:56:57 PM PDT 24
Finished Aug 11 05:56:58 PM PDT 24
Peak memory 205708 kb
Host smart-8d953df3-4ce3-47af-86f3-bfd75865ec39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717457689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2717457689
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.292303955
Short name T1072
Test name
Test status
Simulation time 413739455 ps
CPU time 1.53 seconds
Started Aug 11 05:56:57 PM PDT 24
Finished Aug 11 05:56:58 PM PDT 24
Peak memory 206064 kb
Host smart-f32bf0ab-54a8-49e7-b700-ef603e6b51cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292303955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.292303955
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3167628841
Short name T127
Test name
Test status
Simulation time 166332607 ps
CPU time 4.42 seconds
Started Aug 11 05:56:52 PM PDT 24
Finished Aug 11 05:56:56 PM PDT 24
Peak memory 214584 kb
Host smart-de955e01-f1dc-4cc8-b9ca-baf745ad15a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167628841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3167628841
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2102279528
Short name T133
Test name
Test status
Simulation time 1137746839 ps
CPU time 6.26 seconds
Started Aug 11 05:56:50 PM PDT 24
Finished Aug 11 05:56:56 PM PDT 24
Peak memory 214560 kb
Host smart-4e4ec9d7-5b05-4258-9ac2-ec43f5ee8d28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102279528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2102279528
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1441047957
Short name T918
Test name
Test status
Simulation time 21029654 ps
CPU time 1.54 seconds
Started Aug 11 05:56:52 PM PDT 24
Finished Aug 11 05:56:54 PM PDT 24
Peak memory 214344 kb
Host smart-a8ede888-6612-4621-a139-02338174dc9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441047957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1441047957
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2187390094
Short name T168
Test name
Test status
Simulation time 497718098 ps
CPU time 7.58 seconds
Started Aug 11 05:56:59 PM PDT 24
Finished Aug 11 05:57:06 PM PDT 24
Peak memory 214344 kb
Host smart-970453dc-5ed7-4c52-b614-569038dd250b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187390094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2187390094
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3082767464
Short name T341
Test name
Test status
Simulation time 105434666 ps
CPU time 2.67 seconds
Started Aug 11 06:04:13 PM PDT 24
Finished Aug 11 06:04:16 PM PDT 24
Peak memory 214260 kb
Host smart-726f7484-18ec-4381-98c4-8e5e1fdf2133
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082767464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3082767464
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2970480478
Short name T220
Test name
Test status
Simulation time 209332268 ps
CPU time 2.97 seconds
Started Aug 11 06:04:14 PM PDT 24
Finished Aug 11 06:04:17 PM PDT 24
Peak memory 214188 kb
Host smart-c2ded9f6-f516-4908-b93b-31a05c9c0d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970480478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2970480478
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2959724861
Short name T552
Test name
Test status
Simulation time 67849025 ps
CPU time 3.1 seconds
Started Aug 11 06:04:15 PM PDT 24
Finished Aug 11 06:04:19 PM PDT 24
Peak memory 209184 kb
Host smart-f8c45f78-52d5-4338-aa8b-452332d19924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959724861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2959724861
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3681855772
Short name T255
Test name
Test status
Simulation time 451727290 ps
CPU time 2.62 seconds
Started Aug 11 06:04:10 PM PDT 24
Finished Aug 11 06:04:13 PM PDT 24
Peak memory 214340 kb
Host smart-6929053f-7419-4bce-8c89-69cdb5025fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681855772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3681855772
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3535229422
Short name T619
Test name
Test status
Simulation time 688287148 ps
CPU time 4.23 seconds
Started Aug 11 06:04:12 PM PDT 24
Finished Aug 11 06:04:16 PM PDT 24
Peak memory 214320 kb
Host smart-ac478c36-a2e5-4464-a2fe-9f610126230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535229422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3535229422
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.365932936
Short name T50
Test name
Test status
Simulation time 738331547 ps
CPU time 3.67 seconds
Started Aug 11 06:04:14 PM PDT 24
Finished Aug 11 06:04:18 PM PDT 24
Peak memory 222400 kb
Host smart-028df3fb-35b8-4aac-b28c-9e03cd8e1427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365932936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.365932936
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.4165971627
Short name T763
Test name
Test status
Simulation time 180150206 ps
CPU time 4.77 seconds
Started Aug 11 06:04:12 PM PDT 24
Finished Aug 11 06:04:17 PM PDT 24
Peak memory 214228 kb
Host smart-4279f45c-166d-4ef9-9481-75fd32908967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165971627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.4165971627
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.331728256
Short name T9
Test name
Test status
Simulation time 1018154472 ps
CPU time 8.48 seconds
Started Aug 11 06:04:25 PM PDT 24
Finished Aug 11 06:04:34 PM PDT 24
Peak memory 230588 kb
Host smart-023b8c22-87b0-4218-9011-581448ea4d0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331728256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.331728256
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2649382135
Short name T538
Test name
Test status
Simulation time 336725863 ps
CPU time 2.36 seconds
Started Aug 11 06:04:13 PM PDT 24
Finished Aug 11 06:04:16 PM PDT 24
Peak memory 207032 kb
Host smart-66d6dfa5-53cc-421b-9599-164b8c233f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649382135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2649382135
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3202610246
Short name T142
Test name
Test status
Simulation time 74713583 ps
CPU time 1.82 seconds
Started Aug 11 06:04:14 PM PDT 24
Finished Aug 11 06:04:16 PM PDT 24
Peak memory 206852 kb
Host smart-e6969ce5-9eb4-4e74-bcf7-c1f5f9ab3846
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202610246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3202610246
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.359177035
Short name T308
Test name
Test status
Simulation time 1545281957 ps
CPU time 3.29 seconds
Started Aug 11 06:04:12 PM PDT 24
Finished Aug 11 06:04:16 PM PDT 24
Peak memory 208500 kb
Host smart-afb2ebc1-a487-4617-b6b9-b92b6d7bc375
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359177035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.359177035
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3199321555
Short name T275
Test name
Test status
Simulation time 170746732 ps
CPU time 3.84 seconds
Started Aug 11 06:04:13 PM PDT 24
Finished Aug 11 06:04:17 PM PDT 24
Peak memory 208736 kb
Host smart-9d33bfb8-52f4-431a-a430-bb3d328f757f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199321555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3199321555
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4065173864
Short name T503
Test name
Test status
Simulation time 224108022 ps
CPU time 1.97 seconds
Started Aug 11 06:04:13 PM PDT 24
Finished Aug 11 06:04:15 PM PDT 24
Peak memory 207236 kb
Host smart-f65ace54-10a3-4e5f-8b58-94e47905e5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065173864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4065173864
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1726990884
Short name T667
Test name
Test status
Simulation time 1585315451 ps
CPU time 33.29 seconds
Started Aug 11 06:04:12 PM PDT 24
Finished Aug 11 06:04:45 PM PDT 24
Peak memory 207876 kb
Host smart-37f20741-f373-48ea-b586-b93d32dc09de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726990884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1726990884
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2675419658
Short name T910
Test name
Test status
Simulation time 139830158 ps
CPU time 9.07 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:32 PM PDT 24
Peak memory 222784 kb
Host smart-0d8171c1-c993-4cac-904a-1d29bdf5b332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675419658 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2675419658
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3683900202
Short name T559
Test name
Test status
Simulation time 104340281 ps
CPU time 4.91 seconds
Started Aug 11 06:04:13 PM PDT 24
Finished Aug 11 06:04:18 PM PDT 24
Peak memory 209380 kb
Host smart-1ec767f4-7667-4a2e-af7c-218e2d940cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683900202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3683900202
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3742505050
Short name T865
Test name
Test status
Simulation time 72335850 ps
CPU time 1.91 seconds
Started Aug 11 06:04:12 PM PDT 24
Finished Aug 11 06:04:14 PM PDT 24
Peak memory 210216 kb
Host smart-3ac37c09-111d-45b0-a048-6fbff8136f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742505050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3742505050
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3593869108
Short name T605
Test name
Test status
Simulation time 21427316 ps
CPU time 1 seconds
Started Aug 11 06:04:23 PM PDT 24
Finished Aug 11 06:04:24 PM PDT 24
Peak memory 205944 kb
Host smart-4acb3ff8-c192-43d5-83db-832350002a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593869108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3593869108
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.912845988
Short name T149
Test name
Test status
Simulation time 89047128 ps
CPU time 3.46 seconds
Started Aug 11 06:04:19 PM PDT 24
Finished Aug 11 06:04:22 PM PDT 24
Peak memory 214736 kb
Host smart-9fc7f16b-f1cf-4580-ae70-afb81de07271
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912845988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.912845988
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2525690149
Short name T591
Test name
Test status
Simulation time 372344662 ps
CPU time 3.87 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:27 PM PDT 24
Peak memory 207272 kb
Host smart-a554d926-0744-4d7b-88d2-f3629fefee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525690149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2525690149
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.4194258482
Short name T102
Test name
Test status
Simulation time 489506094 ps
CPU time 4.66 seconds
Started Aug 11 06:04:23 PM PDT 24
Finished Aug 11 06:04:28 PM PDT 24
Peak memory 208456 kb
Host smart-f34612d9-fe03-4033-8ba9-f7b0f2ae811b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194258482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.4194258482
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2656081516
Short name T384
Test name
Test status
Simulation time 44970565 ps
CPU time 2.03 seconds
Started Aug 11 06:04:23 PM PDT 24
Finished Aug 11 06:04:25 PM PDT 24
Peak memory 214212 kb
Host smart-7808d121-e2db-46f6-9fca-4a457c7b6f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656081516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2656081516
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.896798029
Short name T76
Test name
Test status
Simulation time 91613023 ps
CPU time 2.8 seconds
Started Aug 11 06:04:27 PM PDT 24
Finished Aug 11 06:04:30 PM PDT 24
Peak memory 210200 kb
Host smart-e5a1d786-5385-4231-8396-6d1f9c4f390b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896798029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.896798029
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.4229389082
Short name T909
Test name
Test status
Simulation time 3020720179 ps
CPU time 19.82 seconds
Started Aug 11 06:04:27 PM PDT 24
Finished Aug 11 06:04:47 PM PDT 24
Peak memory 214440 kb
Host smart-5ef1a11c-5e52-45dd-afdf-898080a8221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229389082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.4229389082
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2811672999
Short name T113
Test name
Test status
Simulation time 2235951823 ps
CPU time 15.92 seconds
Started Aug 11 06:04:21 PM PDT 24
Finished Aug 11 06:04:37 PM PDT 24
Peak memory 238028 kb
Host smart-a6855d03-ad8f-491e-bf22-85a7195ae559
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811672999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2811672999
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1735702857
Short name T466
Test name
Test status
Simulation time 234411043 ps
CPU time 2.41 seconds
Started Aug 11 06:04:19 PM PDT 24
Finished Aug 11 06:04:22 PM PDT 24
Peak memory 206840 kb
Host smart-4b9c1df4-2e04-442a-8ba0-a8da9facdc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735702857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1735702857
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1557505710
Short name T457
Test name
Test status
Simulation time 1764344022 ps
CPU time 5.53 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:27 PM PDT 24
Peak memory 207036 kb
Host smart-051567ff-5707-4f08-8b3f-05d70d034ac2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557505710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1557505710
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.748344706
Short name T873
Test name
Test status
Simulation time 846147615 ps
CPU time 5.82 seconds
Started Aug 11 06:04:23 PM PDT 24
Finished Aug 11 06:04:29 PM PDT 24
Peak memory 208664 kb
Host smart-55250455-62c2-4dfc-b944-0db274f8a0af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748344706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.748344706
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1240063360
Short name T526
Test name
Test status
Simulation time 4040158825 ps
CPU time 19.94 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:42 PM PDT 24
Peak memory 208292 kb
Host smart-17f29bf0-0e45-4b77-bb8c-d772f3bc8f27
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240063360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1240063360
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3698299151
Short name T454
Test name
Test status
Simulation time 801125592 ps
CPU time 24.33 seconds
Started Aug 11 06:04:23 PM PDT 24
Finished Aug 11 06:04:47 PM PDT 24
Peak memory 209036 kb
Host smart-751e5d37-5cf9-4e37-a080-f990461d9dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698299151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3698299151
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.4173397277
Short name T877
Test name
Test status
Simulation time 1338103102 ps
CPU time 32.74 seconds
Started Aug 11 06:04:21 PM PDT 24
Finished Aug 11 06:04:54 PM PDT 24
Peak memory 207696 kb
Host smart-0b7da4ae-53da-46f4-81b4-e1beb7cfa8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173397277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.4173397277
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1873730932
Short name T83
Test name
Test status
Simulation time 553183828 ps
CPU time 3.88 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:26 PM PDT 24
Peak memory 207468 kb
Host smart-1bcb34b0-4792-4839-9ead-85c4483e335c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873730932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1873730932
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2791818369
Short name T46
Test name
Test status
Simulation time 197430522 ps
CPU time 11.39 seconds
Started Aug 11 06:04:23 PM PDT 24
Finished Aug 11 06:04:34 PM PDT 24
Peak memory 220700 kb
Host smart-90011250-e447-4c6c-8a59-4193fd5ccf34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791818369 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2791818369
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3652888193
Short name T292
Test name
Test status
Simulation time 300399483 ps
CPU time 3.99 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:26 PM PDT 24
Peak memory 209936 kb
Host smart-2b546ed2-618f-454d-bee3-4a1406f11798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652888193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3652888193
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3884462616
Short name T528
Test name
Test status
Simulation time 113559373 ps
CPU time 0.79 seconds
Started Aug 11 06:05:09 PM PDT 24
Finished Aug 11 06:05:10 PM PDT 24
Peak memory 205844 kb
Host smart-7a0df50e-f707-4b78-a291-348efb169879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884462616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3884462616
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1365864446
Short name T347
Test name
Test status
Simulation time 232195680 ps
CPU time 4.15 seconds
Started Aug 11 06:05:10 PM PDT 24
Finished Aug 11 06:05:14 PM PDT 24
Peak memory 215744 kb
Host smart-21b14c91-6abb-4ef0-9942-4960ffc008e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365864446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1365864446
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.4208082757
Short name T796
Test name
Test status
Simulation time 84647385 ps
CPU time 1.41 seconds
Started Aug 11 06:05:07 PM PDT 24
Finished Aug 11 06:05:09 PM PDT 24
Peak memory 207516 kb
Host smart-3457af4f-0b6f-4de5-a6ac-de4d55a28520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208082757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4208082757
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1516417030
Short name T808
Test name
Test status
Simulation time 191707673 ps
CPU time 6.83 seconds
Started Aug 11 06:05:05 PM PDT 24
Finished Aug 11 06:05:12 PM PDT 24
Peak memory 214344 kb
Host smart-8f62ac93-cee4-4c32-a893-4604a804ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516417030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1516417030
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1801979183
Short name T576
Test name
Test status
Simulation time 95738963 ps
CPU time 3.11 seconds
Started Aug 11 06:05:03 PM PDT 24
Finished Aug 11 06:05:06 PM PDT 24
Peak memory 214288 kb
Host smart-d5b0e306-7cea-4582-b731-44268a0dacc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801979183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1801979183
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1790142347
Short name T445
Test name
Test status
Simulation time 235238312 ps
CPU time 1.57 seconds
Started Aug 11 06:05:05 PM PDT 24
Finished Aug 11 06:05:07 PM PDT 24
Peak memory 214244 kb
Host smart-508992eb-eb50-4de6-bd8f-13797eaa20ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790142347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1790142347
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2961660180
Short name T61
Test name
Test status
Simulation time 2748166559 ps
CPU time 21.17 seconds
Started Aug 11 06:05:06 PM PDT 24
Finished Aug 11 06:05:28 PM PDT 24
Peak memory 220804 kb
Host smart-9aa8754d-797b-43cb-a33d-e9600af6c285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961660180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2961660180
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.783847412
Short name T339
Test name
Test status
Simulation time 553354772 ps
CPU time 6.25 seconds
Started Aug 11 06:05:06 PM PDT 24
Finished Aug 11 06:05:12 PM PDT 24
Peak memory 209284 kb
Host smart-61ba9b00-a166-4a94-9d7f-52ebea599d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783847412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.783847412
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3933994668
Short name T3
Test name
Test status
Simulation time 301417015 ps
CPU time 4.59 seconds
Started Aug 11 06:05:17 PM PDT 24
Finished Aug 11 06:05:21 PM PDT 24
Peak memory 206720 kb
Host smart-2f8e16b4-7a85-436f-a79c-060330e1ca3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933994668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3933994668
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2939171284
Short name T306
Test name
Test status
Simulation time 158109399 ps
CPU time 4.24 seconds
Started Aug 11 06:05:09 PM PDT 24
Finished Aug 11 06:05:13 PM PDT 24
Peak memory 208616 kb
Host smart-f9d42298-fce2-4d63-ae63-4e0d630f67c0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939171284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2939171284
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2351872335
Short name T621
Test name
Test status
Simulation time 498484570 ps
CPU time 4.37 seconds
Started Aug 11 06:05:07 PM PDT 24
Finished Aug 11 06:05:12 PM PDT 24
Peak memory 206928 kb
Host smart-1badfb3d-1fc2-428a-a867-4a0d8c7c5073
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351872335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2351872335
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.371478451
Short name T487
Test name
Test status
Simulation time 87473003 ps
CPU time 4.26 seconds
Started Aug 11 06:05:04 PM PDT 24
Finished Aug 11 06:05:08 PM PDT 24
Peak memory 208772 kb
Host smart-2cacb716-3197-4711-af13-0902655f5550
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371478451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.371478451
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.577166565
Short name T912
Test name
Test status
Simulation time 76198509 ps
CPU time 2.31 seconds
Started Aug 11 06:05:07 PM PDT 24
Finished Aug 11 06:05:09 PM PDT 24
Peak memory 208636 kb
Host smart-9f69961c-eaa6-4afb-b3e7-b124b884f0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577166565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.577166565
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.265946227
Short name T861
Test name
Test status
Simulation time 116536363 ps
CPU time 1.82 seconds
Started Aug 11 06:05:17 PM PDT 24
Finished Aug 11 06:05:19 PM PDT 24
Peak memory 208352 kb
Host smart-b1e0a7b3-5d5c-4d54-abf3-013193172319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265946227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.265946227
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1416703632
Short name T246
Test name
Test status
Simulation time 2001002179 ps
CPU time 18.72 seconds
Started Aug 11 06:05:08 PM PDT 24
Finished Aug 11 06:05:27 PM PDT 24
Peak memory 216448 kb
Host smart-a29921bf-68c3-4c70-8b50-2f935319a0f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416703632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1416703632
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1590872911
Short name T401
Test name
Test status
Simulation time 4087853438 ps
CPU time 43 seconds
Started Aug 11 06:05:10 PM PDT 24
Finished Aug 11 06:05:53 PM PDT 24
Peak memory 209348 kb
Host smart-53c1933f-d949-4c0d-9704-5795fa9cb893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590872911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1590872911
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1218315488
Short name T56
Test name
Test status
Simulation time 1613124945 ps
CPU time 15.1 seconds
Started Aug 11 06:05:06 PM PDT 24
Finished Aug 11 06:05:22 PM PDT 24
Peak memory 210808 kb
Host smart-b02fb5c2-c433-40b7-b531-530bbb14841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218315488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1218315488
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1314949258
Short name T711
Test name
Test status
Simulation time 55507875 ps
CPU time 0.76 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:15 PM PDT 24
Peak memory 205928 kb
Host smart-591ee808-da69-4195-b9e0-0e61999a0759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314949258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1314949258
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1700033229
Short name T371
Test name
Test status
Simulation time 41703005 ps
CPU time 3.26 seconds
Started Aug 11 06:05:13 PM PDT 24
Finished Aug 11 06:05:17 PM PDT 24
Peak memory 215748 kb
Host smart-19038adb-0b0e-41fc-9b61-0fd758f92ec3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1700033229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1700033229
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3947615347
Short name T887
Test name
Test status
Simulation time 49050944 ps
CPU time 1.52 seconds
Started Aug 11 06:05:16 PM PDT 24
Finished Aug 11 06:05:17 PM PDT 24
Peak memory 207592 kb
Host smart-bc36ace4-f540-4d2c-85b2-06c29e0801d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947615347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3947615347
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.108496310
Short name T671
Test name
Test status
Simulation time 553786030 ps
CPU time 4.28 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:18 PM PDT 24
Peak memory 211872 kb
Host smart-aa8e0be0-92b7-4c64-b666-5a2fbe5e1b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108496310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.108496310
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3279750726
Short name T596
Test name
Test status
Simulation time 425950965 ps
CPU time 2.7 seconds
Started Aug 11 06:05:13 PM PDT 24
Finished Aug 11 06:05:16 PM PDT 24
Peak memory 215972 kb
Host smart-9534d109-4f4d-4b93-8eb2-9b2739074468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279750726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3279750726
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2644813172
Short name T831
Test name
Test status
Simulation time 733356051 ps
CPU time 6.18 seconds
Started Aug 11 06:05:13 PM PDT 24
Finished Aug 11 06:05:19 PM PDT 24
Peak memory 214228 kb
Host smart-aafac980-545c-4526-9d30-626815d57023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644813172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2644813172
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3166939190
Short name T694
Test name
Test status
Simulation time 186633948 ps
CPU time 2.84 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:17 PM PDT 24
Peak memory 206968 kb
Host smart-4e422eff-46a7-4e5a-b5ec-ad4e0c438497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166939190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3166939190
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.5520579
Short name T592
Test name
Test status
Simulation time 216924634 ps
CPU time 3.03 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:17 PM PDT 24
Peak memory 206800 kb
Host smart-22f93024-6322-4b8b-b5bf-6918309b701b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5520579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.5520579
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2654439615
Short name T915
Test name
Test status
Simulation time 371694597 ps
CPU time 4.63 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:19 PM PDT 24
Peak memory 206984 kb
Host smart-98601a93-1cd0-4ead-8d87-35d861f3851f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654439615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2654439615
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2025408286
Short name T215
Test name
Test status
Simulation time 332992262 ps
CPU time 8.22 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:22 PM PDT 24
Peak memory 208684 kb
Host smart-a066c79a-3a1e-4264-aaae-5d3839b1b30a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025408286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2025408286
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.33810154
Short name T688
Test name
Test status
Simulation time 36858463 ps
CPU time 2.76 seconds
Started Aug 11 06:05:13 PM PDT 24
Finished Aug 11 06:05:16 PM PDT 24
Peak memory 214320 kb
Host smart-9b617447-2140-49dd-acba-beeed0c8a5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33810154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.33810154
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1262202567
Short name T833
Test name
Test status
Simulation time 20701874620 ps
CPU time 52.93 seconds
Started Aug 11 06:05:15 PM PDT 24
Finished Aug 11 06:06:08 PM PDT 24
Peak memory 208844 kb
Host smart-bec31ec5-f9e7-4590-add0-09a129c3eb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262202567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1262202567
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3805637592
Short name T304
Test name
Test status
Simulation time 1764723435 ps
CPU time 34.89 seconds
Started Aug 11 06:05:10 PM PDT 24
Finished Aug 11 06:05:45 PM PDT 24
Peak memory 222408 kb
Host smart-617a1081-8088-4a39-804d-c8b17d29204b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805637592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3805637592
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2216224274
Short name T185
Test name
Test status
Simulation time 379779574 ps
CPU time 12.79 seconds
Started Aug 11 06:05:17 PM PDT 24
Finished Aug 11 06:05:30 PM PDT 24
Peak memory 222548 kb
Host smart-468b766e-221c-4b29-b9fb-907a807ddd8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216224274 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2216224274
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2904664579
Short name T281
Test name
Test status
Simulation time 147363857 ps
CPU time 5.19 seconds
Started Aug 11 06:05:16 PM PDT 24
Finished Aug 11 06:05:21 PM PDT 24
Peak memory 208388 kb
Host smart-6a5c6c4a-7c72-4fa7-874c-b5b1ad9eeecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904664579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2904664579
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1332364190
Short name T172
Test name
Test status
Simulation time 257897099 ps
CPU time 2.44 seconds
Started Aug 11 06:05:13 PM PDT 24
Finished Aug 11 06:05:16 PM PDT 24
Peak memory 210044 kb
Host smart-c4a0f8c7-8be3-4256-953b-d4f2f995cad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332364190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1332364190
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.527291127
Short name T869
Test name
Test status
Simulation time 44696665 ps
CPU time 0.85 seconds
Started Aug 11 06:05:24 PM PDT 24
Finished Aug 11 06:05:25 PM PDT 24
Peak memory 206004 kb
Host smart-8cb91737-6fcf-4fb8-9ec4-01f52c197e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527291127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.527291127
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2534116575
Short name T67
Test name
Test status
Simulation time 31119821 ps
CPU time 1.89 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:16 PM PDT 24
Peak memory 215500 kb
Host smart-e6e10473-9716-4aed-ac78-2152612b6f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534116575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2534116575
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1085295544
Short name T360
Test name
Test status
Simulation time 116293009 ps
CPU time 2.17 seconds
Started Aug 11 06:05:12 PM PDT 24
Finished Aug 11 06:05:14 PM PDT 24
Peak memory 222380 kb
Host smart-a602a1d6-de20-4d39-8cfd-f0caf261d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085295544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1085295544
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.808974757
Short name T614
Test name
Test status
Simulation time 38716658 ps
CPU time 2.83 seconds
Started Aug 11 06:05:15 PM PDT 24
Finished Aug 11 06:05:17 PM PDT 24
Peak memory 220324 kb
Host smart-94627ecf-5c4f-4c2f-b06d-e4a5ec60cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808974757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.808974757
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1414507581
Short name T513
Test name
Test status
Simulation time 29096074 ps
CPU time 2.12 seconds
Started Aug 11 06:05:12 PM PDT 24
Finished Aug 11 06:05:15 PM PDT 24
Peak memory 219272 kb
Host smart-41969319-251c-498c-bf4c-2275612526a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414507581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1414507581
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3517844653
Short name T914
Test name
Test status
Simulation time 476432168 ps
CPU time 5.55 seconds
Started Aug 11 06:05:15 PM PDT 24
Finished Aug 11 06:05:21 PM PDT 24
Peak memory 207924 kb
Host smart-03128a3d-5920-459c-819a-8b8e7362cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517844653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3517844653
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3844306063
Short name T84
Test name
Test status
Simulation time 350154035 ps
CPU time 3.72 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:18 PM PDT 24
Peak memory 206828 kb
Host smart-b8eca382-06ad-489b-9e4f-cc11207511e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844306063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3844306063
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.310540725
Short name T620
Test name
Test status
Simulation time 194984211 ps
CPU time 2.74 seconds
Started Aug 11 06:05:13 PM PDT 24
Finished Aug 11 06:05:16 PM PDT 24
Peak memory 206888 kb
Host smart-32a49744-8ffc-441a-b8dc-6d7a6adb877a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310540725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.310540725
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.314407754
Short name T724
Test name
Test status
Simulation time 21624367 ps
CPU time 1.8 seconds
Started Aug 11 06:05:14 PM PDT 24
Finished Aug 11 06:05:16 PM PDT 24
Peak memory 206972 kb
Host smart-594dc550-2039-49d2-9b6a-9a592b73f015
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314407754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.314407754
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.469662651
Short name T268
Test name
Test status
Simulation time 157048690 ps
CPU time 3.64 seconds
Started Aug 11 06:05:16 PM PDT 24
Finished Aug 11 06:05:20 PM PDT 24
Peak memory 218332 kb
Host smart-dae5c6a8-d022-4f00-a821-d9163458882b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469662651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.469662651
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2908425706
Short name T622
Test name
Test status
Simulation time 186440290 ps
CPU time 2.5 seconds
Started Aug 11 06:05:18 PM PDT 24
Finished Aug 11 06:05:20 PM PDT 24
Peak memory 206720 kb
Host smart-467f83a9-e8b1-4aaf-ab30-52d7ac186622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908425706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2908425706
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1392085108
Short name T68
Test name
Test status
Simulation time 50666715822 ps
CPU time 509.14 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:13:51 PM PDT 24
Peak memory 218168 kb
Host smart-9953afb6-12f5-4e40-bd2b-ebb4d4b5abd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392085108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1392085108
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2740576882
Short name T184
Test name
Test status
Simulation time 1399493628 ps
CPU time 14.3 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:05:36 PM PDT 24
Peak memory 220804 kb
Host smart-ec9f7d13-8793-47ff-a222-960b58ff730e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740576882 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2740576882
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2279079815
Short name T373
Test name
Test status
Simulation time 384116226 ps
CPU time 6.15 seconds
Started Aug 11 06:05:15 PM PDT 24
Finished Aug 11 06:05:21 PM PDT 24
Peak memory 209240 kb
Host smart-d55ab969-23df-4a93-93b4-d4a1b4f9ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279079815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2279079815
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3934625974
Short name T655
Test name
Test status
Simulation time 73017872 ps
CPU time 3 seconds
Started Aug 11 06:05:20 PM PDT 24
Finished Aug 11 06:05:23 PM PDT 24
Peak memory 209764 kb
Host smart-ca4b2d4e-704a-43d4-a14b-3da48a0fa9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934625974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3934625974
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2318664624
Short name T452
Test name
Test status
Simulation time 97974230 ps
CPU time 0.76 seconds
Started Aug 11 06:05:23 PM PDT 24
Finished Aug 11 06:05:24 PM PDT 24
Peak memory 205848 kb
Host smart-ba9a12ff-7b65-4206-9f98-6803929eb213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318664624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2318664624
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.345728928
Short name T601
Test name
Test status
Simulation time 96362186 ps
CPU time 4.04 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:05:26 PM PDT 24
Peak memory 208988 kb
Host smart-f33b7206-5dc1-4e00-b3cb-d7a0d0580c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345728928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.345728928
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3463826555
Short name T301
Test name
Test status
Simulation time 157054854 ps
CPU time 4.58 seconds
Started Aug 11 06:05:25 PM PDT 24
Finished Aug 11 06:05:30 PM PDT 24
Peak memory 209700 kb
Host smart-051b5aff-97d1-42f5-94c0-bde671aa2546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463826555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3463826555
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.159202161
Short name T541
Test name
Test status
Simulation time 297718463 ps
CPU time 6.67 seconds
Started Aug 11 06:05:25 PM PDT 24
Finished Aug 11 06:05:31 PM PDT 24
Peak memory 214276 kb
Host smart-5bfa68ba-959b-4c14-b0a7-a7a4009ff6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159202161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.159202161
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1062743523
Short name T825
Test name
Test status
Simulation time 289696712 ps
CPU time 3.42 seconds
Started Aug 11 06:05:23 PM PDT 24
Finished Aug 11 06:05:26 PM PDT 24
Peak memory 214144 kb
Host smart-e25285e1-23d8-407d-8db6-a9b250b3954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062743523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1062743523
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.554752260
Short name T868
Test name
Test status
Simulation time 204789267 ps
CPU time 2.76 seconds
Started Aug 11 06:05:21 PM PDT 24
Finished Aug 11 06:05:24 PM PDT 24
Peak memory 222432 kb
Host smart-ff946ebf-d80f-4ea3-89f0-bad26d322e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554752260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.554752260
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3408396330
Short name T358
Test name
Test status
Simulation time 36283812 ps
CPU time 1.89 seconds
Started Aug 11 06:05:21 PM PDT 24
Finished Aug 11 06:05:23 PM PDT 24
Peak memory 206888 kb
Host smart-5512a25a-df43-4084-88fd-3b5fd1cc42d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408396330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3408396330
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2122104685
Short name T531
Test name
Test status
Simulation time 134545615 ps
CPU time 4.95 seconds
Started Aug 11 06:05:21 PM PDT 24
Finished Aug 11 06:05:26 PM PDT 24
Peak memory 208124 kb
Host smart-cc9fc6f7-d04a-4204-b537-0c0031e2a160
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122104685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2122104685
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2134480699
Short name T916
Test name
Test status
Simulation time 135181660 ps
CPU time 3.43 seconds
Started Aug 11 06:05:26 PM PDT 24
Finished Aug 11 06:05:29 PM PDT 24
Peak memory 207628 kb
Host smart-96d4d6c0-1004-4454-b739-be6d3e4fab6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134480699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2134480699
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1151256744
Short name T482
Test name
Test status
Simulation time 237031290 ps
CPU time 3.57 seconds
Started Aug 11 06:05:24 PM PDT 24
Finished Aug 11 06:05:28 PM PDT 24
Peak memory 218308 kb
Host smart-b6a3a5c0-950e-48bc-8b22-93ab78f64190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151256744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1151256744
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.632150117
Short name T573
Test name
Test status
Simulation time 187098803 ps
CPU time 2.55 seconds
Started Aug 11 06:05:23 PM PDT 24
Finished Aug 11 06:05:26 PM PDT 24
Peak memory 206756 kb
Host smart-c3fe0fde-5850-4c70-8c86-a62e5c756648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632150117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.632150117
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2795573634
Short name T836
Test name
Test status
Simulation time 3309512575 ps
CPU time 37.47 seconds
Started Aug 11 06:05:23 PM PDT 24
Finished Aug 11 06:06:01 PM PDT 24
Peak memory 217008 kb
Host smart-63697a69-9ddd-4a79-88e9-e69e4e1f5bc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795573634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2795573634
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1628398192
Short name T848
Test name
Test status
Simulation time 203425075 ps
CPU time 7.22 seconds
Started Aug 11 06:05:25 PM PDT 24
Finished Aug 11 06:05:33 PM PDT 24
Peak memory 222404 kb
Host smart-ffd909ab-07a0-4253-bb85-2266033c5c04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628398192 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1628398192
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2250557518
Short name T283
Test name
Test status
Simulation time 81700901 ps
CPU time 3.95 seconds
Started Aug 11 06:05:23 PM PDT 24
Finished Aug 11 06:05:28 PM PDT 24
Peak memory 209824 kb
Host smart-0ab7e504-e9c0-40a4-b6a3-659f36c02fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250557518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2250557518
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.680055706
Short name T170
Test name
Test status
Simulation time 241623143 ps
CPU time 3.53 seconds
Started Aug 11 06:05:20 PM PDT 24
Finished Aug 11 06:05:24 PM PDT 24
Peak memory 210532 kb
Host smart-df615d07-b824-4fed-b7a6-190b04ea1a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680055706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.680055706
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1176356566
Short name T499
Test name
Test status
Simulation time 179282018 ps
CPU time 0.81 seconds
Started Aug 11 06:05:35 PM PDT 24
Finished Aug 11 06:05:36 PM PDT 24
Peak memory 206000 kb
Host smart-936826a0-4a07-4f7d-bfc7-c3a5e88c3819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176356566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1176356566
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2196735121
Short name T888
Test name
Test status
Simulation time 710204161 ps
CPU time 5.21 seconds
Started Aug 11 06:05:24 PM PDT 24
Finished Aug 11 06:05:29 PM PDT 24
Peak memory 210112 kb
Host smart-3504cbdf-1aa9-4350-b666-1494cee9cc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196735121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2196735121
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.4283624510
Short name T319
Test name
Test status
Simulation time 149113205 ps
CPU time 3.09 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:05:25 PM PDT 24
Peak memory 207464 kb
Host smart-1ea63592-7b8f-413e-b66d-fdbe21eebbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283624510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.4283624510
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.152521482
Short name T701
Test name
Test status
Simulation time 67472161 ps
CPU time 2.74 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:05:25 PM PDT 24
Peak memory 214476 kb
Host smart-4c7fdfbb-d166-4e65-b6e4-1650106d3a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152521482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.152521482
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3373469331
Short name T646
Test name
Test status
Simulation time 355333100 ps
CPU time 3.75 seconds
Started Aug 11 06:05:24 PM PDT 24
Finished Aug 11 06:05:27 PM PDT 24
Peak memory 222492 kb
Host smart-70b9f428-27ad-47c7-9288-7f36ed522d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373469331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3373469331
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1677883454
Short name T235
Test name
Test status
Simulation time 68296550 ps
CPU time 4.12 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:05:27 PM PDT 24
Peak memory 209364 kb
Host smart-cd310cd5-15c0-4722-aec4-b9346d93cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677883454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1677883454
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3144930589
Short name T494
Test name
Test status
Simulation time 205274130 ps
CPU time 3.7 seconds
Started Aug 11 06:05:23 PM PDT 24
Finished Aug 11 06:05:27 PM PDT 24
Peak memory 207592 kb
Host smart-49091dd1-1ec3-4269-b095-6597a84d4765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144930589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3144930589
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1671647653
Short name T647
Test name
Test status
Simulation time 232384606 ps
CPU time 3.13 seconds
Started Aug 11 06:05:19 PM PDT 24
Finished Aug 11 06:05:23 PM PDT 24
Peak memory 208708 kb
Host smart-2fdd833c-f882-49b8-85f9-57a9bee239b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671647653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1671647653
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1630334504
Short name T305
Test name
Test status
Simulation time 65278567 ps
CPU time 3.25 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:05:25 PM PDT 24
Peak memory 208860 kb
Host smart-441306ab-3efb-4b83-9502-f03844ca98b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630334504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1630334504
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3349724728
Short name T784
Test name
Test status
Simulation time 52454894 ps
CPU time 2.75 seconds
Started Aug 11 06:05:25 PM PDT 24
Finished Aug 11 06:05:28 PM PDT 24
Peak memory 206864 kb
Host smart-f08027ee-f354-4bdf-874d-123bb23bd825
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349724728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3349724728
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.474140994
Short name T484
Test name
Test status
Simulation time 27982590 ps
CPU time 1.89 seconds
Started Aug 11 06:05:22 PM PDT 24
Finished Aug 11 06:05:24 PM PDT 24
Peak memory 206808 kb
Host smart-77ff8568-ee1a-4519-846f-e8ca0429f767
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474140994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.474140994
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1177075520
Short name T263
Test name
Test status
Simulation time 221580245 ps
CPU time 2.35 seconds
Started Aug 11 06:05:25 PM PDT 24
Finished Aug 11 06:05:27 PM PDT 24
Peak memory 208372 kb
Host smart-23180437-a761-49a2-baa1-646a2ae41fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177075520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1177075520
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1442867306
Short name T679
Test name
Test status
Simulation time 346039784 ps
CPU time 9.76 seconds
Started Aug 11 06:05:23 PM PDT 24
Finished Aug 11 06:05:33 PM PDT 24
Peak memory 208768 kb
Host smart-e5e3ca34-f309-4dec-a1be-9bf2e4b49fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442867306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1442867306
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3424805538
Short name T857
Test name
Test status
Simulation time 656446539 ps
CPU time 18.47 seconds
Started Aug 11 06:05:24 PM PDT 24
Finished Aug 11 06:05:43 PM PDT 24
Peak memory 216932 kb
Host smart-c4fdb9ca-da90-4a3a-a279-b9bfed7cacb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424805538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3424805538
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.394517097
Short name T844
Test name
Test status
Simulation time 211892099 ps
CPU time 5.13 seconds
Started Aug 11 06:05:24 PM PDT 24
Finished Aug 11 06:05:29 PM PDT 24
Peak memory 214344 kb
Host smart-b473de68-3302-4ec9-9926-810da32cb00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394517097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.394517097
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1422861685
Short name T749
Test name
Test status
Simulation time 1208113529 ps
CPU time 4.08 seconds
Started Aug 11 06:05:23 PM PDT 24
Finished Aug 11 06:05:28 PM PDT 24
Peak memory 210324 kb
Host smart-130a202f-1447-4b41-bb5e-8f9f259c2a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422861685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1422861685
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2394490235
Short name T105
Test name
Test status
Simulation time 79019656 ps
CPU time 0.94 seconds
Started Aug 11 06:05:37 PM PDT 24
Finished Aug 11 06:05:38 PM PDT 24
Peak memory 206100 kb
Host smart-b6756859-bf4d-4560-ae6e-3a031d7068cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394490235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2394490235
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1458081056
Short name T421
Test name
Test status
Simulation time 83466478 ps
CPU time 3.71 seconds
Started Aug 11 06:05:37 PM PDT 24
Finished Aug 11 06:05:41 PM PDT 24
Peak memory 222372 kb
Host smart-050b138e-aaa3-4e66-87a6-ccc8c8e7fc2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458081056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1458081056
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.68892231
Short name T2
Test name
Test status
Simulation time 51481680 ps
CPU time 1.93 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:40 PM PDT 24
Peak memory 214320 kb
Host smart-44da6ab5-5385-47a3-88d4-edb78c548dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68892231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.68892231
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.755178239
Short name T609
Test name
Test status
Simulation time 283094634 ps
CPU time 7.44 seconds
Started Aug 11 06:05:32 PM PDT 24
Finished Aug 11 06:05:40 PM PDT 24
Peak memory 214232 kb
Host smart-499f30ee-42ba-42c7-bb75-9a08fc00357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755178239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.755178239
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2066084558
Short name T115
Test name
Test status
Simulation time 110021292 ps
CPU time 2.12 seconds
Started Aug 11 06:05:36 PM PDT 24
Finished Aug 11 06:05:38 PM PDT 24
Peak memory 214140 kb
Host smart-72f1f36d-e6bf-494a-9a7f-ffdb211b6323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066084558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2066084558
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3360041117
Short name T755
Test name
Test status
Simulation time 329827767 ps
CPU time 3.21 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:42 PM PDT 24
Peak memory 207044 kb
Host smart-76bc3c61-8a56-4aae-b2e9-24417984c3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360041117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3360041117
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1430750754
Short name T350
Test name
Test status
Simulation time 121132354 ps
CPU time 3.33 seconds
Started Aug 11 06:05:31 PM PDT 24
Finished Aug 11 06:05:34 PM PDT 24
Peak memory 207436 kb
Host smart-6d563746-91b8-42fb-b496-b8d087331cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430750754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1430750754
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3731148681
Short name T314
Test name
Test status
Simulation time 118009402 ps
CPU time 2.93 seconds
Started Aug 11 06:05:30 PM PDT 24
Finished Aug 11 06:05:33 PM PDT 24
Peak memory 206796 kb
Host smart-a3cb30ef-e285-461b-ba10-c2b479f7fdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731148681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3731148681
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1431782512
Short name T438
Test name
Test status
Simulation time 105700799 ps
CPU time 3.46 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:42 PM PDT 24
Peak memory 208468 kb
Host smart-2a122187-942a-4156-9690-5eab2b60fd94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431782512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1431782512
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2411672820
Short name T571
Test name
Test status
Simulation time 290118416 ps
CPU time 3.72 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:42 PM PDT 24
Peak memory 208940 kb
Host smart-ef441eae-903e-41b9-a176-a1608ab0cc70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411672820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2411672820
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1825346129
Short name T261
Test name
Test status
Simulation time 97986383 ps
CPU time 2.94 seconds
Started Aug 11 06:05:29 PM PDT 24
Finished Aug 11 06:05:32 PM PDT 24
Peak memory 206924 kb
Host smart-af7892a4-d614-4cf3-9531-220fa91a483b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825346129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1825346129
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.417090718
Short name T443
Test name
Test status
Simulation time 197490731 ps
CPU time 2.8 seconds
Started Aug 11 06:05:32 PM PDT 24
Finished Aug 11 06:05:35 PM PDT 24
Peak memory 215580 kb
Host smart-5f227b12-5cab-4937-bd6e-401fc73a3e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417090718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.417090718
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.4031188733
Short name T623
Test name
Test status
Simulation time 40016036 ps
CPU time 2.69 seconds
Started Aug 11 06:05:30 PM PDT 24
Finished Aug 11 06:05:33 PM PDT 24
Peak memory 208876 kb
Host smart-ab9fda50-ed05-48b7-8e34-d0659790c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031188733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4031188733
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3284527866
Short name T72
Test name
Test status
Simulation time 277083832 ps
CPU time 3.57 seconds
Started Aug 11 06:05:31 PM PDT 24
Finished Aug 11 06:05:34 PM PDT 24
Peak memory 209988 kb
Host smart-c1be4a5b-7bbe-4306-a024-9707db777bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284527866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3284527866
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3215560602
Short name T854
Test name
Test status
Simulation time 1527802009 ps
CPU time 7.14 seconds
Started Aug 11 06:05:30 PM PDT 24
Finished Aug 11 06:05:37 PM PDT 24
Peak memory 208560 kb
Host smart-8a9293c7-66ca-4f8e-a073-19f56f952915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215560602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3215560602
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1634280309
Short name T734
Test name
Test status
Simulation time 143806382 ps
CPU time 3.29 seconds
Started Aug 11 06:05:36 PM PDT 24
Finished Aug 11 06:05:39 PM PDT 24
Peak memory 210312 kb
Host smart-cffff747-bf1c-426e-908a-3b4e5272d1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634280309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1634280309
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4170801824
Short name T786
Test name
Test status
Simulation time 80797654 ps
CPU time 0.91 seconds
Started Aug 11 06:05:32 PM PDT 24
Finished Aug 11 06:05:33 PM PDT 24
Peak memory 206148 kb
Host smart-f6d8f645-a79e-4cee-a265-fbb5256446f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170801824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4170801824
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.949151657
Short name T785
Test name
Test status
Simulation time 345576966 ps
CPU time 4.05 seconds
Started Aug 11 06:05:27 PM PDT 24
Finished Aug 11 06:05:32 PM PDT 24
Peak memory 214192 kb
Host smart-18e375cb-3594-4ed0-9163-6b78c19e836d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949151657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.949151657
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1825967817
Short name T635
Test name
Test status
Simulation time 176545255 ps
CPU time 2.02 seconds
Started Aug 11 06:05:30 PM PDT 24
Finished Aug 11 06:05:32 PM PDT 24
Peak memory 214336 kb
Host smart-7ad7bdb3-1385-4d7e-b4af-c52cc473f1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825967817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1825967817
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1168264004
Short name T93
Test name
Test status
Simulation time 104695915 ps
CPU time 3.15 seconds
Started Aug 11 06:05:32 PM PDT 24
Finished Aug 11 06:05:35 PM PDT 24
Peak memory 222680 kb
Host smart-6e003775-8d54-4873-b90a-e90696360eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168264004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1168264004
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3522958455
Short name T690
Test name
Test status
Simulation time 378578013 ps
CPU time 3.04 seconds
Started Aug 11 06:05:40 PM PDT 24
Finished Aug 11 06:05:43 PM PDT 24
Peak memory 214240 kb
Host smart-86374596-0201-4827-bc0b-3baece29f6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522958455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3522958455
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4164965407
Short name T224
Test name
Test status
Simulation time 843631995 ps
CPU time 3.11 seconds
Started Aug 11 06:05:34 PM PDT 24
Finished Aug 11 06:05:37 PM PDT 24
Peak memory 214360 kb
Host smart-0a670b00-29d7-4cba-9cdb-f5eaae437bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164965407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4164965407
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.675196503
Short name T12
Test name
Test status
Simulation time 278211847 ps
CPU time 7.37 seconds
Started Aug 11 06:05:35 PM PDT 24
Finished Aug 11 06:05:43 PM PDT 24
Peak memory 207900 kb
Host smart-ffb6f5a2-d146-412b-9db0-7eac131fa7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675196503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.675196503
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.329744944
Short name T773
Test name
Test status
Simulation time 82891182 ps
CPU time 1.75 seconds
Started Aug 11 06:05:29 PM PDT 24
Finished Aug 11 06:05:31 PM PDT 24
Peak memory 207492 kb
Host smart-692d39e2-b5d5-4799-8e16-c16c7416a926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329744944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.329744944
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.149726417
Short name T204
Test name
Test status
Simulation time 1841286262 ps
CPU time 42.51 seconds
Started Aug 11 06:05:30 PM PDT 24
Finished Aug 11 06:06:12 PM PDT 24
Peak memory 208156 kb
Host smart-224b81c4-0ef2-4069-8b62-6ee86ee5ebf5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149726417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.149726417
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.649803508
Short name T522
Test name
Test status
Simulation time 1220575310 ps
CPU time 4.67 seconds
Started Aug 11 06:05:40 PM PDT 24
Finished Aug 11 06:05:44 PM PDT 24
Peak memory 208348 kb
Host smart-eef53e1c-870f-4259-b02b-fe66969f64d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649803508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.649803508
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3424994245
Short name T495
Test name
Test status
Simulation time 151453046 ps
CPU time 2.42 seconds
Started Aug 11 06:05:36 PM PDT 24
Finished Aug 11 06:05:38 PM PDT 24
Peak memory 206832 kb
Host smart-a6eeb46f-fd97-4765-957d-da823972a326
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424994245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3424994245
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4015250495
Short name T462
Test name
Test status
Simulation time 551002512 ps
CPU time 6.63 seconds
Started Aug 11 06:05:36 PM PDT 24
Finished Aug 11 06:05:43 PM PDT 24
Peak memory 218448 kb
Host smart-1cea48e8-0401-4af6-a683-2cae54f25bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015250495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4015250495
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.442249298
Short name T791
Test name
Test status
Simulation time 100947471 ps
CPU time 2.59 seconds
Started Aug 11 06:05:35 PM PDT 24
Finished Aug 11 06:05:37 PM PDT 24
Peak memory 206700 kb
Host smart-89c2f71e-5382-4ecc-b674-5acbed79b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442249298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.442249298
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.564169014
Short name T71
Test name
Test status
Simulation time 1337729151 ps
CPU time 28.5 seconds
Started Aug 11 06:05:28 PM PDT 24
Finished Aug 11 06:05:57 PM PDT 24
Peak memory 216260 kb
Host smart-5b6556b0-3511-405a-be7d-e124deaa4730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564169014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.564169014
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4136332904
Short name T186
Test name
Test status
Simulation time 2363391982 ps
CPU time 29.1 seconds
Started Aug 11 06:05:29 PM PDT 24
Finished Aug 11 06:05:59 PM PDT 24
Peak memory 222596 kb
Host smart-8effec89-8bce-49aa-9c3f-f58c0b171c0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136332904 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4136332904
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1419681857
Short name T636
Test name
Test status
Simulation time 2360388989 ps
CPU time 6.98 seconds
Started Aug 11 06:05:29 PM PDT 24
Finished Aug 11 06:05:36 PM PDT 24
Peak memory 218804 kb
Host smart-815edd49-1b1c-4fe2-b1cc-870dfd4fb5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419681857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1419681857
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2766089412
Short name T78
Test name
Test status
Simulation time 108287647 ps
CPU time 2.18 seconds
Started Aug 11 06:05:32 PM PDT 24
Finished Aug 11 06:05:34 PM PDT 24
Peak memory 210104 kb
Host smart-fa3c4026-8a03-4e3a-9f57-67036023b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766089412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2766089412
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2259531624
Short name T516
Test name
Test status
Simulation time 9098615 ps
CPU time 0.8 seconds
Started Aug 11 06:05:41 PM PDT 24
Finished Aug 11 06:05:42 PM PDT 24
Peak memory 205920 kb
Host smart-366ee469-952c-4d3c-aeaa-7e2c5fe9f75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259531624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2259531624
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.500857961
Short name T27
Test name
Test status
Simulation time 462570820 ps
CPU time 7.52 seconds
Started Aug 11 06:05:40 PM PDT 24
Finished Aug 11 06:05:48 PM PDT 24
Peak memory 214468 kb
Host smart-18a00540-948b-4fa3-829e-1a95ec245141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500857961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.500857961
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.419981324
Short name T295
Test name
Test status
Simulation time 299415505 ps
CPU time 3.03 seconds
Started Aug 11 06:05:34 PM PDT 24
Finished Aug 11 06:05:38 PM PDT 24
Peak memory 214240 kb
Host smart-a0a000ec-e985-4f73-88fe-4fe1964260e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419981324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.419981324
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2307633057
Short name T644
Test name
Test status
Simulation time 87766512 ps
CPU time 4.11 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:42 PM PDT 24
Peak memory 214288 kb
Host smart-1adf0b37-7885-4ebd-94ef-0138857b14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307633057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2307633057
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.386592847
Short name T902
Test name
Test status
Simulation time 290419001 ps
CPU time 2.34 seconds
Started Aug 11 06:05:37 PM PDT 24
Finished Aug 11 06:05:39 PM PDT 24
Peak memory 208348 kb
Host smart-f23333cf-f37c-4612-b7c8-2f543691d19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386592847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.386592847
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.814141298
Short name T895
Test name
Test status
Simulation time 112315497 ps
CPU time 4.96 seconds
Started Aug 11 06:05:30 PM PDT 24
Finished Aug 11 06:05:35 PM PDT 24
Peak memory 209992 kb
Host smart-5f67ca06-3dfe-4d46-84fb-a3559436a8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814141298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.814141298
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3546101896
Short name T288
Test name
Test status
Simulation time 542532147 ps
CPU time 4.29 seconds
Started Aug 11 06:05:35 PM PDT 24
Finished Aug 11 06:05:40 PM PDT 24
Peak memory 206848 kb
Host smart-ecf2c43d-45f3-46ae-ab61-b8ae42b15e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546101896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3546101896
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3783815824
Short name T653
Test name
Test status
Simulation time 74388608 ps
CPU time 2.93 seconds
Started Aug 11 06:05:36 PM PDT 24
Finished Aug 11 06:05:39 PM PDT 24
Peak memory 206816 kb
Host smart-47522a85-ba07-4b71-9a82-f9abe205a2af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783815824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3783815824
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1742092298
Short name T213
Test name
Test status
Simulation time 2990987946 ps
CPU time 19.53 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:58 PM PDT 24
Peak memory 208816 kb
Host smart-267a963b-7ee6-4b48-bd97-89548d37a63f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742092298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1742092298
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.4257136340
Short name T708
Test name
Test status
Simulation time 172409003 ps
CPU time 2.66 seconds
Started Aug 11 06:05:36 PM PDT 24
Finished Aug 11 06:05:39 PM PDT 24
Peak memory 207144 kb
Host smart-36f1b6fc-b1a0-4bf1-bbf4-beac9dedb816
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257136340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.4257136340
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1546521729
Short name T630
Test name
Test status
Simulation time 3028640268 ps
CPU time 5.57 seconds
Started Aug 11 06:05:37 PM PDT 24
Finished Aug 11 06:05:42 PM PDT 24
Peak memory 209756 kb
Host smart-691068cd-6beb-4a51-ae00-9e137afe7079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546521729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1546521729
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1805571353
Short name T496
Test name
Test status
Simulation time 541129972 ps
CPU time 4.23 seconds
Started Aug 11 06:05:28 PM PDT 24
Finished Aug 11 06:05:33 PM PDT 24
Peak memory 207948 kb
Host smart-75f34b5a-e2ce-4a95-a45a-db96e772c230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805571353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1805571353
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1966708510
Short name T312
Test name
Test status
Simulation time 2608811066 ps
CPU time 22.8 seconds
Started Aug 11 06:05:42 PM PDT 24
Finished Aug 11 06:06:05 PM PDT 24
Peak memory 221036 kb
Host smart-fba05f31-d6e7-4508-aba7-e16ce056eb87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966708510 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1966708510
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3063837607
Short name T198
Test name
Test status
Simulation time 944181107 ps
CPU time 5.74 seconds
Started Aug 11 06:05:30 PM PDT 24
Finished Aug 11 06:05:36 PM PDT 24
Peak memory 210360 kb
Host smart-4235673c-c517-490e-a8f1-57627c30b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063837607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3063837607
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3421475949
Short name T758
Test name
Test status
Simulation time 150146653 ps
CPU time 2.14 seconds
Started Aug 11 06:05:40 PM PDT 24
Finished Aug 11 06:05:42 PM PDT 24
Peak memory 210272 kb
Host smart-7622f703-40db-4d27-8ac3-96c7df5fd5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421475949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3421475949
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.33100823
Short name T707
Test name
Test status
Simulation time 29614928 ps
CPU time 0.83 seconds
Started Aug 11 06:05:42 PM PDT 24
Finished Aug 11 06:05:43 PM PDT 24
Peak memory 205636 kb
Host smart-cbd29590-35f6-44ea-be94-4d496ac08f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33100823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.33100823
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.505451434
Short name T410
Test name
Test status
Simulation time 131711266 ps
CPU time 2.86 seconds
Started Aug 11 06:05:39 PM PDT 24
Finished Aug 11 06:05:42 PM PDT 24
Peak memory 214244 kb
Host smart-d56b8755-1986-4ff1-b4b0-1c284f341e83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505451434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.505451434
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4239656787
Short name T380
Test name
Test status
Simulation time 411067389 ps
CPU time 7.35 seconds
Started Aug 11 06:05:44 PM PDT 24
Finished Aug 11 06:05:51 PM PDT 24
Peak memory 207756 kb
Host smart-df7c1a51-0ee4-4943-8e4d-dcfb05ccb033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239656787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4239656787
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3638629688
Short name T361
Test name
Test status
Simulation time 177971213 ps
CPU time 2.49 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:40 PM PDT 24
Peak memory 214184 kb
Host smart-ec234c94-c165-4123-833b-f1f63bf2114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638629688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3638629688
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.486087413
Short name T111
Test name
Test status
Simulation time 132063652 ps
CPU time 3.76 seconds
Started Aug 11 06:05:45 PM PDT 24
Finished Aug 11 06:05:49 PM PDT 24
Peak memory 220748 kb
Host smart-ace25511-2133-4cd5-a13a-838d7d8cf95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486087413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.486087413
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2062607448
Short name T530
Test name
Test status
Simulation time 437341991 ps
CPU time 2.56 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:41 PM PDT 24
Peak memory 207752 kb
Host smart-064d3413-312a-4e6c-885c-9840f940e0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062607448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2062607448
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3273209008
Short name T311
Test name
Test status
Simulation time 76857329 ps
CPU time 3.63 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:42 PM PDT 24
Peak memory 218296 kb
Host smart-ec518cd1-693c-4762-b4e0-f78f26085158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273209008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3273209008
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.867372189
Short name T386
Test name
Test status
Simulation time 117027331 ps
CPU time 3.51 seconds
Started Aug 11 06:05:42 PM PDT 24
Finished Aug 11 06:05:45 PM PDT 24
Peak memory 206572 kb
Host smart-b628fa1a-d3d9-4efd-b40d-c1bb5e7c0f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867372189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.867372189
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.533906691
Short name T882
Test name
Test status
Simulation time 971027390 ps
CPU time 3.11 seconds
Started Aug 11 06:05:38 PM PDT 24
Finished Aug 11 06:05:41 PM PDT 24
Peak memory 208520 kb
Host smart-2fe9dc23-df45-4d86-b3e4-a9fb4715e74f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533906691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.533906691
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3980434674
Short name T884
Test name
Test status
Simulation time 1579211018 ps
CPU time 24.36 seconds
Started Aug 11 06:05:40 PM PDT 24
Finished Aug 11 06:06:05 PM PDT 24
Peak memory 207820 kb
Host smart-e8d4c7d4-f008-4b5b-b15f-5101e7852b3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980434674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3980434674
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.541197816
Short name T815
Test name
Test status
Simulation time 196131774 ps
CPU time 2.7 seconds
Started Aug 11 06:05:36 PM PDT 24
Finished Aug 11 06:05:38 PM PDT 24
Peak memory 206708 kb
Host smart-caab717f-f18e-4b4d-a755-45f4a58e8dd6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541197816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.541197816
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.614318151
Short name T81
Test name
Test status
Simulation time 112199728 ps
CPU time 3.46 seconds
Started Aug 11 06:05:42 PM PDT 24
Finished Aug 11 06:05:45 PM PDT 24
Peak memory 207372 kb
Host smart-b124cbbd-9df0-4ada-806e-848b68d20b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614318151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.614318151
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.75272224
Short name T431
Test name
Test status
Simulation time 603785220 ps
CPU time 3.66 seconds
Started Aug 11 06:05:42 PM PDT 24
Finished Aug 11 06:05:45 PM PDT 24
Peak memory 208704 kb
Host smart-a0f480c6-b002-4f80-b674-f975ecac2b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75272224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.75272224
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3441416657
Short name T334
Test name
Test status
Simulation time 7456406386 ps
CPU time 175.79 seconds
Started Aug 11 06:05:39 PM PDT 24
Finished Aug 11 06:08:35 PM PDT 24
Peak memory 217296 kb
Host smart-b6cdb78e-1f2e-4688-8174-677f65bcc433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441416657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3441416657
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.982385644
Short name T843
Test name
Test status
Simulation time 368197364 ps
CPU time 4.48 seconds
Started Aug 11 06:05:40 PM PDT 24
Finished Aug 11 06:05:45 PM PDT 24
Peak memory 208832 kb
Host smart-df1a7a3f-4343-4075-aada-b9c3fdf5aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982385644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.982385644
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3439446047
Short name T637
Test name
Test status
Simulation time 147256412 ps
CPU time 2.61 seconds
Started Aug 11 06:05:36 PM PDT 24
Finished Aug 11 06:05:39 PM PDT 24
Peak memory 210296 kb
Host smart-c1338c7f-16d0-418e-a11a-c22cfe009605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439446047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3439446047
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.219780636
Short name T106
Test name
Test status
Simulation time 48704034 ps
CPU time 0.93 seconds
Started Aug 11 06:05:44 PM PDT 24
Finished Aug 11 06:05:45 PM PDT 24
Peak memory 206072 kb
Host smart-f0ad7b03-f82b-4352-834b-ad25cb27f3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219780636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.219780636
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.397129867
Short name T485
Test name
Test status
Simulation time 594128260 ps
CPU time 4.57 seconds
Started Aug 11 06:05:48 PM PDT 24
Finished Aug 11 06:05:52 PM PDT 24
Peak memory 218196 kb
Host smart-5c9e9902-5f60-4172-ba82-8ce48fc5a946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397129867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.397129867
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4221036049
Short name T405
Test name
Test status
Simulation time 3902185027 ps
CPU time 19.81 seconds
Started Aug 11 06:05:45 PM PDT 24
Finished Aug 11 06:06:05 PM PDT 24
Peak memory 208936 kb
Host smart-c00d6bc2-51c7-48d6-8342-15a39b7deda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221036049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4221036049
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1899469949
Short name T222
Test name
Test status
Simulation time 215614968 ps
CPU time 3.7 seconds
Started Aug 11 06:05:46 PM PDT 24
Finished Aug 11 06:05:50 PM PDT 24
Peak memory 214524 kb
Host smart-49c3d56b-2e62-4d37-8e23-e4ba802e200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899469949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1899469949
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1782358974
Short name T700
Test name
Test status
Simulation time 111735960 ps
CPU time 2.47 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:57 PM PDT 24
Peak memory 208296 kb
Host smart-ce6ff089-a751-4674-8836-e506f5f442a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782358974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1782358974
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.393085903
Short name T733
Test name
Test status
Simulation time 6584934318 ps
CPU time 25.73 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:06:19 PM PDT 24
Peak memory 208696 kb
Host smart-92a21b86-db8a-4167-8227-e7b057cd6cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393085903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.393085903
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2617867165
Short name T537
Test name
Test status
Simulation time 192568415 ps
CPU time 2.87 seconds
Started Aug 11 06:05:49 PM PDT 24
Finished Aug 11 06:05:52 PM PDT 24
Peak memory 207232 kb
Host smart-2b5c7faa-0ff3-48ee-9583-0b2b1d818a4c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617867165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2617867165
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.686041040
Short name T768
Test name
Test status
Simulation time 507760017 ps
CPU time 4.74 seconds
Started Aug 11 06:05:44 PM PDT 24
Finished Aug 11 06:05:49 PM PDT 24
Peak memory 208560 kb
Host smart-e5edd667-c86b-4878-8a5d-14fd9efe4066
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686041040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.686041040
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3005093694
Short name T206
Test name
Test status
Simulation time 357174403 ps
CPU time 3.28 seconds
Started Aug 11 06:05:47 PM PDT 24
Finished Aug 11 06:05:51 PM PDT 24
Peak memory 208564 kb
Host smart-a7c8d858-9d76-4ee2-ba49-7e46662dd6c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005093694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3005093694
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.194259156
Short name T483
Test name
Test status
Simulation time 68407840 ps
CPU time 2.01 seconds
Started Aug 11 06:05:47 PM PDT 24
Finished Aug 11 06:05:49 PM PDT 24
Peak memory 218268 kb
Host smart-af80f903-0d12-4938-96c8-4981f216137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194259156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.194259156
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3313469969
Short name T476
Test name
Test status
Simulation time 1064748781 ps
CPU time 3.89 seconds
Started Aug 11 06:05:37 PM PDT 24
Finished Aug 11 06:05:41 PM PDT 24
Peak memory 206828 kb
Host smart-191b3c95-96b0-42ee-abf0-e7a634425f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313469969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3313469969
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1698601963
Short name T23
Test name
Test status
Simulation time 154448211 ps
CPU time 4.82 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:59 PM PDT 24
Peak memory 210696 kb
Host smart-d4cef668-6ed2-4091-9bb7-e1243368a8ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698601963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1698601963
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1754378253
Short name T856
Test name
Test status
Simulation time 165494163 ps
CPU time 5.35 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:06:00 PM PDT 24
Peak memory 207572 kb
Host smart-ed00911d-9238-4ada-b1c1-d88f7e6b352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754378253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1754378253
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3082077432
Short name T389
Test name
Test status
Simulation time 269813441 ps
CPU time 1.55 seconds
Started Aug 11 06:05:46 PM PDT 24
Finished Aug 11 06:05:47 PM PDT 24
Peak memory 208512 kb
Host smart-0d25dd90-bc76-4317-a5e0-99ba7abf5f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082077432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3082077432
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.103275999
Short name T775
Test name
Test status
Simulation time 14356076 ps
CPU time 0.78 seconds
Started Aug 11 06:04:26 PM PDT 24
Finished Aug 11 06:04:27 PM PDT 24
Peak memory 205848 kb
Host smart-809dc75f-93d0-40ae-9d23-66fa24ee8310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103275999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.103275999
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.830696332
Short name T230
Test name
Test status
Simulation time 910635732 ps
CPU time 5.7 seconds
Started Aug 11 06:04:30 PM PDT 24
Finished Aug 11 06:04:36 PM PDT 24
Peak memory 221660 kb
Host smart-475d9c2b-9079-401b-891a-9638a48187c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830696332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.830696332
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.93110706
Short name T270
Test name
Test status
Simulation time 853697681 ps
CPU time 2.71 seconds
Started Aug 11 06:04:23 PM PDT 24
Finished Aug 11 06:04:25 PM PDT 24
Peak memory 209112 kb
Host smart-7daaf3e0-b087-4abf-bf83-e75ddab26de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93110706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.93110706
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1158062762
Short name T886
Test name
Test status
Simulation time 624960474 ps
CPU time 2.83 seconds
Started Aug 11 06:04:34 PM PDT 24
Finished Aug 11 06:04:37 PM PDT 24
Peak memory 214284 kb
Host smart-e4606e3d-a51b-44b8-b87e-226f97fe3cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158062762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1158062762
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.658187781
Short name T237
Test name
Test status
Simulation time 77699058 ps
CPU time 3.84 seconds
Started Aug 11 06:04:30 PM PDT 24
Finished Aug 11 06:04:34 PM PDT 24
Peak memory 209976 kb
Host smart-383c57d8-f96f-4bb9-ac72-e497065ef76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658187781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.658187781
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.259993599
Short name T693
Test name
Test status
Simulation time 1072617209 ps
CPU time 7.74 seconds
Started Aug 11 06:04:27 PM PDT 24
Finished Aug 11 06:04:34 PM PDT 24
Peak memory 207500 kb
Host smart-b0747885-7b98-4b23-bf4c-b6f8dfae65c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259993599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.259993599
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4045098200
Short name T11
Test name
Test status
Simulation time 459963004 ps
CPU time 14.28 seconds
Started Aug 11 06:04:29 PM PDT 24
Finished Aug 11 06:04:43 PM PDT 24
Peak memory 230428 kb
Host smart-52391dc5-ab1a-4e90-9a88-d37225cea3ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045098200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4045098200
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1745069609
Short name T375
Test name
Test status
Simulation time 30118011 ps
CPU time 1.86 seconds
Started Aug 11 06:04:23 PM PDT 24
Finished Aug 11 06:04:25 PM PDT 24
Peak memory 206644 kb
Host smart-1b7f6c78-8dab-425c-9da5-dff02c69e2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745069609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1745069609
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3199282696
Short name T770
Test name
Test status
Simulation time 75929485 ps
CPU time 3.51 seconds
Started Aug 11 06:04:22 PM PDT 24
Finished Aug 11 06:04:26 PM PDT 24
Peak memory 208712 kb
Host smart-759cc09d-8fe1-41e9-a10a-4f897fea4a8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199282696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3199282696
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1873033389
Short name T628
Test name
Test status
Simulation time 567876166 ps
CPU time 8.26 seconds
Started Aug 11 06:04:26 PM PDT 24
Finished Aug 11 06:04:34 PM PDT 24
Peak memory 208672 kb
Host smart-5f742fae-c5ff-4e3a-a575-8431c333d52d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873033389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1873033389
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3079012524
Short name T897
Test name
Test status
Simulation time 613805679 ps
CPU time 14.82 seconds
Started Aug 11 06:04:23 PM PDT 24
Finished Aug 11 06:04:38 PM PDT 24
Peak memory 208440 kb
Host smart-93cba1fb-7829-4421-ae58-b36b52b4cd6c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079012524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3079012524
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.184215142
Short name T600
Test name
Test status
Simulation time 149008175 ps
CPU time 4.35 seconds
Started Aug 11 06:04:26 PM PDT 24
Finished Aug 11 06:04:30 PM PDT 24
Peak memory 208372 kb
Host smart-3c119f5d-a9e1-40e3-93dc-17cbcc8b89fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184215142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.184215142
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1320555921
Short name T563
Test name
Test status
Simulation time 215739460 ps
CPU time 2.43 seconds
Started Aug 11 06:04:21 PM PDT 24
Finished Aug 11 06:04:23 PM PDT 24
Peak memory 206808 kb
Host smart-72e5cb09-7a8a-486a-ac40-2a9be0cb59a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320555921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1320555921
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1510909480
Short name T328
Test name
Test status
Simulation time 1739632820 ps
CPU time 18.92 seconds
Started Aug 11 06:04:28 PM PDT 24
Finished Aug 11 06:04:47 PM PDT 24
Peak memory 220436 kb
Host smart-85f3b1d3-0782-4073-bca2-f549541c4e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510909480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1510909480
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3783042614
Short name T629
Test name
Test status
Simulation time 378625618 ps
CPU time 4.86 seconds
Started Aug 11 06:04:30 PM PDT 24
Finished Aug 11 06:04:35 PM PDT 24
Peak memory 210140 kb
Host smart-c48652d9-bf49-4055-a148-997305838043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783042614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3783042614
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.47981616
Short name T35
Test name
Test status
Simulation time 59785630 ps
CPU time 1.72 seconds
Started Aug 11 06:04:28 PM PDT 24
Finished Aug 11 06:04:30 PM PDT 24
Peak memory 209836 kb
Host smart-7bb2e9b9-32c8-473f-bde7-d562ec46e6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47981616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.47981616
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1064143925
Short name T478
Test name
Test status
Simulation time 60284389 ps
CPU time 0.69 seconds
Started Aug 11 06:05:56 PM PDT 24
Finished Aug 11 06:05:57 PM PDT 24
Peak memory 205908 kb
Host smart-85af8c02-f0e3-4268-adee-4157b4d01171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064143925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1064143925
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3939328097
Short name T652
Test name
Test status
Simulation time 122503734 ps
CPU time 2.95 seconds
Started Aug 11 06:05:53 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 220204 kb
Host smart-25def20c-f5af-4f5d-ae30-754c798dfbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939328097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3939328097
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1881291562
Short name T568
Test name
Test status
Simulation time 91421703 ps
CPU time 2.01 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 218424 kb
Host smart-efe862e6-4de5-4fb5-8828-1e643b2926e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881291562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1881291562
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1675263074
Short name T855
Test name
Test status
Simulation time 593998624 ps
CPU time 3.42 seconds
Started Aug 11 06:05:45 PM PDT 24
Finished Aug 11 06:05:48 PM PDT 24
Peak memory 221008 kb
Host smart-4752cb51-7b13-4054-a99c-cd3aee675772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675263074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1675263074
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_random.3988623426
Short name T117
Test name
Test status
Simulation time 983163135 ps
CPU time 35.02 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:06:29 PM PDT 24
Peak memory 214388 kb
Host smart-e3f8d7e3-8da7-4923-b9c8-2c66911d4d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988623426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3988623426
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3427218137
Short name T453
Test name
Test status
Simulation time 53748021 ps
CPU time 1.85 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 207128 kb
Host smart-9b3fa244-481c-482f-b669-add9f5ff5e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427218137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3427218137
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3564111566
Short name T279
Test name
Test status
Simulation time 197715084 ps
CPU time 2.82 seconds
Started Aug 11 06:05:46 PM PDT 24
Finished Aug 11 06:05:49 PM PDT 24
Peak memory 208980 kb
Host smart-4e9a1a20-e245-4f72-8e5e-c5d409acde27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564111566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3564111566
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2033178384
Short name T480
Test name
Test status
Simulation time 799272149 ps
CPU time 14.95 seconds
Started Aug 11 06:05:44 PM PDT 24
Finished Aug 11 06:05:59 PM PDT 24
Peak memory 208852 kb
Host smart-5db95120-4c1c-493a-aea7-0b6f2b7a1b59
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033178384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2033178384
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3291698742
Short name T634
Test name
Test status
Simulation time 63426056 ps
CPU time 2.34 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 209836 kb
Host smart-61654b29-f96d-4360-9f09-c57700bdf177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291698742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3291698742
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3218498628
Short name T199
Test name
Test status
Simulation time 1976526090 ps
CPU time 44.49 seconds
Started Aug 11 06:05:45 PM PDT 24
Finished Aug 11 06:06:30 PM PDT 24
Peak memory 208596 kb
Host smart-eff6649c-b6ca-4e54-94fd-2eea67a99317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218498628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3218498628
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1048530364
Short name T681
Test name
Test status
Simulation time 4070255311 ps
CPU time 28.32 seconds
Started Aug 11 06:05:53 PM PDT 24
Finished Aug 11 06:06:22 PM PDT 24
Peak memory 215264 kb
Host smart-29d348ee-bfaf-4fff-b026-9b590b7114aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048530364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1048530364
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1454493402
Short name T826
Test name
Test status
Simulation time 47639371 ps
CPU time 3.33 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:57 PM PDT 24
Peak memory 209944 kb
Host smart-eb81ecbc-c098-4159-9821-30921c1e71bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454493402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1454493402
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2969033405
Short name T723
Test name
Test status
Simulation time 50002769 ps
CPU time 2.13 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 210076 kb
Host smart-83786ae7-7a86-40b7-8cf6-c3785cc1f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969033405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2969033405
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3050292639
Short name T116
Test name
Test status
Simulation time 45615041 ps
CPU time 0.87 seconds
Started Aug 11 06:05:55 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 205912 kb
Host smart-3c7a6ec4-77a7-4141-a824-e0d1b2d82e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050292639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3050292639
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1940572418
Short name T381
Test name
Test status
Simulation time 26989255 ps
CPU time 2.03 seconds
Started Aug 11 06:05:55 PM PDT 24
Finished Aug 11 06:05:57 PM PDT 24
Peak memory 214348 kb
Host smart-83e68b7f-c532-42ee-a4f9-e094c8364519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940572418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1940572418
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3080171073
Short name T242
Test name
Test status
Simulation time 93042307 ps
CPU time 4.17 seconds
Started Aug 11 06:05:53 PM PDT 24
Finished Aug 11 06:05:57 PM PDT 24
Peak memory 222384 kb
Host smart-d0fdfe03-4382-4be1-9fdd-10f90bd74651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080171073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3080171073
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.951053005
Short name T290
Test name
Test status
Simulation time 141548004 ps
CPU time 2.91 seconds
Started Aug 11 06:05:56 PM PDT 24
Finished Aug 11 06:05:59 PM PDT 24
Peak memory 222256 kb
Host smart-62b164d6-0516-4bb8-a325-3cab8d5be65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951053005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.951053005
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.206560656
Short name T556
Test name
Test status
Simulation time 138041895 ps
CPU time 3.67 seconds
Started Aug 11 06:05:52 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 219448 kb
Host smart-8b542538-7c08-43fb-ace2-02c36edbf4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206560656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.206560656
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2108864598
Short name T604
Test name
Test status
Simulation time 1356913185 ps
CPU time 8.73 seconds
Started Aug 11 06:05:53 PM PDT 24
Finished Aug 11 06:06:01 PM PDT 24
Peak memory 209916 kb
Host smart-f8730159-c971-4520-b13d-e4ef4cb7fee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108864598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2108864598
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1184632416
Short name T754
Test name
Test status
Simulation time 4814098152 ps
CPU time 32.39 seconds
Started Aug 11 06:05:56 PM PDT 24
Finished Aug 11 06:06:28 PM PDT 24
Peak memory 209044 kb
Host smart-18f147e7-5b17-4a3f-a6c1-9a5566fc5cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184632416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1184632416
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.72460313
Short name T842
Test name
Test status
Simulation time 545975231 ps
CPU time 14.49 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:06:08 PM PDT 24
Peak memory 208016 kb
Host smart-d83a74f5-715e-43e7-9e66-2ebf98a4bc8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72460313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.72460313
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.141319327
Short name T318
Test name
Test status
Simulation time 1317795808 ps
CPU time 14.15 seconds
Started Aug 11 06:05:55 PM PDT 24
Finished Aug 11 06:06:10 PM PDT 24
Peak memory 208460 kb
Host smart-bb1134c9-430e-445e-898b-225708ee16d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141319327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.141319327
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1665098249
Short name T841
Test name
Test status
Simulation time 96696221 ps
CPU time 3.29 seconds
Started Aug 11 06:05:52 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 206812 kb
Host smart-a5576e7e-a0b0-4f42-bdad-8417bcc45807
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665098249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1665098249
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.214962829
Short name T336
Test name
Test status
Simulation time 324818867 ps
CPU time 4.98 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:06:00 PM PDT 24
Peak memory 209264 kb
Host smart-3fdd18f6-ae3a-4170-8bb1-eec44e367299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214962829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.214962829
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1362377407
Short name T448
Test name
Test status
Simulation time 110049248 ps
CPU time 3.85 seconds
Started Aug 11 06:05:52 PM PDT 24
Finished Aug 11 06:05:55 PM PDT 24
Peak memory 207336 kb
Host smart-12508118-2f3a-41b7-9454-2962b7a6e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362377407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1362377407
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2731955356
Short name T892
Test name
Test status
Simulation time 1552423007 ps
CPU time 15.02 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:06:09 PM PDT 24
Peak memory 220344 kb
Host smart-059959f9-5628-4fdd-85fe-e0082b46be94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731955356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2731955356
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3139842787
Short name T780
Test name
Test status
Simulation time 313471080 ps
CPU time 12.56 seconds
Started Aug 11 06:05:55 PM PDT 24
Finished Aug 11 06:06:08 PM PDT 24
Peak memory 222460 kb
Host smart-f6443302-6008-4485-a97d-e4a8afc47ac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139842787 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3139842787
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.4179580607
Short name T698
Test name
Test status
Simulation time 369797917 ps
CPU time 4.92 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:59 PM PDT 24
Peak memory 210344 kb
Host smart-c8a56036-1e65-4e1a-a836-dce38a6a9501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179580607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.4179580607
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.4280790664
Short name T479
Test name
Test status
Simulation time 10615900 ps
CPU time 0.82 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:55 PM PDT 24
Peak memory 205956 kb
Host smart-b8e37bfd-1d98-444c-805e-2ca4d90c348e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280790664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4280790664
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1957220868
Short name T546
Test name
Test status
Simulation time 268762854 ps
CPU time 2.19 seconds
Started Aug 11 06:05:56 PM PDT 24
Finished Aug 11 06:05:58 PM PDT 24
Peak memory 209164 kb
Host smart-45885249-77eb-4224-8453-2d260816c905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957220868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1957220868
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1847101703
Short name T13
Test name
Test status
Simulation time 137631427 ps
CPU time 1.7 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 207624 kb
Host smart-801aec36-635c-4d2b-b9db-17368f5f44a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847101703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1847101703
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.4188012782
Short name T781
Test name
Test status
Simulation time 89845513 ps
CPU time 4.3 seconds
Started Aug 11 06:05:56 PM PDT 24
Finished Aug 11 06:06:00 PM PDT 24
Peak memory 220620 kb
Host smart-af5c6444-5943-4200-9139-6a48fa742416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188012782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.4188012782
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2707182265
Short name T42
Test name
Test status
Simulation time 136172373 ps
CPU time 3.19 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:58 PM PDT 24
Peak memory 214288 kb
Host smart-371b711d-500b-4e46-a524-d3664234e955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707182265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2707182265
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1122874681
Short name T229
Test name
Test status
Simulation time 1504488195 ps
CPU time 3.77 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:58 PM PDT 24
Peak memory 219788 kb
Host smart-3ab06695-0fb5-40a8-9c4a-0db4d8effabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122874681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1122874681
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.661868058
Short name T507
Test name
Test status
Simulation time 384432847 ps
CPU time 4.47 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:58 PM PDT 24
Peak memory 209664 kb
Host smart-3b138f0b-361a-4eda-b662-b85199588e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661868058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.661868058
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.893904313
Short name T248
Test name
Test status
Simulation time 528345448 ps
CPU time 3.98 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:58 PM PDT 24
Peak memory 206888 kb
Host smart-e8b8a6f2-1411-4645-a54a-7da09a986d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893904313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.893904313
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2974172221
Short name T488
Test name
Test status
Simulation time 164056972 ps
CPU time 4.69 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:59 PM PDT 24
Peak memory 208392 kb
Host smart-03e184ea-3f05-4f84-9ac9-fecc1ca84e31
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974172221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2974172221
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1870141248
Short name T875
Test name
Test status
Simulation time 1238686463 ps
CPU time 15.35 seconds
Started Aug 11 06:05:55 PM PDT 24
Finished Aug 11 06:06:10 PM PDT 24
Peak memory 208196 kb
Host smart-7f786be4-48c4-4fbd-bad6-b5005d02a3cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870141248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1870141248
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3019238780
Short name T658
Test name
Test status
Simulation time 59140085 ps
CPU time 2.36 seconds
Started Aug 11 06:05:53 PM PDT 24
Finished Aug 11 06:05:55 PM PDT 24
Peak memory 206904 kb
Host smart-b61fd7b0-e781-40ec-9386-b99e8ce7cf39
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019238780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3019238780
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.888208114
Short name T194
Test name
Test status
Simulation time 154901748 ps
CPU time 2.47 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:57 PM PDT 24
Peak memory 215288 kb
Host smart-86e71baf-0448-4f05-9382-314819c38bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888208114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.888208114
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.889133142
Short name T553
Test name
Test status
Simulation time 270816791 ps
CPU time 3.11 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:57 PM PDT 24
Peak memory 208488 kb
Host smart-93da28a5-9f12-4837-8af4-04195eaf2f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889133142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.889133142
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2862373081
Short name T228
Test name
Test status
Simulation time 2123014523 ps
CPU time 30.88 seconds
Started Aug 11 06:05:57 PM PDT 24
Finished Aug 11 06:06:28 PM PDT 24
Peak memory 216604 kb
Host smart-47a7765a-1b15-4e14-8f84-7d4b5c73bc05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862373081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2862373081
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1526861135
Short name T391
Test name
Test status
Simulation time 148673022 ps
CPU time 1.8 seconds
Started Aug 11 06:05:53 PM PDT 24
Finished Aug 11 06:05:55 PM PDT 24
Peak memory 209784 kb
Host smart-3530371b-4fb2-46b5-8919-347ebd7fe060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526861135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1526861135
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4006969038
Short name T88
Test name
Test status
Simulation time 12248652 ps
CPU time 0.83 seconds
Started Aug 11 06:06:04 PM PDT 24
Finished Aug 11 06:06:05 PM PDT 24
Peak memory 206116 kb
Host smart-21ffbd27-a609-43c0-ac4f-bcc74bee2764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006969038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4006969038
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2388942846
Short name T426
Test name
Test status
Simulation time 743754636 ps
CPU time 4.82 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:07 PM PDT 24
Peak memory 215300 kb
Host smart-b3405e67-2f68-4c56-b8cc-207ebc6a0850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388942846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2388942846
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3777828159
Short name T32
Test name
Test status
Simulation time 270858780 ps
CPU time 3.73 seconds
Started Aug 11 06:06:03 PM PDT 24
Finished Aug 11 06:06:07 PM PDT 24
Peak memory 210272 kb
Host smart-bbdd42a8-13cb-421a-bb85-8182ba622347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777828159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3777828159
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.283501818
Short name T114
Test name
Test status
Simulation time 82905797 ps
CPU time 3.5 seconds
Started Aug 11 06:05:59 PM PDT 24
Finished Aug 11 06:06:03 PM PDT 24
Peak memory 210156 kb
Host smart-20a0f4a2-8666-4fd8-a4c2-19fb8545b335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283501818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.283501818
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1482019614
Short name T551
Test name
Test status
Simulation time 99085391 ps
CPU time 2.27 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:04 PM PDT 24
Peak memory 214308 kb
Host smart-9aad9765-8b58-491b-b17e-f519561fa6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482019614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1482019614
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3184094861
Short name T89
Test name
Test status
Simulation time 109423658 ps
CPU time 4.96 seconds
Started Aug 11 06:06:01 PM PDT 24
Finished Aug 11 06:06:07 PM PDT 24
Peak memory 215068 kb
Host smart-ce914c65-acca-448b-8609-82865b82051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184094861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3184094861
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1440508247
Short name T548
Test name
Test status
Simulation time 315993452 ps
CPU time 3.12 seconds
Started Aug 11 06:06:04 PM PDT 24
Finished Aug 11 06:06:07 PM PDT 24
Peak memory 215244 kb
Host smart-0c6f88c6-f1af-460a-9d50-07cdbc07946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440508247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1440508247
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.387023164
Short name T746
Test name
Test status
Simulation time 76348848 ps
CPU time 3.73 seconds
Started Aug 11 06:06:03 PM PDT 24
Finished Aug 11 06:06:07 PM PDT 24
Peak memory 210436 kb
Host smart-b1eefaa2-27dd-4b17-8938-f8a040672c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387023164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.387023164
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.212368353
Short name T824
Test name
Test status
Simulation time 145280753 ps
CPU time 2.42 seconds
Started Aug 11 06:05:53 PM PDT 24
Finished Aug 11 06:05:56 PM PDT 24
Peak memory 206784 kb
Host smart-5bb8c293-5a9a-4bd6-b354-ad82bd164d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212368353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.212368353
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.92592506
Short name T257
Test name
Test status
Simulation time 237354128 ps
CPU time 3.31 seconds
Started Aug 11 06:06:04 PM PDT 24
Finished Aug 11 06:06:07 PM PDT 24
Peak memory 208420 kb
Host smart-6526a34b-638b-45da-b2ae-be0b90898734
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92592506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.92592506
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1488369393
Short name T661
Test name
Test status
Simulation time 126219045 ps
CPU time 4.43 seconds
Started Aug 11 06:05:55 PM PDT 24
Finished Aug 11 06:05:59 PM PDT 24
Peak memory 208368 kb
Host smart-283bd06f-4b0f-4a4a-8b8f-de7fdba5c613
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488369393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1488369393
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3298837554
Short name T706
Test name
Test status
Simulation time 431492524 ps
CPU time 6.72 seconds
Started Aug 11 06:06:03 PM PDT 24
Finished Aug 11 06:06:10 PM PDT 24
Peak memory 207812 kb
Host smart-fc95433c-fca2-46f9-92ef-881a2d04b161
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298837554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3298837554
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3952781001
Short name T598
Test name
Test status
Simulation time 39822053 ps
CPU time 1.72 seconds
Started Aug 11 06:06:04 PM PDT 24
Finished Aug 11 06:06:05 PM PDT 24
Peak memory 215948 kb
Host smart-579d56a1-1808-4851-bdc6-233236547dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952781001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3952781001
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3281453544
Short name T463
Test name
Test status
Simulation time 309816159 ps
CPU time 3.13 seconds
Started Aug 11 06:05:54 PM PDT 24
Finished Aug 11 06:05:57 PM PDT 24
Peak memory 208472 kb
Host smart-7a1e627b-52a5-4475-805c-b657f866b857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281453544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3281453544
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3313037511
Short name T442
Test name
Test status
Simulation time 191528549 ps
CPU time 7.61 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:10 PM PDT 24
Peak memory 215112 kb
Host smart-b33ef6b7-dd68-413e-89e5-05e1070fa36e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313037511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3313037511
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.840232729
Short name T136
Test name
Test status
Simulation time 119438205 ps
CPU time 5.39 seconds
Started Aug 11 06:06:01 PM PDT 24
Finished Aug 11 06:06:07 PM PDT 24
Peak memory 222544 kb
Host smart-8ab20442-d34e-4d05-9d2f-5d3be3c4ff0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840232729 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.840232729
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.720117498
Short name T748
Test name
Test status
Simulation time 222368032 ps
CPU time 4.64 seconds
Started Aug 11 06:06:03 PM PDT 24
Finished Aug 11 06:06:08 PM PDT 24
Peak memory 207580 kb
Host smart-9fe51f34-2cc2-4e98-998f-5e606f887fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720117498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.720117498
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3687423204
Short name T704
Test name
Test status
Simulation time 124994127 ps
CPU time 1.91 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:04 PM PDT 24
Peak memory 209752 kb
Host smart-9e5eae21-b402-4cfe-b168-4e8de2b4225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687423204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3687423204
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3946794289
Short name T885
Test name
Test status
Simulation time 49856725 ps
CPU time 0.89 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:03 PM PDT 24
Peak memory 205968 kb
Host smart-78299781-d7cc-46c1-8cf3-c649a274d293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946794289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3946794289
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3415583283
Short name T408
Test name
Test status
Simulation time 197059123 ps
CPU time 4.17 seconds
Started Aug 11 06:06:01 PM PDT 24
Finished Aug 11 06:06:05 PM PDT 24
Peak memory 214300 kb
Host smart-5473dd22-9d1f-42cd-9ec7-d22a55f69d62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415583283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3415583283
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4020172203
Short name T14
Test name
Test status
Simulation time 45346179 ps
CPU time 2.3 seconds
Started Aug 11 06:06:03 PM PDT 24
Finished Aug 11 06:06:06 PM PDT 24
Peak memory 209268 kb
Host smart-d5c279dd-0b09-41c0-be61-345c33cd641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020172203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4020172203
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1161648563
Short name T352
Test name
Test status
Simulation time 53518641 ps
CPU time 2.97 seconds
Started Aug 11 06:05:58 PM PDT 24
Finished Aug 11 06:06:01 PM PDT 24
Peak memory 207692 kb
Host smart-acfe97b5-c79e-4765-abff-70404c601cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161648563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1161648563
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1856580280
Short name T639
Test name
Test status
Simulation time 101951579 ps
CPU time 3.45 seconds
Started Aug 11 06:06:00 PM PDT 24
Finished Aug 11 06:06:04 PM PDT 24
Peak memory 214420 kb
Host smart-29a02c7d-ccb6-4451-adea-de58084669c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856580280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1856580280
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2444719567
Short name T226
Test name
Test status
Simulation time 81831241 ps
CPU time 3.26 seconds
Started Aug 11 06:05:59 PM PDT 24
Finished Aug 11 06:06:03 PM PDT 24
Peak memory 220244 kb
Host smart-d360769a-7aa7-42a3-9130-05e8190d3921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444719567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2444719567
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2851895638
Short name T264
Test name
Test status
Simulation time 68706760 ps
CPU time 3.25 seconds
Started Aug 11 06:05:59 PM PDT 24
Finished Aug 11 06:06:02 PM PDT 24
Peak memory 207460 kb
Host smart-ce946c82-e0b5-49d9-b7a1-c449cddf9e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851895638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2851895638
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1556371119
Short name T403
Test name
Test status
Simulation time 123105996 ps
CPU time 2.39 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:04 PM PDT 24
Peak memory 207180 kb
Host smart-134603b7-d217-4f37-8af3-cc77e9b77e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556371119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1556371119
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3220436467
Short name T588
Test name
Test status
Simulation time 50210066 ps
CPU time 2.5 seconds
Started Aug 11 06:06:03 PM PDT 24
Finished Aug 11 06:06:06 PM PDT 24
Peak memory 206956 kb
Host smart-68e09546-79a4-412f-a47f-24b2358f96f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220436467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3220436467
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1980876596
Short name T77
Test name
Test status
Simulation time 73866694 ps
CPU time 2.22 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:04 PM PDT 24
Peak memory 206856 kb
Host smart-1a8489c9-895b-4ec3-828a-61165067d2df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980876596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1980876596
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3100993775
Short name T207
Test name
Test status
Simulation time 100315144 ps
CPU time 3.34 seconds
Started Aug 11 06:06:04 PM PDT 24
Finished Aug 11 06:06:08 PM PDT 24
Peak memory 208592 kb
Host smart-85656118-7343-4771-ae60-17fed39444ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100993775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3100993775
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1096829955
Short name T500
Test name
Test status
Simulation time 474317530 ps
CPU time 9.21 seconds
Started Aug 11 06:05:58 PM PDT 24
Finished Aug 11 06:06:07 PM PDT 24
Peak memory 218200 kb
Host smart-41d3c892-d006-41d5-bb08-3e8cb907ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096829955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1096829955
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2529328927
Short name T891
Test name
Test status
Simulation time 34985332 ps
CPU time 2.42 seconds
Started Aug 11 06:06:05 PM PDT 24
Finished Aug 11 06:06:07 PM PDT 24
Peak memory 208428 kb
Host smart-89e6d773-a8d4-4697-9e55-404c09df8ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529328927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2529328927
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.863771463
Short name T327
Test name
Test status
Simulation time 156185218 ps
CPU time 6.23 seconds
Started Aug 11 06:06:04 PM PDT 24
Finished Aug 11 06:06:10 PM PDT 24
Peak memory 216476 kb
Host smart-b764edfa-fc9a-4339-9da5-3766906b2804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863771463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.863771463
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2384683456
Short name T138
Test name
Test status
Simulation time 282858552 ps
CPU time 6.21 seconds
Started Aug 11 06:06:03 PM PDT 24
Finished Aug 11 06:06:09 PM PDT 24
Peak memory 222504 kb
Host smart-ee2a8848-1727-4178-a8ba-208ed10e8dce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384683456 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2384683456
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3353965300
Short name T193
Test name
Test status
Simulation time 472137605 ps
CPU time 4.21 seconds
Started Aug 11 06:06:01 PM PDT 24
Finished Aug 11 06:06:06 PM PDT 24
Peak memory 208116 kb
Host smart-1fee01e4-c74a-4bec-94e1-3fcef09765a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353965300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3353965300
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3696353407
Short name T400
Test name
Test status
Simulation time 70604933 ps
CPU time 2.9 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:05 PM PDT 24
Peak memory 210152 kb
Host smart-91a4d5e7-172e-4f72-b908-bfcb5031224d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696353407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3696353407
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2182439005
Short name T714
Test name
Test status
Simulation time 11608398 ps
CPU time 0.83 seconds
Started Aug 11 06:06:09 PM PDT 24
Finished Aug 11 06:06:10 PM PDT 24
Peak memory 205860 kb
Host smart-4118bd91-1b1b-461b-a168-24c92c609abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182439005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2182439005
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1309834902
Short name T19
Test name
Test status
Simulation time 62201069 ps
CPU time 2.66 seconds
Started Aug 11 06:06:13 PM PDT 24
Finished Aug 11 06:06:16 PM PDT 24
Peak memory 210224 kb
Host smart-33ab5f24-caf4-47d9-9f2e-0ade09222626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309834902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1309834902
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.458981375
Short name T52
Test name
Test status
Simulation time 180032617 ps
CPU time 1.71 seconds
Started Aug 11 06:06:08 PM PDT 24
Finished Aug 11 06:06:10 PM PDT 24
Peak memory 207380 kb
Host smart-786ef6a0-12b8-488c-a326-d0d036caafa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458981375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.458981375
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1901498517
Short name T481
Test name
Test status
Simulation time 47582114 ps
CPU time 2.29 seconds
Started Aug 11 06:06:13 PM PDT 24
Finished Aug 11 06:06:15 PM PDT 24
Peak memory 214412 kb
Host smart-8d683b4e-7e29-4d30-bd85-814751755462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901498517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1901498517
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3388259361
Short name T627
Test name
Test status
Simulation time 108256036 ps
CPU time 2.59 seconds
Started Aug 11 06:06:10 PM PDT 24
Finished Aug 11 06:06:13 PM PDT 24
Peak memory 214168 kb
Host smart-f6ed7cfe-3b1e-423e-b19b-f095a0213fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388259361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3388259361
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4045519392
Short name T800
Test name
Test status
Simulation time 1909093636 ps
CPU time 6.79 seconds
Started Aug 11 06:06:09 PM PDT 24
Finished Aug 11 06:06:16 PM PDT 24
Peak memory 222384 kb
Host smart-9e6671aa-ee6b-4e3d-86e7-a85bb06fe336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045519392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4045519392
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1644370600
Short name T505
Test name
Test status
Simulation time 302924449 ps
CPU time 7.76 seconds
Started Aug 11 06:06:10 PM PDT 24
Finished Aug 11 06:06:18 PM PDT 24
Peak memory 209228 kb
Host smart-f4077911-694f-40c7-845d-4ae94e496817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644370600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1644370600
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1591325582
Short name T297
Test name
Test status
Simulation time 6492431710 ps
CPU time 44.18 seconds
Started Aug 11 06:06:03 PM PDT 24
Finished Aug 11 06:06:48 PM PDT 24
Peak memory 208760 kb
Host smart-7b90afd5-8c77-4017-b6f4-294b1f8a1910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591325582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1591325582
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2530019806
Short name T506
Test name
Test status
Simulation time 75527984 ps
CPU time 1.88 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:04 PM PDT 24
Peak memory 206836 kb
Host smart-ff636a5f-923e-4a5f-8553-37e9abccc458
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530019806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2530019806
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2596900841
Short name T508
Test name
Test status
Simulation time 207075463 ps
CPU time 3.88 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:06 PM PDT 24
Peak memory 206984 kb
Host smart-051bc7bb-c77a-4ca1-9b27-c24dedd739b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596900841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2596900841
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1633138751
Short name T449
Test name
Test status
Simulation time 1257367697 ps
CPU time 9.8 seconds
Started Aug 11 06:06:08 PM PDT 24
Finished Aug 11 06:06:18 PM PDT 24
Peak memory 207052 kb
Host smart-94f30a69-76c1-4e5e-a5c9-d4490be2648d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633138751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1633138751
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2299433865
Short name T823
Test name
Test status
Simulation time 131305051 ps
CPU time 3.2 seconds
Started Aug 11 06:06:10 PM PDT 24
Finished Aug 11 06:06:13 PM PDT 24
Peak memory 215672 kb
Host smart-914df571-e4a1-4788-8f92-8b931e693bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299433865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2299433865
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1932462376
Short name T467
Test name
Test status
Simulation time 102947538 ps
CPU time 2.4 seconds
Started Aug 11 06:06:02 PM PDT 24
Finished Aug 11 06:06:04 PM PDT 24
Peak memory 206640 kb
Host smart-5e5835fa-f8d5-4b83-b047-ab479845d70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932462376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1932462376
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.305231317
Short name T260
Test name
Test status
Simulation time 322890771 ps
CPU time 4.47 seconds
Started Aug 11 06:06:10 PM PDT 24
Finished Aug 11 06:06:14 PM PDT 24
Peak memory 207328 kb
Host smart-554ecb57-4000-4657-9e8a-77526d7bf796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305231317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.305231317
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.296892328
Short name T638
Test name
Test status
Simulation time 10068735 ps
CPU time 0.73 seconds
Started Aug 11 06:06:14 PM PDT 24
Finished Aug 11 06:06:15 PM PDT 24
Peak memory 205848 kb
Host smart-1f372960-4ee2-4cd2-a7bf-69056c7b8d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296892328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.296892328
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.365368769
Short name T394
Test name
Test status
Simulation time 67246693 ps
CPU time 2.76 seconds
Started Aug 11 06:06:11 PM PDT 24
Finished Aug 11 06:06:14 PM PDT 24
Peak memory 214224 kb
Host smart-75b2838c-4e23-45e6-9dda-56573ab0d529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365368769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.365368769
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3352184082
Short name T26
Test name
Test status
Simulation time 187720266 ps
CPU time 1.89 seconds
Started Aug 11 06:06:09 PM PDT 24
Finished Aug 11 06:06:11 PM PDT 24
Peak memory 214440 kb
Host smart-9142a58c-9c62-484a-b45b-60436dd732db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352184082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3352184082
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3802225024
Short name T718
Test name
Test status
Simulation time 548195945 ps
CPU time 4.31 seconds
Started Aug 11 06:06:11 PM PDT 24
Finished Aug 11 06:06:16 PM PDT 24
Peak memory 218228 kb
Host smart-af20bc45-3de0-41f8-8e2e-1c88d8fd5d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802225024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3802225024
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2888084214
Short name T362
Test name
Test status
Simulation time 352646659 ps
CPU time 3.36 seconds
Started Aug 11 06:06:12 PM PDT 24
Finished Aug 11 06:06:15 PM PDT 24
Peak memory 219952 kb
Host smart-4c2fd2ef-707d-45bd-b8f3-8faf97ee3dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888084214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2888084214
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3102416551
Short name T669
Test name
Test status
Simulation time 410265783 ps
CPU time 5.22 seconds
Started Aug 11 06:06:14 PM PDT 24
Finished Aug 11 06:06:20 PM PDT 24
Peak memory 214212 kb
Host smart-db2319b6-0764-40e5-ac13-603aab8ea70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102416551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3102416551
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4023970370
Short name T262
Test name
Test status
Simulation time 442201086 ps
CPU time 8.82 seconds
Started Aug 11 06:06:11 PM PDT 24
Finished Aug 11 06:06:20 PM PDT 24
Peak memory 208464 kb
Host smart-b1f12110-1100-491f-9c44-fec8d4702c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023970370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4023970370
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1411390262
Short name T853
Test name
Test status
Simulation time 20073417 ps
CPU time 1.74 seconds
Started Aug 11 06:06:09 PM PDT 24
Finished Aug 11 06:06:11 PM PDT 24
Peak memory 207440 kb
Host smart-0c44fa26-d990-4347-9f7b-21b79dcc9e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411390262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1411390262
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.258179669
Short name T607
Test name
Test status
Simulation time 448005160 ps
CPU time 13.26 seconds
Started Aug 11 06:06:13 PM PDT 24
Finished Aug 11 06:06:26 PM PDT 24
Peak memory 206968 kb
Host smart-bcea2e29-1b99-49a4-81e4-4da4f754568b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258179669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.258179669
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1492412908
Short name T867
Test name
Test status
Simulation time 347506735 ps
CPU time 3.67 seconds
Started Aug 11 06:06:10 PM PDT 24
Finished Aug 11 06:06:14 PM PDT 24
Peak memory 208572 kb
Host smart-98278906-279e-4335-9065-60c961899abb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492412908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1492412908
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3125574028
Short name T641
Test name
Test status
Simulation time 7286350551 ps
CPU time 44.68 seconds
Started Aug 11 06:06:06 PM PDT 24
Finished Aug 11 06:06:51 PM PDT 24
Peak memory 208264 kb
Host smart-5fdd67cf-feec-49bc-b692-6f1817ef6898
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125574028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3125574028
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2664002664
Short name T493
Test name
Test status
Simulation time 91156172 ps
CPU time 1.99 seconds
Started Aug 11 06:06:11 PM PDT 24
Finished Aug 11 06:06:13 PM PDT 24
Peak memory 207968 kb
Host smart-de5ba042-fc38-404f-8cb2-c61364a45746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664002664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2664002664
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1145175121
Short name T404
Test name
Test status
Simulation time 316486840 ps
CPU time 3.09 seconds
Started Aug 11 06:06:09 PM PDT 24
Finished Aug 11 06:06:12 PM PDT 24
Peak memory 206768 kb
Host smart-831df646-94ba-4859-a180-320d0bec4e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145175121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1145175121
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3391578976
Short name T269
Test name
Test status
Simulation time 395175164 ps
CPU time 3.69 seconds
Started Aug 11 06:06:08 PM PDT 24
Finished Aug 11 06:06:11 PM PDT 24
Peak memory 207712 kb
Host smart-742603a1-4f9d-4767-8303-62b2b75a5c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391578976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3391578976
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1228345952
Short name T903
Test name
Test status
Simulation time 54825403 ps
CPU time 2.98 seconds
Started Aug 11 06:06:12 PM PDT 24
Finished Aug 11 06:06:15 PM PDT 24
Peak memory 210324 kb
Host smart-6454526c-5eb5-47e5-8901-b34c7fec48cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228345952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1228345952
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3816071564
Short name T429
Test name
Test status
Simulation time 26859479 ps
CPU time 0.77 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:18 PM PDT 24
Peak memory 205944 kb
Host smart-f319d4c3-e0c2-4333-b906-ab8d3ec2c945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816071564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3816071564
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2352726411
Short name T146
Test name
Test status
Simulation time 102700503 ps
CPU time 2.31 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:20 PM PDT 24
Peak memory 214260 kb
Host smart-170332c2-4d05-486f-9e97-74d53d19750e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352726411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2352726411
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.4241657844
Short name T682
Test name
Test status
Simulation time 169371611 ps
CPU time 3.06 seconds
Started Aug 11 06:06:16 PM PDT 24
Finished Aug 11 06:06:19 PM PDT 24
Peak memory 218240 kb
Host smart-4f44b2fd-844c-4b69-9e37-90a6569ec954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241657844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.4241657844
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2709212179
Short name T764
Test name
Test status
Simulation time 638977193 ps
CPU time 2.73 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:22 PM PDT 24
Peak memory 221992 kb
Host smart-7b7e34e1-98c2-4864-9107-9ea60a9f8b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709212179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2709212179
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.412767593
Short name T716
Test name
Test status
Simulation time 97288712 ps
CPU time 2.61 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:20 PM PDT 24
Peak memory 209604 kb
Host smart-db1b7e34-d99a-4964-8ffe-5b687d865b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412767593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.412767593
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2897658134
Short name T790
Test name
Test status
Simulation time 810827974 ps
CPU time 19.71 seconds
Started Aug 11 06:06:11 PM PDT 24
Finished Aug 11 06:06:31 PM PDT 24
Peak memory 209116 kb
Host smart-90311c73-dcdc-463d-aafc-366b3b5c2464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897658134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2897658134
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.456090824
Short name T683
Test name
Test status
Simulation time 353147275 ps
CPU time 7.62 seconds
Started Aug 11 06:06:08 PM PDT 24
Finished Aug 11 06:06:16 PM PDT 24
Peak memory 208096 kb
Host smart-b8bb2a76-c7e8-4289-8977-7292de977087
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456090824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.456090824
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1516102389
Short name T890
Test name
Test status
Simulation time 39283250 ps
CPU time 2.39 seconds
Started Aug 11 06:06:12 PM PDT 24
Finished Aug 11 06:06:14 PM PDT 24
Peak memory 206804 kb
Host smart-39117e96-3eef-4f20-9541-0325aa586dde
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516102389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1516102389
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2063783110
Short name T316
Test name
Test status
Simulation time 532912737 ps
CPU time 17.17 seconds
Started Aug 11 06:06:11 PM PDT 24
Finished Aug 11 06:06:29 PM PDT 24
Peak memory 207932 kb
Host smart-9ac0975b-f15a-45cf-a196-a6ce7b927f13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063783110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2063783110
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2396079532
Short name T612
Test name
Test status
Simulation time 842525107 ps
CPU time 5.44 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:25 PM PDT 24
Peak memory 209776 kb
Host smart-12b1b6fa-ddac-4812-9cdf-d53dfb5bd284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396079532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2396079532
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3156493453
Short name T447
Test name
Test status
Simulation time 235455833 ps
CPU time 2.91 seconds
Started Aug 11 06:06:08 PM PDT 24
Finished Aug 11 06:06:11 PM PDT 24
Peak memory 206936 kb
Host smart-86d8fedb-ebfa-4abc-8f16-82a1a4595c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156493453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3156493453
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3581614529
Short name T266
Test name
Test status
Simulation time 1437562619 ps
CPU time 42.07 seconds
Started Aug 11 06:06:22 PM PDT 24
Finished Aug 11 06:07:04 PM PDT 24
Peak memory 222456 kb
Host smart-3b2c8c9b-1fe2-48d0-be1a-1dda8510b161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581614529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3581614529
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1029443754
Short name T555
Test name
Test status
Simulation time 585201349 ps
CPU time 8.33 seconds
Started Aug 11 06:06:18 PM PDT 24
Finished Aug 11 06:06:26 PM PDT 24
Peak memory 219132 kb
Host smart-c4a47895-10c5-427e-a53a-982484ad09e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029443754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1029443754
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3001199361
Short name T216
Test name
Test status
Simulation time 28857893 ps
CPU time 1.22 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:20 PM PDT 24
Peak memory 208316 kb
Host smart-c6e583de-38ad-4a46-9488-b769a2310aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001199361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3001199361
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2925510748
Short name T788
Test name
Test status
Simulation time 13909413 ps
CPU time 0.75 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:20 PM PDT 24
Peak memory 205892 kb
Host smart-af326d95-da57-4217-8b45-ec10914eb117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925510748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2925510748
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.136952226
Short name T317
Test name
Test status
Simulation time 122765277 ps
CPU time 6.68 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:24 PM PDT 24
Peak memory 214220 kb
Host smart-e30a5b4f-adf9-4d3b-8fa5-6cbf9512125a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=136952226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.136952226
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2693584336
Short name T221
Test name
Test status
Simulation time 217742088 ps
CPU time 3.6 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:21 PM PDT 24
Peak memory 220844 kb
Host smart-8e0bfceb-d8ec-4ccc-891a-c6c3c3cc43d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693584336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2693584336
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2955393591
Short name T692
Test name
Test status
Simulation time 1364649076 ps
CPU time 3.36 seconds
Started Aug 11 06:06:18 PM PDT 24
Finished Aug 11 06:06:22 PM PDT 24
Peak memory 208400 kb
Host smart-0b5f7564-e95b-4857-a1f1-0f4b13211043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955393591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2955393591
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3283321330
Short name T97
Test name
Test status
Simulation time 307233019 ps
CPU time 3.51 seconds
Started Aug 11 06:06:22 PM PDT 24
Finished Aug 11 06:06:25 PM PDT 24
Peak memory 214440 kb
Host smart-54dd00c0-c4b6-445d-8db6-b51530c16739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283321330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3283321330
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4031667189
Short name T324
Test name
Test status
Simulation time 236783226 ps
CPU time 5.67 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:23 PM PDT 24
Peak memory 222404 kb
Host smart-bd1bfd92-60e4-4aef-be2f-5db56f687284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031667189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4031667189
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1656792343
Short name T819
Test name
Test status
Simulation time 49611637 ps
CPU time 2.69 seconds
Started Aug 11 06:06:22 PM PDT 24
Finished Aug 11 06:06:25 PM PDT 24
Peak memory 214416 kb
Host smart-68337d96-33e2-483c-93b9-3b14c5648fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656792343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1656792343
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4219859071
Short name T515
Test name
Test status
Simulation time 859105281 ps
CPU time 10.67 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:28 PM PDT 24
Peak memory 209304 kb
Host smart-a0b68e16-4345-49c0-ac70-9670da6b94cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219859071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4219859071
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1222305046
Short name T461
Test name
Test status
Simulation time 86496601 ps
CPU time 3.93 seconds
Started Aug 11 06:06:23 PM PDT 24
Finished Aug 11 06:06:27 PM PDT 24
Peak memory 208700 kb
Host smart-4e8333f3-05d3-4dcd-81bb-1ccbf292b5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222305046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1222305046
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4112491254
Short name T673
Test name
Test status
Simulation time 3135727079 ps
CPU time 25.5 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:44 PM PDT 24
Peak memory 208676 kb
Host smart-952ab913-6158-4b95-b830-da1aadaedb50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112491254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4112491254
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.743707414
Short name T251
Test name
Test status
Simulation time 35976675 ps
CPU time 2.31 seconds
Started Aug 11 06:06:15 PM PDT 24
Finished Aug 11 06:06:17 PM PDT 24
Peak memory 206904 kb
Host smart-dd154568-fb8f-42ec-883c-818dd5bf94ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743707414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.743707414
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1609664219
Short name T529
Test name
Test status
Simulation time 237541624 ps
CPU time 3.27 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:23 PM PDT 24
Peak memory 206112 kb
Host smart-d579fe33-074c-4db2-8acc-bd2ab1784ed4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609664219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1609664219
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1344033858
Short name T39
Test name
Test status
Simulation time 47649091 ps
CPU time 2.03 seconds
Started Aug 11 06:06:14 PM PDT 24
Finished Aug 11 06:06:16 PM PDT 24
Peak memory 208692 kb
Host smart-e9c72066-2de9-40e4-8538-40b782911c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344033858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1344033858
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3901658641
Short name T747
Test name
Test status
Simulation time 22224740 ps
CPU time 1.79 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:21 PM PDT 24
Peak memory 206504 kb
Host smart-7193d088-ab33-46cc-b88e-8003a2e95852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901658641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3901658641
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1615243823
Short name T74
Test name
Test status
Simulation time 2984521582 ps
CPU time 59.05 seconds
Started Aug 11 06:06:16 PM PDT 24
Finished Aug 11 06:07:15 PM PDT 24
Peak memory 215748 kb
Host smart-ae661c96-9f6d-4480-9527-0cd233101b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615243823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1615243823
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.4145135822
Short name T372
Test name
Test status
Simulation time 9055911368 ps
CPU time 20.78 seconds
Started Aug 11 06:06:18 PM PDT 24
Finished Aug 11 06:06:38 PM PDT 24
Peak memory 222744 kb
Host smart-a9448c15-1765-4f4e-9c33-740063b5290b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145135822 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.4145135822
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3196312845
Short name T736
Test name
Test status
Simulation time 1612271230 ps
CPU time 45.71 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:07:04 PM PDT 24
Peak memory 214204 kb
Host smart-d97971c5-a013-4e19-9b16-799fc2d1e027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196312845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3196312845
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3937316877
Short name T406
Test name
Test status
Simulation time 92635950 ps
CPU time 1.83 seconds
Started Aug 11 06:06:23 PM PDT 24
Finished Aug 11 06:06:25 PM PDT 24
Peak memory 209668 kb
Host smart-e24781c2-676d-4632-80fc-6288b304236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937316877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3937316877
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1671488037
Short name T517
Test name
Test status
Simulation time 59333539 ps
CPU time 0.76 seconds
Started Aug 11 06:06:28 PM PDT 24
Finished Aug 11 06:06:29 PM PDT 24
Peak memory 205900 kb
Host smart-702c7bb5-dc37-4463-8a35-7cf5fe5cb76a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671488037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1671488037
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2003399657
Short name T420
Test name
Test status
Simulation time 1041902962 ps
CPU time 13.76 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:33 PM PDT 24
Peak memory 214188 kb
Host smart-ea9fba21-3450-4cf9-a898-06194c2afed9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003399657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2003399657
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1424200519
Short name T342
Test name
Test status
Simulation time 224019722 ps
CPU time 6.06 seconds
Started Aug 11 06:06:16 PM PDT 24
Finished Aug 11 06:06:23 PM PDT 24
Peak memory 209576 kb
Host smart-847feaf0-e84f-40ce-b200-6e70330a2e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424200519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1424200519
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3792238546
Short name T344
Test name
Test status
Simulation time 55771604 ps
CPU time 2.24 seconds
Started Aug 11 06:06:15 PM PDT 24
Finished Aug 11 06:06:17 PM PDT 24
Peak memory 214296 kb
Host smart-0a2501d9-7426-4d11-b2d0-267cca03ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792238546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3792238546
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1345212017
Short name T110
Test name
Test status
Simulation time 60816180 ps
CPU time 1.76 seconds
Started Aug 11 06:06:17 PM PDT 24
Finished Aug 11 06:06:19 PM PDT 24
Peak memory 211488 kb
Host smart-437e03a9-232b-48e5-98b9-28c86ebfb0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345212017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1345212017
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2766973611
Short name T797
Test name
Test status
Simulation time 92330156 ps
CPU time 3.67 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:22 PM PDT 24
Peak memory 214368 kb
Host smart-64f1f6ab-6ae0-4b2a-b83d-cb4e7aa04d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766973611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2766973611
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2304368898
Short name T672
Test name
Test status
Simulation time 1035731348 ps
CPU time 7.05 seconds
Started Aug 11 06:06:20 PM PDT 24
Finished Aug 11 06:06:27 PM PDT 24
Peak memory 209440 kb
Host smart-50d8789a-e939-4f9a-a019-2343fabb9f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304368898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2304368898
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2970915986
Short name T851
Test name
Test status
Simulation time 420215156 ps
CPU time 3.89 seconds
Started Aug 11 06:06:15 PM PDT 24
Finished Aug 11 06:06:19 PM PDT 24
Peak memory 208404 kb
Host smart-47b3d5b5-fc3a-4827-8d18-395d42ed2bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970915986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2970915986
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.626464579
Short name T739
Test name
Test status
Simulation time 919513683 ps
CPU time 24.55 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:44 PM PDT 24
Peak memory 208676 kb
Host smart-b35a0f7b-d168-498d-96db-1933b30c414f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626464579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.626464579
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1764574483
Short name T807
Test name
Test status
Simulation time 328778958 ps
CPU time 2.74 seconds
Started Aug 11 06:06:19 PM PDT 24
Finished Aug 11 06:06:22 PM PDT 24
Peak memory 206932 kb
Host smart-dc77d6ce-8064-45fa-8d2d-c5dd3fa6fd03
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764574483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1764574483
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3044801340
Short name T603
Test name
Test status
Simulation time 439874478 ps
CPU time 5.42 seconds
Started Aug 11 06:06:23 PM PDT 24
Finished Aug 11 06:06:28 PM PDT 24
Peak memory 208436 kb
Host smart-dbba1412-1786-49ca-841d-87aae58211a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044801340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3044801340
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3458750778
Short name T455
Test name
Test status
Simulation time 108606524 ps
CPU time 2.65 seconds
Started Aug 11 06:06:16 PM PDT 24
Finished Aug 11 06:06:19 PM PDT 24
Peak memory 206952 kb
Host smart-2e642866-5def-42ff-932a-d7c67411658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458750778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3458750778
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.750244064
Short name T346
Test name
Test status
Simulation time 1311371407 ps
CPU time 15.87 seconds
Started Aug 11 06:06:27 PM PDT 24
Finished Aug 11 06:06:43 PM PDT 24
Peak memory 216448 kb
Host smart-80bc1de5-bf5b-4591-88bd-658ff379575f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750244064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.750244064
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1096137344
Short name T757
Test name
Test status
Simulation time 377169214 ps
CPU time 6.58 seconds
Started Aug 11 06:06:25 PM PDT 24
Finished Aug 11 06:06:32 PM PDT 24
Peak memory 222648 kb
Host smart-f99bb303-9c96-415f-9ec7-44a2e189ed3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096137344 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1096137344
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2273138059
Short name T625
Test name
Test status
Simulation time 1074222099 ps
CPU time 11.25 seconds
Started Aug 11 06:06:22 PM PDT 24
Finished Aug 11 06:06:34 PM PDT 24
Peak memory 209084 kb
Host smart-1ab33375-0757-4dca-bb9b-c33cc161e1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273138059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2273138059
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1550244433
Short name T778
Test name
Test status
Simulation time 3066166048 ps
CPU time 25.58 seconds
Started Aug 11 06:06:18 PM PDT 24
Finished Aug 11 06:06:44 PM PDT 24
Peak memory 210972 kb
Host smart-5b7cef6a-f5a0-4123-ac21-131c21c9a8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550244433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1550244433
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.67733709
Short name T654
Test name
Test status
Simulation time 40029039 ps
CPU time 0.72 seconds
Started Aug 11 06:04:35 PM PDT 24
Finished Aug 11 06:04:35 PM PDT 24
Peak memory 205924 kb
Host smart-33e91a1d-77cd-4304-a0c6-5bb8c9ab24c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67733709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.67733709
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1195960546
Short name T310
Test name
Test status
Simulation time 293944915 ps
CPU time 8.37 seconds
Started Aug 11 06:04:33 PM PDT 24
Finished Aug 11 06:04:42 PM PDT 24
Peak memory 222444 kb
Host smart-8bd0c752-e707-4395-9e13-d6f094e19c83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1195960546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1195960546
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3881507150
Short name T725
Test name
Test status
Simulation time 258369480 ps
CPU time 3.68 seconds
Started Aug 11 06:04:34 PM PDT 24
Finished Aug 11 06:04:37 PM PDT 24
Peak memory 218464 kb
Host smart-4472a25b-cbe4-4a05-a919-f9fbda63f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881507150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3881507150
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1265031284
Short name T822
Test name
Test status
Simulation time 114876874 ps
CPU time 3.73 seconds
Started Aug 11 06:04:28 PM PDT 24
Finished Aug 11 06:04:31 PM PDT 24
Peak memory 214292 kb
Host smart-29a75ca3-5e2e-433d-a14c-a362a7f26389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265031284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1265031284
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2576919127
Short name T821
Test name
Test status
Simulation time 51771961 ps
CPU time 2.66 seconds
Started Aug 11 06:04:35 PM PDT 24
Finished Aug 11 06:04:37 PM PDT 24
Peak memory 222324 kb
Host smart-5bbe67fb-9108-455c-8df7-8198594e6dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576919127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2576919127
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2655579172
Short name T238
Test name
Test status
Simulation time 68881745 ps
CPU time 4.58 seconds
Started Aug 11 06:04:35 PM PDT 24
Finished Aug 11 06:04:40 PM PDT 24
Peak memory 222376 kb
Host smart-364dcf3c-425f-46e1-b367-5497abc26df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655579172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2655579172
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2983440857
Short name T565
Test name
Test status
Simulation time 97292991 ps
CPU time 4.02 seconds
Started Aug 11 06:04:28 PM PDT 24
Finished Aug 11 06:04:32 PM PDT 24
Peak memory 218268 kb
Host smart-ff80dbb1-5364-44bb-ac35-9c790755d2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983440857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2983440857
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.887754855
Short name T835
Test name
Test status
Simulation time 679743899 ps
CPU time 5.56 seconds
Started Aug 11 06:04:30 PM PDT 24
Finished Aug 11 06:04:36 PM PDT 24
Peak memory 208336 kb
Host smart-53333b4b-5c2d-4eae-b9af-d71824d1cb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887754855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.887754855
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.82374907
Short name T721
Test name
Test status
Simulation time 99564458 ps
CPU time 2.6 seconds
Started Aug 11 06:04:30 PM PDT 24
Finished Aug 11 06:04:33 PM PDT 24
Peak memory 208480 kb
Host smart-8676f9ef-d85c-44d3-a59c-78d27e00b314
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82374907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.82374907
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1386242283
Short name T726
Test name
Test status
Simulation time 4500277017 ps
CPU time 15.83 seconds
Started Aug 11 06:04:28 PM PDT 24
Finished Aug 11 06:04:44 PM PDT 24
Peak memory 208392 kb
Host smart-f1ae3acb-6705-4738-bc90-64658ab88f05
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386242283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1386242283
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3527564270
Short name T871
Test name
Test status
Simulation time 271937566 ps
CPU time 4.45 seconds
Started Aug 11 06:04:35 PM PDT 24
Finished Aug 11 06:04:39 PM PDT 24
Peak memory 206728 kb
Host smart-3bbc0dc1-e7b9-4e98-af2f-107f68b95ae9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527564270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3527564270
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3102803643
Short name T572
Test name
Test status
Simulation time 208358557 ps
CPU time 2.29 seconds
Started Aug 11 06:04:38 PM PDT 24
Finished Aug 11 06:04:40 PM PDT 24
Peak memory 208984 kb
Host smart-6c0c62bc-34a5-4fe5-9f26-6519165dbf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102803643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3102803643
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1895772059
Short name T738
Test name
Test status
Simulation time 2806625959 ps
CPU time 25.02 seconds
Started Aug 11 06:04:30 PM PDT 24
Finished Aug 11 06:04:55 PM PDT 24
Peak memory 208104 kb
Host smart-b4556c90-81d4-40a5-8a6e-5e31f6cd1485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895772059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1895772059
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1474382715
Short name T908
Test name
Test status
Simulation time 990698272 ps
CPU time 18.04 seconds
Started Aug 11 06:04:38 PM PDT 24
Finished Aug 11 06:04:56 PM PDT 24
Peak memory 215264 kb
Host smart-2ec06329-ba57-4e44-9f35-0ee544f58269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474382715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1474382715
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4014048843
Short name T779
Test name
Test status
Simulation time 363998326 ps
CPU time 7.55 seconds
Started Aug 11 06:04:30 PM PDT 24
Finished Aug 11 06:04:38 PM PDT 24
Peak memory 209624 kb
Host smart-4fcbf8ba-8db7-4476-9679-a9e6fef7ab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014048843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4014048843
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3120543495
Short name T392
Test name
Test status
Simulation time 76649813 ps
CPU time 2.67 seconds
Started Aug 11 06:04:37 PM PDT 24
Finished Aug 11 06:04:39 PM PDT 24
Peak memory 210200 kb
Host smart-e6730b45-4727-4c0c-9ef9-deb8a2d8216b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120543495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3120543495
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.413796408
Short name T458
Test name
Test status
Simulation time 16107694 ps
CPU time 0.76 seconds
Started Aug 11 06:06:26 PM PDT 24
Finished Aug 11 06:06:26 PM PDT 24
Peak memory 205944 kb
Host smart-534f6936-8345-44c1-a3a3-5358ba4349dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413796408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.413796408
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1982452716
Short name T419
Test name
Test status
Simulation time 858492770 ps
CPU time 8.87 seconds
Started Aug 11 06:06:25 PM PDT 24
Finished Aug 11 06:06:34 PM PDT 24
Peak memory 214364 kb
Host smart-6997e2f2-f38e-4144-868b-009c2a20e365
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982452716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1982452716
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4138432787
Short name T60
Test name
Test status
Simulation time 95362018 ps
CPU time 4.66 seconds
Started Aug 11 06:06:23 PM PDT 24
Finished Aug 11 06:06:28 PM PDT 24
Peak memory 220396 kb
Host smart-cc0d0cc6-abe8-4350-9b3d-91c24e7bb2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138432787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4138432787
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3117406087
Short name T69
Test name
Test status
Simulation time 301057160 ps
CPU time 3.49 seconds
Started Aug 11 06:06:32 PM PDT 24
Finished Aug 11 06:06:36 PM PDT 24
Peak memory 218268 kb
Host smart-d8a70999-728c-440d-9795-1507a0c25cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117406087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3117406087
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.265133484
Short name T103
Test name
Test status
Simulation time 241291258 ps
CPU time 3.55 seconds
Started Aug 11 06:06:25 PM PDT 24
Finished Aug 11 06:06:29 PM PDT 24
Peak memory 214464 kb
Host smart-dbcaa9c4-a476-494a-87bd-46873e480a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265133484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.265133484
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3388274904
Short name T385
Test name
Test status
Simulation time 118590888 ps
CPU time 3.22 seconds
Started Aug 11 06:06:26 PM PDT 24
Finished Aug 11 06:06:29 PM PDT 24
Peak memory 214140 kb
Host smart-22ad4457-abd1-484c-9720-52c615fef09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388274904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3388274904
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3421233141
Short name T367
Test name
Test status
Simulation time 160407208 ps
CPU time 5.1 seconds
Started Aug 11 06:06:37 PM PDT 24
Finished Aug 11 06:06:43 PM PDT 24
Peak memory 214312 kb
Host smart-1f304808-40a6-49b3-ab0d-f2b730f5de38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421233141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3421233141
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1216239354
Short name T590
Test name
Test status
Simulation time 52456607 ps
CPU time 3.29 seconds
Started Aug 11 06:06:26 PM PDT 24
Finished Aug 11 06:06:30 PM PDT 24
Peak memory 207452 kb
Host smart-769dd26c-fbc0-4e23-8644-bd6468406aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216239354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1216239354
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3915864899
Short name T906
Test name
Test status
Simulation time 221588576 ps
CPU time 6.4 seconds
Started Aug 11 06:06:27 PM PDT 24
Finished Aug 11 06:06:33 PM PDT 24
Peak memory 208600 kb
Host smart-3665ff8e-63e3-4415-98dc-fa294e58e54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915864899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3915864899
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1948611733
Short name T539
Test name
Test status
Simulation time 135979349 ps
CPU time 3.73 seconds
Started Aug 11 06:06:29 PM PDT 24
Finished Aug 11 06:06:32 PM PDT 24
Peak memory 208872 kb
Host smart-7f005116-22dc-4b01-8d84-ee2903b3c349
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948611733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1948611733
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2058414653
Short name T878
Test name
Test status
Simulation time 50414967 ps
CPU time 2.85 seconds
Started Aug 11 06:06:29 PM PDT 24
Finished Aug 11 06:06:32 PM PDT 24
Peak memory 206944 kb
Host smart-e40691c9-ef00-44eb-b67e-c75bb0226e46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058414653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2058414653
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2540804004
Short name T665
Test name
Test status
Simulation time 990623530 ps
CPU time 5.15 seconds
Started Aug 11 06:06:33 PM PDT 24
Finished Aug 11 06:06:38 PM PDT 24
Peak memory 208716 kb
Host smart-69c5e25e-d5b8-4649-a5d9-a0143d059b8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540804004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2540804004
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2944804078
Short name T645
Test name
Test status
Simulation time 325966230 ps
CPU time 7.77 seconds
Started Aug 11 06:06:23 PM PDT 24
Finished Aug 11 06:06:31 PM PDT 24
Peak memory 209364 kb
Host smart-f3bcd3a9-1680-4817-a718-0afdd56dd2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944804078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2944804078
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2799715539
Short name T399
Test name
Test status
Simulation time 107259374 ps
CPU time 3 seconds
Started Aug 11 06:06:24 PM PDT 24
Finished Aug 11 06:06:28 PM PDT 24
Peak memory 206656 kb
Host smart-a32fb8e7-9872-4f06-a0f1-cdfbf9886035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799715539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2799715539
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.9416470
Short name T608
Test name
Test status
Simulation time 871979942 ps
CPU time 28.63 seconds
Started Aug 11 06:06:25 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 214332 kb
Host smart-f02f8fa8-ad27-46fc-b692-a9094e9e2f74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9416470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.9416470
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2274192947
Short name T119
Test name
Test status
Simulation time 191833941 ps
CPU time 3.24 seconds
Started Aug 11 06:06:24 PM PDT 24
Finished Aug 11 06:06:28 PM PDT 24
Peak memory 208464 kb
Host smart-ed8d59be-eb5f-4b81-9cef-7ed0268454a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274192947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2274192947
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3871902318
Short name T728
Test name
Test status
Simulation time 45739521 ps
CPU time 1.81 seconds
Started Aug 11 06:06:38 PM PDT 24
Finished Aug 11 06:06:40 PM PDT 24
Peak memory 209584 kb
Host smart-e46c2787-f61a-4ddd-8d73-8a419b3772f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871902318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3871902318
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3466672040
Short name T710
Test name
Test status
Simulation time 37624095 ps
CPU time 0.78 seconds
Started Aug 11 06:06:25 PM PDT 24
Finished Aug 11 06:06:26 PM PDT 24
Peak memory 205964 kb
Host smart-78e1c715-6920-419e-8b9a-ccb744ee7db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466672040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3466672040
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4019423378
Short name T37
Test name
Test status
Simulation time 110673554 ps
CPU time 4.48 seconds
Started Aug 11 06:06:29 PM PDT 24
Finished Aug 11 06:06:34 PM PDT 24
Peak memory 214528 kb
Host smart-924aac19-e526-43ab-9984-a6163a26550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019423378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4019423378
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1366874962
Short name T348
Test name
Test status
Simulation time 161542198 ps
CPU time 2.8 seconds
Started Aug 11 06:06:27 PM PDT 24
Finished Aug 11 06:06:30 PM PDT 24
Peak memory 214388 kb
Host smart-441da767-0afc-42cb-9789-115669508b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366874962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1366874962
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2052270827
Short name T536
Test name
Test status
Simulation time 382880831 ps
CPU time 3.85 seconds
Started Aug 11 06:06:37 PM PDT 24
Finished Aug 11 06:06:41 PM PDT 24
Peak memory 220692 kb
Host smart-d7c849d5-c670-406a-81fc-90404b3490c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052270827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2052270827
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3115671859
Short name T63
Test name
Test status
Simulation time 140641529 ps
CPU time 5.1 seconds
Started Aug 11 06:06:32 PM PDT 24
Finished Aug 11 06:06:37 PM PDT 24
Peak memory 218268 kb
Host smart-88a3d849-3b68-459b-9700-d70b2447bcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115671859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3115671859
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2207709536
Short name T569
Test name
Test status
Simulation time 69546507 ps
CPU time 2.81 seconds
Started Aug 11 06:06:22 PM PDT 24
Finished Aug 11 06:06:25 PM PDT 24
Peak memory 218276 kb
Host smart-754c4a6a-d51e-4768-a890-838cdfb2cc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207709536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2207709536
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1683657361
Short name T840
Test name
Test status
Simulation time 160421277 ps
CPU time 5.22 seconds
Started Aug 11 06:06:24 PM PDT 24
Finished Aug 11 06:06:29 PM PDT 24
Peak memory 208444 kb
Host smart-13c27991-9c29-4063-8390-4d190901cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683657361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1683657361
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3113902573
Short name T806
Test name
Test status
Simulation time 142113144 ps
CPU time 5.05 seconds
Started Aug 11 06:06:33 PM PDT 24
Finished Aug 11 06:06:38 PM PDT 24
Peak memory 208780 kb
Host smart-bd068c4a-8f4a-49fe-9537-8dfe09a98f08
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113902573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3113902573
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2877485270
Short name T811
Test name
Test status
Simulation time 43430794 ps
CPU time 2.78 seconds
Started Aug 11 06:06:28 PM PDT 24
Finished Aug 11 06:06:30 PM PDT 24
Peak memory 208772 kb
Host smart-f33f2d93-2564-4ed2-b514-974641611738
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877485270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2877485270
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3317359570
Short name T870
Test name
Test status
Simulation time 78047474 ps
CPU time 1.71 seconds
Started Aug 11 06:06:22 PM PDT 24
Finished Aug 11 06:06:23 PM PDT 24
Peak memory 206756 kb
Host smart-f8470f48-d0e3-4424-9efa-72f1beddde8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317359570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3317359570
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3876226641
Short name T535
Test name
Test status
Simulation time 125183796 ps
CPU time 2.73 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:37 PM PDT 24
Peak memory 209780 kb
Host smart-eadd8a1d-ea3f-4892-aaa5-4d75ca2e2ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876226641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3876226641
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2551318736
Short name T589
Test name
Test status
Simulation time 119964664 ps
CPU time 1.76 seconds
Started Aug 11 06:06:27 PM PDT 24
Finished Aug 11 06:06:29 PM PDT 24
Peak memory 206864 kb
Host smart-0df9b511-0240-4ebf-9eaa-5648a343f2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551318736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2551318736
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.458693510
Short name T75
Test name
Test status
Simulation time 1889707288 ps
CPU time 21.31 seconds
Started Aug 11 06:06:28 PM PDT 24
Finished Aug 11 06:06:49 PM PDT 24
Peak memory 215124 kb
Host smart-e5b833b5-d330-4c29-a6bd-4b42bfcef764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458693510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.458693510
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1925683035
Short name T729
Test name
Test status
Simulation time 227044177 ps
CPU time 9.8 seconds
Started Aug 11 06:06:26 PM PDT 24
Finished Aug 11 06:06:36 PM PDT 24
Peak memory 222472 kb
Host smart-12efe483-16a8-4f9d-83d3-7dd706f8bf33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925683035 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1925683035
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1342098635
Short name T335
Test name
Test status
Simulation time 167930669 ps
CPU time 3.02 seconds
Started Aug 11 06:06:33 PM PDT 24
Finished Aug 11 06:06:36 PM PDT 24
Peak memory 207424 kb
Host smart-2585a267-799b-42cc-8ce4-3e26accc6648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342098635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1342098635
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1154566173
Short name T390
Test name
Test status
Simulation time 72164315 ps
CPU time 3.03 seconds
Started Aug 11 06:06:38 PM PDT 24
Finished Aug 11 06:06:41 PM PDT 24
Peak memory 210252 kb
Host smart-60da0c1a-2369-4064-a58a-21c9901b4009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154566173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1154566173
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1337128034
Short name T118
Test name
Test status
Simulation time 35765670 ps
CPU time 0.72 seconds
Started Aug 11 06:06:33 PM PDT 24
Finished Aug 11 06:06:34 PM PDT 24
Peak memory 205920 kb
Host smart-22566cbb-f8df-49ad-8c6e-0fc50909f159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337128034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1337128034
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.861112885
Short name T691
Test name
Test status
Simulation time 296197522 ps
CPU time 2.09 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:36 PM PDT 24
Peak memory 208112 kb
Host smart-ae18fec0-cdbf-4915-bd1c-9d139d0bb122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861112885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.861112885
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3014322338
Short name T100
Test name
Test status
Simulation time 92717467 ps
CPU time 3.26 seconds
Started Aug 11 06:06:35 PM PDT 24
Finished Aug 11 06:06:38 PM PDT 24
Peak memory 209288 kb
Host smart-959c8266-76cb-4277-958b-7bcacbed6e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014322338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3014322338
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.4115563901
Short name T879
Test name
Test status
Simulation time 503563844 ps
CPU time 7.69 seconds
Started Aug 11 06:06:36 PM PDT 24
Finished Aug 11 06:06:44 PM PDT 24
Peak memory 214456 kb
Host smart-2202420d-cf2c-4908-85cf-fb98a7ad8cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115563901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.4115563901
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.333052439
Short name T412
Test name
Test status
Simulation time 33967943 ps
CPU time 2.69 seconds
Started Aug 11 06:06:38 PM PDT 24
Finished Aug 11 06:06:41 PM PDT 24
Peak memory 209804 kb
Host smart-576ba7f7-40a0-473f-99dc-ab83d0555938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333052439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.333052439
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1133692644
Short name T518
Test name
Test status
Simulation time 183800531 ps
CPU time 3.15 seconds
Started Aug 11 06:06:33 PM PDT 24
Finished Aug 11 06:06:37 PM PDT 24
Peak memory 209924 kb
Host smart-018940d0-fa6b-4d27-87b4-c3749a0a3c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133692644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1133692644
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2346897697
Short name T740
Test name
Test status
Simulation time 455236634 ps
CPU time 6.79 seconds
Started Aug 11 06:06:26 PM PDT 24
Finished Aug 11 06:06:33 PM PDT 24
Peak memory 208476 kb
Host smart-a46c41d2-23be-42e8-a2b1-fa0bf50a9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346897697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2346897697
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1887794833
Short name T904
Test name
Test status
Simulation time 140410158 ps
CPU time 2.27 seconds
Started Aug 11 06:06:31 PM PDT 24
Finished Aug 11 06:06:34 PM PDT 24
Peak memory 206892 kb
Host smart-42b6f906-d2e3-419e-be18-f16a82233355
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887794833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1887794833
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.704507868
Short name T799
Test name
Test status
Simulation time 38339255 ps
CPU time 2.74 seconds
Started Aug 11 06:06:29 PM PDT 24
Finished Aug 11 06:06:32 PM PDT 24
Peak memory 209088 kb
Host smart-2a1ee337-5e0e-4167-9132-0bd6f93fc214
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704507868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.704507868
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3647014806
Short name T685
Test name
Test status
Simulation time 190909808 ps
CPU time 6.43 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:41 PM PDT 24
Peak memory 208496 kb
Host smart-50852ce7-4510-4006-9bb8-828b079d83ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647014806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3647014806
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3233249339
Short name T814
Test name
Test status
Simulation time 158892872 ps
CPU time 2.25 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:36 PM PDT 24
Peak memory 207136 kb
Host smart-8c52d8aa-4245-4d00-a074-288fe4aa63d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233249339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3233249339
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.463098354
Short name T567
Test name
Test status
Simulation time 213095696 ps
CPU time 2.11 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:36 PM PDT 24
Peak memory 206808 kb
Host smart-9612709a-2421-4451-849a-f2574d6396ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463098354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.463098354
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1531299212
Short name T801
Test name
Test status
Simulation time 354944065 ps
CPU time 11.97 seconds
Started Aug 11 06:06:35 PM PDT 24
Finished Aug 11 06:06:48 PM PDT 24
Peak memory 221652 kb
Host smart-baf27e85-aa96-4ef2-86c4-1a1a439bd6a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531299212 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1531299212
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.424208965
Short name T414
Test name
Test status
Simulation time 8634662592 ps
CPU time 58.24 seconds
Started Aug 11 06:06:36 PM PDT 24
Finished Aug 11 06:07:35 PM PDT 24
Peak memory 209724 kb
Host smart-e82f2a11-4f0d-4787-bdc7-abe25246fefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424208965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.424208965
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3033105169
Short name T178
Test name
Test status
Simulation time 188662363 ps
CPU time 7.49 seconds
Started Aug 11 06:06:33 PM PDT 24
Finished Aug 11 06:06:40 PM PDT 24
Peak memory 210868 kb
Host smart-5d6c7aa1-884b-45b6-a35d-6d591958b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033105169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3033105169
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3395966232
Short name T880
Test name
Test status
Simulation time 10667544 ps
CPU time 0.8 seconds
Started Aug 11 06:06:33 PM PDT 24
Finished Aug 11 06:06:34 PM PDT 24
Peak memory 205912 kb
Host smart-24b25ed2-99fc-4a6a-90e5-daaf8171d2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395966232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3395966232
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1772801468
Short name T858
Test name
Test status
Simulation time 94175824 ps
CPU time 3.74 seconds
Started Aug 11 06:06:36 PM PDT 24
Finished Aug 11 06:06:40 PM PDT 24
Peak memory 209496 kb
Host smart-7d38825a-9955-44ff-b73f-7111e508ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772801468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1772801468
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.985109144
Short name T343
Test name
Test status
Simulation time 59962336 ps
CPU time 3.02 seconds
Started Aug 11 06:06:35 PM PDT 24
Finished Aug 11 06:06:39 PM PDT 24
Peak memory 214588 kb
Host smart-b0f2f23a-a142-4b37-b4ef-3d915e1f5e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985109144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.985109144
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3111875948
Short name T303
Test name
Test status
Simulation time 189052018 ps
CPU time 4.18 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:38 PM PDT 24
Peak memory 222348 kb
Host smart-4d44c002-d8e9-4b2b-92c9-6cb86bd784ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111875948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3111875948
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_random.1870962430
Short name T298
Test name
Test status
Simulation time 517776086 ps
CPU time 5.59 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:39 PM PDT 24
Peak memory 214256 kb
Host smart-baad373d-2590-4d19-a912-e0eabc1a0a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870962430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1870962430
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2026610100
Short name T441
Test name
Test status
Simulation time 66112895 ps
CPU time 3.5 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:38 PM PDT 24
Peak memory 208688 kb
Host smart-4ab47c5b-811a-4763-bb32-fd9477448954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026610100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2026610100
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.945147227
Short name T593
Test name
Test status
Simulation time 438613036 ps
CPU time 3.65 seconds
Started Aug 11 06:06:40 PM PDT 24
Finished Aug 11 06:06:44 PM PDT 24
Peak memory 206804 kb
Host smart-4643aee9-6e1d-42e9-ad74-1e0f5fc11e03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945147227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.945147227
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.638226263
Short name T331
Test name
Test status
Simulation time 84692053 ps
CPU time 1.96 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:36 PM PDT 24
Peak memory 207404 kb
Host smart-f7962f48-7678-470a-875f-9e82dfc79b21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638226263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.638226263
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4216325953
Short name T743
Test name
Test status
Simulation time 331422873 ps
CPU time 4.48 seconds
Started Aug 11 06:06:31 PM PDT 24
Finished Aug 11 06:06:35 PM PDT 24
Peak memory 206820 kb
Host smart-fead9e65-c944-44d0-9d63-a0cb1981cf3d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216325953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4216325953
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3328788126
Short name T293
Test name
Test status
Simulation time 82944127 ps
CPU time 3.33 seconds
Started Aug 11 06:06:37 PM PDT 24
Finished Aug 11 06:06:40 PM PDT 24
Peak memory 214324 kb
Host smart-a74e6991-2e15-422b-881e-e4b81b30f3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328788126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3328788126
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1860624367
Short name T486
Test name
Test status
Simulation time 350690505 ps
CPU time 5.86 seconds
Started Aug 11 06:06:32 PM PDT 24
Finished Aug 11 06:06:38 PM PDT 24
Peak memory 208688 kb
Host smart-24c2d507-2a60-48eb-97a1-f9af33a8fce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860624367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1860624367
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.927034251
Short name T650
Test name
Test status
Simulation time 3539511008 ps
CPU time 44.4 seconds
Started Aug 11 06:06:31 PM PDT 24
Finished Aug 11 06:07:16 PM PDT 24
Peak memory 222432 kb
Host smart-d497307f-ea74-432e-af01-8270a1bf8a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927034251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.927034251
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3992443890
Short name T830
Test name
Test status
Simulation time 51078497 ps
CPU time 3.14 seconds
Started Aug 11 06:06:38 PM PDT 24
Finished Aug 11 06:06:41 PM PDT 24
Peak memory 207368 kb
Host smart-ef20fbb3-3c55-4af0-8eed-245ba0de938c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992443890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3992443890
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1530451290
Short name T432
Test name
Test status
Simulation time 269202438 ps
CPU time 1.94 seconds
Started Aug 11 06:06:40 PM PDT 24
Finished Aug 11 06:06:42 PM PDT 24
Peak memory 210124 kb
Host smart-a4ab7738-b52d-40d7-aa49-f8868765aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530451290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1530451290
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1846240701
Short name T872
Test name
Test status
Simulation time 22858697 ps
CPU time 1 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:43 PM PDT 24
Peak memory 206032 kb
Host smart-0eb19a69-8d3e-4253-b61e-a8849add2d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846240701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1846240701
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2822732245
Short name T889
Test name
Test status
Simulation time 59694473 ps
CPU time 2.63 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:46 PM PDT 24
Peak memory 222436 kb
Host smart-6eaabde6-89fc-437b-9a00-15b0531ab416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822732245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2822732245
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.794612750
Short name T846
Test name
Test status
Simulation time 256174078 ps
CPU time 2.57 seconds
Started Aug 11 06:06:40 PM PDT 24
Finished Aug 11 06:06:43 PM PDT 24
Peak memory 218180 kb
Host smart-e97f294e-b282-47aa-a095-b4ed837c7fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794612750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.794612750
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1233942067
Short name T241
Test name
Test status
Simulation time 20561563280 ps
CPU time 54.14 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:07:40 PM PDT 24
Peak memory 222508 kb
Host smart-33027fa2-f208-40f7-928e-72b2d6927c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233942067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1233942067
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2862675137
Short name T702
Test name
Test status
Simulation time 33227058 ps
CPU time 2.39 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:06:49 PM PDT 24
Peak memory 214228 kb
Host smart-10d85039-82ee-4f70-8b25-6f8c3d29fea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862675137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2862675137
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1408638843
Short name T402
Test name
Test status
Simulation time 329397489 ps
CPU time 4.87 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:47 PM PDT 24
Peak memory 210244 kb
Host smart-3c3a5c4b-dda8-4f83-a7b6-98ab480daf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408638843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1408638843
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.536128877
Short name T287
Test name
Test status
Simulation time 451662205 ps
CPU time 4.76 seconds
Started Aug 11 06:06:34 PM PDT 24
Finished Aug 11 06:06:39 PM PDT 24
Peak memory 209192 kb
Host smart-91063b39-98ae-4188-a601-83c9a8a4c41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536128877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.536128877
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.419636503
Short name T602
Test name
Test status
Simulation time 1018136730 ps
CPU time 3.63 seconds
Started Aug 11 06:06:35 PM PDT 24
Finished Aug 11 06:06:39 PM PDT 24
Peak memory 208500 kb
Host smart-fbf1ca05-063b-42e7-bfb4-ad87423c0531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419636503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.419636503
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1389342814
Short name T368
Test name
Test status
Simulation time 455119952 ps
CPU time 4 seconds
Started Aug 11 06:06:35 PM PDT 24
Finished Aug 11 06:06:39 PM PDT 24
Peak memory 208764 kb
Host smart-2a999eb6-e60a-449f-a407-f97a3bbaca20
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389342814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1389342814
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1859587344
Short name T502
Test name
Test status
Simulation time 1185410256 ps
CPU time 2.92 seconds
Started Aug 11 06:06:32 PM PDT 24
Finished Aug 11 06:06:35 PM PDT 24
Peak memory 206916 kb
Host smart-c670db52-2a78-4264-a49e-e69904145d4f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859587344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1859587344
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3686388872
Short name T511
Test name
Test status
Simulation time 572515330 ps
CPU time 9.74 seconds
Started Aug 11 06:06:40 PM PDT 24
Finished Aug 11 06:06:50 PM PDT 24
Peak memory 208388 kb
Host smart-9ee38024-158d-4b64-84bf-59fb561e1390
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686388872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3686388872
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1883230955
Short name T616
Test name
Test status
Simulation time 407708392 ps
CPU time 2.71 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:45 PM PDT 24
Peak memory 207228 kb
Host smart-0a918b12-2cbe-4226-a54d-d86f1a70488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883230955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1883230955
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1817452678
Short name T579
Test name
Test status
Simulation time 63342225 ps
CPU time 2.66 seconds
Started Aug 11 06:06:37 PM PDT 24
Finished Aug 11 06:06:39 PM PDT 24
Peak memory 207372 kb
Host smart-622ed433-7041-465c-95a8-e2327fb3fef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817452678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1817452678
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2458031306
Short name T218
Test name
Test status
Simulation time 1071966562 ps
CPU time 13.54 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:56 PM PDT 24
Peak memory 222584 kb
Host smart-ab13a90e-63ec-4e99-bcd8-7efba052e4bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458031306 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2458031306
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2482898305
Short name T498
Test name
Test status
Simulation time 50475981 ps
CPU time 3.01 seconds
Started Aug 11 06:06:41 PM PDT 24
Finished Aug 11 06:06:44 PM PDT 24
Peak memory 208372 kb
Host smart-f0db8b71-e39a-4801-9915-0eead3fc1a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482898305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2482898305
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2638761076
Short name T640
Test name
Test status
Simulation time 8581495211 ps
CPU time 15.71 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:58 PM PDT 24
Peak memory 210920 kb
Host smart-a04dadb5-b7d2-41c4-b1e0-cdf388958b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638761076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2638761076
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2626999693
Short name T570
Test name
Test status
Simulation time 42391454 ps
CPU time 0.78 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:43 PM PDT 24
Peak memory 205956 kb
Host smart-41045fde-5ff2-40f8-8c6d-e04f4fea92cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626999693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2626999693
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1489732587
Short name T795
Test name
Test status
Simulation time 84345299 ps
CPU time 4.21 seconds
Started Aug 11 06:06:47 PM PDT 24
Finished Aug 11 06:06:51 PM PDT 24
Peak memory 209836 kb
Host smart-22efc483-1835-4701-8951-0e33dead8cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489732587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1489732587
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.136993211
Short name T730
Test name
Test status
Simulation time 87414515 ps
CPU time 2 seconds
Started Aug 11 06:06:44 PM PDT 24
Finished Aug 11 06:06:46 PM PDT 24
Peak memory 207888 kb
Host smart-d965eed3-b86c-4a1f-8fcd-17fc41bdf4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136993211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.136993211
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1980499973
Short name T21
Test name
Test status
Simulation time 128930930 ps
CPU time 2.59 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:06:49 PM PDT 24
Peak memory 220872 kb
Host smart-d656458f-636d-41e2-b1c1-6d5bd2c54bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980499973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1980499973
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1087195474
Short name T320
Test name
Test status
Simulation time 115503252 ps
CPU time 4.9 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:48 PM PDT 24
Peak memory 222328 kb
Host smart-4dd257e8-c86f-4885-9adc-c36e292e8359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087195474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1087195474
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2168369168
Short name T51
Test name
Test status
Simulation time 187366636 ps
CPU time 3.59 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:46 PM PDT 24
Peak memory 209520 kb
Host smart-3ef05e56-b81f-4913-ab9e-7d7aff7ca2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168369168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2168369168
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3782490892
Short name T881
Test name
Test status
Simulation time 201917505 ps
CPU time 5.43 seconds
Started Aug 11 06:06:47 PM PDT 24
Finished Aug 11 06:06:52 PM PDT 24
Peak memory 209772 kb
Host smart-9ace68bb-8912-46ce-9ff9-2e63b8454ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782490892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3782490892
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3090904093
Short name T379
Test name
Test status
Simulation time 392586043 ps
CPU time 3.22 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:46 PM PDT 24
Peak memory 206916 kb
Host smart-ab4d395c-bf47-4d13-a76c-57c155d2b175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090904093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3090904093
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3843564051
Short name T803
Test name
Test status
Simulation time 438386262 ps
CPU time 4.93 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:48 PM PDT 24
Peak memory 208140 kb
Host smart-a7915c72-029a-45a6-889a-4e9cf09a710c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843564051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3843564051
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.901401553
Short name T468
Test name
Test status
Simulation time 1337795023 ps
CPU time 32.19 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:07:15 PM PDT 24
Peak memory 208104 kb
Host smart-2c0a9f40-fa00-482d-9918-df852318f0b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901401553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.901401553
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.639340402
Short name T829
Test name
Test status
Simulation time 33021751 ps
CPU time 2.37 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:06:49 PM PDT 24
Peak memory 206448 kb
Host smart-fdf57944-f5e1-4d7b-9838-297b974ede7b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639340402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.639340402
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4046686279
Short name T687
Test name
Test status
Simulation time 154388494 ps
CPU time 2.3 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:45 PM PDT 24
Peak memory 214392 kb
Host smart-28f9e644-b1da-43ea-b52c-9bde31eb9406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046686279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4046686279
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2612681739
Short name T195
Test name
Test status
Simulation time 2371716385 ps
CPU time 20.65 seconds
Started Aug 11 06:06:44 PM PDT 24
Finished Aug 11 06:07:05 PM PDT 24
Peak memory 208844 kb
Host smart-7cb74191-7fae-4e90-a66d-264fedf6cb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612681739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2612681739
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4281582827
Short name T239
Test name
Test status
Simulation time 1040915610 ps
CPU time 13.05 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:07:00 PM PDT 24
Peak memory 215196 kb
Host smart-f3de2ec1-94e4-4534-8760-f1104b00bd2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281582827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4281582827
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2338067768
Short name T595
Test name
Test status
Simulation time 852101001 ps
CPU time 9.15 seconds
Started Aug 11 06:06:45 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 207208 kb
Host smart-bb41d9fc-c0cf-4a59-a6ef-59b0e74be05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338067768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2338067768
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1331745440
Short name T577
Test name
Test status
Simulation time 1273775819 ps
CPU time 13.32 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:06:59 PM PDT 24
Peak memory 210856 kb
Host smart-35ef6929-4596-42dc-8ccf-4dfaff298116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331745440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1331745440
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.825731442
Short name T523
Test name
Test status
Simulation time 34031655 ps
CPU time 0.82 seconds
Started Aug 11 06:06:45 PM PDT 24
Finished Aug 11 06:06:47 PM PDT 24
Peak memory 205880 kb
Host smart-19bf4ce0-9965-4f94-b81d-021dd39aee4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825731442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.825731442
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3578350673
Short name T374
Test name
Test status
Simulation time 388275920 ps
CPU time 4.04 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:47 PM PDT 24
Peak memory 215088 kb
Host smart-81939d06-1faf-45d7-b4d5-03e482cd0aa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3578350673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3578350673
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1891138086
Short name T893
Test name
Test status
Simulation time 225519597 ps
CPU time 3.69 seconds
Started Aug 11 06:06:45 PM PDT 24
Finished Aug 11 06:06:49 PM PDT 24
Peak memory 208708 kb
Host smart-5c77e2fe-6f19-4cd4-ab3e-63bbe46257ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891138086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1891138086
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3494216771
Short name T273
Test name
Test status
Simulation time 288640461 ps
CPU time 4.22 seconds
Started Aug 11 06:06:45 PM PDT 24
Finished Aug 11 06:06:49 PM PDT 24
Peak memory 214268 kb
Host smart-bb1035fe-238a-490c-88ee-1a6923090a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494216771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3494216771
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4218846915
Short name T253
Test name
Test status
Simulation time 136651569 ps
CPU time 1.87 seconds
Started Aug 11 06:06:45 PM PDT 24
Finished Aug 11 06:06:47 PM PDT 24
Peak memory 214224 kb
Host smart-3a38f2f6-9d10-4ca3-a76b-1ea2852551a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218846915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4218846915
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.650362993
Short name T54
Test name
Test status
Simulation time 7041012618 ps
CPU time 24.32 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:07:07 PM PDT 24
Peak memory 219264 kb
Host smart-f25ead2a-19e4-4c90-8c5f-45afb620fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650362993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.650362993
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1675962737
Short name T657
Test name
Test status
Simulation time 7511929491 ps
CPU time 70.54 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:07:56 PM PDT 24
Peak memory 217040 kb
Host smart-9112b051-4dbe-4a4b-9c3e-1418c27ab591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675962737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1675962737
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3959600202
Short name T265
Test name
Test status
Simulation time 50990452 ps
CPU time 2.41 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:45 PM PDT 24
Peak memory 206892 kb
Host smart-e2dfffd4-f21c-435c-b93e-786aa382482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959600202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3959600202
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2389639349
Short name T80
Test name
Test status
Simulation time 181122673 ps
CPU time 7.38 seconds
Started Aug 11 06:06:41 PM PDT 24
Finished Aug 11 06:06:49 PM PDT 24
Peak memory 208564 kb
Host smart-15818394-ec55-40f9-a0c9-92aa40e98b48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389639349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2389639349
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4203327599
Short name T434
Test name
Test status
Simulation time 973934937 ps
CPU time 5.43 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:06:51 PM PDT 24
Peak memory 208072 kb
Host smart-f2272b8f-6897-46ff-ae5d-f0a5910e027d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203327599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4203327599
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4141501377
Short name T660
Test name
Test status
Simulation time 556978594 ps
CPU time 4.15 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:46 PM PDT 24
Peak memory 206780 kb
Host smart-c6fdb740-5bcc-494b-af7b-1c68f77234e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141501377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4141501377
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1780640498
Short name T809
Test name
Test status
Simulation time 148328986 ps
CPU time 3.05 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:46 PM PDT 24
Peak memory 214420 kb
Host smart-bfc884a2-b209-4c62-9c65-ee31787a1efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780640498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1780640498
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3939405749
Short name T606
Test name
Test status
Simulation time 2331049412 ps
CPU time 4.66 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:47 PM PDT 24
Peak memory 208600 kb
Host smart-661d83c4-a227-4418-b659-210aa86eeb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939405749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3939405749
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3550452829
Short name T720
Test name
Test status
Simulation time 2288710914 ps
CPU time 19.61 seconds
Started Aug 11 06:06:44 PM PDT 24
Finished Aug 11 06:07:04 PM PDT 24
Peak memory 222244 kb
Host smart-0d8b3625-9494-44de-98f3-0f3bd28ef179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550452829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3550452829
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3035165408
Short name T774
Test name
Test status
Simulation time 370246445 ps
CPU time 9.68 seconds
Started Aug 11 06:06:45 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 222588 kb
Host smart-70e828fd-c017-4b25-b78e-c95170dce109
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035165408 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3035165408
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1336832431
Short name T464
Test name
Test status
Simulation time 421163207 ps
CPU time 8.19 seconds
Started Aug 11 06:06:44 PM PDT 24
Finished Aug 11 06:06:53 PM PDT 24
Peak memory 217952 kb
Host smart-3256af11-6707-4470-ba38-02a2c1b046a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336832431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1336832431
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1533085515
Short name T428
Test name
Test status
Simulation time 13610436 ps
CPU time 0.74 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:52 PM PDT 24
Peak memory 205924 kb
Host smart-8d3b9f74-68d9-4f0f-a084-ba5b5642cc93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533085515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1533085515
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.36507205
Short name T425
Test name
Test status
Simulation time 61572858 ps
CPU time 4.68 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:48 PM PDT 24
Peak memory 214368 kb
Host smart-5f66f090-ccab-410e-abad-76562c5dd031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36507205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.36507205
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2983240159
Short name T31
Test name
Test status
Simulation time 370461760 ps
CPU time 2.9 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 209204 kb
Host smart-dfdadd7c-6a64-4952-ac49-81eb79e1e491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983240159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2983240159
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3856826631
Short name T338
Test name
Test status
Simulation time 541171592 ps
CPU time 6.47 seconds
Started Aug 11 06:06:40 PM PDT 24
Finished Aug 11 06:06:46 PM PDT 24
Peak memory 208576 kb
Host smart-8d1d1c5c-def6-4bd9-916b-355b571dd491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856826631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3856826631
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2466120063
Short name T22
Test name
Test status
Simulation time 181602899 ps
CPU time 4.61 seconds
Started Aug 11 06:06:50 PM PDT 24
Finished Aug 11 06:06:55 PM PDT 24
Peak memory 209620 kb
Host smart-5f791c9d-d055-4f0d-87fc-5048df9199be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466120063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2466120063
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3476264088
Short name T364
Test name
Test status
Simulation time 91683255 ps
CPU time 3.38 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:06:59 PM PDT 24
Peak memory 221632 kb
Host smart-e5b14e7e-4ed0-4065-8289-cc6159718d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476264088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3476264088
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1671715841
Short name T444
Test name
Test status
Simulation time 503901140 ps
CPU time 4.61 seconds
Started Aug 11 06:06:46 PM PDT 24
Finished Aug 11 06:06:50 PM PDT 24
Peak memory 214344 kb
Host smart-1a80faf6-0845-470e-9f1d-3848493f8a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671715841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1671715841
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.224918988
Short name T244
Test name
Test status
Simulation time 186047147 ps
CPU time 3.03 seconds
Started Aug 11 06:06:45 PM PDT 24
Finished Aug 11 06:06:48 PM PDT 24
Peak memory 214320 kb
Host smart-76a83598-c94e-4c8a-89c2-256f884ec285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224918988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.224918988
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2984069361
Short name T274
Test name
Test status
Simulation time 141093854 ps
CPU time 3.59 seconds
Started Aug 11 06:06:44 PM PDT 24
Finished Aug 11 06:06:48 PM PDT 24
Peak memory 208936 kb
Host smart-8a41580a-a6cc-4aae-ae8b-12b257347371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984069361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2984069361
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2657110946
Short name T771
Test name
Test status
Simulation time 256349627 ps
CPU time 3.41 seconds
Started Aug 11 06:06:45 PM PDT 24
Finished Aug 11 06:06:48 PM PDT 24
Peak memory 208908 kb
Host smart-1fc78a64-d1ab-4014-a13f-81227a6e92fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657110946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2657110946
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2479098710
Short name T713
Test name
Test status
Simulation time 203563447 ps
CPU time 5.9 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:49 PM PDT 24
Peak memory 207888 kb
Host smart-ba12d4c7-28f3-40e4-8185-bc2fe8f71a27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479098710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2479098710
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3157950274
Short name T519
Test name
Test status
Simulation time 71718488 ps
CPU time 3.63 seconds
Started Aug 11 06:06:42 PM PDT 24
Finished Aug 11 06:06:45 PM PDT 24
Peak memory 208616 kb
Host smart-275ff670-9727-4f2f-b5e0-3bc810d7fab0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157950274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3157950274
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.751896916
Short name T547
Test name
Test status
Simulation time 70527705 ps
CPU time 2.29 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 208264 kb
Host smart-6b98a2d6-590a-4bb4-9c46-5d79b26cf7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751896916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.751896916
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1837605961
Short name T472
Test name
Test status
Simulation time 78913141 ps
CPU time 3.19 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:46 PM PDT 24
Peak memory 208640 kb
Host smart-655138ab-c723-4dc9-a495-33f8f90b995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837605961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1837605961
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1334267607
Short name T874
Test name
Test status
Simulation time 1215730989 ps
CPU time 49.32 seconds
Started Aug 11 06:06:49 PM PDT 24
Finished Aug 11 06:07:39 PM PDT 24
Peak memory 216476 kb
Host smart-ada0526b-a2df-4946-b8ef-a2544971496f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334267607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1334267607
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1449072761
Short name T340
Test name
Test status
Simulation time 2129365710 ps
CPU time 10.28 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:07:03 PM PDT 24
Peak memory 218688 kb
Host smart-ef71aa06-1ddd-4914-a9f3-1f9adc5dcccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449072761 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1449072761
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.772809392
Short name T300
Test name
Test status
Simulation time 526415065 ps
CPU time 4.17 seconds
Started Aug 11 06:06:43 PM PDT 24
Finished Aug 11 06:06:47 PM PDT 24
Peak memory 209424 kb
Host smart-5f848757-c566-44e9-8aab-caff4510cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772809392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.772809392
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.324921006
Short name T860
Test name
Test status
Simulation time 231702448 ps
CPU time 1.99 seconds
Started Aug 11 06:06:50 PM PDT 24
Finished Aug 11 06:06:52 PM PDT 24
Peak memory 210532 kb
Host smart-43f3b4fa-7481-474c-b317-4d2d340115f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324921006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.324921006
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2659064429
Short name T793
Test name
Test status
Simulation time 41472331 ps
CPU time 0.76 seconds
Started Aug 11 06:06:53 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 206028 kb
Host smart-9804a51d-e136-4818-a802-31b3bbe44e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659064429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2659064429
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3257512951
Short name T387
Test name
Test status
Simulation time 871354690 ps
CPU time 24.54 seconds
Started Aug 11 06:06:53 PM PDT 24
Finished Aug 11 06:07:18 PM PDT 24
Peak memory 215584 kb
Host smart-3e32e8c8-06dd-458c-8588-d60126ed4c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257512951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3257512951
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1456481504
Short name T533
Test name
Test status
Simulation time 106878131 ps
CPU time 3.23 seconds
Started Aug 11 06:06:48 PM PDT 24
Finished Aug 11 06:06:51 PM PDT 24
Peak memory 210024 kb
Host smart-8b61e7de-c31a-4b4f-9bdc-862e6e208b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456481504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1456481504
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.154737706
Short name T617
Test name
Test status
Simulation time 41106562 ps
CPU time 1.69 seconds
Started Aug 11 06:06:50 PM PDT 24
Finished Aug 11 06:06:52 PM PDT 24
Peak memory 222472 kb
Host smart-757e4a9c-1c59-4243-80aa-fc2ea03c0d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154737706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.154737706
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.221481412
Short name T96
Test name
Test status
Simulation time 73709464 ps
CPU time 2.3 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 214632 kb
Host smart-10ac6cc3-b5e3-4c7a-ad23-470a6124b023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221481412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.221481412
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2346951179
Short name T715
Test name
Test status
Simulation time 33747883 ps
CPU time 2.62 seconds
Started Aug 11 06:06:50 PM PDT 24
Finished Aug 11 06:06:53 PM PDT 24
Peak memory 218460 kb
Host smart-113b2c22-d2a8-47c5-86b3-7d2036892642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346951179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2346951179
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3542771235
Short name T666
Test name
Test status
Simulation time 169539274 ps
CPU time 3.95 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:55 PM PDT 24
Peak memory 209208 kb
Host smart-1fefdf70-d251-44d8-93e7-49b0fb180ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542771235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3542771235
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3481015800
Short name T284
Test name
Test status
Simulation time 116732475 ps
CPU time 2.28 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 208468 kb
Host smart-7adc5e5f-5272-4269-baa3-a03a33717a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481015800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3481015800
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2031667865
Short name T756
Test name
Test status
Simulation time 1638913763 ps
CPU time 8 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:07:04 PM PDT 24
Peak memory 208924 kb
Host smart-7bc32f5a-7f1d-4a41-9e93-083e5ae82f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031667865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2031667865
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2651057724
Short name T141
Test name
Test status
Simulation time 223808634 ps
CPU time 2.87 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:06:55 PM PDT 24
Peak memory 207004 kb
Host smart-d812445c-c7a9-4de7-a7bf-f623614b1bcf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651057724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2651057724
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1776985236
Short name T436
Test name
Test status
Simulation time 71505108 ps
CPU time 3.27 seconds
Started Aug 11 06:06:49 PM PDT 24
Finished Aug 11 06:06:53 PM PDT 24
Peak memory 206968 kb
Host smart-5b586829-be83-47aa-873f-94c9cea6ec09
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776985236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1776985236
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.267109631
Short name T766
Test name
Test status
Simulation time 6186389180 ps
CPU time 35.58 seconds
Started Aug 11 06:06:47 PM PDT 24
Finished Aug 11 06:07:23 PM PDT 24
Peak memory 209024 kb
Host smart-2b727057-e4e6-444f-b5f0-0821a40e4abd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267109631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.267109631
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3015163875
Short name T675
Test name
Test status
Simulation time 417761824 ps
CPU time 3.67 seconds
Started Aug 11 06:06:49 PM PDT 24
Finished Aug 11 06:06:53 PM PDT 24
Peak memory 208436 kb
Host smart-8617ff11-9575-454d-a225-5da122d7a8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015163875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3015163875
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1462584350
Short name T649
Test name
Test status
Simulation time 177848240 ps
CPU time 2.47 seconds
Started Aug 11 06:06:53 PM PDT 24
Finished Aug 11 06:06:56 PM PDT 24
Peak memory 206708 kb
Host smart-71ad006a-f612-478c-8e61-fc0c5b1291cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462584350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1462584350
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3979674058
Short name T686
Test name
Test status
Simulation time 1463986345 ps
CPU time 19.3 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:07:10 PM PDT 24
Peak memory 215676 kb
Host smart-15f0d414-f8ef-447a-85b7-d5c8bff8adb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979674058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3979674058
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1620968947
Short name T330
Test name
Test status
Simulation time 614029843 ps
CPU time 24.28 seconds
Started Aug 11 06:06:50 PM PDT 24
Finished Aug 11 06:07:15 PM PDT 24
Peak memory 222464 kb
Host smart-d7210817-3684-46a5-8131-73530029d682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620968947 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1620968947
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2586152367
Short name T469
Test name
Test status
Simulation time 46633345 ps
CPU time 3.09 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:06:55 PM PDT 24
Peak memory 207036 kb
Host smart-16069a4d-880e-4da9-9a58-b44c1c618095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586152367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2586152367
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3009232561
Short name T719
Test name
Test status
Simulation time 557791208 ps
CPU time 2.81 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:06:58 PM PDT 24
Peak memory 209752 kb
Host smart-d5055878-bcdd-444f-bf68-597c9c4c9525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009232561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3009232561
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1865549958
Short name T760
Test name
Test status
Simulation time 31319920 ps
CPU time 0.79 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:06:53 PM PDT 24
Peak memory 205956 kb
Host smart-d9dee076-8ae7-4031-9eab-d5f3fbbb43ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865549958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1865549958
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1399187406
Short name T427
Test name
Test status
Simulation time 435102151 ps
CPU time 2.18 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 214232 kb
Host smart-19b43e8f-b3cc-4f6c-a0bc-c646ac9bbde0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399187406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1399187406
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4256887942
Short name T696
Test name
Test status
Simulation time 59022256 ps
CPU time 2.77 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:06:55 PM PDT 24
Peak memory 214276 kb
Host smart-b0b75d07-80ce-401d-af41-8f9949da92c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256887942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4256887942
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2318352864
Short name T911
Test name
Test status
Simulation time 776700215 ps
CPU time 2.58 seconds
Started Aug 11 06:06:53 PM PDT 24
Finished Aug 11 06:06:56 PM PDT 24
Peak memory 208440 kb
Host smart-3c40a6d9-3b59-465f-b466-36c47de7a3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318352864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2318352864
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1592775396
Short name T712
Test name
Test status
Simulation time 262025188 ps
CPU time 2.94 seconds
Started Aug 11 06:06:49 PM PDT 24
Finished Aug 11 06:06:53 PM PDT 24
Peak memory 214292 kb
Host smart-cab3cd70-ef2c-4fed-9793-be33cdbf4f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592775396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1592775396
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3856611377
Short name T663
Test name
Test status
Simulation time 362211686 ps
CPU time 3.75 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 222332 kb
Host smart-5eba8780-07e2-42b8-98a8-598e6f00161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856611377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3856611377
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2355077760
Short name T761
Test name
Test status
Simulation time 415880661 ps
CPU time 5.09 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:56 PM PDT 24
Peak memory 206064 kb
Host smart-a95883ec-dfbe-4e29-a057-62d287307b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355077760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2355077760
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2595965113
Short name T276
Test name
Test status
Simulation time 679847964 ps
CPU time 4.04 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:07:03 PM PDT 24
Peak memory 209896 kb
Host smart-905c93e9-7033-46c7-adac-5943fe485f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595965113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2595965113
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4237854527
Short name T326
Test name
Test status
Simulation time 1082856164 ps
CPU time 8.42 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:07:00 PM PDT 24
Peak memory 208404 kb
Host smart-53b25e3c-7ba1-4e47-a637-6a5c4e87da1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237854527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4237854527
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2391736290
Short name T624
Test name
Test status
Simulation time 11832303843 ps
CPU time 47.17 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:07:39 PM PDT 24
Peak memory 208196 kb
Host smart-0df2224d-fabe-44f3-b425-a7af01d9e71e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391736290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2391736290
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3633486778
Short name T86
Test name
Test status
Simulation time 60530908 ps
CPU time 2.28 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:00 PM PDT 24
Peak memory 206812 kb
Host smart-55a13779-9ded-45aa-9eb9-d78c6336216d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633486778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3633486778
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1919051120
Short name T205
Test name
Test status
Simulation time 152664848 ps
CPU time 2.26 seconds
Started Aug 11 06:06:53 PM PDT 24
Finished Aug 11 06:06:56 PM PDT 24
Peak memory 207008 kb
Host smart-5f8c53aa-7f9a-4812-b142-a4cd26e1fa1b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919051120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1919051120
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3978852123
Short name T492
Test name
Test status
Simulation time 81830189 ps
CPU time 1.74 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:06:57 PM PDT 24
Peak memory 207884 kb
Host smart-b8e5171d-c140-485d-8841-57ead5a1e00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978852123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3978852123
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.858101540
Short name T896
Test name
Test status
Simulation time 85518415 ps
CPU time 2.49 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 206864 kb
Host smart-3a851410-7558-4283-865e-952d4b044a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858101540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.858101540
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1254243607
Short name T643
Test name
Test status
Simulation time 583760628 ps
CPU time 12.33 seconds
Started Aug 11 06:06:49 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 222592 kb
Host smart-19a208f5-4bd3-42a9-9057-7962ab350e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254243607 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1254243607
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1219390040
Short name T783
Test name
Test status
Simulation time 3527990270 ps
CPU time 55.81 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:07:51 PM PDT 24
Peak memory 209176 kb
Host smart-2d3405d0-a762-4be4-8578-e594f0621b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219390040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1219390040
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.349808774
Short name T557
Test name
Test status
Simulation time 13829749 ps
CPU time 0.91 seconds
Started Aug 11 06:04:41 PM PDT 24
Finished Aug 11 06:04:42 PM PDT 24
Peak memory 206084 kb
Host smart-0001f24b-d94d-4f31-a123-4af404c858f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349808774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.349808774
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2438788750
Short name T413
Test name
Test status
Simulation time 237077754 ps
CPU time 3.41 seconds
Started Aug 11 06:04:36 PM PDT 24
Finished Aug 11 06:04:39 PM PDT 24
Peak memory 205864 kb
Host smart-bcc0ca20-f334-4460-9e4f-bb262f6de505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438788750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2438788750
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1076115942
Short name T73
Test name
Test status
Simulation time 52970542 ps
CPU time 1.69 seconds
Started Aug 11 06:04:35 PM PDT 24
Finished Aug 11 06:04:37 PM PDT 24
Peak memory 207824 kb
Host smart-a6967b47-5927-495d-a890-b17ec8ab7490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076115942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1076115942
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3521133890
Short name T104
Test name
Test status
Simulation time 1000576613 ps
CPU time 10.91 seconds
Started Aug 11 06:04:37 PM PDT 24
Finished Aug 11 06:04:48 PM PDT 24
Peak memory 214284 kb
Host smart-15676e51-6bb5-44d5-aa30-f8da3477e2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521133890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3521133890
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.99799200
Short name T599
Test name
Test status
Simulation time 188004156 ps
CPU time 2.57 seconds
Started Aug 11 06:04:43 PM PDT 24
Finished Aug 11 06:04:46 PM PDT 24
Peak memory 219784 kb
Host smart-91fc42d8-4284-4246-9518-e9371ea7dfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99799200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.99799200
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3183548490
Short name T564
Test name
Test status
Simulation time 781351965 ps
CPU time 8.95 seconds
Started Aug 11 06:04:37 PM PDT 24
Finished Aug 11 06:04:46 PM PDT 24
Peak memory 209532 kb
Host smart-0231377d-2427-4d38-9419-ebf9f4af0053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183548490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3183548490
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1556990675
Short name T112
Test name
Test status
Simulation time 1284543498 ps
CPU time 6.68 seconds
Started Aug 11 06:04:37 PM PDT 24
Finished Aug 11 06:04:43 PM PDT 24
Peak memory 229928 kb
Host smart-aedd8cc2-ffb9-4ebd-8bdf-b1ea53510451
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556990675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1556990675
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.770452440
Short name T477
Test name
Test status
Simulation time 501103581 ps
CPU time 5.85 seconds
Started Aug 11 06:04:38 PM PDT 24
Finished Aug 11 06:04:44 PM PDT 24
Peak memory 209016 kb
Host smart-26ef9295-d3f4-4a1f-b0f1-5478b6371944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770452440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.770452440
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.240887806
Short name T613
Test name
Test status
Simulation time 423785879 ps
CPU time 3.72 seconds
Started Aug 11 06:04:35 PM PDT 24
Finished Aug 11 06:04:39 PM PDT 24
Peak memory 208724 kb
Host smart-381aa3c2-8953-45c9-a0ae-a22fbf844b10
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240887806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.240887806
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3792790269
Short name T789
Test name
Test status
Simulation time 13045084164 ps
CPU time 27.49 seconds
Started Aug 11 06:04:36 PM PDT 24
Finished Aug 11 06:05:03 PM PDT 24
Peak memory 208412 kb
Host smart-91cc423a-082d-4e23-bdfb-47bfbbb08606
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792790269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3792790269
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2933268649
Short name T777
Test name
Test status
Simulation time 59409534 ps
CPU time 2.05 seconds
Started Aug 11 06:04:36 PM PDT 24
Finished Aug 11 06:04:38 PM PDT 24
Peak memory 208868 kb
Host smart-27d4bdfa-f37a-4871-baf2-3b5260cdf24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933268649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2933268649
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.820549619
Short name T446
Test name
Test status
Simulation time 111902883 ps
CPU time 2.46 seconds
Started Aug 11 06:04:38 PM PDT 24
Finished Aug 11 06:04:40 PM PDT 24
Peak memory 206828 kb
Host smart-c3913649-8991-42b0-8677-8d535462c041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820549619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.820549619
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.4122926986
Short name T190
Test name
Test status
Simulation time 5130602548 ps
CPU time 39.39 seconds
Started Aug 11 06:04:36 PM PDT 24
Finished Aug 11 06:05:15 PM PDT 24
Peak memory 216968 kb
Host smart-ab95d6e5-5783-40f3-8615-1f7c68ff31df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122926986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4122926986
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3205047390
Short name T47
Test name
Test status
Simulation time 298644284 ps
CPU time 11.3 seconds
Started Aug 11 06:04:37 PM PDT 24
Finished Aug 11 06:04:48 PM PDT 24
Peak memory 222544 kb
Host smart-f28cc360-2e0a-419c-8540-c7d8c599f7df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205047390 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3205047390
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.721980134
Short name T859
Test name
Test status
Simulation time 4018117590 ps
CPU time 9.35 seconds
Started Aug 11 06:04:36 PM PDT 24
Finished Aug 11 06:04:45 PM PDT 24
Peak memory 209744 kb
Host smart-a84a3272-9721-4d66-a14e-b06cc2808bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721980134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.721980134
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.928498871
Short name T167
Test name
Test status
Simulation time 173863592 ps
CPU time 2.49 seconds
Started Aug 11 06:04:41 PM PDT 24
Finished Aug 11 06:04:43 PM PDT 24
Peak memory 210848 kb
Host smart-2c78002c-ca48-4430-af59-9a50b879c30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928498871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.928498871
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1544580201
Short name T677
Test name
Test status
Simulation time 13481018 ps
CPU time 0.8 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:06:59 PM PDT 24
Peak memory 205908 kb
Host smart-d631ffb9-6bba-43ed-8774-00cb355a9183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544580201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1544580201
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2282967499
Short name T259
Test name
Test status
Simulation time 44352292 ps
CPU time 3.41 seconds
Started Aug 11 06:06:50 PM PDT 24
Finished Aug 11 06:06:53 PM PDT 24
Peak memory 215424 kb
Host smart-12da6134-b35c-4f32-aa6f-3ef7ef36a721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282967499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2282967499
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3120635934
Short name T17
Test name
Test status
Simulation time 58254239 ps
CPU time 2.22 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:00 PM PDT 24
Peak memory 216168 kb
Host smart-2928f54a-c9c5-42c8-9916-5c78588fd758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120635934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3120635934
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.4086144486
Short name T802
Test name
Test status
Simulation time 93955581 ps
CPU time 3.61 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:06:59 PM PDT 24
Peak memory 210200 kb
Host smart-95d119bc-156f-4830-beca-0c35ae6bac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086144486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.4086144486
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1144998168
Short name T382
Test name
Test status
Simulation time 315636656 ps
CPU time 3.18 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:07:03 PM PDT 24
Peak memory 214212 kb
Host smart-e841b914-9ea5-47b3-b7a6-28a02cb99cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144998168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1144998168
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2396157599
Short name T898
Test name
Test status
Simulation time 1231775172 ps
CPU time 17.01 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:07:12 PM PDT 24
Peak memory 209632 kb
Host smart-f313bc0f-bc85-4de8-8d61-3b8bcb5be031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396157599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2396157599
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3302025189
Short name T471
Test name
Test status
Simulation time 981491257 ps
CPU time 4.66 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:55 PM PDT 24
Peak memory 207316 kb
Host smart-22369ae4-8ce4-4f3c-949e-9a1a47d597fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302025189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3302025189
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3978127853
Short name T542
Test name
Test status
Simulation time 374388074 ps
CPU time 3.33 seconds
Started Aug 11 06:06:50 PM PDT 24
Finished Aug 11 06:06:53 PM PDT 24
Peak memory 206784 kb
Host smart-693a23b4-e780-4040-bc1d-a62d3aebab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978127853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3978127853
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1420172933
Short name T520
Test name
Test status
Simulation time 358893275 ps
CPU time 2.89 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 207020 kb
Host smart-6a3035ad-a998-473f-b7d3-8a74dcc842d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420172933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1420172933
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.4168287841
Short name T585
Test name
Test status
Simulation time 11655460568 ps
CPU time 16.85 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:07:08 PM PDT 24
Peak memory 208176 kb
Host smart-2174629d-05de-401c-b7e4-0fb9c88374e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168287841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4168287841
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.359624043
Short name T847
Test name
Test status
Simulation time 122255091 ps
CPU time 2.64 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:06:54 PM PDT 24
Peak memory 206724 kb
Host smart-e3a2187b-a2f4-43af-bbb4-c689afeccd04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359624043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.359624043
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2574668041
Short name T832
Test name
Test status
Simulation time 503557379 ps
CPU time 3.35 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 209144 kb
Host smart-57381718-00fb-4e68-9cd2-9309fc29dbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574668041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2574668041
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2782210631
Short name T430
Test name
Test status
Simulation time 1104844579 ps
CPU time 17.95 seconds
Started Aug 11 06:06:51 PM PDT 24
Finished Aug 11 06:07:09 PM PDT 24
Peak memory 208024 kb
Host smart-ca1c52da-9a64-4f55-92e0-68496ac173cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782210631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2782210631
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2264035752
Short name T544
Test name
Test status
Simulation time 4775083788 ps
CPU time 21.47 seconds
Started Aug 11 06:07:00 PM PDT 24
Finished Aug 11 06:07:21 PM PDT 24
Peak memory 222572 kb
Host smart-0b98a905-4a8d-4e54-9e46-ca51bddd5da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264035752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2264035752
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2944562799
Short name T137
Test name
Test status
Simulation time 248368081 ps
CPU time 17.24 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:15 PM PDT 24
Peak memory 222544 kb
Host smart-7b9d04cb-4e43-4cde-947d-3f1ca674978a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944562799 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2944562799
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1267163590
Short name T258
Test name
Test status
Simulation time 251338857 ps
CPU time 4.05 seconds
Started Aug 11 06:06:52 PM PDT 24
Finished Aug 11 06:06:56 PM PDT 24
Peak memory 209560 kb
Host smart-940a866a-125a-4aae-91b1-eda58aaf04c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267163590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1267163590
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2409532483
Short name T817
Test name
Test status
Simulation time 317074990 ps
CPU time 4.97 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:03 PM PDT 24
Peak memory 210956 kb
Host smart-b78009bb-dd0c-4b84-88e2-eac4509ecf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409532483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2409532483
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1933484147
Short name T473
Test name
Test status
Simulation time 16603857 ps
CPU time 0.96 seconds
Started Aug 11 06:07:00 PM PDT 24
Finished Aug 11 06:07:01 PM PDT 24
Peak memory 206148 kb
Host smart-46514b5c-8345-4d95-83c8-97fc120ebd48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933484147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1933484147
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.170131331
Short name T664
Test name
Test status
Simulation time 144081796 ps
CPU time 2.83 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:01 PM PDT 24
Peak memory 210648 kb
Host smart-42a99797-cea4-4fcc-a8f6-923520fc971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170131331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.170131331
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2061641710
Short name T580
Test name
Test status
Simulation time 1007769559 ps
CPU time 34.59 seconds
Started Aug 11 06:07:00 PM PDT 24
Finished Aug 11 06:07:34 PM PDT 24
Peak memory 218456 kb
Host smart-ab76b273-0213-4a61-ad68-0e6dfee5e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061641710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2061641710
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1182517917
Short name T91
Test name
Test status
Simulation time 164431728 ps
CPU time 3.05 seconds
Started Aug 11 06:07:00 PM PDT 24
Finished Aug 11 06:07:04 PM PDT 24
Peak memory 214360 kb
Host smart-fb105543-8526-4341-ab3c-7d75a4cf7283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182517917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1182517917
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3560719076
Short name T271
Test name
Test status
Simulation time 53987397 ps
CPU time 2.24 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:07:01 PM PDT 24
Peak memory 214396 kb
Host smart-a4f90738-f0ae-4365-b909-07f13e68cfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560719076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3560719076
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1200318313
Short name T62
Test name
Test status
Simulation time 240658877 ps
CPU time 5.98 seconds
Started Aug 11 06:07:01 PM PDT 24
Finished Aug 11 06:07:07 PM PDT 24
Peak memory 222376 kb
Host smart-8a440d0c-6287-44c7-8516-a2a9ca4d5b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200318313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1200318313
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2279171754
Short name T561
Test name
Test status
Simulation time 86424638 ps
CPU time 4.03 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:06:59 PM PDT 24
Peak memory 218160 kb
Host smart-29eea3a7-9c07-4839-8f1d-673a85930dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279171754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2279171754
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2169815513
Short name T735
Test name
Test status
Simulation time 817719121 ps
CPU time 5.38 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:03 PM PDT 24
Peak memory 207412 kb
Host smart-8a27a789-fad0-40a6-af1a-86829eecfccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169815513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2169815513
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.485516490
Short name T737
Test name
Test status
Simulation time 1070459266 ps
CPU time 3.19 seconds
Started Aug 11 06:06:57 PM PDT 24
Finished Aug 11 06:07:00 PM PDT 24
Peak memory 206932 kb
Host smart-384254af-57c0-4b96-b355-ffccd4545be9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485516490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.485516490
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.722145839
Short name T143
Test name
Test status
Simulation time 48082845 ps
CPU time 2.03 seconds
Started Aug 11 06:07:00 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 208940 kb
Host smart-8105f8fa-1b95-429d-a071-6306f8ea7141
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722145839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.722145839
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.671492851
Short name T689
Test name
Test status
Simulation time 446261248 ps
CPU time 4.89 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:03 PM PDT 24
Peak memory 208048 kb
Host smart-373a33ae-b322-4e2e-a6b9-b78f1b8e7f70
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671492851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.671492851
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4110145884
Short name T566
Test name
Test status
Simulation time 2122373466 ps
CPU time 4.98 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:03 PM PDT 24
Peak memory 208776 kb
Host smart-09f6ef79-76d6-4c68-9d5e-45a3772aae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110145884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4110145884
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1008458321
Short name T550
Test name
Test status
Simulation time 582930891 ps
CPU time 2.84 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:01 PM PDT 24
Peak memory 206836 kb
Host smart-fbb4da6a-16a7-4bfd-a443-67da3f3db0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008458321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1008458321
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1163986495
Short name T202
Test name
Test status
Simulation time 889285761 ps
CPU time 9.69 seconds
Started Aug 11 06:07:01 PM PDT 24
Finished Aug 11 06:07:10 PM PDT 24
Peak memory 222440 kb
Host smart-1116d26c-387a-442b-942f-dcffea37dc3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163986495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1163986495
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.196269203
Short name T651
Test name
Test status
Simulation time 1993181762 ps
CPU time 17.95 seconds
Started Aug 11 06:07:01 PM PDT 24
Finished Aug 11 06:07:19 PM PDT 24
Peak memory 222536 kb
Host smart-be7855ea-db03-4b26-b307-7b7cd72a0b7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196269203 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.196269203
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1045680932
Short name T828
Test name
Test status
Simulation time 109055680 ps
CPU time 4.77 seconds
Started Aug 11 06:07:00 PM PDT 24
Finished Aug 11 06:07:05 PM PDT 24
Peak memory 207380 kb
Host smart-6036efed-64aa-4900-911f-ded823595701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045680932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1045680932
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2800767344
Short name T794
Test name
Test status
Simulation time 1313622889 ps
CPU time 4.13 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:06:59 PM PDT 24
Peak memory 210388 kb
Host smart-5038449c-3a98-4d5a-8ddb-a99887d82a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800767344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2800767344
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3206195423
Short name T827
Test name
Test status
Simulation time 13807746 ps
CPU time 0.73 seconds
Started Aug 11 06:07:06 PM PDT 24
Finished Aug 11 06:07:07 PM PDT 24
Peak memory 205924 kb
Host smart-68c75861-21e5-42cc-9928-cd374f0e07c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206195423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3206195423
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.545694241
Short name T776
Test name
Test status
Simulation time 144060445 ps
CPU time 2.22 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 214176 kb
Host smart-922478e4-df66-47ca-b72e-72ac00371a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545694241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.545694241
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.4107497705
Short name T465
Test name
Test status
Simulation time 30382984 ps
CPU time 2.12 seconds
Started Aug 11 06:07:00 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 207236 kb
Host smart-cb12877f-7773-44d8-a45e-2fbdb2539e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107497705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4107497705
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2450977591
Short name T44
Test name
Test status
Simulation time 131199395 ps
CPU time 2.4 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:01 PM PDT 24
Peak memory 214536 kb
Host smart-a7eaa518-c146-491c-a7ef-97e14566281c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450977591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2450977591
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1406792609
Short name T648
Test name
Test status
Simulation time 87652856 ps
CPU time 3 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:01 PM PDT 24
Peak memory 214204 kb
Host smart-19a00cc8-c897-48f6-8b86-778027225d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406792609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1406792609
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.879102634
Short name T145
Test name
Test status
Simulation time 97897902 ps
CPU time 4.36 seconds
Started Aug 11 06:07:00 PM PDT 24
Finished Aug 11 06:07:04 PM PDT 24
Peak memory 214260 kb
Host smart-e13dd61e-d72a-4c05-b6e5-abe77da8c63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879102634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.879102634
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3028747804
Short name T717
Test name
Test status
Simulation time 57696658 ps
CPU time 3.16 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 207668 kb
Host smart-c8c03855-7e02-4b3c-9524-dda5112c79c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028747804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3028747804
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3381608884
Short name T208
Test name
Test status
Simulation time 77968161 ps
CPU time 3.6 seconds
Started Aug 11 06:06:56 PM PDT 24
Finished Aug 11 06:07:00 PM PDT 24
Peak memory 208724 kb
Host smart-b83897a8-25db-484f-8b55-a7c6f7a7fa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381608884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3381608884
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2104880899
Short name T203
Test name
Test status
Simulation time 577059876 ps
CPU time 16.28 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:07:16 PM PDT 24
Peak memory 209368 kb
Host smart-e8d03f6c-1673-4d3e-a021-77189279a43e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104880899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2104880899
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1594085153
Short name T767
Test name
Test status
Simulation time 987211020 ps
CPU time 8.27 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:07:07 PM PDT 24
Peak memory 208384 kb
Host smart-f31c61ad-48d2-4477-879d-c3dcff765d35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594085153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1594085153
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1489482813
Short name T631
Test name
Test status
Simulation time 45224330 ps
CPU time 2.17 seconds
Started Aug 11 06:07:00 PM PDT 24
Finished Aug 11 06:07:02 PM PDT 24
Peak memory 208760 kb
Host smart-05d99860-1ed5-499c-86ca-9c24f21e3269
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489482813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1489482813
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4122288265
Short name T245
Test name
Test status
Simulation time 98959355 ps
CPU time 2.45 seconds
Started Aug 11 06:06:55 PM PDT 24
Finished Aug 11 06:06:58 PM PDT 24
Peak memory 208932 kb
Host smart-9f4bc922-a40e-46c6-a730-678bfe1c4f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122288265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4122288265
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3540461200
Short name T451
Test name
Test status
Simulation time 1046095462 ps
CPU time 7.12 seconds
Started Aug 11 06:06:59 PM PDT 24
Finished Aug 11 06:07:06 PM PDT 24
Peak memory 206704 kb
Host smart-fe4c4876-07f7-4ae5-9971-5929554d390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540461200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3540461200
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.87024778
Short name T315
Test name
Test status
Simulation time 8623851922 ps
CPU time 29.69 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:37 PM PDT 24
Peak memory 222556 kb
Host smart-ad494e48-91cc-4d42-90ac-14a6303129c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87024778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.87024778
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1929440655
Short name T611
Test name
Test status
Simulation time 8288185697 ps
CPU time 50.66 seconds
Started Aug 11 06:06:58 PM PDT 24
Finished Aug 11 06:07:49 PM PDT 24
Peak memory 218184 kb
Host smart-ab6211fc-ae4a-412c-885b-b9fa55b8c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929440655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1929440655
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1180552707
Short name T38
Test name
Test status
Simulation time 237479726 ps
CPU time 3.07 seconds
Started Aug 11 06:07:09 PM PDT 24
Finished Aug 11 06:07:12 PM PDT 24
Peak memory 210212 kb
Host smart-8e5e5b25-4a9d-42ca-a4a0-aa1f5988bff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180552707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1180552707
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.796145917
Short name T905
Test name
Test status
Simulation time 71520014 ps
CPU time 0.73 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:08 PM PDT 24
Peak memory 205928 kb
Host smart-60a5c4e7-9545-44e4-a8e7-9e7c77a0e359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796145917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.796145917
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1473006213
Short name T407
Test name
Test status
Simulation time 44242920 ps
CPU time 3.12 seconds
Started Aug 11 06:07:09 PM PDT 24
Finished Aug 11 06:07:13 PM PDT 24
Peak memory 215136 kb
Host smart-f472c8de-982d-45c3-b925-58dd382dc966
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473006213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1473006213
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1635019552
Short name T751
Test name
Test status
Simulation time 54170334 ps
CPU time 1.86 seconds
Started Aug 11 06:07:05 PM PDT 24
Finished Aug 11 06:07:07 PM PDT 24
Peak memory 214236 kb
Host smart-53591a1f-77ef-4b1a-9005-af412dd19ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635019552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1635019552
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.227566793
Short name T913
Test name
Test status
Simulation time 392469971 ps
CPU time 6.19 seconds
Started Aug 11 06:07:06 PM PDT 24
Finished Aug 11 06:07:12 PM PDT 24
Peak memory 208212 kb
Host smart-b0bf6df5-2374-419a-b308-621c235c5901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227566793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.227566793
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.857003885
Short name T109
Test name
Test status
Simulation time 89106328 ps
CPU time 2.8 seconds
Started Aug 11 06:07:09 PM PDT 24
Finished Aug 11 06:07:12 PM PDT 24
Peak memory 214288 kb
Host smart-f1474440-0da9-47cf-a30c-ce9588098a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857003885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.857003885
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1266924567
Short name T234
Test name
Test status
Simulation time 1050942694 ps
CPU time 3.62 seconds
Started Aug 11 06:07:09 PM PDT 24
Finished Aug 11 06:07:13 PM PDT 24
Peak memory 209884 kb
Host smart-94eb618c-cfd3-4971-98a3-5ce479496c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266924567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1266924567
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3848322996
Short name T782
Test name
Test status
Simulation time 251107732 ps
CPU time 8.38 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:15 PM PDT 24
Peak memory 208204 kb
Host smart-34ef28a3-2ab2-477a-a80c-8308961b7d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848322996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3848322996
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2597471809
Short name T744
Test name
Test status
Simulation time 291379328 ps
CPU time 4.61 seconds
Started Aug 11 06:07:05 PM PDT 24
Finished Aug 11 06:07:10 PM PDT 24
Peak memory 208000 kb
Host smart-9494e947-2545-43ec-bf1b-74d645beddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597471809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2597471809
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1255886583
Short name T834
Test name
Test status
Simulation time 169091523 ps
CPU time 2.98 seconds
Started Aug 11 06:07:06 PM PDT 24
Finished Aug 11 06:07:09 PM PDT 24
Peak memory 206956 kb
Host smart-74ef00bd-3091-4054-a85e-a2bffbd550ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255886583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1255886583
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3749555094
Short name T4
Test name
Test status
Simulation time 6822224639 ps
CPU time 44.64 seconds
Started Aug 11 06:07:09 PM PDT 24
Finished Aug 11 06:07:54 PM PDT 24
Peak memory 208700 kb
Host smart-38ecbf2d-4a9a-4011-b5b1-3cf02d883ab4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749555094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3749555094
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2246329671
Short name T792
Test name
Test status
Simulation time 174192677 ps
CPU time 4.11 seconds
Started Aug 11 06:07:08 PM PDT 24
Finished Aug 11 06:07:12 PM PDT 24
Peak memory 208692 kb
Host smart-c16a61be-da9a-48c6-bbdc-6e3ca8a73659
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246329671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2246329671
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.4025106916
Short name T282
Test name
Test status
Simulation time 49043872 ps
CPU time 2.44 seconds
Started Aug 11 06:07:08 PM PDT 24
Finished Aug 11 06:07:11 PM PDT 24
Peak memory 209080 kb
Host smart-9ab01133-f59f-4560-9f9b-3577cdb6edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025106916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.4025106916
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.574950697
Short name T597
Test name
Test status
Simulation time 22999195 ps
CPU time 1.85 seconds
Started Aug 11 06:07:06 PM PDT 24
Finished Aug 11 06:07:08 PM PDT 24
Peak memory 208504 kb
Host smart-1a3ffd14-974a-424e-888d-18db5e6b9d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574950697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.574950697
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1281131617
Short name T633
Test name
Test status
Simulation time 1919958503 ps
CPU time 49.5 seconds
Started Aug 11 06:07:12 PM PDT 24
Finished Aug 11 06:08:02 PM PDT 24
Peak memory 209572 kb
Host smart-329b507b-16bd-411f-8abb-8bdaa35f2c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281131617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1281131617
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1109658163
Short name T201
Test name
Test status
Simulation time 37090841 ps
CPU time 3.24 seconds
Started Aug 11 06:07:03 PM PDT 24
Finished Aug 11 06:07:06 PM PDT 24
Peak memory 208012 kb
Host smart-36ed9eb9-d80b-441e-8f61-5f599ece76ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109658163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1109658163
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1909400459
Short name T55
Test name
Test status
Simulation time 45604675 ps
CPU time 2.18 seconds
Started Aug 11 06:07:06 PM PDT 24
Finished Aug 11 06:07:09 PM PDT 24
Peak memory 209752 kb
Host smart-378bc057-d1b1-4405-a1ec-baf90fc57655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909400459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1909400459
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.765497466
Short name T805
Test name
Test status
Simulation time 41865135 ps
CPU time 0.72 seconds
Started Aug 11 06:07:10 PM PDT 24
Finished Aug 11 06:07:11 PM PDT 24
Peak memory 205964 kb
Host smart-34b96b83-94ef-4404-bbd1-c53b1c71da82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765497466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.765497466
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.442201141
Short name T581
Test name
Test status
Simulation time 138813054 ps
CPU time 2.19 seconds
Started Aug 11 06:07:05 PM PDT 24
Finished Aug 11 06:07:08 PM PDT 24
Peak memory 209372 kb
Host smart-21d43873-d7e7-45bb-a331-ec3fc70c3cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442201141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.442201141
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3170461869
Short name T642
Test name
Test status
Simulation time 41341512 ps
CPU time 2.09 seconds
Started Aug 11 06:07:09 PM PDT 24
Finished Aug 11 06:07:11 PM PDT 24
Peak memory 214344 kb
Host smart-f664054d-3a3a-455a-bb72-17aff0c43fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170461869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3170461869
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4046386747
Short name T705
Test name
Test status
Simulation time 175808261 ps
CPU time 4.52 seconds
Started Aug 11 06:07:04 PM PDT 24
Finished Aug 11 06:07:09 PM PDT 24
Peak memory 222300 kb
Host smart-136ed19c-11cf-4d18-a53a-d2293a42d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046386747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4046386747
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2796042498
Short name T219
Test name
Test status
Simulation time 244664406 ps
CPU time 2.37 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:09 PM PDT 24
Peak memory 214328 kb
Host smart-d9a2f4e1-29cd-48bf-89cb-735ca53ecea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796042498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2796042498
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2705943876
Short name T354
Test name
Test status
Simulation time 111626353 ps
CPU time 3.94 seconds
Started Aug 11 06:07:08 PM PDT 24
Finished Aug 11 06:07:12 PM PDT 24
Peak memory 209128 kb
Host smart-91518dfe-0ea6-4de4-a11e-49c676e9fd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705943876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2705943876
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3040318533
Short name T615
Test name
Test status
Simulation time 225490901 ps
CPU time 5.53 seconds
Started Aug 11 06:07:04 PM PDT 24
Finished Aug 11 06:07:10 PM PDT 24
Peak memory 207872 kb
Host smart-4163b3d2-1a90-4153-b0ec-2b2e289e54af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040318533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3040318533
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2501366240
Short name T460
Test name
Test status
Simulation time 376976475 ps
CPU time 3.69 seconds
Started Aug 11 06:07:09 PM PDT 24
Finished Aug 11 06:07:13 PM PDT 24
Peak memory 207492 kb
Host smart-3da46a76-58e6-474c-9a5c-e8b6db69b2d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501366240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2501366240
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1977834503
Short name T574
Test name
Test status
Simulation time 920107997 ps
CPU time 13.85 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:21 PM PDT 24
Peak memory 208572 kb
Host smart-c5008a37-98c7-4db3-8787-5c62b73c8320
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977834503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1977834503
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3563304158
Short name T816
Test name
Test status
Simulation time 267272076 ps
CPU time 2.96 seconds
Started Aug 11 06:07:10 PM PDT 24
Finished Aug 11 06:07:13 PM PDT 24
Peak memory 207020 kb
Host smart-060d11bf-3190-41b1-bbc6-4b743de898fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563304158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3563304158
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.657725250
Short name T684
Test name
Test status
Simulation time 1809354827 ps
CPU time 11.07 seconds
Started Aug 11 06:07:10 PM PDT 24
Finished Aug 11 06:07:21 PM PDT 24
Peak memory 214352 kb
Host smart-36af830b-35ad-492d-8e7b-85c8c6b5cdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657725250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.657725250
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2770164923
Short name T439
Test name
Test status
Simulation time 121787426 ps
CPU time 3.38 seconds
Started Aug 11 06:07:04 PM PDT 24
Finished Aug 11 06:07:08 PM PDT 24
Peak memory 208588 kb
Host smart-0a2c62e1-d3a1-4a06-9d33-b3abc3555253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770164923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2770164923
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1607260517
Short name T349
Test name
Test status
Simulation time 1449805240 ps
CPU time 10.03 seconds
Started Aug 11 06:07:12 PM PDT 24
Finished Aug 11 06:07:22 PM PDT 24
Peak memory 222576 kb
Host smart-b09e5be3-229c-4295-a2a2-6bdc25292789
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607260517 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1607260517
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.605719641
Short name T196
Test name
Test status
Simulation time 418065807 ps
CPU time 4.18 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:11 PM PDT 24
Peak memory 207660 kb
Host smart-6b71c204-4944-43ad-934f-b7c1c1309e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605719641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.605719641
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2594288328
Short name T839
Test name
Test status
Simulation time 57846684 ps
CPU time 1.58 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:09 PM PDT 24
Peak memory 209900 kb
Host smart-1fb19996-e7bc-4ed2-8e57-9f09b2c8b1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594288328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2594288328
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.4024353430
Short name T587
Test name
Test status
Simulation time 11401389 ps
CPU time 0.78 seconds
Started Aug 11 06:07:13 PM PDT 24
Finished Aug 11 06:07:14 PM PDT 24
Peak memory 205984 kb
Host smart-f17d6974-ffb5-4b17-a1d8-cfe967da96d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024353430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4024353430
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1622886171
Short name T296
Test name
Test status
Simulation time 326148445 ps
CPU time 5.06 seconds
Started Aug 11 06:07:08 PM PDT 24
Finished Aug 11 06:07:14 PM PDT 24
Peak memory 214932 kb
Host smart-ca94227e-7a29-4ef5-ac91-1a2d65c39873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622886171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1622886171
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3375698162
Short name T18
Test name
Test status
Simulation time 42894683 ps
CPU time 1.84 seconds
Started Aug 11 06:07:11 PM PDT 24
Finished Aug 11 06:07:13 PM PDT 24
Peak memory 215256 kb
Host smart-3f177741-7ad5-4e6c-86e4-54c131175461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375698162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3375698162
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3938115978
Short name T668
Test name
Test status
Simulation time 105601005 ps
CPU time 4.43 seconds
Started Aug 11 06:07:10 PM PDT 24
Finished Aug 11 06:07:14 PM PDT 24
Peak memory 209292 kb
Host smart-0b7221e1-39fe-4613-ac8c-71e9418355fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938115978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3938115978
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.737486420
Short name T894
Test name
Test status
Simulation time 73254462 ps
CPU time 1.6 seconds
Started Aug 11 06:07:15 PM PDT 24
Finished Aug 11 06:07:16 PM PDT 24
Peak memory 214236 kb
Host smart-b8adc8ca-fdb8-45a3-ace3-eb4bd6063406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737486420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.737486420
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1209687687
Short name T850
Test name
Test status
Simulation time 1290039516 ps
CPU time 12.48 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:20 PM PDT 24
Peak memory 209188 kb
Host smart-d88d789f-1bb5-44fe-a44c-0a0882b09ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209687687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1209687687
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2677915170
Short name T417
Test name
Test status
Simulation time 83556141 ps
CPU time 4.35 seconds
Started Aug 11 06:07:06 PM PDT 24
Finished Aug 11 06:07:10 PM PDT 24
Peak memory 207644 kb
Host smart-dc1adafd-6604-4828-be09-4d916e74483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677915170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2677915170
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2196163904
Short name T525
Test name
Test status
Simulation time 223612045 ps
CPU time 3.29 seconds
Started Aug 11 06:07:03 PM PDT 24
Finished Aug 11 06:07:07 PM PDT 24
Peak memory 206812 kb
Host smart-c80f6f74-dbc3-4ee7-8501-419b8c51a5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196163904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2196163904
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.206896563
Short name T907
Test name
Test status
Simulation time 496635170 ps
CPU time 3.71 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:11 PM PDT 24
Peak memory 208624 kb
Host smart-55b6b51c-438d-452c-96e7-6b5e2dd27fb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206896563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.206896563
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3837240781
Short name T278
Test name
Test status
Simulation time 214645893 ps
CPU time 2.56 seconds
Started Aug 11 06:07:06 PM PDT 24
Finished Aug 11 06:07:08 PM PDT 24
Peak memory 208632 kb
Host smart-b201e7d2-53bc-4e49-b585-825a76d81ea7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837240781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3837240781
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1583036941
Short name T435
Test name
Test status
Simulation time 233852449 ps
CPU time 5.99 seconds
Started Aug 11 06:07:07 PM PDT 24
Finished Aug 11 06:07:13 PM PDT 24
Peak memory 208788 kb
Host smart-b2222e2c-9049-43d0-a6e7-4e9276152953
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583036941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1583036941
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2810760203
Short name T79
Test name
Test status
Simulation time 218962849 ps
CPU time 2.62 seconds
Started Aug 11 06:07:15 PM PDT 24
Finished Aug 11 06:07:18 PM PDT 24
Peak memory 222388 kb
Host smart-5e5a781f-520e-4f75-a7b5-f98777dc867a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810760203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2810760203
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3549875683
Short name T491
Test name
Test status
Simulation time 1544137949 ps
CPU time 2.82 seconds
Started Aug 11 06:07:05 PM PDT 24
Finished Aug 11 06:07:07 PM PDT 24
Peak memory 206840 kb
Host smart-bba2a5a7-893b-4466-a9da-827d26d44fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549875683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3549875683
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2497327128
Short name T852
Test name
Test status
Simulation time 133655306 ps
CPU time 4.95 seconds
Started Aug 11 06:07:05 PM PDT 24
Finished Aug 11 06:07:10 PM PDT 24
Peak memory 207752 kb
Host smart-9c2815ab-ea0a-4ee4-942f-dc762fcb300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497327128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2497327128
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1162015909
Short name T33
Test name
Test status
Simulation time 61804643 ps
CPU time 2.59 seconds
Started Aug 11 06:07:11 PM PDT 24
Finished Aug 11 06:07:14 PM PDT 24
Peak memory 210128 kb
Host smart-31d13039-5ff5-4e07-93fc-8f63cb0ca326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162015909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1162015909
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.962062655
Short name T450
Test name
Test status
Simulation time 43938926 ps
CPU time 0.93 seconds
Started Aug 11 06:07:20 PM PDT 24
Finished Aug 11 06:07:21 PM PDT 24
Peak memory 205856 kb
Host smart-891db598-fc6c-414c-9ebd-0903156271b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962062655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.962062655
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1070809515
Short name T812
Test name
Test status
Simulation time 104044446 ps
CPU time 3.22 seconds
Started Aug 11 06:07:15 PM PDT 24
Finished Aug 11 06:07:18 PM PDT 24
Peak memory 214744 kb
Host smart-8f7af2b2-f521-4780-b8a2-48f62d69c4ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070809515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1070809515
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1170425279
Short name T16
Test name
Test status
Simulation time 78455017 ps
CPU time 2.72 seconds
Started Aug 11 06:07:15 PM PDT 24
Finished Aug 11 06:07:18 PM PDT 24
Peak memory 207460 kb
Host smart-744d4977-4ca1-4c0d-bcd4-331f8c3fe902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170425279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1170425279
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.200428556
Short name T24
Test name
Test status
Simulation time 464704664 ps
CPU time 6.65 seconds
Started Aug 11 06:07:15 PM PDT 24
Finished Aug 11 06:07:21 PM PDT 24
Peak memory 209200 kb
Host smart-48b036fe-b14d-40e0-8da4-27533642bbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200428556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.200428556
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1226365156
Short name T883
Test name
Test status
Simulation time 510864848 ps
CPU time 2.04 seconds
Started Aug 11 06:07:16 PM PDT 24
Finished Aug 11 06:07:18 PM PDT 24
Peak memory 214452 kb
Host smart-416e2e26-96b4-4db6-a730-0b56dde8e79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226365156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1226365156
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2635162738
Short name T250
Test name
Test status
Simulation time 653213283 ps
CPU time 6.28 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:07:20 PM PDT 24
Peak memory 214244 kb
Host smart-67c39b82-e143-423f-869d-9a9213b17701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635162738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2635162738
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1430779050
Short name T366
Test name
Test status
Simulation time 2351583728 ps
CPU time 50.76 seconds
Started Aug 11 06:07:18 PM PDT 24
Finished Aug 11 06:08:09 PM PDT 24
Peak memory 214364 kb
Host smart-b0b013c5-7541-4299-9c12-acd4bba65522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430779050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1430779050
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3831053838
Short name T514
Test name
Test status
Simulation time 375502937 ps
CPU time 3.5 seconds
Started Aug 11 06:07:13 PM PDT 24
Finished Aug 11 06:07:17 PM PDT 24
Peak memory 209196 kb
Host smart-152fe3b4-f4e2-447c-a36f-8f4c788a6b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831053838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3831053838
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1804868831
Short name T632
Test name
Test status
Simulation time 155899552 ps
CPU time 2.91 seconds
Started Aug 11 06:07:16 PM PDT 24
Finished Aug 11 06:07:19 PM PDT 24
Peak memory 206936 kb
Host smart-c904ed2e-bd56-4ee2-9f72-369ab296d9d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804868831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1804868831
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1733873282
Short name T703
Test name
Test status
Simulation time 203072670 ps
CPU time 6.05 seconds
Started Aug 11 06:07:13 PM PDT 24
Finished Aug 11 06:07:19 PM PDT 24
Peak memory 207900 kb
Host smart-184b3b4f-88a5-4126-8ac3-205061018b86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733873282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1733873282
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.4070724483
Short name T509
Test name
Test status
Simulation time 1740570755 ps
CPU time 36.69 seconds
Started Aug 11 06:07:20 PM PDT 24
Finished Aug 11 06:07:56 PM PDT 24
Peak memory 208724 kb
Host smart-5ecaef08-d55f-4c8d-842f-bf84a4679df4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070724483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.4070724483
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1850104370
Short name T353
Test name
Test status
Simulation time 144019605 ps
CPU time 4.07 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:07:18 PM PDT 24
Peak memory 209404 kb
Host smart-9b7b96a0-14ad-4ee7-8d41-9a70726e0667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850104370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1850104370
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2951922162
Short name T618
Test name
Test status
Simulation time 2366975773 ps
CPU time 5.22 seconds
Started Aug 11 06:07:15 PM PDT 24
Finished Aug 11 06:07:20 PM PDT 24
Peak memory 208592 kb
Host smart-b03b6f7a-9c38-4f33-a3c2-fc1c4c53a467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951922162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2951922162
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2300939772
Short name T209
Test name
Test status
Simulation time 68241173 ps
CPU time 3.63 seconds
Started Aug 11 06:07:15 PM PDT 24
Finished Aug 11 06:07:19 PM PDT 24
Peak memory 215288 kb
Host smart-0324d8de-2aac-4605-b71c-4e5a15c330c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300939772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2300939772
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.4150680611
Short name T674
Test name
Test status
Simulation time 2045660682 ps
CPU time 14.68 seconds
Started Aug 11 06:07:13 PM PDT 24
Finished Aug 11 06:07:28 PM PDT 24
Peak memory 222536 kb
Host smart-f088e4cb-ba74-457e-8656-c3f8b1bd8748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150680611 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.4150680611
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3500334939
Short name T267
Test name
Test status
Simulation time 340010808 ps
CPU time 4.47 seconds
Started Aug 11 06:07:11 PM PDT 24
Finished Aug 11 06:07:16 PM PDT 24
Peak memory 207428 kb
Host smart-995847f1-bcad-4b6b-9aa7-00c964d17b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500334939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3500334939
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2676458864
Short name T433
Test name
Test status
Simulation time 13290987 ps
CPU time 0.91 seconds
Started Aug 11 06:07:20 PM PDT 24
Finished Aug 11 06:07:21 PM PDT 24
Peak memory 206096 kb
Host smart-b3d2f4f0-0572-40bc-ad37-aec0a1f81416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676458864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2676458864
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2072666568
Short name T294
Test name
Test status
Simulation time 2259075102 ps
CPU time 31.21 seconds
Started Aug 11 06:07:15 PM PDT 24
Finished Aug 11 06:07:46 PM PDT 24
Peak memory 222568 kb
Host smart-60c3d5b0-256c-4974-bbed-cfd088533818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072666568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2072666568
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.4125894189
Short name T813
Test name
Test status
Simulation time 710165417 ps
CPU time 22.03 seconds
Started Aug 11 06:07:13 PM PDT 24
Finished Aug 11 06:07:36 PM PDT 24
Peak memory 214396 kb
Host smart-b687a02f-b7a8-493e-985e-8b92c6389e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125894189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4125894189
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3086561424
Short name T742
Test name
Test status
Simulation time 123482958 ps
CPU time 2.76 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:07:17 PM PDT 24
Peak memory 209404 kb
Host smart-d535e9e0-2582-4fa9-9228-fa588ee7b7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086561424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3086561424
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1264893038
Short name T99
Test name
Test status
Simulation time 309034916 ps
CPU time 3.87 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:07:19 PM PDT 24
Peak memory 222396 kb
Host smart-ec0e4117-6076-4659-877c-32572c6db788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264893038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1264893038
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4052481772
Short name T120
Test name
Test status
Simulation time 182040568 ps
CPU time 4.69 seconds
Started Aug 11 06:07:13 PM PDT 24
Finished Aug 11 06:07:18 PM PDT 24
Peak memory 220976 kb
Host smart-c4825d72-cfa1-49ff-997b-c70e8ddc2b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052481772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4052481772
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2430896185
Short name T65
Test name
Test status
Simulation time 130214797 ps
CPU time 4.61 seconds
Started Aug 11 06:07:15 PM PDT 24
Finished Aug 11 06:07:20 PM PDT 24
Peak memory 220060 kb
Host smart-6fcb4fcf-dca4-4f50-a2ed-deffafc6dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430896185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2430896185
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.732525838
Short name T474
Test name
Test status
Simulation time 1295644976 ps
CPU time 21.38 seconds
Started Aug 11 06:07:18 PM PDT 24
Finished Aug 11 06:07:40 PM PDT 24
Peak memory 208640 kb
Host smart-a179312a-6086-4cc8-bc79-6850a1977b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732525838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.732525838
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.4132722459
Short name T560
Test name
Test status
Simulation time 174885775 ps
CPU time 2.85 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:07:17 PM PDT 24
Peak memory 207604 kb
Host smart-24a12894-5dcd-406f-ba65-b1beac3bdb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132722459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.4132722459
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.875234725
Short name T697
Test name
Test status
Simulation time 3134243226 ps
CPU time 23.05 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:07:37 PM PDT 24
Peak memory 209020 kb
Host smart-e85ea416-e199-4140-8c8d-c96be04aba4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875234725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.875234725
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2920987597
Short name T837
Test name
Test status
Simulation time 72505079 ps
CPU time 1.8 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:07:16 PM PDT 24
Peak memory 206864 kb
Host smart-ab387584-030d-42b5-8c54-79ad597302b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920987597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2920987597
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1423384705
Short name T862
Test name
Test status
Simulation time 160329053 ps
CPU time 2.5 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:07:17 PM PDT 24
Peak memory 206956 kb
Host smart-316b304b-ef89-40ae-a799-86e097263cf7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423384705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1423384705
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1784792410
Short name T396
Test name
Test status
Simulation time 122339840 ps
CPU time 2.38 seconds
Started Aug 11 06:07:11 PM PDT 24
Finished Aug 11 06:07:14 PM PDT 24
Peak memory 208200 kb
Host smart-d6fda299-12d7-4869-895f-91068a60c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784792410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1784792410
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1314244726
Short name T200
Test name
Test status
Simulation time 46996464 ps
CPU time 2.39 seconds
Started Aug 11 06:07:13 PM PDT 24
Finished Aug 11 06:07:16 PM PDT 24
Peak memory 206928 kb
Host smart-e9be3805-02c9-4d79-8216-0edb102aee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314244726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1314244726
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2060531687
Short name T397
Test name
Test status
Simulation time 375561317 ps
CPU time 4.57 seconds
Started Aug 11 06:07:22 PM PDT 24
Finished Aug 11 06:07:27 PM PDT 24
Peak memory 219336 kb
Host smart-9380ecb8-4649-4d8b-83e3-4f9466da0586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060531687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2060531687
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2538652290
Short name T863
Test name
Test status
Simulation time 654981584 ps
CPU time 11.2 seconds
Started Aug 11 06:07:20 PM PDT 24
Finished Aug 11 06:07:31 PM PDT 24
Peak memory 222584 kb
Host smart-2c6b23fc-3e45-4717-9de1-94cf272a7ba0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538652290 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2538652290
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3736584431
Short name T753
Test name
Test status
Simulation time 253630157 ps
CPU time 4.58 seconds
Started Aug 11 06:07:14 PM PDT 24
Finished Aug 11 06:07:19 PM PDT 24
Peak memory 214280 kb
Host smart-f5502793-e139-4eae-891a-949081887d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736584431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3736584431
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3134574027
Short name T864
Test name
Test status
Simulation time 46478484 ps
CPU time 2.27 seconds
Started Aug 11 06:07:21 PM PDT 24
Finished Aug 11 06:07:23 PM PDT 24
Peak memory 210032 kb
Host smart-82651848-03d6-4de6-8cde-fbab4d904dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134574027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3134574027
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.74177891
Short name T670
Test name
Test status
Simulation time 13499295 ps
CPU time 0.85 seconds
Started Aug 11 06:07:20 PM PDT 24
Finished Aug 11 06:07:21 PM PDT 24
Peak memory 205912 kb
Host smart-611480fd-b899-4af5-81b5-ddefee3a7669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74177891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.74177891
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2092428059
Short name T423
Test name
Test status
Simulation time 111014086 ps
CPU time 2.45 seconds
Started Aug 11 06:07:27 PM PDT 24
Finished Aug 11 06:07:30 PM PDT 24
Peak memory 222352 kb
Host smart-33d128a5-4865-40ee-81aa-d2f4fabe19b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092428059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2092428059
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.132828833
Short name T558
Test name
Test status
Simulation time 1297474528 ps
CPU time 33.09 seconds
Started Aug 11 06:07:20 PM PDT 24
Finished Aug 11 06:07:53 PM PDT 24
Peak memory 222684 kb
Host smart-2d6e625e-0e7a-4dcd-a6e8-fc6eaaae6f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132828833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.132828833
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4274163943
Short name T512
Test name
Test status
Simulation time 229435258 ps
CPU time 3.04 seconds
Started Aug 11 06:07:22 PM PDT 24
Finished Aug 11 06:07:26 PM PDT 24
Peak memory 210388 kb
Host smart-490c2fb4-a18a-47a0-9322-2b1f3c98ea8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274163943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4274163943
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2849266143
Short name T727
Test name
Test status
Simulation time 224171605 ps
CPU time 3.88 seconds
Started Aug 11 06:07:22 PM PDT 24
Finished Aug 11 06:07:26 PM PDT 24
Peak memory 222452 kb
Host smart-34ccde31-5683-4780-99cd-85ca77b2bade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849266143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2849266143
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2940387265
Short name T762
Test name
Test status
Simulation time 119014507 ps
CPU time 3.04 seconds
Started Aug 11 06:07:24 PM PDT 24
Finished Aug 11 06:07:27 PM PDT 24
Peak memory 214288 kb
Host smart-66e55b4b-99fd-4b6a-a7c0-3cfc00557094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940387265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2940387265
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2309668333
Short name T156
Test name
Test status
Simulation time 1294879263 ps
CPU time 4.01 seconds
Started Aug 11 06:07:19 PM PDT 24
Finished Aug 11 06:07:23 PM PDT 24
Peak memory 220248 kb
Host smart-ae67a764-15b6-4b54-af55-e5aecc2cbce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309668333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2309668333
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2261937760
Short name T521
Test name
Test status
Simulation time 265607195 ps
CPU time 5.03 seconds
Started Aug 11 06:07:24 PM PDT 24
Finished Aug 11 06:07:29 PM PDT 24
Peak memory 207524 kb
Host smart-a421f60e-7827-4a67-a85c-73e79b7e9a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261937760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2261937760
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2900077401
Short name T87
Test name
Test status
Simulation time 218036085 ps
CPU time 6.7 seconds
Started Aug 11 06:07:23 PM PDT 24
Finished Aug 11 06:07:29 PM PDT 24
Peak memory 208212 kb
Host smart-17b707ff-a2df-4aea-be1c-5d98f7e17808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900077401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2900077401
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1208933761
Short name T398
Test name
Test status
Simulation time 1930309585 ps
CPU time 13.29 seconds
Started Aug 11 06:07:21 PM PDT 24
Finished Aug 11 06:07:35 PM PDT 24
Peak memory 208264 kb
Host smart-08483783-7eac-4816-a77f-1646fd04ad04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208933761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1208933761
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1259872753
Short name T359
Test name
Test status
Simulation time 52442392 ps
CPU time 2.45 seconds
Started Aug 11 06:07:20 PM PDT 24
Finished Aug 11 06:07:23 PM PDT 24
Peak memory 208092 kb
Host smart-b188eed1-c327-4ce9-8a5f-ba882d48218c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259872753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1259872753
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.736525590
Short name T699
Test name
Test status
Simulation time 157503276 ps
CPU time 3.19 seconds
Started Aug 11 06:07:21 PM PDT 24
Finished Aug 11 06:07:25 PM PDT 24
Peak memory 206784 kb
Host smart-0b2fc75f-94b1-4ac8-81f2-f726a6e737c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736525590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.736525590
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1937650703
Short name T732
Test name
Test status
Simulation time 34166968 ps
CPU time 2.65 seconds
Started Aug 11 06:07:26 PM PDT 24
Finished Aug 11 06:07:29 PM PDT 24
Peak memory 210380 kb
Host smart-55f71567-71e9-43ff-a76f-9ee096f3634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937650703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1937650703
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.252891148
Short name T917
Test name
Test status
Simulation time 475123998 ps
CPU time 5.07 seconds
Started Aug 11 06:07:21 PM PDT 24
Finished Aug 11 06:07:26 PM PDT 24
Peak memory 207368 kb
Host smart-54935afd-5afd-4fbb-8aa4-939311870b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252891148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.252891148
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.488916167
Short name T356
Test name
Test status
Simulation time 193041244 ps
CPU time 4.41 seconds
Started Aug 11 06:07:21 PM PDT 24
Finished Aug 11 06:07:25 PM PDT 24
Peak memory 210440 kb
Host smart-f5a8dff2-a1c5-4149-9962-3aea34e519e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488916167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.488916167
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2144093617
Short name T211
Test name
Test status
Simulation time 865974808 ps
CPU time 5.66 seconds
Started Aug 11 06:07:28 PM PDT 24
Finished Aug 11 06:07:34 PM PDT 24
Peak memory 207512 kb
Host smart-ab96c124-03cc-4285-87ce-c54ff93a8e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144093617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2144093617
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2379398126
Short name T388
Test name
Test status
Simulation time 33217614 ps
CPU time 1.37 seconds
Started Aug 11 06:07:22 PM PDT 24
Finished Aug 11 06:07:23 PM PDT 24
Peak memory 208536 kb
Host smart-9122b827-79bd-47a3-971a-0b758648643d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379398126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2379398126
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.295883626
Short name T562
Test name
Test status
Simulation time 19595260 ps
CPU time 0.8 seconds
Started Aug 11 06:07:24 PM PDT 24
Finished Aug 11 06:07:25 PM PDT 24
Peak memory 205988 kb
Host smart-95c1aa79-985c-4735-8654-4fccd05069ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295883626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.295883626
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3977169609
Short name T409
Test name
Test status
Simulation time 499359816 ps
CPU time 7.74 seconds
Started Aug 11 06:07:20 PM PDT 24
Finished Aug 11 06:07:28 PM PDT 24
Peak memory 214416 kb
Host smart-74cb2f24-f992-411b-a0e9-7adc7e301d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977169609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3977169609
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1691788333
Short name T497
Test name
Test status
Simulation time 264175825 ps
CPU time 3.52 seconds
Started Aug 11 06:07:24 PM PDT 24
Finished Aug 11 06:07:27 PM PDT 24
Peak memory 208880 kb
Host smart-68e17f87-0dd5-4006-b8b4-622156f8f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691788333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1691788333
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2498660141
Short name T254
Test name
Test status
Simulation time 197403906 ps
CPU time 4.56 seconds
Started Aug 11 06:07:21 PM PDT 24
Finished Aug 11 06:07:26 PM PDT 24
Peak memory 214256 kb
Host smart-e648be9a-2dc1-443e-acf3-00fcbb71518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498660141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2498660141
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.410014711
Short name T524
Test name
Test status
Simulation time 89167063 ps
CPU time 3.6 seconds
Started Aug 11 06:07:23 PM PDT 24
Finished Aug 11 06:07:27 PM PDT 24
Peak memory 220432 kb
Host smart-53e5aef6-2218-479c-8e9f-28390121886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410014711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.410014711
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.872601945
Short name T307
Test name
Test status
Simulation time 381174311 ps
CPU time 6.48 seconds
Started Aug 11 06:07:21 PM PDT 24
Finished Aug 11 06:07:28 PM PDT 24
Peak memory 210108 kb
Host smart-c278c8a3-e28c-4ec6-a925-62d067b3caa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872601945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.872601945
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3154928095
Short name T355
Test name
Test status
Simulation time 54478651 ps
CPU time 2.64 seconds
Started Aug 11 06:07:19 PM PDT 24
Finished Aug 11 06:07:22 PM PDT 24
Peak memory 206864 kb
Host smart-11ac892f-8b8d-4a17-8838-b8637e1b298c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154928095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3154928095
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2272171350
Short name T210
Test name
Test status
Simulation time 920426036 ps
CPU time 4.09 seconds
Started Aug 11 06:07:22 PM PDT 24
Finished Aug 11 06:07:26 PM PDT 24
Peak memory 207696 kb
Host smart-d538e3d5-a57f-4190-aba6-43c0b2731070
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272171350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2272171350
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2636020005
Short name T545
Test name
Test status
Simulation time 170967534 ps
CPU time 6.06 seconds
Started Aug 11 06:07:27 PM PDT 24
Finished Aug 11 06:07:33 PM PDT 24
Peak memory 207936 kb
Host smart-2dc35671-94f4-4db5-bff5-ac52c7166792
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636020005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2636020005
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.598206577
Short name T377
Test name
Test status
Simulation time 1194358565 ps
CPU time 8.82 seconds
Started Aug 11 06:07:23 PM PDT 24
Finished Aug 11 06:07:32 PM PDT 24
Peak memory 208832 kb
Host smart-5b6d7420-0410-4256-9357-3e113171d25c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598206577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.598206577
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.578043590
Short name T695
Test name
Test status
Simulation time 293651942 ps
CPU time 3.18 seconds
Started Aug 11 06:07:28 PM PDT 24
Finished Aug 11 06:07:32 PM PDT 24
Peak memory 209008 kb
Host smart-715b4d57-0c88-4bb2-ad53-1c3085dbc7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578043590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.578043590
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1375762196
Short name T899
Test name
Test status
Simulation time 84722060 ps
CPU time 2.86 seconds
Started Aug 11 06:07:25 PM PDT 24
Finished Aug 11 06:07:28 PM PDT 24
Peak memory 208716 kb
Host smart-de06adfb-2735-4358-81c1-263dbfaa8f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375762196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1375762196
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2557285270
Short name T192
Test name
Test status
Simulation time 1412244756 ps
CPU time 50.2 seconds
Started Aug 11 06:07:30 PM PDT 24
Finished Aug 11 06:08:20 PM PDT 24
Peak memory 216400 kb
Host smart-098d4a94-f924-45d4-9f5d-fb16f361cfd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557285270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2557285270
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3073807158
Short name T787
Test name
Test status
Simulation time 11199550445 ps
CPU time 88.56 seconds
Started Aug 11 06:07:20 PM PDT 24
Finished Aug 11 06:08:49 PM PDT 24
Peak memory 209292 kb
Host smart-bbc4e1d1-dcde-49ce-9789-494c2f453c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073807158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3073807158
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1519402185
Short name T765
Test name
Test status
Simulation time 75307919 ps
CPU time 2.26 seconds
Started Aug 11 06:07:22 PM PDT 24
Finished Aug 11 06:07:25 PM PDT 24
Peak memory 210184 kb
Host smart-a9874aee-aedd-466b-8097-b76f47349db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519402185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1519402185
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2964546437
Short name T578
Test name
Test status
Simulation time 92882070 ps
CPU time 0.82 seconds
Started Aug 11 06:04:44 PM PDT 24
Finished Aug 11 06:04:45 PM PDT 24
Peak memory 205956 kb
Host smart-31a73a45-46ec-443f-a13a-905d9d1a7795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964546437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2964546437
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.179599096
Short name T422
Test name
Test status
Simulation time 228753754 ps
CPU time 4.23 seconds
Started Aug 11 06:04:43 PM PDT 24
Finished Aug 11 06:04:48 PM PDT 24
Peak memory 215316 kb
Host smart-1d8a6bd2-74eb-4850-948e-bd2ccd8b502c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179599096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.179599096
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.397007206
Short name T759
Test name
Test status
Simulation time 192002939 ps
CPU time 4.16 seconds
Started Aug 11 06:04:43 PM PDT 24
Finished Aug 11 06:04:48 PM PDT 24
Peak memory 210416 kb
Host smart-a0f57116-f1f9-4be3-8d05-61325a358767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397007206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.397007206
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.352650089
Short name T532
Test name
Test status
Simulation time 67999649 ps
CPU time 2.19 seconds
Started Aug 11 06:04:42 PM PDT 24
Finished Aug 11 06:04:44 PM PDT 24
Peak memory 214248 kb
Host smart-e26d6c26-d543-4b5f-89a0-b46ab85a15ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352650089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.352650089
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1038769661
Short name T322
Test name
Test status
Simulation time 106764800 ps
CPU time 2.36 seconds
Started Aug 11 06:04:45 PM PDT 24
Finished Aug 11 06:04:47 PM PDT 24
Peak memory 214428 kb
Host smart-cea37b2a-bdfc-43ef-b432-be134896ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038769661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1038769661
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1589253897
Short name T82
Test name
Test status
Simulation time 98485010 ps
CPU time 3.25 seconds
Started Aug 11 06:04:50 PM PDT 24
Finished Aug 11 06:04:54 PM PDT 24
Peak memory 222348 kb
Host smart-4e6f7965-d650-4b5d-8fe2-130e25fed59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589253897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1589253897
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1584196511
Short name T41
Test name
Test status
Simulation time 129192873 ps
CPU time 3.38 seconds
Started Aug 11 06:04:49 PM PDT 24
Finished Aug 11 06:04:53 PM PDT 24
Peak memory 214288 kb
Host smart-4b50fa01-15ea-4483-b7ed-29728b085f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584196511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1584196511
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.424716155
Short name T527
Test name
Test status
Simulation time 203454131 ps
CPU time 4.31 seconds
Started Aug 11 06:04:44 PM PDT 24
Finished Aug 11 06:04:48 PM PDT 24
Peak memory 209080 kb
Host smart-3121c54b-4f19-4996-938a-250984b6d698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424716155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.424716155
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1241289730
Short name T798
Test name
Test status
Simulation time 134257562 ps
CPU time 4.63 seconds
Started Aug 11 06:04:44 PM PDT 24
Finished Aug 11 06:04:49 PM PDT 24
Peak memory 208028 kb
Host smart-74d934af-a850-454d-90ec-e5c4bca98bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241289730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1241289730
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4145411786
Short name T680
Test name
Test status
Simulation time 1438429414 ps
CPU time 25.3 seconds
Started Aug 11 06:04:44 PM PDT 24
Finished Aug 11 06:05:10 PM PDT 24
Peak memory 207280 kb
Host smart-acbc3240-00ca-4dfa-80b2-b10403d3884c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145411786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4145411786
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.15718616
Short name T678
Test name
Test status
Simulation time 909201636 ps
CPU time 2.99 seconds
Started Aug 11 06:04:42 PM PDT 24
Finished Aug 11 06:04:45 PM PDT 24
Peak memory 206880 kb
Host smart-d8f5e8e9-85ce-4b82-b316-a87ef413b01c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15718616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.15718616
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1103307340
Short name T214
Test name
Test status
Simulation time 713272164 ps
CPU time 5.54 seconds
Started Aug 11 06:04:47 PM PDT 24
Finished Aug 11 06:04:53 PM PDT 24
Peak memory 208268 kb
Host smart-e98d90f7-57fd-4e11-bc0c-492bab1b8121
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103307340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1103307340
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2423045450
Short name T249
Test name
Test status
Simulation time 100724076 ps
CPU time 2.16 seconds
Started Aug 11 06:04:45 PM PDT 24
Finished Aug 11 06:04:47 PM PDT 24
Peak memory 215456 kb
Host smart-376873eb-a15e-43d4-aaf9-d84a6e83a686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423045450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2423045450
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2197743805
Short name T85
Test name
Test status
Simulation time 43458653 ps
CPU time 1.9 seconds
Started Aug 11 06:04:43 PM PDT 24
Finished Aug 11 06:04:45 PM PDT 24
Peak memory 207084 kb
Host smart-21256206-8265-4579-8614-d60d5a31994a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197743805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2197743805
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2681381369
Short name T277
Test name
Test status
Simulation time 3057341186 ps
CPU time 10.66 seconds
Started Aug 11 06:04:46 PM PDT 24
Finished Aug 11 06:04:56 PM PDT 24
Peak memory 214368 kb
Host smart-edb36f82-43fd-4e53-ab83-50d19d9f7d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681381369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2681381369
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2484724274
Short name T901
Test name
Test status
Simulation time 141825019 ps
CPU time 2.89 seconds
Started Aug 11 06:04:50 PM PDT 24
Finished Aug 11 06:04:53 PM PDT 24
Peak memory 210456 kb
Host smart-5ab5d784-f06e-47e4-8759-cd18650d657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484724274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2484724274
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1207246505
Short name T490
Test name
Test status
Simulation time 47053798 ps
CPU time 0.8 seconds
Started Aug 11 06:04:56 PM PDT 24
Finished Aug 11 06:04:57 PM PDT 24
Peak memory 205908 kb
Host smart-d73525cf-af9a-4619-94af-cc226da4729c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207246505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1207246505
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1124187475
Short name T302
Test name
Test status
Simulation time 6899751235 ps
CPU time 15.79 seconds
Started Aug 11 06:04:50 PM PDT 24
Finished Aug 11 06:05:06 PM PDT 24
Peak memory 214300 kb
Host smart-c67cac87-c195-4256-b95f-e770e0630fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124187475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1124187475
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.959015181
Short name T92
Test name
Test status
Simulation time 255572627 ps
CPU time 2.92 seconds
Started Aug 11 06:04:50 PM PDT 24
Finished Aug 11 06:04:53 PM PDT 24
Peak memory 214740 kb
Host smart-8084d565-a9dc-4227-873d-7021e24fdae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959015181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.959015181
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1975116761
Short name T656
Test name
Test status
Simulation time 76834914 ps
CPU time 3.12 seconds
Started Aug 11 06:04:56 PM PDT 24
Finished Aug 11 06:04:59 PM PDT 24
Peak memory 220828 kb
Host smart-d37f17b5-b784-4a0f-a07c-38ee66d1ee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975116761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1975116761
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2828518445
Short name T584
Test name
Test status
Simulation time 468160590 ps
CPU time 3.98 seconds
Started Aug 11 06:04:43 PM PDT 24
Finished Aug 11 06:04:47 PM PDT 24
Peak memory 215084 kb
Host smart-714d4532-d1a8-471b-bc1f-ac9941e1fcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828518445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2828518445
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3045025298
Short name T750
Test name
Test status
Simulation time 177836454 ps
CPU time 6.13 seconds
Started Aug 11 06:04:44 PM PDT 24
Finished Aug 11 06:04:50 PM PDT 24
Peak memory 208664 kb
Host smart-49bdacd7-71e8-492b-b80a-19b5aff180af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045025298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3045025298
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.701963348
Short name T197
Test name
Test status
Simulation time 103442930 ps
CPU time 2.7 seconds
Started Aug 11 06:04:42 PM PDT 24
Finished Aug 11 06:04:45 PM PDT 24
Peak memory 208508 kb
Host smart-3bc3e62e-247d-4c3e-a385-7d7d63c57a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701963348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.701963348
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.519094751
Short name T731
Test name
Test status
Simulation time 73259122 ps
CPU time 3.24 seconds
Started Aug 11 06:04:45 PM PDT 24
Finished Aug 11 06:04:49 PM PDT 24
Peak memory 208620 kb
Host smart-b6586fc9-ee9a-4651-8d37-be0f0a38765c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519094751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.519094751
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1526890230
Short name T610
Test name
Test status
Simulation time 162627033 ps
CPU time 2.51 seconds
Started Aug 11 06:04:44 PM PDT 24
Finished Aug 11 06:04:46 PM PDT 24
Peak memory 206832 kb
Host smart-5e46e3e3-5aec-43ee-94dc-6afcb89a89cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526890230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1526890230
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.983285993
Short name T676
Test name
Test status
Simulation time 447270885 ps
CPU time 3.95 seconds
Started Aug 11 06:04:51 PM PDT 24
Finished Aug 11 06:04:55 PM PDT 24
Peak memory 206868 kb
Host smart-bad8e1d3-1a19-4325-af43-b34839716625
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983285993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.983285993
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.513128957
Short name T900
Test name
Test status
Simulation time 66310635 ps
CPU time 1.61 seconds
Started Aug 11 06:04:53 PM PDT 24
Finished Aug 11 06:04:55 PM PDT 24
Peak memory 207660 kb
Host smart-1e1c8d58-70cd-4ff7-9149-45332edd057a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513128957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.513128957
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2877613265
Short name T543
Test name
Test status
Simulation time 218679095 ps
CPU time 3.27 seconds
Started Aug 11 06:04:42 PM PDT 24
Finished Aug 11 06:04:46 PM PDT 24
Peak memory 208440 kb
Host smart-b5067760-89e6-473f-bb1f-a5843daf4465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877613265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2877613265
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2810842408
Short name T345
Test name
Test status
Simulation time 352934975 ps
CPU time 7.28 seconds
Started Aug 11 06:04:46 PM PDT 24
Finished Aug 11 06:04:54 PM PDT 24
Peak memory 222380 kb
Host smart-ed596b8e-879f-4dbb-9339-c9601385c034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810842408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2810842408
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2335503741
Short name T134
Test name
Test status
Simulation time 108809702 ps
CPU time 2.24 seconds
Started Aug 11 06:04:48 PM PDT 24
Finished Aug 11 06:04:50 PM PDT 24
Peak memory 209768 kb
Host smart-1b41b774-65a1-4365-9432-9102165d86db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335503741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2335503741
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1057447965
Short name T849
Test name
Test status
Simulation time 77151186 ps
CPU time 0.69 seconds
Started Aug 11 06:04:57 PM PDT 24
Finished Aug 11 06:04:58 PM PDT 24
Peak memory 205876 kb
Host smart-46a8fcd9-7e98-4dec-9819-34ac837b422a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057447965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1057447965
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3155759238
Short name T424
Test name
Test status
Simulation time 643075666 ps
CPU time 6.68 seconds
Started Aug 11 06:04:50 PM PDT 24
Finished Aug 11 06:04:57 PM PDT 24
Peak memory 214752 kb
Host smart-fca85c79-52fc-4a57-beab-02c47ffb2462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155759238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3155759238
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2574254054
Short name T70
Test name
Test status
Simulation time 385947881 ps
CPU time 2.41 seconds
Started Aug 11 06:04:51 PM PDT 24
Finished Aug 11 06:04:54 PM PDT 24
Peak memory 208228 kb
Host smart-0546f305-4916-4242-b7e8-7cbb82adc3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574254054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2574254054
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3200259037
Short name T594
Test name
Test status
Simulation time 63142046 ps
CPU time 2.19 seconds
Started Aug 11 06:04:49 PM PDT 24
Finished Aug 11 06:04:51 PM PDT 24
Peak memory 214308 kb
Host smart-442cd408-e36e-41f1-b47d-31da6d787298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200259037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3200259037
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2168719355
Short name T291
Test name
Test status
Simulation time 126857536 ps
CPU time 5.33 seconds
Started Aug 11 06:04:51 PM PDT 24
Finished Aug 11 06:04:57 PM PDT 24
Peak memory 206172 kb
Host smart-dd306ef5-d25e-4792-9811-f7b92df7462d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168719355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2168719355
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3873517455
Short name T626
Test name
Test status
Simulation time 136231410 ps
CPU time 4.11 seconds
Started Aug 11 06:04:51 PM PDT 24
Finished Aug 11 06:04:55 PM PDT 24
Peak memory 220496 kb
Host smart-70c2e870-e824-46b0-ae07-c4ea7b048227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873517455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3873517455
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1180070740
Short name T818
Test name
Test status
Simulation time 324753983 ps
CPU time 3.97 seconds
Started Aug 11 06:04:53 PM PDT 24
Finished Aug 11 06:04:58 PM PDT 24
Peak memory 210308 kb
Host smart-3078f669-fde7-4f62-823f-69bd20ae38f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180070740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1180070740
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1633905650
Short name T752
Test name
Test status
Simulation time 856577093 ps
CPU time 24.53 seconds
Started Aug 11 06:04:48 PM PDT 24
Finished Aug 11 06:05:13 PM PDT 24
Peak memory 208244 kb
Host smart-2002f0a4-19a3-4f6f-8157-bb5521b2427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633905650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1633905650
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2709331418
Short name T332
Test name
Test status
Simulation time 127364013 ps
CPU time 2.48 seconds
Started Aug 11 06:04:54 PM PDT 24
Finished Aug 11 06:04:57 PM PDT 24
Peak memory 207568 kb
Host smart-d53c552f-2743-4b0a-ad1e-0dd34ef0648f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709331418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2709331418
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1964051781
Short name T459
Test name
Test status
Simulation time 108703247 ps
CPU time 3.45 seconds
Started Aug 11 06:04:52 PM PDT 24
Finished Aug 11 06:04:56 PM PDT 24
Peak memory 208728 kb
Host smart-4a29cfa0-bd8f-4d25-a63f-e92a1ad51f6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964051781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1964051781
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2439139417
Short name T504
Test name
Test status
Simulation time 433159055 ps
CPU time 6.88 seconds
Started Aug 11 06:04:50 PM PDT 24
Finished Aug 11 06:04:57 PM PDT 24
Peak memory 206916 kb
Host smart-ebbda6f8-7402-4985-b2aa-bf2057e6dac6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439139417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2439139417
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2001511608
Short name T575
Test name
Test status
Simulation time 121563156 ps
CPU time 3.52 seconds
Started Aug 11 06:04:59 PM PDT 24
Finished Aug 11 06:05:03 PM PDT 24
Peak memory 208612 kb
Host smart-eebe1ab2-8b26-4a38-9741-77a105154e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001511608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2001511608
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1456316435
Short name T876
Test name
Test status
Simulation time 152549668 ps
CPU time 2.43 seconds
Started Aug 11 06:04:52 PM PDT 24
Finished Aug 11 06:04:55 PM PDT 24
Peak memory 208476 kb
Host smart-3daf92b2-f67c-4b15-9558-2c42d7179082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456316435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1456316435
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2400015429
Short name T191
Test name
Test status
Simulation time 1273954375 ps
CPU time 47.68 seconds
Started Aug 11 06:04:59 PM PDT 24
Finished Aug 11 06:05:46 PM PDT 24
Peak memory 222632 kb
Host smart-463b9a7d-6010-4700-a423-f00c5bd1adc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400015429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2400015429
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1005834972
Short name T280
Test name
Test status
Simulation time 294684577 ps
CPU time 3.53 seconds
Started Aug 11 06:04:53 PM PDT 24
Finished Aug 11 06:04:57 PM PDT 24
Peak memory 214232 kb
Host smart-fcf2d539-fff3-48ac-8f4e-8a7f0ac266c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005834972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1005834972
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3344854450
Short name T769
Test name
Test status
Simulation time 49830825 ps
CPU time 0.79 seconds
Started Aug 11 06:05:01 PM PDT 24
Finished Aug 11 06:05:02 PM PDT 24
Peak memory 206116 kb
Host smart-9676acbd-339e-4ba1-a6e5-6f7e1651e7c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344854450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3344854450
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.624396679
Short name T395
Test name
Test status
Simulation time 47388712 ps
CPU time 2.87 seconds
Started Aug 11 06:05:08 PM PDT 24
Finished Aug 11 06:05:11 PM PDT 24
Peak memory 215364 kb
Host smart-86ba09f2-3ac2-46ab-9ca1-900058183221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=624396679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.624396679
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.335601264
Short name T804
Test name
Test status
Simulation time 117795645 ps
CPU time 4.81 seconds
Started Aug 11 06:04:59 PM PDT 24
Finished Aug 11 06:05:04 PM PDT 24
Peak memory 221452 kb
Host smart-60cb00e6-6c7d-4612-8fa1-0fbe32c21129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335601264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.335601264
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3656054818
Short name T489
Test name
Test status
Simulation time 128161046 ps
CPU time 4.29 seconds
Started Aug 11 06:05:07 PM PDT 24
Finished Aug 11 06:05:12 PM PDT 24
Peak memory 208648 kb
Host smart-002a0e36-4b2d-444e-9687-23e5047ac291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656054818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3656054818
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1089257029
Short name T323
Test name
Test status
Simulation time 65899627 ps
CPU time 2.78 seconds
Started Aug 11 06:04:59 PM PDT 24
Finished Aug 11 06:05:02 PM PDT 24
Peak memory 214328 kb
Host smart-b80d4755-95f1-492d-8a15-fd2a6dd0a067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089257029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1089257029
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2917148258
Short name T745
Test name
Test status
Simulation time 201888320 ps
CPU time 2.84 seconds
Started Aug 11 06:04:58 PM PDT 24
Finished Aug 11 06:05:01 PM PDT 24
Peak memory 214284 kb
Host smart-af084441-233f-41df-87b5-04f13fbef48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917148258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2917148258
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.97792413
Short name T236
Test name
Test status
Simulation time 155039675 ps
CPU time 4.02 seconds
Started Aug 11 06:05:00 PM PDT 24
Finished Aug 11 06:05:04 PM PDT 24
Peak memory 222352 kb
Host smart-dedde0fc-d441-434e-b5b4-02027abe93e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97792413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.97792413
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3379661705
Short name T820
Test name
Test status
Simulation time 385127314 ps
CPU time 10.21 seconds
Started Aug 11 06:05:01 PM PDT 24
Finished Aug 11 06:05:11 PM PDT 24
Peak memory 208960 kb
Host smart-b2a5b3e4-96f5-4355-886b-dd8385a1bfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379661705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3379661705
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3457773346
Short name T772
Test name
Test status
Simulation time 58151857 ps
CPU time 2.96 seconds
Started Aug 11 06:04:58 PM PDT 24
Finished Aug 11 06:05:01 PM PDT 24
Peak memory 208172 kb
Host smart-d25ae415-bc72-4a30-9c29-90b9e355e80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457773346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3457773346
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3773258148
Short name T741
Test name
Test status
Simulation time 294950012 ps
CPU time 4.54 seconds
Started Aug 11 06:05:07 PM PDT 24
Finished Aug 11 06:05:12 PM PDT 24
Peak memory 208416 kb
Host smart-7d0ddb59-8527-4b9b-8b03-92e3466072ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773258148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3773258148
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.115988920
Short name T534
Test name
Test status
Simulation time 179944929 ps
CPU time 4.04 seconds
Started Aug 11 06:04:59 PM PDT 24
Finished Aug 11 06:05:03 PM PDT 24
Peak memory 206920 kb
Host smart-a04af9f6-a26f-45b9-9c33-7f9c8ffe96f0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115988920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.115988920
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2812438254
Short name T376
Test name
Test status
Simulation time 323145783 ps
CPU time 4.98 seconds
Started Aug 11 06:05:01 PM PDT 24
Finished Aug 11 06:05:06 PM PDT 24
Peak memory 209108 kb
Host smart-609fdef7-41a3-4583-a5ed-6b19cdcba6f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812438254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2812438254
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2880343901
Short name T709
Test name
Test status
Simulation time 380103161 ps
CPU time 4.3 seconds
Started Aug 11 06:04:59 PM PDT 24
Finished Aug 11 06:05:04 PM PDT 24
Peak memory 209184 kb
Host smart-27afeba4-189a-48ed-913b-5b027e9027bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880343901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2880343901
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2445461385
Short name T510
Test name
Test status
Simulation time 231581318 ps
CPU time 4.56 seconds
Started Aug 11 06:05:00 PM PDT 24
Finished Aug 11 06:05:04 PM PDT 24
Peak memory 206812 kb
Host smart-1c239b1d-60e7-4d45-bdd0-c0cf83450805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445461385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2445461385
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1512419547
Short name T845
Test name
Test status
Simulation time 90979047 ps
CPU time 2.82 seconds
Started Aug 11 06:05:01 PM PDT 24
Finished Aug 11 06:05:03 PM PDT 24
Peak memory 207356 kb
Host smart-074b4647-8798-49bd-9b0e-ff46a80d3c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512419547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1512419547
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.707062026
Short name T475
Test name
Test status
Simulation time 359341797 ps
CPU time 2.25 seconds
Started Aug 11 06:04:59 PM PDT 24
Finished Aug 11 06:05:01 PM PDT 24
Peak memory 210020 kb
Host smart-b0ce363b-25bb-47a3-939a-583593b6aa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707062026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.707062026
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.605350688
Short name T838
Test name
Test status
Simulation time 11101344 ps
CPU time 0.87 seconds
Started Aug 11 06:05:10 PM PDT 24
Finished Aug 11 06:05:11 PM PDT 24
Peak memory 205964 kb
Host smart-8d1906e9-1251-408f-a40e-3c56476fa782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605350688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.605350688
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.239992670
Short name T416
Test name
Test status
Simulation time 73587186 ps
CPU time 4.25 seconds
Started Aug 11 06:05:07 PM PDT 24
Finished Aug 11 06:05:11 PM PDT 24
Peak memory 214380 kb
Host smart-3725a735-1402-42b4-9bc9-8cc05c829913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239992670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.239992670
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.323749412
Short name T30
Test name
Test status
Simulation time 436313386 ps
CPU time 4.36 seconds
Started Aug 11 06:05:10 PM PDT 24
Finished Aug 11 06:05:15 PM PDT 24
Peak memory 207060 kb
Host smart-5f0ff9bb-c2a8-4ec8-970c-df176e4f678c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323749412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.323749412
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3147908460
Short name T554
Test name
Test status
Simulation time 297273007 ps
CPU time 3.32 seconds
Started Aug 11 06:05:04 PM PDT 24
Finished Aug 11 06:05:07 PM PDT 24
Peak memory 208688 kb
Host smart-a6745d0e-e6f9-4b52-9f2d-61a7890dd59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147908460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3147908460
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3849584972
Short name T95
Test name
Test status
Simulation time 206790217 ps
CPU time 3.76 seconds
Started Aug 11 06:05:07 PM PDT 24
Finished Aug 11 06:05:11 PM PDT 24
Peak memory 214332 kb
Host smart-6181444a-85cb-4dfa-9bf8-db87750a2fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849584972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3849584972
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1888441568
Short name T440
Test name
Test status
Simulation time 147537757 ps
CPU time 3.57 seconds
Started Aug 11 06:05:05 PM PDT 24
Finished Aug 11 06:05:09 PM PDT 24
Peak memory 209812 kb
Host smart-e8b4bf6f-7657-4956-b501-d0e170431f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888441568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1888441568
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.461347231
Short name T582
Test name
Test status
Simulation time 375537060 ps
CPU time 4.14 seconds
Started Aug 11 06:05:08 PM PDT 24
Finished Aug 11 06:05:12 PM PDT 24
Peak memory 207180 kb
Host smart-ce3027a4-7e1e-405f-947f-e846969d232f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461347231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.461347231
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.26933932
Short name T299
Test name
Test status
Simulation time 82370673 ps
CPU time 1.81 seconds
Started Aug 11 06:05:07 PM PDT 24
Finished Aug 11 06:05:09 PM PDT 24
Peak memory 206848 kb
Host smart-e51b31af-a5e3-44fd-9988-fa0cbd666266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26933932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.26933932
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3044008996
Short name T437
Test name
Test status
Simulation time 391059088 ps
CPU time 13.08 seconds
Started Aug 11 06:05:09 PM PDT 24
Finished Aug 11 06:05:22 PM PDT 24
Peak memory 208692 kb
Host smart-210c7b47-b8ff-4458-82d0-cf07b393c97e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044008996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3044008996
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2038291164
Short name T810
Test name
Test status
Simulation time 357288229 ps
CPU time 3.71 seconds
Started Aug 11 06:05:06 PM PDT 24
Finished Aug 11 06:05:10 PM PDT 24
Peak memory 208700 kb
Host smart-86919bed-dd5d-4572-a43c-b8fb65ef08f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038291164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2038291164
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.924539640
Short name T662
Test name
Test status
Simulation time 129167782 ps
CPU time 2.46 seconds
Started Aug 11 06:05:08 PM PDT 24
Finished Aug 11 06:05:10 PM PDT 24
Peak memory 207152 kb
Host smart-9463767d-9930-4a59-a025-e7c4be061ce7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924539640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.924539640
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1279654028
Short name T549
Test name
Test status
Simulation time 371527432 ps
CPU time 4.04 seconds
Started Aug 11 06:05:16 PM PDT 24
Finished Aug 11 06:05:20 PM PDT 24
Peak memory 210128 kb
Host smart-4c8ac87d-a803-4bc3-867f-e4c397ea67d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279654028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1279654028
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2484685016
Short name T866
Test name
Test status
Simulation time 47509265 ps
CPU time 2.08 seconds
Started Aug 11 06:05:09 PM PDT 24
Finished Aug 11 06:05:11 PM PDT 24
Peak memory 206780 kb
Host smart-1d88acb7-1d50-4c22-b072-6e2f6876b04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484685016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2484685016
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.266157743
Short name T722
Test name
Test status
Simulation time 8042982572 ps
CPU time 181.68 seconds
Started Aug 11 06:05:11 PM PDT 24
Finished Aug 11 06:08:13 PM PDT 24
Peak memory 222464 kb
Host smart-9dd72e65-40ec-4489-be92-b1d6a6935273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266157743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.266157743
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4119295954
Short name T540
Test name
Test status
Simulation time 1193026387 ps
CPU time 28.02 seconds
Started Aug 11 06:05:16 PM PDT 24
Finished Aug 11 06:05:44 PM PDT 24
Peak memory 208872 kb
Host smart-0d862a8c-a55d-48c3-b06b-171616cbd24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119295954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4119295954
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4090228346
Short name T470
Test name
Test status
Simulation time 35407462 ps
CPU time 2.1 seconds
Started Aug 11 06:05:09 PM PDT 24
Finished Aug 11 06:05:11 PM PDT 24
Peak memory 209992 kb
Host smart-005b26d0-e3e7-4f4f-a4a2-3f039db01f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090228346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4090228346
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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