Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	76	254	76.97

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	57	223	79.64	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4611

1

T1

6

T2

1

T4

3

auto[1]

557

1

T13

2

T17

3

T200

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4611

1

T1

6

T2

1

T4

3

auto[1]

557

1

T13

2

T17

3

T200

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4633

1

T1

6

T2

1

T4

3

auto[1]

535

1

T16

2

T37

3

T50

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4633

1

T1

6

T2

1

T4

3

auto[1]

535

1

T16

2

T37

3

T50

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	434	1			T1	1		T12	1		T16	1
auto[OpGenId]	1040	1			T1	2		T2	1		T4	1
auto[OpGenSwOut]	1035	1			T1	2		T13	3		T80	2
auto[OpGenHwOut]	2581	1			T1	1		T4	1		T13	2
auto[OpDisable]	78	1			T4	1		T49	1		T50	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	434	1			T1	1		T12	1		T16	1
auto[OpGenId]	1040	1			T1	2		T2	1		T4	1
auto[OpGenSwOut]	1035	1			T1	2		T13	3		T80	2
auto[OpGenHwOut]	2581	1			T1	1		T4	1		T13	2
auto[OpDisable]	78	1			T4	1		T49	1		T50	2

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4681

1

T1

6

T2

1

T4

3

auto[1]

487

1

T13

1

T14

1

T16

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4681

1

T1

6

T2

1

T4

3

auto[1]

487

1

T13

1

T14

1

T16

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4877

1

T1

6

T2

1

T4

3

auto[1]

291

1

T112

7

T139

3

T140

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1759	1			T1	2		T2	1		T4	1
auto[1]	697	1			T1	3		T4	1		T16	2
auto[2]	666	1			T13	2		T17	2		T18	1
auto[3]	716	1			T1	1		T14	2		T17	2
auto[4]	305	1			T13	1		T14	1		T16	1
auto[5]	322	1			T17	1		T50	1		T76	1
auto[6]	365	1			T4	1		T14	2		T16	1
auto[7]	338	1			T13	1		T14	1		T16	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1330	1			T4	1		T13	2		T14	4
clear_one[1]	697	1			T1	3		T4	1		T16	2
clear_one[2]	666	1			T13	2		T17	2		T18	1
clear_one[3]	716	1			T1	1		T14	2		T17	2
clear_none	1759	1			T1	2		T2	1		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	964	1			T13	3		T16	2		T17	3
auto[StInit]	656	1			T4	1		T14	1		T16	1
auto[StCreatorRootKey]	586	1			T2	1		T4	1		T12	1
auto[StOwnerIntKey]	475	1			T14	1		T16	1		T17	1
auto[StOwnerKey]	451	1			T14	1		T16	1		T17	1
auto[StDisabled]	1783	1			T4	1		T13	2		T14	4
auto[StInvalid]	253	1			T1	6		T51	3		T40	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	964	1			T13	3		T16	2		T17	3
auto[StInit]	656	1			T4	1		T14	1		T16	1
auto[StCreatorRootKey]	586	1			T2	1		T4	1		T12	1
auto[StOwnerIntKey]	475	1			T14	1		T16	1		T17	1
auto[StOwnerKey]	451	1			T14	1		T16	1		T17	1
auto[StDisabled]	1783	1			T4	1		T13	2		T14	4
auto[StInvalid]	253	1			T1	6		T51	3		T40	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StOwnerIntKey]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit]]	[auto[OpGenId]]	0	1	1
[auto[6]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T221	1		T222	1		T223	1
auto[0]	auto[StReset]	auto[OpGenId]	160	1			T80	1		T47	1		T96	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	145	1			T13	1		T58	2		T49	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	267	1			T16	1		T17	1		T18	2
auto[0]	auto[StInit]	auto[OpAdvance]	48	1			T46	1		T125	1		T48	1
auto[0]	auto[StInit]	auto[OpGenId]	95	1			T49	1		T21	1		T46	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	74	1			T81	1		T112	1		T47	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	172	1			T4	1		T14	1		T79	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	28	1			T12	1		T21	1		T46	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	40	1			T2	1		T28	1		T46	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	41	1			T46	1		T5	1		T224	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	84	1			T13	1		T112	2		T124	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	17	1			T77	1		T112	1		T5	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T38	1		T46	1		T196	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	23	1			T50	1		T84	1		T48	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	64	1			T16	1		T46	2		T47	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T225	1		T226	1		T227	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	10	1			T118	1		T185	1		T228	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T84	1		T112	1		T46	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T112	1		T229	1		T230	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	33	1			T139	1		T5	1		T231	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T16	1		T49	1		T196	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T46	1		T198	1		T48	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	159	1			T14	1		T16	1		T17	1
auto[0]	auto[StDisabled]	auto[OpDisable]	23	1			T49	1		T56	1		T232	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T97	1		T233	1		T234	1
auto[0]	auto[StInvalid]	auto[OpGenId]	17	1			T51	1		T59	1		T235	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T1	1		T40	1		T52	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T1	1		T52	1		T236	1
auto[1]	auto[StReset]	auto[OpGenId]	23	1			T5	1		T237	1		T234	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	17	1			T139	1		T193	1		T5	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	51	1			T199	1		T238	1		T60	1
auto[1]	auto[StInit]	auto[OpAdvance]	5	1			T67	1		T239	1		T240	1
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T16	1		T118	1		T241	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	14	1			T5	1		T105	2		T83	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	29	1			T17	1		T18	1		T46	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T48	1		T242	1		T66	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T48	1		T139	2		T5	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T139	1		T243	1		T244	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T49	1		T245	1		T246	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T231	1		T247	2		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T46	1		T69	1		T249	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T46	1		T48	1		T250	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T18	1		T245	1		T193	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T185	1		T208	1		T187	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	14	1			T139	1		T251	1		T208	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T208	1		T53	1		T244	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T200	1		T46	1		T238	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	24	1			T84	1		T46	1		T67	1
auto[1]	auto[StDisabled]	auto[OpGenId]	56	1			T16	1		T46	1		T48	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T112	1		T124	1		T46	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	143	1			T18	1		T37	1		T50	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T4	1		T224	1		T252	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	12	1			T1	1		T253	2		T254	1
auto[1]	auto[StInvalid]	auto[OpGenId]	13	1			T1	1		T255	1		T233	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T1	1		T59	2		T256	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T255	1		T257	2		T258	1
auto[2]	auto[StReset]	auto[OpGenId]	23	1			T13	1		T193	1		T5	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	6	1			T105	1		T259	1		T260	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	50	1			T200	1		T47	1		T238	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T66	1		T261	1		T262	2
auto[2]	auto[StInit]	auto[OpGenId]	4	1			T59	1		T259	1		T263	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T192	1		T264	1		T265	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T37	1		T24	1		T245	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T21	1		T266	1		T267	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T50	1		T213	1		T262	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T46	1		T5	1		T106	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	51	1			T200	1		T78	1		T67	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T268	1		T269	1		T208	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T128	2		T243	1		T259	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T46	1		T125	1		T5	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T17	1		T200	1		T198	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T270	1		T271	1		-	-
auto[2]	auto[StOwnerKey]	auto[OpGenId]	11	1			T48	1		T60	1		T272	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T49	1		T48	1		T273	2
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T81	1		T50	1		T78	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	27	1			T274	1		T185	1		T275	1
auto[2]	auto[StDisabled]	auto[OpGenId]	50	1			T81	1		T84	1		T199	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T125	1		T48	1		T276	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	148	1			T13	1		T17	1		T18	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T50	1		T69	1		T5	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T277	1		T278	1		T279	2
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T257	1		T280	1		T281	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T236	1		T282	1		T254	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T283	1		T284	1		T285	2
auto[3]	auto[StReset]	auto[OpGenId]	13	1			T76	1		T5	1		T282	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	17	1			T193	1		T5	1		T67	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	52	1			T17	2		T37	1		T49	1
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T46	1		T286	1		T287	1
auto[3]	auto[StInit]	auto[OpGenId]	13	1			T24	1		T69	1		T5	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T49	1		T288	1		T289	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	28	1			T24	1		T96	1		T199	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T290	1		T291	1		T292	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T46	1		T66	1		T293	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T46	1		T140	1		T117	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T14	1		T18	1		T37	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T28	1		T274	1		T294	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T295	1		T64	1		T117	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T80	1		T49	1		T47	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T124	1		T126	1		T296	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T53	1		T297	1		T266	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T46	1		T48	1		T264	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T96	1		T48	1		T274	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T198	1		T245	1		T298	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	29	1			T199	1		T193	1		T127	1
auto[3]	auto[StDisabled]	auto[OpGenId]	51	1			T46	1		T47	1		T199	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T81	1		T46	2		T48	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T14	1		T81	1		T200	1
auto[3]	auto[StDisabled]	auto[OpDisable]	14	1			T46	1		T196	1		T60	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	10	1			T51	1		T236	1		T254	1
auto[3]	auto[StInvalid]	auto[OpGenId]	13	1			T1	1		T236	1		T97	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T257	1		T280	1		T258	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T51	1		T234	1		T256	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T299	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T5	1		T300	1		T301	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T268	1		T207	1		T267	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	14	1			T18	1		T48	1		T296	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T302	1		T303	1		T304	1
auto[4]	auto[StInit]	auto[OpGenId]	9	1			T66	1		T86	1		T305	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T306	1		T206	1		T307	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	16	1			T296	1		T117	1		T308	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T87	1		-	-		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T21	1		T105	1		T53	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T192	1		T269	1		T66	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T80	1		T125	1		T126	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T5	1		T60	1		T92	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T309	1		T310	1		T311	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T238	1		T312	1		T264	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T16	1		T313	1		T209	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	4	1			T199	1		T185	1		T314	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T5	1		T230	1		T315	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T14	1		T37	1		T46	2
auto[4]	auto[StDisabled]	auto[OpAdvance]	8	1			T80	1		T28	1		T213	1
auto[4]	auto[StDisabled]	auto[OpGenId]	23	1			T124	1		T47	1		T5	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T13	1		T80	1		T198	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T18	1		T37	1		T200	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T105	1		T72	1		T66	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T316	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T236	1		T317	1		T283	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T40	1		T318	1		T283	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T235	1		T258	1		T319	1
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T31	1		T63	1		T253	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T46	1		T59	1		T185	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	22	1			T5	1		T241	1		T320	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T321	1		T322	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	8	1			T76	1		T46	1		T103	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T274	1		T83	1		T73	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	16	1			T193	1		T323	1		T324	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T222	2		T325	1		T322	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T105	1		T25	1		T185	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T117	1		T72	1		T310	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T198	1		T312	1		T117	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T187	1		T326	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T46	1		T85	1		T327	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T213	1		T222	1		T314	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T78	1		T328	1		T329	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T140	1		T208	1		T225	2
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T67	1		T140	1		T330	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T331	1		T117	1		T73	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T17	1		T60	1		T332	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T46	1		T333	2		T141	1
auto[5]	auto[StDisabled]	auto[OpGenId]	21	1			T46	1		T47	1		T48	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T67	1		T60	2		T195	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T50	1		T84	1		T46	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T192	1		T47	1		T66	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	3	1			T334	1		T316	1		T335	1
auto[5]	auto[StInvalid]	auto[OpGenId]	2	1			T40	1		T336	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T59	1		T253	1		T337	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T338	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T196	1		T67	1		T202	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	5	1			T46	1		T5	1		T206	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T16	1		T245	1		T71	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T86	1		T339	1		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	1	1			T240	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	14	1			T298	1		T340	1		T290	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T61	1		T95	1		T333	3
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T4	1		T341	2		T187	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T76	1		T47	1		T36	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T17	1		T342	1		T185	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T304	1		-	-		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T333	3		T343	1		T206	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T5	1		T221	1		T314	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T14	1		T344	1		T345	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T231	1		T333	1		T346	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	4	1			T46	1		T347	1		T323	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T231	1		T117	1		T185	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T18	1		T38	1		T231	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	13	1			T230	2		T105	1		T247	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T46	1		T48	1		T67	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T112	1		T48	1		T230	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T14	1		T17	2		T200	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T206	1		T348	1		T349	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T253	1		T350	1		T335	1
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T282	1		T350	1		T281	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T350	1		T351	1		T352	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T52	1		T97	1		T353	1
auto[7]	auto[StReset]	auto[OpGenId]	9	1			T48	1		T60	1		T202	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T13	1		T6	1		T354	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	13	1			T37	1		T238	1		T48	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T130	1		T303	1		T355	1
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T46	1		T286	1		T356	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	10	1			T357	1		T358	1		T219	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T200	1		T238	1		T359	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T16	1		T85	1		T360	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T46	2		T60	1		T117	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T47	1		T238	1		T361	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T362	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T244	1		T218	1		T363	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T117	1		T290	1		T185	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	13	1			T37	1		T48	1		T364	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T185	1		T218	1		T365	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T28	1		T63	1		T205	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T105	1		T366	1		T309	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T67	1		T106	1		T342	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T46	1		T273	1		T176	1
auto[7]	auto[StDisabled]	auto[OpGenId]	21	1			T231	2		T367	1		T208	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T46	2		T5	2		T60	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T14	1		T18	1		T46	2
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T50	1		T177	1		T368	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T369	1		T370	1		T371	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T97	1		T369	1		T277	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T372	1		T353	1		T283	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T40	1		T372	1		T373	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1330

1

T4

1

T13

2

T14

4

clear_one[1]

auto[0]

auto[0]

auto[0]

437

1

T1

3

T4

1

T16

1

clear_one[1]

auto[0]

auto[0]

auto[1]

123

1

T18

2

T298

1

T67

1

clear_one[1]

auto[0]

auto[1]

auto[0]

110

1

T37

1

T112

1

T124

1

clear_one[1]

auto[0]

auto[1]

auto[1]

27

1

T16

1

T46

2

T47

1

clear_one[2]

auto[0]

auto[0]

auto[0]

384

1

T13

1

T37

2

T49

1

clear_one[2]

auto[0]

auto[0]

auto[1]

116

1

T18

1

T81

2

T84

1

clear_one[2]

auto[1]

auto[0]

auto[0]

122

1

T17

2

T200

2

T50

1

clear_one[2]

auto[1]

auto[0]

auto[1]

44

1

T13

1

T48

2

T230

1

clear_one[3]

auto[0]

auto[0]

auto[0]

404

1

T1

1

T14

2

T17

2

clear_one[3]

auto[0]

auto[1]

auto[0]

133

1

T37

1

T50

1

T124

2

clear_one[3]

auto[1]

auto[0]

auto[0]

135

1

T200

1

T28

1

T70

1

clear_one[3]

auto[1]

auto[1]

auto[0]

44

1

T46

2

T295

1

T306

1

clear_none

auto[0]

auto[0]

auto[0]

1287

1

T1

2

T2

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

105

1

T14

1

T16

2

T84

1

clear_none

auto[0]

auto[1]

auto[0]

133

1

T16

1

T37

1

T124

1

clear_none

auto[0]

auto[1]

auto[1]

22

1

T46

1

T230

1

T105

2

clear_none

auto[1]

auto[0]

auto[0]

124

1

T13

1

T17

1

T200

1

clear_none

auto[1]

auto[0]

auto[1]

22

1

T46

1

T48

1

T67

1

clear_none

auto[1]

auto[1]

auto[0]

38

1

T112

2

T46

2

T295

1

clear_none

auto[1]

auto[1]

auto[1]

28

1

T197

1

T202

1

T230

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1243	1			T4	1		T13	2		T14	4
clear_all	auto[1]	87	1			T112	1		T140	3		T231	5
clear_one[1]	auto[0]	654	1			T1	3		T4	1		T16	2
clear_one[1]	auto[1]	43	1			T139	3		T231	4		T374	1
clear_one[2]	auto[0]	620	1			T13	2		T17	2		T18	1
clear_one[2]	auto[1]	46	1			T273	2		T375	1		T128	1
clear_one[3]	auto[0]	670	1			T1	1		T14	2		T17	2
clear_one[3]	auto[1]	46	1			T375	3		T128	1		T376	4
clear_none	auto[0]	1690	1			T1	2		T2	1		T4	1
clear_none	auto[1]	69	1			T112	6		T231	4		T127	2