Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10681

1

T2

7

T4

9

T12

5

auto[Attestation]

7391

1

T2

4

T4

1

T13

12

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2717	1			T2	1		T4	4		T13	9
auto[Aes]	3283	1			T2	1		T12	2		T13	6
auto[Kmac]	3184	1			T4	3		T12	1		T13	5
auto[Otbn]	3225	1			T2	3		T13	4		T14	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7335	1			T1	1		T2	2		T4	3
auto[OpGenId]	5663	1			T2	6		T4	3		T12	2
auto[OpGenSwOut]	5595	1			T4	2		T12	2		T13	12
auto[OpGenHwOut]	6814	1			T2	5		T4	5		T12	1
auto[OpDisable]	140	1			T4	1		T49	1		T50	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10156

1

T1

1

T2

9

T4

7

auto[OpDoneFail]

15391

1

T2

4

T4

7

T12

4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6334	1			T1	1		T2	1		T4	4
auto[StInit]	3741	1			T2	5		T4	4		T12	5
auto[StCreatorRootKey]	3017	1			T2	7		T4	3		T12	1
auto[StOwnerIntKey]	2644	1			T4	2		T12	2		T13	6
auto[StOwnerKey]	2357	1			T13	4		T14	2		T16	1
auto[StDisabled]	7454	1			T4	1		T13	11		T14	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	325	1			T13	3		T79	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T49	1		T24	1		T112	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T79	1		T28	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T49	1		T50	2		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T48	1		T193	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	183	1			T80	1		T81	1		T84	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	289	1			T13	1		T16	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	94	1			T12	1		T49	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	74	1			T79	1		T46	1		T125	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	69	1			T194	1		T46	1		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T194	1		T112	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	195	1			T79	1		T112	2		T46	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	319	1			T4	2		T13	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	104	1			T12	1		T21	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	70	1			T194	1		T50	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	58	1			T13	1		T80	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	54	1			T46	1		T67	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	177	1			T112	1		T46	4		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	335	1			T49	1		T51	2		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	93	1			T81	1		T24	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	69	1			T50	2		T84	1		T46	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	60	1			T46	3		T196	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	53	1			T46	1		T48	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	205	1			T16	1		T79	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T50	1		T47	2		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	105	1			T50	1		T56	1		T112	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	98	1			T38	1		T46	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T13	1		T46	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	64	1			T49	1		T125	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	223	1			T13	1		T49	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	70	1			T49	1		T48	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	101	1			T13	1		T79	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	87	1			T76	2		T46	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	60	1			T47	1		T48	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	51	1			T84	1		T112	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	227	1			T79	1		T194	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	65	1			T50	1		T46	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	101	1			T50	1		T48	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T13	1		T38	1		T21	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T16	1		T84	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	64	1			T46	2		T5	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	211	1			T79	1		T194	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T49	1		T46	2		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	98	1			T21	2		T70	2		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	68	1			T84	1		T46	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T13	1		T50	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	63	1			T38	1		T46	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	214	1			T13	1		T79	1		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	308	1			T13	1		T16	2		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	96	1			T4	2		T13	1		T50	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	82	1			T2	1		T198	1		T48	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T4	1		T46	2		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	53	1			T80	1		T84	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	146	1			T80	1		T49	1		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	479	1			T17	6		T79	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	126	1			T17	1		T79	2		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T2	1		T17	1		T28	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	96	1			T12	1		T200	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	93	1			T200	1		T78	1		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	262	1			T13	1		T17	2		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	457	1			T13	1		T37	8		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	113	1			T16	1		T50	1		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T37	1		T81	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T201	2		T48	3		T193	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	72	1			T38	1		T79	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	288	1			T4	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	486	1			T13	1		T18	11		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	104	1			T2	1		T14	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T2	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	87	1			T18	1		T46	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	81	1			T14	1		T18	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	250	1			T14	1		T16	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T49	2		T46	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T4	1		T21	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	76	1			T16	1		T49	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T13	1		T50	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	44	1			T46	1		T48	1		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	181	1			T13	1		T16	1		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	40	1			T49	1		T47	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	121	1			T49	1		T200	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	112	1			T13	1		T58	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	87	1			T13	1		T17	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	99	1			T17	1		T38	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	284	1			T13	1		T17	2		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	47	1			T50	1		T47	2		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	120	1			T16	1		T37	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T76	1		T46	1		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T16	1		T37	1		T49	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	97	1			T37	1		T112	1		T46	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	243	1			T37	1		T50	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	63	1			T50	2		T46	2		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	114	1			T18	1		T21	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T2	1		T18	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T14	1		T46	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	82	1			T13	1		T38	2		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	258	1			T14	3		T18	2		T80	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	201	1			T79	1		T49	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	623	1			T13	3		T79	1		T80	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	183	1			T79	1		T194	2		T112	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	600	1			T12	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T13	1		T80	1		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	607	1			T4	2		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	170	1			T50	2		T84	1		T46	7
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	645	1			T16	1		T79	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	200	1			T13	1		T38	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	415	1			T13	1		T49	1		T50	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	180	1			T76	2		T84	1		T112	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	416	1			T13	1		T79	2		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	188	1			T13	1		T16	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	394	1			T79	1		T194	1		T50	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	211	1			T13	1		T38	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	387	1			T13	1		T79	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	187	1			T2	1		T4	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	566	1			T4	2		T13	2		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	283	1			T2	1		T12	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	878	1			T13	1		T17	9		T79	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	246	1			T37	1		T38	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	865	1			T4	1		T13	2		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	250	1			T2	1		T14	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	858	1			T2	1		T13	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	164	1			T13	1		T16	1		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	361	1			T4	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	278	1			T13	2		T17	2		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	465	1			T13	1		T17	2		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	288	1			T16	1		T37	2		T49	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	421	1			T16	1		T37	2		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	261	1			T2	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	443	1			T14	3		T18	3		T80	1