Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31217

1

T1

30

T2

14

T3

1

auto[1]

269

1

T112

10

T139

3

T140

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31228	1			T1	30		T2	14		T3	1
auto[134217728:268435455]	11	1			T140	1		T231	1		T376	1
auto[268435456:402653183]	9	1			T231	1		T376	1		T333	1
auto[402653184:536870911]	6	1			T248	1		T271	1		T401	1
auto[536870912:671088639]	9	1			T112	1		T222	1		T402	1
auto[671088640:805306367]	10	1			T112	2		T231	1		T341	1
auto[805306368:939524095]	9	1			T112	1		T140	1		T341	1
auto[939524096:1073741823]	9	1			T112	1		T275	1		T333	1
auto[1073741824:1207959551]	11	1			T231	1		T375	1		T275	1
auto[1207959552:1342177279]	8	1			T112	1		T139	1		T275	1
auto[1342177280:1476395007]	9	1			T273	1		T275	1		T341	1
auto[1476395008:1610612735]	8	1			T231	1		T127	1		T375	1
auto[1610612736:1744830463]	5	1			T341	1		T403	1		T226	1
auto[1744830464:1879048191]	8	1			T112	1		T341	1		T225	1
auto[1879048192:2013265919]	9	1			T231	2		T375	1		T404	1
auto[2013265920:2147483647]	5	1			T127	1		T384	1		T222	1
auto[2147483648:2281701375]	8	1			T231	1		T127	1		T375	1
auto[2281701376:2415919103]	7	1			T231	1		T333	1		T267	1
auto[2415919104:2550136831]	7	1			T376	1		T341	1		T404	1
auto[2550136832:2684354559]	6	1			T231	1		T273	1		T375	1
auto[2684354560:2818572287]	9	1			T273	1		T129	2		T267	1
auto[2818572288:2952790015]	8	1			T341	1		T221	1		T267	2
auto[2952790016:3087007743]	10	1			T112	2		T376	1		T333	2
auto[3087007744:3221225471]	7	1			T112	1		T140	1		T247	1
auto[3221225472:3355443199]	8	1			T231	1		T374	1		T375	1
auto[3355443200:3489660927]	12	1			T333	1		T266	1		T384	1
auto[3489660928:3623878655]	9	1			T375	2		T376	1		T129	1
auto[3623878656:3758096383]	7	1			T231	2		T129	1		T333	1
auto[3758096384:3892314111]	6	1			T139	2		T231	2		T401	1
auto[3892314112:4026531839]	12	1			T231	1		T341	2		T221	1
auto[4026531840:4160749567]	10	1			T375	2		T221	1		T346	1
auto[4160749568:4294967295]	6	1			T275	1		T222	1		T248	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31217	1			T1	30		T2	14		T3	1
auto[0:134217727]	auto[1]	11	1			T275	2		T341	2		T346	1
auto[134217728:268435455]	auto[1]	11	1			T140	1		T231	1		T376	1
auto[268435456:402653183]	auto[1]	9	1			T231	1		T376	1		T333	1
auto[402653184:536870911]	auto[1]	6	1			T248	1		T271	1		T401	1
auto[536870912:671088639]	auto[1]	9	1			T112	1		T222	1		T402	1
auto[671088640:805306367]	auto[1]	10	1			T112	2		T231	1		T341	1
auto[805306368:939524095]	auto[1]	9	1			T112	1		T140	1		T341	1
auto[939524096:1073741823]	auto[1]	9	1			T112	1		T275	1		T333	1
auto[1073741824:1207959551]	auto[1]	11	1			T231	1		T375	1		T275	1
auto[1207959552:1342177279]	auto[1]	8	1			T112	1		T139	1		T275	1
auto[1342177280:1476395007]	auto[1]	9	1			T273	1		T275	1		T341	1
auto[1476395008:1610612735]	auto[1]	8	1			T231	1		T127	1		T375	1
auto[1610612736:1744830463]	auto[1]	5	1			T341	1		T403	1		T226	1
auto[1744830464:1879048191]	auto[1]	8	1			T112	1		T341	1		T225	1
auto[1879048192:2013265919]	auto[1]	9	1			T231	2		T375	1		T404	1
auto[2013265920:2147483647]	auto[1]	5	1			T127	1		T384	1		T222	1
auto[2147483648:2281701375]	auto[1]	8	1			T231	1		T127	1		T375	1
auto[2281701376:2415919103]	auto[1]	7	1			T231	1		T333	1		T267	1
auto[2415919104:2550136831]	auto[1]	7	1			T376	1		T341	1		T404	1
auto[2550136832:2684354559]	auto[1]	6	1			T231	1		T273	1		T375	1
auto[2684354560:2818572287]	auto[1]	9	1			T273	1		T129	2		T267	1
auto[2818572288:2952790015]	auto[1]	8	1			T341	1		T221	1		T267	2
auto[2952790016:3087007743]	auto[1]	10	1			T112	2		T376	1		T333	2
auto[3087007744:3221225471]	auto[1]	7	1			T112	1		T140	1		T247	1
auto[3221225472:3355443199]	auto[1]	8	1			T231	1		T374	1		T375	1
auto[3355443200:3489660927]	auto[1]	12	1			T333	1		T266	1		T384	1
auto[3489660928:3623878655]	auto[1]	9	1			T375	2		T376	1		T129	1
auto[3623878656:3758096383]	auto[1]	7	1			T231	2		T129	1		T333	1
auto[3758096384:3892314111]	auto[1]	6	1			T139	2		T231	2		T401	1
auto[3892314112:4026531839]	auto[1]	12	1			T231	1		T341	2		T221	1
auto[4026531840:4160749567]	auto[1]	10	1			T375	2		T221	1		T346	1
auto[4160749568:4294967295]	auto[1]	6	1			T275	1		T222	1		T248	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1552

1

T2

2

T13

3

T38

2

auto[1]

1746

1

T1

5

T3

1

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T38	1		T51	2		T125	1
auto[134217728:268435455]	126	1			T79	2		T49	1		T28	1
auto[268435456:402653183]	110	1			T16	1		T58	1		T51	1
auto[402653184:536870911]	114	1			T13	1		T80	1		T51	1
auto[536870912:671088639]	103	1			T16	1		T70	1		T192	1
auto[671088640:805306367]	98	1			T4	1		T13	1		T58	1
auto[805306368:939524095]	104	1			T1	1		T79	1		T80	1
auto[939524096:1073741823]	102	1			T13	1		T80	2		T46	2
auto[1073741824:1207959551]	98	1			T49	1		T46	1		T96	1
auto[1207959552:1342177279]	96	1			T38	1		T57	1		T46	2
auto[1342177280:1476395007]	115	1			T1	1		T21	1		T51	1
auto[1476395008:1610612735]	103	1			T13	1		T16	1		T5	4
auto[1610612736:1744830463]	115	1			T12	1		T112	1		T46	1
auto[1744830464:1879048191]	108	1			T1	1		T84	2		T46	1
auto[1879048192:2013265919]	90	1			T13	1		T80	1		T49	1
auto[2013265920:2147483647]	93	1			T51	1		T24	1		T46	1
auto[2147483648:2281701375]	107	1			T80	1		T192	1		T46	1
auto[2281701376:2415919103]	86	1			T58	2		T49	1		T47	1
auto[2415919104:2550136831]	119	1			T49	1		T24	2		T192	1
auto[2550136832:2684354559]	93	1			T21	1		T28	1		T112	1
auto[2684354560:2818572287]	101	1			T84	1		T47	2		T96	1
auto[2818572288:2952790015]	95	1			T21	1		T51	1		T50	1
auto[2952790016:3087007743]	111	1			T21	1		T84	1		T201	1
auto[3087007744:3221225471]	117	1			T3	1		T13	1		T58	1
auto[3221225472:3355443199]	96	1			T79	1		T46	3		T47	1
auto[3355443200:3489660927]	104	1			T79	1		T80	1		T49	1
auto[3489660928:3623878655]	110	1			T1	1		T49	1		T46	2
auto[3623878656:3758096383]	95	1			T16	1		T58	1		T49	1
auto[3758096384:3892314111]	85	1			T2	1		T24	1		T40	1
auto[3892314112:4026531839]	90	1			T58	1		T50	1		T40	1
auto[4026531840:4160749567]	97	1			T1	1		T13	1		T80	1
auto[4160749568:4294967295]	122	1			T2	1		T50	1		T57	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T38	1		T51	1		T60	1
auto[0:134217727]	auto[1]	55	1			T51	1		T125	1		T295	1
auto[134217728:268435455]	auto[0]	56	1			T49	1		T57	1		T112	1
auto[134217728:268435455]	auto[1]	70	1			T79	2		T28	1		T56	1
auto[268435456:402653183]	auto[0]	46	1			T58	1		T46	2		T47	1
auto[268435456:402653183]	auto[1]	64	1			T16	1		T51	1		T46	2
auto[402653184:536870911]	auto[0]	56	1			T80	1		T46	3		T5	1
auto[402653184:536870911]	auto[1]	58	1			T13	1		T51	1		T46	1
auto[536870912:671088639]	auto[0]	43	1			T192	1		T199	2		T48	1
auto[536870912:671088639]	auto[1]	60	1			T16	1		T70	1		T196	1
auto[671088640:805306367]	auto[0]	49	1			T13	1		T58	1		T48	1
auto[671088640:805306367]	auto[1]	49	1			T4	1		T47	1		T193	1
auto[805306368:939524095]	auto[0]	44	1			T46	1		T47	1		T48	1
auto[805306368:939524095]	auto[1]	60	1			T1	1		T79	1		T80	1
auto[939524096:1073741823]	auto[0]	48	1			T80	1		T46	2		T42	1
auto[939524096:1073741823]	auto[1]	54	1			T13	1		T80	1		T47	1
auto[1073741824:1207959551]	auto[0]	48	1			T49	1		T69	1		T67	1
auto[1073741824:1207959551]	auto[1]	50	1			T46	1		T96	1		T193	1
auto[1207959552:1342177279]	auto[0]	47	1			T38	1		T57	1		T47	1
auto[1207959552:1342177279]	auto[1]	49	1			T46	2		T47	1		T139	1
auto[1342177280:1476395007]	auto[0]	52	1			T46	1		T96	1		T69	2
auto[1342177280:1476395007]	auto[1]	63	1			T1	1		T21	1		T51	1
auto[1476395008:1610612735]	auto[0]	40	1			T13	1		T60	1		T105	1
auto[1476395008:1610612735]	auto[1]	63	1			T16	1		T5	4		T268	2
auto[1610612736:1744830463]	auto[0]	54	1			T52	1		T140	1		T97	1
auto[1610612736:1744830463]	auto[1]	61	1			T12	1		T112	1		T46	1
auto[1744830464:1879048191]	auto[0]	51	1			T84	1		T67	1		T236	1
auto[1744830464:1879048191]	auto[1]	57	1			T1	1		T84	1		T46	1
auto[1879048192:2013265919]	auto[0]	41	1			T80	1		T40	1		T199	1
auto[1879048192:2013265919]	auto[1]	49	1			T13	1		T49	1		T50	1
auto[2013265920:2147483647]	auto[0]	52	1			T51	1		T46	1		T48	1
auto[2013265920:2147483647]	auto[1]	41	1			T24	1		T199	1		T48	1
auto[2147483648:2281701375]	auto[0]	52	1			T80	1		T192	1		T5	1
auto[2147483648:2281701375]	auto[1]	55	1			T46	1		T125	1		T30	1
auto[2281701376:2415919103]	auto[0]	29	1			T49	1		T237	1		T105	2
auto[2281701376:2415919103]	auto[1]	57	1			T58	2		T47	1		T199	1
auto[2415919104:2550136831]	auto[0]	58	1			T49	1		T24	2		T46	1
auto[2415919104:2550136831]	auto[1]	61	1			T192	1		T46	3		T199	1
auto[2550136832:2684354559]	auto[0]	45	1			T46	2		T392	1		T318	1
auto[2550136832:2684354559]	auto[1]	48	1			T21	1		T28	1		T112	1
auto[2684354560:2818572287]	auto[0]	46	1			T84	1		T47	1		T96	1
auto[2684354560:2818572287]	auto[1]	55	1			T47	1		T196	1		T5	1
auto[2818572288:2952790015]	auto[0]	44	1			T51	1		T40	1		T69	1
auto[2818572288:2952790015]	auto[1]	51	1			T21	1		T50	1		T46	2
auto[2952790016:3087007743]	auto[0]	57	1			T140	1		T230	1		T398	1
auto[2952790016:3087007743]	auto[1]	54	1			T21	1		T84	1		T201	1
auto[3087007744:3221225471]	auto[0]	60	1			T49	1		T19	1		T196	1
auto[3087007744:3221225471]	auto[1]	57	1			T3	1		T13	1		T58	1
auto[3221225472:3355443199]	auto[0]	55	1			T46	2		T5	2		T392	1
auto[3221225472:3355443199]	auto[1]	41	1			T79	1		T46	1		T47	1
auto[3355443200:3489660927]	auto[0]	59	1			T80	1		T49	1		T51	1
auto[3355443200:3489660927]	auto[1]	45	1			T79	1		T46	1		T48	1
auto[3489660928:3623878655]	auto[0]	48	1			T49	1		T236	1		T60	1
auto[3489660928:3623878655]	auto[1]	62	1			T1	1		T46	2		T47	1
auto[3623878656:3758096383]	auto[0]	45	1			T58	1		T46	1		T47	1
auto[3623878656:3758096383]	auto[1]	50	1			T16	1		T49	1		T51	1
auto[3758096384:3892314111]	auto[0]	40	1			T2	1		T237	1		T306	1
auto[3758096384:3892314111]	auto[1]	45	1			T24	1		T40	1		T48	2
auto[3892314112:4026531839]	auto[0]	39	1			T50	1		T31	1		T5	1
auto[3892314112:4026531839]	auto[1]	51	1			T58	1		T40	1		T112	1
auto[4026531840:4160749567]	auto[0]	52	1			T13	1		T50	1		T46	1
auto[4026531840:4160749567]	auto[1]	45	1			T1	1		T80	1		T48	2
auto[4160749568:4294967295]	auto[0]	56	1			T2	1		T192	1		T67	1
auto[4160749568:4294967295]	auto[1]	66	1			T50	1		T57	1		T46	4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1564

1

T2

2

T4

1

T13

3

auto[1]

1734

1

T1

5

T3

1

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T47	2		T196	1		T48	1
auto[134217728:268435455]	108	1			T12	1		T13	1		T49	1
auto[268435456:402653183]	108	1			T80	2		T58	1		T49	1
auto[402653184:536870911]	103	1			T84	1		T46	3		T47	1
auto[536870912:671088639]	118	1			T1	1		T24	1		T84	1
auto[671088640:805306367]	96	1			T13	1		T50	1		T192	1
auto[805306368:939524095]	107	1			T46	2		T60	2		T104	1
auto[939524096:1073741823]	111	1			T125	1		T96	1		T48	1
auto[1073741824:1207959551]	101	1			T16	1		T79	1		T80	1
auto[1207959552:1342177279]	99	1			T58	1		T46	1		T69	1
auto[1342177280:1476395007]	96	1			T21	1		T51	1		T46	2
auto[1476395008:1610612735]	110	1			T58	1		T57	1		T192	1
auto[1610612736:1744830463]	87	1			T46	2		T48	4		T193	1
auto[1744830464:1879048191]	96	1			T1	1		T21	1		T24	1
auto[1879048192:2013265919]	107	1			T2	1		T80	1		T49	1
auto[2013265920:2147483647]	95	1			T1	1		T38	1		T79	1
auto[2147483648:2281701375]	111	1			T79	1		T80	1		T24	1
auto[2281701376:2415919103]	102	1			T3	1		T13	1		T16	1
auto[2415919104:2550136831]	99	1			T16	1		T38	1		T79	1
auto[2550136832:2684354559]	101	1			T13	1		T51	1		T19	1
auto[2684354560:2818572287]	98	1			T80	1		T49	1		T21	1
auto[2818572288:2952790015]	107	1			T1	1		T51	1		T46	1
auto[2952790016:3087007743]	111	1			T13	1		T80	1		T49	1
auto[3087007744:3221225471]	96	1			T50	1		T70	1		T46	2
auto[3221225472:3355443199]	124	1			T58	1		T46	1		T42	1
auto[3355443200:3489660927]	93	1			T1	1		T49	1		T77	1
auto[3489660928:3623878655]	88	1			T50	1		T96	1		T199	1
auto[3623878656:3758096383]	107	1			T2	1		T4	1		T79	1
auto[3758096384:3892314111]	89	1			T51	1		T46	1		T125	1
auto[3892314112:4026531839]	105	1			T13	1		T50	1		T46	1
auto[4026531840:4160749567]	113	1			T16	1		T58	1		T24	1
auto[4160749568:4294967295]	109	1			T13	1		T51	1		T24	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T196	1		T5	2		T236	2
auto[0:134217727]	auto[1]	60	1			T47	2		T48	1		T5	1
auto[134217728:268435455]	auto[0]	53	1			T13	1		T49	1		T40	1
auto[134217728:268435455]	auto[1]	55	1			T12	1		T112	1		T46	1
auto[268435456:402653183]	auto[0]	47	1			T51	1		T46	2		T60	1
auto[268435456:402653183]	auto[1]	61	1			T80	2		T58	1		T49	1
auto[402653184:536870911]	auto[0]	46	1			T47	1		T52	1		T69	2
auto[402653184:536870911]	auto[1]	57	1			T84	1		T46	3		T48	2
auto[536870912:671088639]	auto[0]	62	1			T24	1		T84	1		T48	1
auto[536870912:671088639]	auto[1]	56	1			T1	1		T47	1		T69	1
auto[671088640:805306367]	auto[0]	51	1			T192	1		T19	1		T46	1
auto[671088640:805306367]	auto[1]	45	1			T13	1		T50	1		T46	1
auto[805306368:939524095]	auto[0]	44	1			T104	1		T367	1		T63	3
auto[805306368:939524095]	auto[1]	63	1			T46	2		T60	2		T105	3
auto[939524096:1073741823]	auto[0]	58	1			T125	1		T140	1		T331	1
auto[939524096:1073741823]	auto[1]	53	1			T96	1		T48	1		T139	1
auto[1073741824:1207959551]	auto[0]	46	1			T80	1		T58	1		T49	1
auto[1073741824:1207959551]	auto[1]	55	1			T16	1		T79	1		T76	1
auto[1207959552:1342177279]	auto[0]	51	1			T236	1		T103	1		T286	1
auto[1207959552:1342177279]	auto[1]	48	1			T58	1		T46	1		T69	1
auto[1342177280:1476395007]	auto[0]	47	1			T51	1		T46	2		T199	2
auto[1342177280:1476395007]	auto[1]	49	1			T21	1		T199	1		T31	1
auto[1476395008:1610612735]	auto[0]	54	1			T192	1		T46	1		T47	1
auto[1476395008:1610612735]	auto[1]	56	1			T58	1		T57	1		T48	2
auto[1610612736:1744830463]	auto[0]	37	1			T48	1		T5	1		T230	1
auto[1610612736:1744830463]	auto[1]	50	1			T46	2		T48	3		T193	1
auto[1744830464:1879048191]	auto[0]	45	1			T48	1		T197	1		T255	1
auto[1744830464:1879048191]	auto[1]	51	1			T1	1		T21	1		T24	1
auto[1879048192:2013265919]	auto[0]	56	1			T2	1		T51	1		T47	2
auto[1879048192:2013265919]	auto[1]	51	1			T80	1		T49	1		T56	1
auto[2013265920:2147483647]	auto[0]	48	1			T38	1		T80	1		T5	2
auto[2013265920:2147483647]	auto[1]	47	1			T1	1		T79	1		T112	1
auto[2147483648:2281701375]	auto[0]	61	1			T80	1		T24	1		T47	1
auto[2147483648:2281701375]	auto[1]	50	1			T79	1		T192	1		T125	1
auto[2281701376:2415919103]	auto[0]	49	1			T49	2		T57	1		T60	1
auto[2281701376:2415919103]	auto[1]	53	1			T3	1		T13	1		T16	1
auto[2415919104:2550136831]	auto[0]	53	1			T51	1		T199	1		T398	1
auto[2415919104:2550136831]	auto[1]	46	1			T16	1		T38	1		T79	1
auto[2550136832:2684354559]	auto[0]	46	1			T51	1		T19	1		T140	1
auto[2550136832:2684354559]	auto[1]	55	1			T13	1		T47	1		T5	1
auto[2684354560:2818572287]	auto[0]	42	1			T80	1		T46	1		T237	1
auto[2684354560:2818572287]	auto[1]	56	1			T49	1		T21	1		T51	1
auto[2818572288:2952790015]	auto[0]	55	1			T46	1		T199	1		T67	1
auto[2818572288:2952790015]	auto[1]	52	1			T1	1		T51	1		T201	1
auto[2952790016:3087007743]	auto[0]	48	1			T80	1		T84	1		T46	1
auto[2952790016:3087007743]	auto[1]	63	1			T13	1		T49	1		T50	1
auto[3087007744:3221225471]	auto[0]	46	1			T48	3		T5	2		T274	1
auto[3087007744:3221225471]	auto[1]	50	1			T50	1		T70	1		T46	2
auto[3221225472:3355443199]	auto[0]	51	1			T58	1		T42	1		T48	1
auto[3221225472:3355443199]	auto[1]	73	1			T46	1		T69	1		T5	1
auto[3355443200:3489660927]	auto[0]	44	1			T49	1		T77	1		T112	1
auto[3355443200:3489660927]	auto[1]	49	1			T1	1		T48	3		T197	1
auto[3489660928:3623878655]	auto[0]	38	1			T60	1		T268	1		T105	1
auto[3489660928:3623878655]	auto[1]	50	1			T50	1		T96	1		T199	1
auto[3623878656:3758096383]	auto[0]	55	1			T2	1		T4	1		T46	1
auto[3623878656:3758096383]	auto[1]	52	1			T79	1		T21	1		T40	1
auto[3758096384:3892314111]	auto[0]	40	1			T125	1		T48	2		T268	1
auto[3758096384:3892314111]	auto[1]	49	1			T51	1		T46	1		T196	1
auto[3892314112:4026531839]	auto[0]	43	1			T13	1		T50	1		T31	1
auto[3892314112:4026531839]	auto[1]	62	1			T46	1		T30	1		T48	1
auto[4026531840:4160749567]	auto[0]	57	1			T58	1		T40	1		T192	1
auto[4026531840:4160749567]	auto[1]	56	1			T16	1		T24	1		T46	3
auto[4160749568:4294967295]	auto[0]	48	1			T13	1		T24	1		T46	1
auto[4160749568:4294967295]	auto[1]	61	1			T51	1		T84	1		T47	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1575

1

T2

2

T4

1

T13

4

auto[1]

1723

1

T1

5

T3

1

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T13	1		T21	1		T51	1
auto[134217728:268435455]	89	1			T3	1		T80	1		T49	1
auto[268435456:402653183]	109	1			T80	2		T51	1		T50	2
auto[402653184:536870911]	109	1			T79	2		T21	1		T112	1
auto[536870912:671088639]	97	1			T13	1		T80	1		T51	1
auto[671088640:805306367]	92	1			T12	1		T49	1		T40	1
auto[805306368:939524095]	110	1			T16	1		T80	1		T46	3
auto[939524096:1073741823]	91	1			T16	1		T192	1		T96	1
auto[1073741824:1207959551]	90	1			T1	1		T13	1		T46	1
auto[1207959552:1342177279]	97	1			T58	1		T49	1		T192	2
auto[1342177280:1476395007]	122	1			T1	1		T2	1		T16	1
auto[1476395008:1610612735]	97	1			T58	1		T28	1		T57	1
auto[1610612736:1744830463]	104	1			T13	1		T51	1		T46	1
auto[1744830464:1879048191]	102	1			T58	1		T76	1		T84	1
auto[1879048192:2013265919]	95	1			T58	1		T112	1		T46	1
auto[2013265920:2147483647]	103	1			T21	1		T50	1		T19	1
auto[2147483648:2281701375]	120	1			T38	1		T49	2		T50	1
auto[2281701376:2415919103]	113	1			T79	1		T40	1		T46	2
auto[2415919104:2550136831]	85	1			T49	1		T46	1		T48	1
auto[2550136832:2684354559]	104	1			T1	1		T13	3		T16	1
auto[2684354560:2818572287]	102	1			T46	2		T47	2		T31	1
auto[2818572288:2952790015]	93	1			T38	1		T56	1		T84	1
auto[2952790016:3087007743]	118	1			T80	1		T51	1		T24	1
auto[3087007744:3221225471]	117	1			T1	1		T2	1		T46	1
auto[3221225472:3355443199]	89	1			T49	1		T46	2		T199	1
auto[3355443200:3489660927]	92	1			T1	1		T79	1		T58	2
auto[3489660928:3623878655]	122	1			T80	1		T58	1		T46	1
auto[3623878656:3758096383]	107	1			T79	1		T80	1		T49	1
auto[3758096384:3892314111]	109	1			T46	1		T47	1		T196	1
auto[3892314112:4026531839]	101	1			T4	1		T21	1		T51	2
auto[4026531840:4160749567]	91	1			T51	1		T24	1		T57	1
auto[4160749568:4294967295]	113	1			T24	1		T46	2		T47	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T51	1		T5	1		T97	1
auto[0:134217727]	auto[1]	60	1			T13	1		T21	1		T50	1
auto[134217728:268435455]	auto[0]	41	1			T49	1		T47	1		T5	1
auto[134217728:268435455]	auto[1]	48	1			T3	1		T80	1		T21	1
auto[268435456:402653183]	auto[0]	52	1			T80	2		T51	1		T40	1
auto[268435456:402653183]	auto[1]	57	1			T50	2		T46	2		T199	1
auto[402653184:536870911]	auto[0]	48	1			T46	1		T48	1		T236	1
auto[402653184:536870911]	auto[1]	61	1			T79	2		T21	1		T112	1
auto[536870912:671088639]	auto[0]	44	1			T13	1		T80	1		T77	1
auto[536870912:671088639]	auto[1]	53	1			T51	1		T193	1		T5	2
auto[671088640:805306367]	auto[0]	42	1			T48	1		T67	1		T97	1
auto[671088640:805306367]	auto[1]	50	1			T12	1		T49	1		T40	1
auto[805306368:939524095]	auto[0]	48	1			T80	1		T46	3		T48	2
auto[805306368:939524095]	auto[1]	62	1			T16	1		T96	1		T48	1
auto[939524096:1073741823]	auto[0]	37	1			T192	1		T61	1		T274	1
auto[939524096:1073741823]	auto[1]	54	1			T16	1		T96	1		T48	1
auto[1073741824:1207959551]	auto[0]	44	1			T13	1		T47	1		T69	1
auto[1073741824:1207959551]	auto[1]	46	1			T1	1		T46	1		T125	1
auto[1207959552:1342177279]	auto[0]	49	1			T58	1		T49	1		T192	2
auto[1207959552:1342177279]	auto[1]	48	1			T112	1		T199	1		T193	1
auto[1342177280:1476395007]	auto[0]	52	1			T2	1		T46	1		T196	1
auto[1342177280:1476395007]	auto[1]	70	1			T1	1		T16	1		T46	2
auto[1476395008:1610612735]	auto[0]	48	1			T28	1		T46	1		T52	1
auto[1476395008:1610612735]	auto[1]	49	1			T58	1		T57	1		T47	1
auto[1610612736:1744830463]	auto[0]	58	1			T13	1		T51	1		T47	1
auto[1610612736:1744830463]	auto[1]	46	1			T46	1		T47	1		T48	1
auto[1744830464:1879048191]	auto[0]	45	1			T58	1		T84	1		T193	1
auto[1744830464:1879048191]	auto[1]	57	1			T76	1		T48	1		T139	2
auto[1879048192:2013265919]	auto[0]	49	1			T58	1		T46	1		T5	1
auto[1879048192:2013265919]	auto[1]	46	1			T112	1		T47	1		T199	1
auto[2013265920:2147483647]	auto[0]	53	1			T50	1		T19	1		T46	2
auto[2013265920:2147483647]	auto[1]	50	1			T21	1		T46	1		T96	1
auto[2147483648:2281701375]	auto[0]	58	1			T49	1		T52	1		T140	1
auto[2147483648:2281701375]	auto[1]	62	1			T38	1		T49	1		T50	1
auto[2281701376:2415919103]	auto[0]	50	1			T40	1		T46	1		T48	1
auto[2281701376:2415919103]	auto[1]	63	1			T79	1		T46	1		T196	1
auto[2415919104:2550136831]	auto[0]	46	1			T49	1		T46	1		T48	1
auto[2415919104:2550136831]	auto[1]	39	1			T69	1		T67	1		T331	1
auto[2550136832:2684354559]	auto[0]	46	1			T13	1		T51	1		T57	1
auto[2550136832:2684354559]	auto[1]	58	1			T1	1		T13	2		T16	1
auto[2684354560:2818572287]	auto[0]	51	1			T46	1		T47	2		T31	1
auto[2684354560:2818572287]	auto[1]	51	1			T46	1		T139	1		T5	1
auto[2818572288:2952790015]	auto[0]	45	1			T38	1		T84	1		T48	1
auto[2818572288:2952790015]	auto[1]	48	1			T56	1		T46	3		T69	1
auto[2952790016:3087007743]	auto[0]	55	1			T80	1		T24	1		T199	1
auto[2952790016:3087007743]	auto[1]	63	1			T51	1		T48	1		T5	2
auto[3087007744:3221225471]	auto[0]	61	1			T2	1		T48	2		T5	3
auto[3087007744:3221225471]	auto[1]	56	1			T1	1		T46	1		T199	1
auto[3221225472:3355443199]	auto[0]	41	1			T49	1		T199	1		T105	1
auto[3221225472:3355443199]	auto[1]	48	1			T46	2		T193	1		T231	1
auto[3355443200:3489660927]	auto[0]	49	1			T79	1		T58	1		T24	1
auto[3355443200:3489660927]	auto[1]	43	1			T1	1		T58	1		T24	1
auto[3489660928:3623878655]	auto[0]	57	1			T46	1		T69	1		T5	1
auto[3489660928:3623878655]	auto[1]	65	1			T80	1		T58	1		T30	1
auto[3623878656:3758096383]	auto[0]	44	1			T49	1		T52	1		T5	2
auto[3623878656:3758096383]	auto[1]	63	1			T79	1		T80	1		T40	1
auto[3758096384:3892314111]	auto[0]	54	1			T46	1		T196	1		T60	1
auto[3758096384:3892314111]	auto[1]	55	1			T47	1		T48	1		T5	2
auto[3892314112:4026531839]	auto[0]	43	1			T4	1		T51	1		T46	1
auto[3892314112:4026531839]	auto[1]	58	1			T21	1		T51	1		T70	1
auto[4026531840:4160749567]	auto[0]	53	1			T46	2		T199	1		T69	1
auto[4026531840:4160749567]	auto[1]	38	1			T51	1		T24	1		T57	1
auto[4160749568:4294967295]	auto[0]	57	1			T46	1		T67	1		T398	1
auto[4160749568:4294967295]	auto[1]	56	1			T24	1		T46	1		T47	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1533

1

T2

1

T4

1

T13

3

auto[1]

1765

1

T1

5

T2

1

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T16	1		T49	1		T51	1
auto[134217728:268435455]	100	1			T1	1		T49	1		T24	1
auto[268435456:402653183]	97	1			T13	2		T24	1		T40	1
auto[402653184:536870911]	118	1			T13	1		T21	1		T51	1
auto[536870912:671088639]	101	1			T80	1		T49	1		T47	1
auto[671088640:805306367]	108	1			T19	1		T96	1		T48	3
auto[805306368:939524095]	106	1			T51	1		T112	1		T46	2
auto[939524096:1073741823]	107	1			T13	1		T58	3		T49	1
auto[1073741824:1207959551]	97	1			T112	1		T46	2		T199	1
auto[1207959552:1342177279]	119	1			T13	1		T79	1		T80	1
auto[1342177280:1476395007]	113	1			T79	1		T80	1		T51	1
auto[1476395008:1610612735]	100	1			T3	1		T46	2		T5	1
auto[1610612736:1744830463]	115	1			T79	1		T80	1		T21	1
auto[1744830464:1879048191]	100	1			T2	1		T16	1		T21	1
auto[1879048192:2013265919]	112	1			T1	1		T58	1		T192	1
auto[2013265920:2147483647]	103	1			T112	1		T46	1		T47	3
auto[2147483648:2281701375]	107	1			T1	1		T38	1		T80	1
auto[2281701376:2415919103]	88	1			T51	1		T77	1		T57	1
auto[2415919104:2550136831]	99	1			T4	1		T79	1		T28	1
auto[2550136832:2684354559]	85	1			T16	1		T46	1		T47	1
auto[2684354560:2818572287]	116	1			T12	1		T58	1		T51	1
auto[2818572288:2952790015]	112	1			T58	1		T46	4		T295	1
auto[2952790016:3087007743]	105	1			T80	1		T28	1		T50	1
auto[3087007744:3221225471]	115	1			T16	1		T79	1		T21	1
auto[3221225472:3355443199]	104	1			T1	1		T49	2		T46	2
auto[3355443200:3489660927]	96	1			T2	1		T13	1		T49	1
auto[3489660928:3623878655]	88	1			T24	1		T46	4		T48	2
auto[3623878656:3758096383]	97	1			T13	1		T51	1		T46	1
auto[3758096384:3892314111]	101	1			T58	1		T49	1		T50	1
auto[3892314112:4026531839]	94	1			T1	1		T80	2		T47	1
auto[4026531840:4160749567]	98	1			T38	1		T49	1		T196	1
auto[4160749568:4294967295]	92	1			T46	1		T196	1		T48	1