Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2920

1

T1

5

T2

2

T4

1

auto[1]

275

1

T112

7

T139

8

T140

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T51	1		T50	1		T112	1
auto[134217728:268435455]	107	1			T46	2		T125	1		T47	2
auto[268435456:402653183]	93	1			T1	2		T80	1		T50	1
auto[402653184:536870911]	88	1			T28	1		T50	1		T40	1
auto[536870912:671088639]	124	1			T13	1		T112	1		T46	1
auto[671088640:805306367]	109	1			T1	1		T112	1		T46	1
auto[805306368:939524095]	95	1			T16	1		T51	1		T192	1
auto[939524096:1073741823]	95	1			T16	1		T49	1		T51	1
auto[1073741824:1207959551]	110	1			T13	1		T84	1		T112	1
auto[1207959552:1342177279]	105	1			T70	1		T24	2		T96	1
auto[1342177280:1476395007]	98	1			T2	1		T80	1		T84	1
auto[1476395008:1610612735]	105	1			T1	1		T16	1		T38	1
auto[1610612736:1744830463]	107	1			T38	1		T80	1		T58	1
auto[1744830464:1879048191]	94	1			T21	1		T50	1		T46	1
auto[1879048192:2013265919]	121	1			T21	1		T46	1		T199	1
auto[2013265920:2147483647]	77	1			T46	1		T199	2		T268	1
auto[2147483648:2281701375]	110	1			T13	1		T19	1		T46	5
auto[2281701376:2415919103]	102	1			T51	1		T112	1		T46	2
auto[2415919104:2550136831]	107	1			T49	1		T46	2		T48	3
auto[2550136832:2684354559]	107	1			T16	1		T79	1		T21	1
auto[2684354560:2818572287]	102	1			T79	1		T80	1		T49	1
auto[2818572288:2952790015]	78	1			T13	2		T46	2		T201	1
auto[2952790016:3087007743]	87	1			T2	1		T192	1		T47	1
auto[3087007744:3221225471]	83	1			T79	1		T21	1		T76	1
auto[3221225472:3355443199]	109	1			T13	1		T21	1		T46	2
auto[3355443200:3489660927]	100	1			T79	1		T49	1		T50	1
auto[3489660928:3623878655]	97	1			T24	1		T192	1		T46	1
auto[3623878656:3758096383]	107	1			T79	1		T49	1		T139	1
auto[3758096384:3892314111]	83	1			T1	1		T12	1		T58	1
auto[3892314112:4026531839]	103	1			T51	2		T46	4		T199	1
auto[4026531840:4160749567]	104	1			T80	1		T51	2		T40	1
auto[4160749568:4294967295]	98	1			T4	1		T80	2		T24	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	79	1			T51	1		T50	1		T46	1
auto[0:134217727]	auto[1]	11	1			T112	1		T375	1		T341	1
auto[134217728:268435455]	auto[0]	102	1			T46	2		T125	1		T47	2
auto[134217728:268435455]	auto[1]	5	1			T273	1		T267	1		T248	1
auto[268435456:402653183]	auto[0]	86	1			T1	2		T80	1		T50	1
auto[268435456:402653183]	auto[1]	7	1			T231	1		T376	1		T267	1
auto[402653184:536870911]	auto[0]	84	1			T28	1		T50	1		T40	1
auto[402653184:536870911]	auto[1]	4	1			T231	1		T266	1		T267	1
auto[536870912:671088639]	auto[0]	117	1			T13	1		T112	1		T46	1
auto[536870912:671088639]	auto[1]	7	1			T375	1		T128	1		T376	1
auto[671088640:805306367]	auto[0]	101	1			T1	1		T46	1		T96	1
auto[671088640:805306367]	auto[1]	8	1			T112	1		T139	1		T273	1
auto[805306368:939524095]	auto[0]	84	1			T16	1		T51	1		T192	1
auto[805306368:939524095]	auto[1]	11	1			T273	1		T129	1		T263	1
auto[939524096:1073741823]	auto[0]	89	1			T16	1		T49	1		T51	1
auto[939524096:1073741823]	auto[1]	6	1			T129	1		T333	1		T404	1
auto[1073741824:1207959551]	auto[0]	100	1			T13	1		T84	1		T112	1
auto[1073741824:1207959551]	auto[1]	10	1			T231	1		T273	1		T129	1
auto[1207959552:1342177279]	auto[0]	98	1			T70	1		T24	2		T96	1
auto[1207959552:1342177279]	auto[1]	7	1			T231	1		T127	1		T129	1
auto[1342177280:1476395007]	auto[0]	89	1			T2	1		T80	1		T84	1
auto[1342177280:1476395007]	auto[1]	9	1			T341	1		T333	1		T266	1
auto[1476395008:1610612735]	auto[0]	97	1			T1	1		T16	1		T38	1
auto[1476395008:1610612735]	auto[1]	8	1			T128	1		T275	1		T248	1
auto[1610612736:1744830463]	auto[0]	99	1			T38	1		T80	1		T58	1
auto[1610612736:1744830463]	auto[1]	8	1			T231	2		T407	1		T333	1
auto[1744830464:1879048191]	auto[0]	84	1			T21	1		T50	1		T46	1
auto[1744830464:1879048191]	auto[1]	10	1			T139	1		T140	1		T266	1
auto[1879048192:2013265919]	auto[0]	107	1			T21	1		T46	1		T199	1
auto[1879048192:2013265919]	auto[1]	14	1			T139	1		T273	1		T375	1
auto[2013265920:2147483647]	auto[0]	71	1			T46	1		T199	2		T268	1
auto[2013265920:2147483647]	auto[1]	6	1			T341	1		T221	2		T262	1
auto[2147483648:2281701375]	auto[0]	103	1			T13	1		T19	1		T46	5
auto[2147483648:2281701375]	auto[1]	7	1			T129	1		T407	2		T221	2
auto[2281701376:2415919103]	auto[0]	89	1			T51	1		T46	2		T52	1
auto[2281701376:2415919103]	auto[1]	13	1			T112	1		T273	1		T127	1
auto[2415919104:2550136831]	auto[0]	99	1			T49	1		T46	2		T48	3
auto[2415919104:2550136831]	auto[1]	8	1			T221	1		T266	3		T267	1
auto[2550136832:2684354559]	auto[0]	95	1			T16	1		T79	1		T21	1
auto[2550136832:2684354559]	auto[1]	12	1			T112	1		T127	2		T375	2
auto[2684354560:2818572287]	auto[0]	93	1			T79	1		T80	1		T49	1
auto[2684354560:2818572287]	auto[1]	9	1			T128	1		T376	2		T341	1
auto[2818572288:2952790015]	auto[0]	71	1			T13	2		T46	2		T201	1
auto[2818572288:2952790015]	auto[1]	7	1			T139	1		T127	1		T333	1
auto[2952790016:3087007743]	auto[0]	76	1			T2	1		T192	1		T47	1
auto[2952790016:3087007743]	auto[1]	11	1			T139	2		T231	1		T273	1
auto[3087007744:3221225471]	auto[0]	78	1			T79	1		T21	1		T76	1
auto[3087007744:3221225471]	auto[1]	5	1			T112	1		T267	1		T384	1
auto[3221225472:3355443199]	auto[0]	99	1			T13	1		T21	1		T46	2
auto[3221225472:3355443199]	auto[1]	10	1			T376	1		T341	2		T384	1
auto[3355443200:3489660927]	auto[0]	93	1			T79	1		T49	1		T50	1
auto[3355443200:3489660927]	auto[1]	7	1			T139	1		T341	1		T404	1
auto[3489660928:3623878655]	auto[0]	90	1			T24	1		T192	1		T46	1
auto[3489660928:3623878655]	auto[1]	7	1			T376	1		T247	1		T333	1
auto[3623878656:3758096383]	auto[0]	99	1			T79	1		T49	1		T139	1
auto[3623878656:3758096383]	auto[1]	8	1			T231	1		T375	1		T275	1
auto[3758096384:3892314111]	auto[0]	77	1			T1	1		T12	1		T58	1
auto[3758096384:3892314111]	auto[1]	6	1			T112	1		T273	1		T247	1
auto[3892314112:4026531839]	auto[0]	90	1			T51	2		T46	4		T199	1
auto[3892314112:4026531839]	auto[1]	13	1			T139	1		T374	3		T275	1
auto[4026531840:4160749567]	auto[0]	95	1			T80	1		T51	2		T40	1
auto[4026531840:4160749567]	auto[1]	9	1			T112	1		T273	2		T267	1
auto[4160749568:4294967295]	auto[0]	86	1			T4	1		T80	2		T24	1
auto[4160749568:4294967295]	auto[1]	12	1			T231	1		T376	1		T275	1