Unified Coverage Report :: Group Instance : sealing_sw_binding_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1573

1

T2

2

T13

4

T38

1

auto[1]

1725

1

T1

5

T3

1

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T13	1		T80	1		T51	1
auto[134217728:268435455]	117	1			T58	1		T49	2		T21	1
auto[268435456:402653183]	104	1			T1	1		T50	1		T56	1
auto[402653184:536870911]	100	1			T51	1		T46	1		T196	1
auto[536870912:671088639]	98	1			T4	1		T16	1		T79	1
auto[671088640:805306367]	114	1			T13	1		T80	2		T24	1
auto[805306368:939524095]	91	1			T1	1		T13	1		T16	1
auto[939524096:1073741823]	103	1			T79	1		T58	1		T48	1
auto[1073741824:1207959551]	88	1			T1	1		T49	1		T40	1
auto[1207959552:1342177279]	104	1			T192	1		T46	4		T96	1
auto[1342177280:1476395007]	105	1			T21	1		T28	1		T57	1
auto[1476395008:1610612735]	105	1			T79	1		T49	1		T21	1
auto[1610612736:1744830463]	101	1			T79	1		T28	1		T19	1
auto[1744830464:1879048191]	113	1			T1	1		T12	1		T13	1
auto[1879048192:2013265919]	101	1			T16	1		T24	1		T19	1
auto[2013265920:2147483647]	110	1			T13	1		T49	2		T51	1
auto[2147483648:2281701375]	121	1			T2	1		T51	1		T46	4
auto[2281701376:2415919103]	120	1			T3	1		T13	2		T49	1
auto[2415919104:2550136831]	109	1			T80	1		T58	2		T49	1
auto[2550136832:2684354559]	106	1			T58	1		T46	1		T47	1
auto[2684354560:2818572287]	81	1			T38	1		T58	1		T112	1
auto[2818572288:2952790015]	109	1			T80	1		T46	2		T47	2
auto[2952790016:3087007743]	106	1			T46	1		T47	1		T96	1
auto[3087007744:3221225471]	101	1			T295	1		T60	1		T230	1
auto[3221225472:3355443199]	100	1			T49	1		T46	3		T47	1
auto[3355443200:3489660927]	97	1			T58	1		T51	1		T112	1
auto[3489660928:3623878655]	118	1			T16	1		T80	1		T50	1
auto[3623878656:3758096383]	102	1			T1	1		T38	1		T47	1
auto[3758096384:3892314111]	90	1			T70	1		T46	1		T47	1
auto[3892314112:4026531839]	102	1			T2	1		T96	1		T199	1
auto[4026531840:4160749567]	88	1			T21	1		T24	1		T46	3
auto[4160749568:4294967295]	83	1			T79	1		T192	1		T46	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T13	1		T77	1		T40	1
auto[0:134217727]	auto[1]	59	1			T80	1		T51	1		T50	1
auto[134217728:268435455]	auto[0]	48	1			T24	1		T84	1		T46	1
auto[134217728:268435455]	auto[1]	69	1			T58	1		T49	2		T21	1
auto[268435456:402653183]	auto[0]	45	1			T196	1		T103	1		T233	1
auto[268435456:402653183]	auto[1]	59	1			T1	1		T50	1		T56	1
auto[402653184:536870911]	auto[0]	42	1			T196	1		T199	1		T48	2
auto[402653184:536870911]	auto[1]	58	1			T51	1		T46	1		T48	2
auto[536870912:671088639]	auto[0]	46	1			T69	1		T255	1		T230	1
auto[536870912:671088639]	auto[1]	52	1			T4	1		T16	1		T79	1
auto[671088640:805306367]	auto[0]	61	1			T13	1		T80	1		T192	1
auto[671088640:805306367]	auto[1]	53	1			T80	1		T24	1		T30	1
auto[805306368:939524095]	auto[0]	46	1			T13	1		T80	1		T84	1
auto[805306368:939524095]	auto[1]	45	1			T1	1		T16	1		T192	1
auto[939524096:1073741823]	auto[0]	56	1			T69	1		T5	2		T32	1
auto[939524096:1073741823]	auto[1]	47	1			T79	1		T58	1		T48	1
auto[1073741824:1207959551]	auto[0]	38	1			T49	1		T40	1		T69	1
auto[1073741824:1207959551]	auto[1]	50	1			T1	1		T112	1		T46	1
auto[1207959552:1342177279]	auto[0]	51	1			T192	1		T46	2		T48	2
auto[1207959552:1342177279]	auto[1]	53	1			T46	2		T96	1		T48	1
auto[1342177280:1476395007]	auto[0]	54	1			T46	2		T47	1		T5	1
auto[1342177280:1476395007]	auto[1]	51	1			T21	1		T28	1		T57	1
auto[1476395008:1610612735]	auto[0]	50	1			T46	2		T199	1		T52	1
auto[1476395008:1610612735]	auto[1]	55	1			T79	1		T49	1		T21	1
auto[1610612736:1744830463]	auto[0]	47	1			T79	1		T19	1		T46	1
auto[1610612736:1744830463]	auto[1]	54	1			T28	1		T46	1		T47	1
auto[1744830464:1879048191]	auto[0]	45	1			T80	1		T21	1		T51	1
auto[1744830464:1879048191]	auto[1]	68	1			T1	1		T12	1		T13	1
auto[1879048192:2013265919]	auto[0]	38	1			T19	1		T46	2		T125	1
auto[1879048192:2013265919]	auto[1]	63	1			T16	1		T24	1		T84	1
auto[2013265920:2147483647]	auto[0]	58	1			T13	1		T49	2		T51	1
auto[2013265920:2147483647]	auto[1]	52	1			T50	1		T76	1		T197	1
auto[2147483648:2281701375]	auto[0]	65	1			T2	1		T48	1		T69	2
auto[2147483648:2281701375]	auto[1]	56	1			T51	1		T46	4		T5	1
auto[2281701376:2415919103]	auto[0]	58	1			T49	1		T46	1		T48	1
auto[2281701376:2415919103]	auto[1]	62	1			T3	1		T13	2		T199	1
auto[2415919104:2550136831]	auto[0]	51	1			T80	1		T58	2		T49	1
auto[2415919104:2550136831]	auto[1]	58	1			T47	1		T48	1		T386	2
auto[2550136832:2684354559]	auto[0]	55	1			T58	1		T48	1		T5	2
auto[2550136832:2684354559]	auto[1]	51	1			T46	1		T47	1		T199	1
auto[2684354560:2818572287]	auto[0]	39	1			T38	1		T112	1		T46	1
auto[2684354560:2818572287]	auto[1]	42	1			T58	1		T96	1		T5	2
auto[2818572288:2952790015]	auto[0]	43	1			T46	2		T47	2		T5	1
auto[2818572288:2952790015]	auto[1]	66	1			T80	1		T48	1		T306	1
auto[2952790016:3087007743]	auto[0]	56	1			T46	1		T268	1		T230	1
auto[2952790016:3087007743]	auto[1]	50	1			T47	1		T96	1		T199	1
auto[3087007744:3221225471]	auto[0]	44	1			T60	1		T230	1		T105	1
auto[3087007744:3221225471]	auto[1]	57	1			T295	1		T104	1		T105	1
auto[3221225472:3355443199]	auto[0]	50	1			T49	1		T46	1		T48	1
auto[3221225472:3355443199]	auto[1]	50	1			T46	2		T47	1		T201	1
auto[3355443200:3489660927]	auto[0]	54	1			T58	1		T51	1		T96	1
auto[3355443200:3489660927]	auto[1]	43	1			T112	1		T46	3		T47	1
auto[3489660928:3623878655]	auto[0]	59	1			T80	1		T47	1		T60	1
auto[3489660928:3623878655]	auto[1]	59	1			T16	1		T50	1		T46	1
auto[3623878656:3758096383]	auto[0]	50	1			T47	1		T31	1		T48	1
auto[3623878656:3758096383]	auto[1]	52	1			T1	1		T38	1		T48	1
auto[3758096384:3892314111]	auto[0]	52	1			T47	1		T67	1		T60	1
auto[3758096384:3892314111]	auto[1]	38	1			T70	1		T46	1		T268	1
auto[3892314112:4026531839]	auto[0]	41	1			T2	1		T268	1		T59	1
auto[3892314112:4026531839]	auto[1]	61	1			T96	1		T199	1		T48	1
auto[4026531840:4160749567]	auto[0]	40	1			T46	2		T82	1		T63	1
auto[4026531840:4160749567]	auto[1]	48	1			T21	1		T24	1		T46	1
auto[4160749568:4294967295]	auto[0]	39	1			T192	1		T5	2		T268	1
auto[4160749568:4294967295]	auto[1]	44	1			T79	1		T46	2		T125	1