Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6868

1

T1

13

T2

3

T4

2

auto[1]

248

1

T112

12

T139

3

T140

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2888	1			T1	6		T2	1		T4	1
auto[134217728:268435455]	185	1			T58	1		T24	1		T40	1
auto[268435456:402653183]	160	1			T38	1		T79	1		T80	1
auto[402653184:536870911]	155	1			T13	1		T38	1		T80	1
auto[536870912:671088639]	150	1			T2	1		T21	1		T28	1
auto[671088640:805306367]	159	1			T79	1		T21	1		T24	1
auto[805306368:939524095]	118	1			T46	1		T47	1		T48	2
auto[939524096:1073741823]	135	1			T13	1		T79	1		T49	1
auto[1073741824:1207959551]	116	1			T1	1		T13	1		T80	1
auto[1207959552:1342177279]	112	1			T21	1		T50	1		T24	1
auto[1342177280:1476395007]	135	1			T50	1		T46	1		T47	3
auto[1476395008:1610612735]	117	1			T16	1		T51	1		T40	1
auto[1610612736:1744830463]	148	1			T13	1		T16	1		T50	1
auto[1744830464:1879048191]	131	1			T79	1		T49	1		T21	1
auto[1879048192:2013265919]	127	1			T1	1		T2	1		T79	2
auto[2013265920:2147483647]	119	1			T13	1		T112	1		T46	4
auto[2147483648:2281701375]	144	1			T112	1		T46	3		T47	1
auto[2281701376:2415919103]	136	1			T80	1		T50	1		T40	1
auto[2415919104:2550136831]	148	1			T79	1		T84	1		T112	1
auto[2550136832:2684354559]	117	1			T51	1		T40	1		T46	1
auto[2684354560:2818572287]	128	1			T1	2		T12	1		T112	2
auto[2818572288:2952790015]	139	1			T13	1		T112	1		T46	2
auto[2952790016:3087007743]	121	1			T70	1		T192	1		T112	1
auto[3087007744:3221225471]	151	1			T16	1		T51	2		T46	1
auto[3221225472:3355443199]	139	1			T1	1		T38	1		T51	1
auto[3355443200:3489660927]	115	1			T80	1		T19	1		T47	1
auto[3489660928:3623878655]	126	1			T13	1		T80	1		T49	1
auto[3623878656:3758096383]	128	1			T1	1		T4	1		T79	1
auto[3758096384:3892314111]	141	1			T13	1		T80	1		T58	1
auto[3892314112:4026531839]	146	1			T1	1		T76	1		T40	1
auto[4026531840:4160749567]	120	1			T80	1		T51	1		T50	1
auto[4160749568:4294967295]	162	1			T21	1		T51	1		T50	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2883	1			T1	6		T2	1		T4	1
auto[0:134217727]	auto[1]	5	1			T341	2		T225	1		T226	1
auto[134217728:268435455]	auto[0]	176	1			T58	1		T24	1		T40	1
auto[134217728:268435455]	auto[1]	9	1			T375	2		T129	1		T275	1
auto[268435456:402653183]	auto[0]	150	1			T38	1		T79	1		T80	1
auto[268435456:402653183]	auto[1]	10	1			T112	1		T139	1		T129	1
auto[402653184:536870911]	auto[0]	147	1			T13	1		T38	1		T80	1
auto[402653184:536870911]	auto[1]	8	1			T275	1		T267	1		T384	1
auto[536870912:671088639]	auto[0]	143	1			T2	1		T21	1		T28	1
auto[536870912:671088639]	auto[1]	7	1			T128	1		T263	1		T267	1
auto[671088640:805306367]	auto[0]	149	1			T79	1		T21	1		T24	1
auto[671088640:805306367]	auto[1]	10	1			T112	2		T139	1		T375	1
auto[805306368:939524095]	auto[0]	113	1			T46	1		T47	1		T48	2
auto[805306368:939524095]	auto[1]	5	1			T231	1		T376	1		T263	1
auto[939524096:1073741823]	auto[0]	128	1			T13	1		T79	1		T49	1
auto[939524096:1073741823]	auto[1]	7	1			T112	1		T404	1		T225	2
auto[1073741824:1207959551]	auto[0]	110	1			T1	1		T13	1		T80	1
auto[1073741824:1207959551]	auto[1]	6	1			T275	1		T341	1		T292	1
auto[1207959552:1342177279]	auto[0]	103	1			T21	1		T50	1		T24	1
auto[1207959552:1342177279]	auto[1]	9	1			T231	1		T341	1		T267	1
auto[1342177280:1476395007]	auto[0]	130	1			T50	1		T46	1		T47	3
auto[1342177280:1476395007]	auto[1]	5	1			T140	1		T376	1		T404	1
auto[1476395008:1610612735]	auto[0]	108	1			T16	1		T51	1		T40	1
auto[1476395008:1610612735]	auto[1]	9	1			T112	1		T341	3		T222	1
auto[1610612736:1744830463]	auto[0]	141	1			T13	1		T16	1		T50	1
auto[1610612736:1744830463]	auto[1]	7	1			T375	1		T267	2		T222	1
auto[1744830464:1879048191]	auto[0]	125	1			T79	1		T49	1		T21	1
auto[1744830464:1879048191]	auto[1]	6	1			T231	1		T275	1		T222	2
auto[1879048192:2013265919]	auto[0]	119	1			T1	1		T2	1		T79	2
auto[1879048192:2013265919]	auto[1]	8	1			T140	1		T231	1		T127	1
auto[2013265920:2147483647]	auto[0]	111	1			T13	1		T46	4		T96	1
auto[2013265920:2147483647]	auto[1]	8	1			T112	1		T231	2		T267	1
auto[2147483648:2281701375]	auto[0]	137	1			T46	3		T47	1		T199	1
auto[2147483648:2281701375]	auto[1]	7	1			T112	1		T341	1		T262	1
auto[2281701376:2415919103]	auto[0]	130	1			T80	1		T50	1		T40	1
auto[2281701376:2415919103]	auto[1]	6	1			T129	1		T333	1		T266	1
auto[2415919104:2550136831]	auto[0]	132	1			T79	1		T84	1		T46	2
auto[2415919104:2550136831]	auto[1]	16	1			T112	1		T231	2		T375	1
auto[2550136832:2684354559]	auto[0]	107	1			T51	1		T40	1		T46	1
auto[2550136832:2684354559]	auto[1]	10	1			T140	1		T231	1		T375	1
auto[2684354560:2818572287]	auto[0]	121	1			T1	2		T12	1		T112	2
auto[2684354560:2818572287]	auto[1]	7	1			T374	1		T275	1		T221	1
auto[2818572288:2952790015]	auto[0]	131	1			T13	1		T46	2		T199	1
auto[2818572288:2952790015]	auto[1]	8	1			T112	1		T376	1		T247	1
auto[2952790016:3087007743]	auto[0]	108	1			T70	1		T192	1		T96	1
auto[2952790016:3087007743]	auto[1]	13	1			T112	1		T273	1		T375	1
auto[3087007744:3221225471]	auto[0]	144	1			T16	1		T51	2		T46	1
auto[3087007744:3221225471]	auto[1]	7	1			T127	1		T376	1		T341	1
auto[3221225472:3355443199]	auto[0]	132	1			T1	1		T38	1		T51	1
auto[3221225472:3355443199]	auto[1]	7	1			T128	1		T292	1		T404	1
auto[3355443200:3489660927]	auto[0]	105	1			T80	1		T19	1		T47	1
auto[3355443200:3489660927]	auto[1]	10	1			T231	1		T273	1		T129	1
auto[3489660928:3623878655]	auto[0]	114	1			T13	1		T80	1		T49	1
auto[3489660928:3623878655]	auto[1]	12	1			T112	1		T231	1		T333	1
auto[3623878656:3758096383]	auto[0]	124	1			T1	1		T4	1		T79	1
auto[3623878656:3758096383]	auto[1]	4	1			T112	1		T267	1		T405	1
auto[3758096384:3892314111]	auto[0]	137	1			T13	1		T80	1		T58	1
auto[3758096384:3892314111]	auto[1]	4	1			T341	1		T248	1		T271	1
auto[3892314112:4026531839]	auto[0]	141	1			T1	1		T76	1		T40	1
auto[3892314112:4026531839]	auto[1]	5	1			T139	1		T231	2		T127	1
auto[4026531840:4160749567]	auto[0]	117	1			T80	1		T51	1		T50	1
auto[4026531840:4160749567]	auto[1]	3	1			T273	1		T221	1		T304	1
auto[4160749568:4294967295]	auto[0]	152	1			T21	1		T51	1		T50	1
auto[4160749568:4294967295]	auto[1]	10	1			T375	1		T341	1		T225	1