Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4522

1

T1

10

T3

2

T13

10

auto[1]

2076

1

T2

4

T4

2

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	220	1			T58	2		T49	2		T51	2
auto[134217728:268435455]	188	1			T80	2		T21	2		T70	2
auto[268435456:402653183]	210	1			T1	2		T16	4		T57	2
auto[402653184:536870911]	164	1			T13	2		T38	2		T24	2
auto[536870912:671088639]	192	1			T21	2		T46	2		T48	4
auto[671088640:805306367]	190	1			T79	2		T58	2		T49	2
auto[805306368:939524095]	176	1			T13	2		T24	2		T192	2
auto[939524096:1073741823]	216	1			T79	2		T80	4		T46	10
auto[1073741824:1207959551]	224	1			T13	4		T49	2		T24	2
auto[1207959552:1342177279]	200	1			T21	2		T50	2		T24	2
auto[1342177280:1476395007]	202	1			T80	2		T49	2		T28	2
auto[1476395008:1610612735]	202	1			T49	2		T46	4		T47	2
auto[1610612736:1744830463]	222	1			T3	2		T79	2		T51	2
auto[1744830464:1879048191]	196	1			T46	4		T199	2		T139	2
auto[1879048192:2013265919]	182	1			T51	2		T47	2		T31	2
auto[2013265920:2147483647]	230	1			T13	2		T84	2		T46	2
auto[2147483648:2281701375]	218	1			T4	2		T79	2		T80	4
auto[2281701376:2415919103]	230	1			T1	2		T2	2		T13	2
auto[2415919104:2550136831]	220	1			T80	2		T50	2		T112	2
auto[2550136832:2684354559]	198	1			T13	2		T58	2		T51	2
auto[2684354560:2818572287]	200	1			T79	2		T49	2		T46	2
auto[2818572288:2952790015]	210	1			T40	2		T46	4		T47	2
auto[2952790016:3087007743]	206	1			T2	2		T21	2		T46	2
auto[3087007744:3221225471]	218	1			T38	2		T58	2		T28	2
auto[3221225472:3355443199]	210	1			T1	2		T58	2		T51	2
auto[3355443200:3489660927]	218	1			T1	2		T51	4		T50	2
auto[3489660928:3623878655]	178	1			T21	2		T48	4		T5	2
auto[3623878656:3758096383]	214	1			T49	2		T50	2		T46	4
auto[3758096384:3892314111]	210	1			T40	2		T192	2		T47	2
auto[3892314112:4026531839]	198	1			T12	2		T16	2		T46	2
auto[4026531840:4160749567]	232	1			T51	2		T84	2		T46	4
auto[4160749568:4294967295]	224	1			T1	2		T56	2		T112	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	164	1			T58	2		T49	2		T47	2
auto[0:134217727]	auto[1]	56	1			T51	2		T112	2		T5	4
auto[134217728:268435455]	auto[0]	106	1			T80	2		T21	2		T70	2
auto[134217728:268435455]	auto[1]	82	1			T46	2		T193	2		T5	2
auto[268435456:402653183]	auto[0]	156	1			T1	2		T16	4		T57	2
auto[268435456:402653183]	auto[1]	54	1			T19	2		T105	2		T347	2
auto[402653184:536870911]	auto[0]	102	1			T13	2		T38	2		T24	2
auto[402653184:536870911]	auto[1]	62	1			T97	2		T105	2		T6	2
auto[536870912:671088639]	auto[0]	134	1			T46	2		T48	2		T69	2
auto[536870912:671088639]	auto[1]	58	1			T21	2		T48	2		T69	2
auto[671088640:805306367]	auto[0]	136	1			T79	2		T58	2		T46	4
auto[671088640:805306367]	auto[1]	54	1			T49	2		T19	2		T46	2
auto[805306368:939524095]	auto[0]	106	1			T13	2		T24	2		T192	2
auto[805306368:939524095]	auto[1]	70	1			T46	2		T47	2		T48	2
auto[939524096:1073741823]	auto[0]	144	1			T79	2		T80	4		T46	6
auto[939524096:1073741823]	auto[1]	72	1			T46	4		T47	2		T48	2
auto[1073741824:1207959551]	auto[0]	146	1			T13	4		T24	2		T57	2
auto[1073741824:1207959551]	auto[1]	78	1			T49	2		T46	2		T69	2
auto[1207959552:1342177279]	auto[0]	136	1			T21	2		T24	2		T46	2
auto[1207959552:1342177279]	auto[1]	64	1			T50	2		T199	2		T398	2
auto[1342177280:1476395007]	auto[0]	148	1			T80	2		T49	2		T28	2
auto[1342177280:1476395007]	auto[1]	54	1			T84	2		T46	2		T48	2
auto[1476395008:1610612735]	auto[0]	138	1			T49	2		T47	2		T48	2
auto[1476395008:1610612735]	auto[1]	64	1			T46	4		T96	2		T197	2
auto[1610612736:1744830463]	auto[0]	148	1			T3	2		T192	2		T139	2
auto[1610612736:1744830463]	auto[1]	74	1			T79	2		T51	2		T32	2
auto[1744830464:1879048191]	auto[0]	138	1			T46	2		T199	2		T139	2
auto[1744830464:1879048191]	auto[1]	58	1			T46	2		T5	2		T100	2
auto[1879048192:2013265919]	auto[0]	138	1			T51	2		T48	4		T52	2
auto[1879048192:2013265919]	auto[1]	44	1			T47	2		T31	2		T60	2
auto[2013265920:2147483647]	auto[0]	160	1			T84	2		T199	2		T48	2
auto[2013265920:2147483647]	auto[1]	70	1			T13	2		T46	2		T5	2
auto[2147483648:2281701375]	auto[0]	162	1			T79	2		T80	4		T58	2
auto[2147483648:2281701375]	auto[1]	56	1			T4	2		T49	2		T84	2
auto[2281701376:2415919103]	auto[0]	162	1			T1	2		T13	2		T80	2
auto[2281701376:2415919103]	auto[1]	68	1			T2	2		T16	2		T58	2
auto[2415919104:2550136831]	auto[0]	142	1			T80	2		T112	2		T46	4
auto[2415919104:2550136831]	auto[1]	78	1			T50	2		T199	2		T48	4
auto[2550136832:2684354559]	auto[0]	140	1			T58	2		T51	2		T46	2
auto[2550136832:2684354559]	auto[1]	58	1			T13	2		T71	2		T34	2
auto[2684354560:2818572287]	auto[0]	136	1			T79	2		T49	2		T96	2
auto[2684354560:2818572287]	auto[1]	64	1			T46	2		T197	2		T230	2
auto[2818572288:2952790015]	auto[0]	144	1			T40	2		T47	2		T199	2
auto[2818572288:2952790015]	auto[1]	66	1			T46	4		T67	2		T282	2
auto[2952790016:3087007743]	auto[0]	140	1			T21	2		T60	2		T268	2
auto[2952790016:3087007743]	auto[1]	66	1			T2	2		T46	2		T47	2
auto[3087007744:3221225471]	auto[0]	146	1			T58	2		T28	2		T51	2
auto[3087007744:3221225471]	auto[1]	72	1			T38	2		T40	2		T47	2
auto[3221225472:3355443199]	auto[0]	146	1			T1	2		T58	2		T46	2
auto[3221225472:3355443199]	auto[1]	64	1			T51	2		T192	2		T47	2
auto[3355443200:3489660927]	auto[0]	158	1			T1	2		T51	2		T50	2
auto[3355443200:3489660927]	auto[1]	60	1			T51	2		T76	2		T77	2
auto[3489660928:3623878655]	auto[0]	130	1			T21	2		T48	2		T5	2
auto[3489660928:3623878655]	auto[1]	48	1			T48	2		T67	2		T398	2
auto[3623878656:3758096383]	auto[0]	136	1			T46	4		T196	2		T48	2
auto[3623878656:3758096383]	auto[1]	78	1			T49	2		T50	2		T67	2
auto[3758096384:3892314111]	auto[0]	140	1			T40	2		T192	2		T47	2
auto[3758096384:3892314111]	auto[1]	70	1			T5	2		T331	2		T105	2
auto[3892314112:4026531839]	auto[0]	144	1			T16	2		T46	2		T48	2
auto[3892314112:4026531839]	auto[1]	54	1			T12	2		T47	2		T48	2
auto[4026531840:4160749567]	auto[0]	136	1			T46	2		T199	2		T193	4
auto[4026531840:4160749567]	auto[1]	96	1			T51	2		T84	2		T46	2
auto[4160749568:4294967295]	auto[0]	160	1			T1	2		T56	2		T46	6
auto[4160749568:4294967295]	auto[1]	64	1			T112	2		T46	2		T196	2