Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.04 98.11 98.61 100.00 99.02 98.41 91.19


Total test records in report: 1081
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T1007 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.715552878 Aug 12 05:00:02 PM PDT 24 Aug 12 05:00:08 PM PDT 24 67073891 ps
T1008 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1612926580 Aug 12 05:00:05 PM PDT 24 Aug 12 05:00:11 PM PDT 24 365319779 ps
T1009 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4252883301 Aug 12 04:59:57 PM PDT 24 Aug 12 04:59:59 PM PDT 24 25714284 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.957995782 Aug 12 04:59:53 PM PDT 24 Aug 12 05:00:01 PM PDT 24 799828500 ps
T1011 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3675013650 Aug 12 05:00:05 PM PDT 24 Aug 12 05:00:09 PM PDT 24 36650932 ps
T1012 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2935183514 Aug 12 04:59:43 PM PDT 24 Aug 12 04:59:44 PM PDT 24 33401268 ps
T1013 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1078186902 Aug 12 04:59:57 PM PDT 24 Aug 12 04:59:59 PM PDT 24 60332831 ps
T1014 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2920685905 Aug 12 05:00:14 PM PDT 24 Aug 12 05:00:15 PM PDT 24 15810649 ps
T1015 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.864614295 Aug 12 04:59:50 PM PDT 24 Aug 12 05:00:03 PM PDT 24 1723318666 ps
T1016 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2293512647 Aug 12 05:00:05 PM PDT 24 Aug 12 05:00:22 PM PDT 24 789066114 ps
T171 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3056145667 Aug 12 05:00:05 PM PDT 24 Aug 12 05:00:11 PM PDT 24 58404593 ps
T1017 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2562678125 Aug 12 04:59:57 PM PDT 24 Aug 12 04:59:59 PM PDT 24 98393255 ps
T1018 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4171394455 Aug 12 05:00:11 PM PDT 24 Aug 12 05:00:12 PM PDT 24 244368122 ps
T174 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4107714587 Aug 12 05:00:09 PM PDT 24 Aug 12 05:00:14 PM PDT 24 166310614 ps
T1019 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.420791647 Aug 12 05:00:21 PM PDT 24 Aug 12 05:00:22 PM PDT 24 17667652 ps
T1020 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3873826519 Aug 12 05:00:19 PM PDT 24 Aug 12 05:00:20 PM PDT 24 16559396 ps
T1021 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2431033950 Aug 12 04:59:53 PM PDT 24 Aug 12 04:59:56 PM PDT 24 118877297 ps
T1022 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.797189966 Aug 12 04:59:56 PM PDT 24 Aug 12 05:00:08 PM PDT 24 774248105 ps
T1023 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3541357562 Aug 12 04:59:50 PM PDT 24 Aug 12 04:59:51 PM PDT 24 151407658 ps
T1024 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2142880346 Aug 12 05:00:09 PM PDT 24 Aug 12 05:00:11 PM PDT 24 118392030 ps
T1025 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4168611489 Aug 12 04:59:56 PM PDT 24 Aug 12 04:59:58 PM PDT 24 37502059 ps
T1026 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4091320065 Aug 12 04:59:57 PM PDT 24 Aug 12 04:59:59 PM PDT 24 169875856 ps
T1027 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3467423152 Aug 12 04:59:42 PM PDT 24 Aug 12 04:59:43 PM PDT 24 21220563 ps
T1028 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1228929357 Aug 12 04:59:48 PM PDT 24 Aug 12 04:59:49 PM PDT 24 14219507 ps
T1029 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3955430824 Aug 12 05:00:14 PM PDT 24 Aug 12 05:00:15 PM PDT 24 9361302 ps
T1030 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2227286173 Aug 12 05:00:05 PM PDT 24 Aug 12 05:00:11 PM PDT 24 425403475 ps
T1031 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.444438616 Aug 12 04:59:59 PM PDT 24 Aug 12 05:00:04 PM PDT 24 161673808 ps
T1032 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4091335546 Aug 12 05:00:10 PM PDT 24 Aug 12 05:00:11 PM PDT 24 20379992 ps
T1033 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.517640128 Aug 12 05:00:11 PM PDT 24 Aug 12 05:00:17 PM PDT 24 202698196 ps
T1034 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3565737274 Aug 12 04:59:44 PM PDT 24 Aug 12 04:59:48 PM PDT 24 523303155 ps
T1035 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.331949605 Aug 12 05:00:12 PM PDT 24 Aug 12 05:00:13 PM PDT 24 18040310 ps
T1036 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.899412433 Aug 12 05:00:03 PM PDT 24 Aug 12 05:00:17 PM PDT 24 691616122 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1744224610 Aug 12 04:59:53 PM PDT 24 Aug 12 04:59:55 PM PDT 24 118407208 ps
T1038 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2539360398 Aug 12 04:59:52 PM PDT 24 Aug 12 04:59:53 PM PDT 24 16775257 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.398569906 Aug 12 05:00:04 PM PDT 24 Aug 12 05:00:10 PM PDT 24 50988342 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2638345929 Aug 12 04:59:49 PM PDT 24 Aug 12 04:59:51 PM PDT 24 90041892 ps
T1041 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2122412679 Aug 12 05:00:04 PM PDT 24 Aug 12 05:00:10 PM PDT 24 107905104 ps
T1042 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4065839452 Aug 12 04:59:57 PM PDT 24 Aug 12 04:59:58 PM PDT 24 27909336 ps
T1043 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2577496593 Aug 12 05:00:11 PM PDT 24 Aug 12 05:00:12 PM PDT 24 24260630 ps
T1044 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2300162017 Aug 12 04:59:42 PM PDT 24 Aug 12 04:59:57 PM PDT 24 515933920 ps
T1045 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.598861599 Aug 12 04:59:47 PM PDT 24 Aug 12 04:59:51 PM PDT 24 70791300 ps
T381 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3869530659 Aug 12 04:59:43 PM PDT 24 Aug 12 04:59:49 PM PDT 24 403675605 ps
T1046 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.360992770 Aug 12 05:00:14 PM PDT 24 Aug 12 05:00:17 PM PDT 24 361324298 ps
T156 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2193975763 Aug 12 04:59:48 PM PDT 24 Aug 12 04:59:52 PM PDT 24 235709728 ps
T1047 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3905931963 Aug 12 04:59:59 PM PDT 24 Aug 12 05:00:02 PM PDT 24 137854964 ps
T1048 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.394576601 Aug 12 05:00:03 PM PDT 24 Aug 12 05:00:09 PM PDT 24 69426861 ps
T1049 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.850548660 Aug 12 05:00:12 PM PDT 24 Aug 12 05:00:13 PM PDT 24 38553597 ps
T1050 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.201351270 Aug 12 05:00:06 PM PDT 24 Aug 12 05:00:12 PM PDT 24 49802966 ps
T1051 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.988814984 Aug 12 05:00:00 PM PDT 24 Aug 12 05:00:03 PM PDT 24 240642468 ps
T1052 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1305115449 Aug 12 05:00:13 PM PDT 24 Aug 12 05:00:16 PM PDT 24 97613773 ps
T1053 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3215843114 Aug 12 05:00:03 PM PDT 24 Aug 12 05:00:15 PM PDT 24 343166549 ps
T1054 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3545380792 Aug 12 04:59:58 PM PDT 24 Aug 12 05:00:00 PM PDT 24 215761199 ps
T1055 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1816701769 Aug 12 04:59:52 PM PDT 24 Aug 12 04:59:54 PM PDT 24 48662413 ps
T1056 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3759903659 Aug 12 05:00:09 PM PDT 24 Aug 12 05:00:10 PM PDT 24 13000037 ps
T1057 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1083060249 Aug 12 05:00:00 PM PDT 24 Aug 12 05:00:01 PM PDT 24 18663917 ps
T1058 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3297316140 Aug 12 04:59:53 PM PDT 24 Aug 12 04:59:55 PM PDT 24 10444446 ps
T1059 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.82003930 Aug 12 05:00:19 PM PDT 24 Aug 12 05:00:20 PM PDT 24 11013348 ps
T157 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.159057047 Aug 12 04:59:49 PM PDT 24 Aug 12 04:59:53 PM PDT 24 515432184 ps
T1060 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2405233764 Aug 12 05:00:24 PM PDT 24 Aug 12 05:00:25 PM PDT 24 23235520 ps
T1061 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.546393299 Aug 12 05:00:09 PM PDT 24 Aug 12 05:00:10 PM PDT 24 69605954 ps
T1062 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2899472517 Aug 12 05:00:03 PM PDT 24 Aug 12 05:00:09 PM PDT 24 34884963 ps
T1063 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1323771981 Aug 12 05:00:05 PM PDT 24 Aug 12 05:00:08 PM PDT 24 12638246 ps
T1064 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3020848516 Aug 12 04:59:50 PM PDT 24 Aug 12 04:59:51 PM PDT 24 25402886 ps
T1065 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1339927345 Aug 12 05:00:06 PM PDT 24 Aug 12 05:00:09 PM PDT 24 23585010 ps
T1066 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1364590455 Aug 12 05:00:10 PM PDT 24 Aug 12 05:00:15 PM PDT 24 605853112 ps
T1067 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.4107527953 Aug 12 04:59:57 PM PDT 24 Aug 12 04:59:58 PM PDT 24 18643130 ps
T1068 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1359061386 Aug 12 05:00:04 PM PDT 24 Aug 12 05:00:09 PM PDT 24 167703947 ps
T1069 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.243746672 Aug 12 05:00:03 PM PDT 24 Aug 12 05:00:08 PM PDT 24 40561079 ps
T158 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3086570676 Aug 12 05:00:24 PM PDT 24 Aug 12 05:00:33 PM PDT 24 689739625 ps
T1070 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.244089329 Aug 12 04:59:52 PM PDT 24 Aug 12 04:59:53 PM PDT 24 38532466 ps
T1071 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3110399094 Aug 12 05:00:13 PM PDT 24 Aug 12 05:00:19 PM PDT 24 731327377 ps
T1072 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3434770695 Aug 12 05:00:12 PM PDT 24 Aug 12 05:00:13 PM PDT 24 177961704 ps
T1073 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2041980309 Aug 12 05:00:04 PM PDT 24 Aug 12 05:00:11 PM PDT 24 82709800 ps
T1074 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.434079252 Aug 12 05:00:11 PM PDT 24 Aug 12 05:00:13 PM PDT 24 140691786 ps
T1075 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3653916553 Aug 12 05:00:05 PM PDT 24 Aug 12 05:00:12 PM PDT 24 177278423 ps
T1076 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2437883107 Aug 12 04:59:57 PM PDT 24 Aug 12 04:59:59 PM PDT 24 74453556 ps
T1077 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.481344675 Aug 12 04:59:50 PM PDT 24 Aug 12 04:59:56 PM PDT 24 611847895 ps
T1078 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2857407904 Aug 12 05:00:03 PM PDT 24 Aug 12 05:00:10 PM PDT 24 113125484 ps
T1079 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3252874847 Aug 12 05:00:22 PM PDT 24 Aug 12 05:00:23 PM PDT 24 75840878 ps
T1080 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4002510041 Aug 12 05:00:04 PM PDT 24 Aug 12 05:00:12 PM PDT 24 114207745 ps
T1081 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3148519925 Aug 12 04:59:54 PM PDT 24 Aug 12 05:00:03 PM PDT 24 1373170871 ps

Test location /workspace/coverage/default/26.keymgr_lc_disable.2408526145
Short name T13
Test name
Test status
Simulation time 623140795 ps
CPU time 3.04 seconds
Started Aug 12 05:02:10 PM PDT 24
Finished Aug 12 05:02:13 PM PDT 24
Peak memory 214804 kb
Host smart-69c3b5e6-bf81-4bd6-bcf1-e8f39f3b61d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408526145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2408526145
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1421054000
Short name T5
Test name
Test status
Simulation time 52404990329 ps
CPU time 304.95 seconds
Started Aug 12 05:01:40 PM PDT 24
Finished Aug 12 05:06:45 PM PDT 24
Peak memory 219488 kb
Host smart-d3281167-cdc6-446c-bd55-135d9e57ca18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421054000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1421054000
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1270765897
Short name T50
Test name
Test status
Simulation time 619627676 ps
CPU time 15.28 seconds
Started Aug 12 05:01:37 PM PDT 24
Finished Aug 12 05:01:52 PM PDT 24
Peak memory 223120 kb
Host smart-165cf516-7d10-4d81-b635-174e27a1e9e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270765897 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1270765897
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.577741158
Short name T46
Test name
Test status
Simulation time 5945803510 ps
CPU time 62.74 seconds
Started Aug 12 05:01:06 PM PDT 24
Finished Aug 12 05:02:09 PM PDT 24
Peak memory 222976 kb
Host smart-76abb001-6d67-4b4e-9ce8-95c8a1e27226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577741158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.577741158
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.641264678
Short name T9
Test name
Test status
Simulation time 5519661207 ps
CPU time 11.72 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:11 PM PDT 24
Peak memory 239420 kb
Host smart-a1058a61-09c3-47e7-b1cb-17cc05acf1b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641264678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.641264678
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1824809593
Short name T49
Test name
Test status
Simulation time 255530648 ps
CPU time 9.24 seconds
Started Aug 12 05:01:17 PM PDT 24
Finished Aug 12 05:01:26 PM PDT 24
Peak memory 222980 kb
Host smart-00c5f51f-be7f-445d-8844-07424563cda7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824809593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1824809593
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3620043513
Short name T105
Test name
Test status
Simulation time 1565825753 ps
CPU time 25.39 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:32 PM PDT 24
Peak memory 223032 kb
Host smart-c717bc4c-b217-402e-bb02-95f7bbf31f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620043513 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3620043513
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1930957031
Short name T231
Test name
Test status
Simulation time 909766532 ps
CPU time 48.86 seconds
Started Aug 12 05:01:32 PM PDT 24
Finished Aug 12 05:02:21 PM PDT 24
Peak memory 215056 kb
Host smart-9f5510fd-48b4-4a51-80b2-43a6b516bafe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930957031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1930957031
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1466459112
Short name T3
Test name
Test status
Simulation time 131672730 ps
CPU time 2.33 seconds
Started Aug 12 05:02:31 PM PDT 24
Finished Aug 12 05:02:34 PM PDT 24
Peak memory 209856 kb
Host smart-58a36511-930e-4c1b-a74b-a19e6cf22251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466459112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1466459112
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3490213863
Short name T51
Test name
Test status
Simulation time 44533173 ps
CPU time 2.34 seconds
Started Aug 12 05:02:22 PM PDT 24
Finished Aug 12 05:02:24 PM PDT 24
Peak memory 216120 kb
Host smart-46f77d1f-5049-49f5-81b8-a347b0a98e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490213863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3490213863
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3951510460
Short name T116
Test name
Test status
Simulation time 106274177 ps
CPU time 4 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 05:00:01 PM PDT 24
Peak memory 214820 kb
Host smart-e7b68787-bdc1-42d2-b9ba-29dc670de3cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951510460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3951510460
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.60137791
Short name T8
Test name
Test status
Simulation time 66575611 ps
CPU time 3.05 seconds
Started Aug 12 05:01:39 PM PDT 24
Finished Aug 12 05:01:42 PM PDT 24
Peak memory 219508 kb
Host smart-4e7e8800-36ed-4a00-8987-e4b6b75c1c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60137791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.60137791
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1101792645
Short name T404
Test name
Test status
Simulation time 270689541 ps
CPU time 13.95 seconds
Started Aug 12 05:01:00 PM PDT 24
Finished Aug 12 05:01:14 PM PDT 24
Peak memory 216324 kb
Host smart-3154c788-697d-4431-aec5-3d8d71d0f97f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101792645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1101792645
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.161072621
Short name T19
Test name
Test status
Simulation time 76015010 ps
CPU time 2.24 seconds
Started Aug 12 05:01:23 PM PDT 24
Finished Aug 12 05:01:25 PM PDT 24
Peak memory 215040 kb
Host smart-df023c31-1c46-425c-a2f6-59cd2e39994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161072621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.161072621
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1285518975
Short name T48
Test name
Test status
Simulation time 3245035026 ps
CPU time 44.43 seconds
Started Aug 12 05:01:43 PM PDT 24
Finished Aug 12 05:02:27 PM PDT 24
Peak memory 223000 kb
Host smart-2d96ebd6-1cc8-4f27-b9cc-97279e1bf291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285518975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1285518975
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.627139693
Short name T83
Test name
Test status
Simulation time 77404648 ps
CPU time 3.51 seconds
Started Aug 12 05:01:40 PM PDT 24
Finished Aug 12 05:01:44 PM PDT 24
Peak memory 210292 kb
Host smart-39f5a223-1845-46d6-8e0a-5db5f3d8e4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627139693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.627139693
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1168054422
Short name T341
Test name
Test status
Simulation time 3161256227 ps
CPU time 38.62 seconds
Started Aug 12 05:01:02 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 216488 kb
Host smart-32348df2-dce5-4ffd-8015-8566efd2f730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168054422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1168054422
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3838095826
Short name T129
Test name
Test status
Simulation time 478185169 ps
CPU time 12.51 seconds
Started Aug 12 05:01:13 PM PDT 24
Finished Aug 12 05:01:26 PM PDT 24
Peak memory 215048 kb
Host smart-e0d22cb6-39ba-4ce7-9645-87fae81ebb5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3838095826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3838095826
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3639710561
Short name T185
Test name
Test status
Simulation time 1871920419 ps
CPU time 54.04 seconds
Started Aug 12 05:01:00 PM PDT 24
Finished Aug 12 05:01:54 PM PDT 24
Peak memory 215576 kb
Host smart-d1eca263-08bc-406f-85c9-bc73e0e84a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639710561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3639710561
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.157405190
Short name T222
Test name
Test status
Simulation time 1148337603 ps
CPU time 14.62 seconds
Started Aug 12 05:02:21 PM PDT 24
Finished Aug 12 05:02:36 PM PDT 24
Peak memory 214956 kb
Host smart-e9cf7549-a84e-46df-8ec3-546317cee46b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157405190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.157405190
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3766824479
Short name T113
Test name
Test status
Simulation time 879569203 ps
CPU time 3.33 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 214640 kb
Host smart-04060d26-b01a-4500-a78d-565518edcf06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766824479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3766824479
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3471869468
Short name T44
Test name
Test status
Simulation time 1170135458 ps
CPU time 9.84 seconds
Started Aug 12 05:02:26 PM PDT 24
Finished Aug 12 05:02:36 PM PDT 24
Peak memory 211268 kb
Host smart-203394af-2488-4a71-bc7e-8c33280a0f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471869468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3471869468
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1978229223
Short name T21
Test name
Test status
Simulation time 328659737 ps
CPU time 3.57 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 218664 kb
Host smart-236c24b2-c324-4433-b6f1-0c93ca6afb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978229223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1978229223
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3198276625
Short name T408
Test name
Test status
Simulation time 4614247144 ps
CPU time 122.55 seconds
Started Aug 12 05:01:01 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 218308 kb
Host smart-436817c0-d1b2-4731-8346-5d031f4f57fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198276625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3198276625
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1979122890
Short name T63
Test name
Test status
Simulation time 1094870280 ps
CPU time 15.09 seconds
Started Aug 12 05:02:56 PM PDT 24
Finished Aug 12 05:03:11 PM PDT 24
Peak memory 220300 kb
Host smart-d45af9c2-18c5-448b-a942-19563bd4e5d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979122890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1979122890
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3228113211
Short name T143
Test name
Test status
Simulation time 90084896 ps
CPU time 4.16 seconds
Started Aug 12 05:02:48 PM PDT 24
Finished Aug 12 05:02:52 PM PDT 24
Peak memory 219024 kb
Host smart-43b00e72-6460-4bd2-b55b-d5b08544e811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228113211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3228113211
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3799447973
Short name T23
Test name
Test status
Simulation time 71368631 ps
CPU time 2.02 seconds
Started Aug 12 05:02:00 PM PDT 24
Finished Aug 12 05:02:02 PM PDT 24
Peak memory 217072 kb
Host smart-2fc68a1e-b872-441e-a8d5-4365e45de506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799447973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3799447973
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.530070605
Short name T33
Test name
Test status
Simulation time 707961023 ps
CPU time 4.92 seconds
Started Aug 12 05:01:31 PM PDT 24
Finished Aug 12 05:01:36 PM PDT 24
Peak memory 214772 kb
Host smart-dd4a416e-6aef-42a6-9057-a3c4d4560340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530070605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.530070605
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.369666979
Short name T53
Test name
Test status
Simulation time 7387946014 ps
CPU time 48.75 seconds
Started Aug 12 05:02:07 PM PDT 24
Finished Aug 12 05:02:55 PM PDT 24
Peak memory 217588 kb
Host smart-969814e0-29f0-4ca7-b79e-6a866d7e6660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369666979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.369666979
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.158694945
Short name T333
Test name
Test status
Simulation time 930605242 ps
CPU time 14.67 seconds
Started Aug 12 05:02:52 PM PDT 24
Finished Aug 12 05:03:06 PM PDT 24
Peak memory 215700 kb
Host smart-84c800a3-1bb6-48d6-a37b-6ee87a22f161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158694945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.158694945
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2343162921
Short name T267
Test name
Test status
Simulation time 1739806198 ps
CPU time 44.94 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 223060 kb
Host smart-92000675-d271-46c0-91ee-bd9fd2259e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2343162921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2343162921
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1194312229
Short name T67
Test name
Test status
Simulation time 1631454686 ps
CPU time 23.27 seconds
Started Aug 12 05:02:47 PM PDT 24
Finished Aug 12 05:03:10 PM PDT 24
Peak memory 223712 kb
Host smart-96f9db51-80f5-4692-8286-a3228d8c72dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194312229 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1194312229
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.600167736
Short name T93
Test name
Test status
Simulation time 20107368 ps
CPU time 1.03 seconds
Started Aug 12 05:01:09 PM PDT 24
Finished Aug 12 05:01:10 PM PDT 24
Peak memory 206616 kb
Host smart-2a33ddf4-5342-4973-8c34-59772495e708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600167736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.600167736
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1078119327
Short name T208
Test name
Test status
Simulation time 3405324462 ps
CPU time 54.96 seconds
Started Aug 12 05:01:22 PM PDT 24
Finished Aug 12 05:02:17 PM PDT 24
Peak memory 215732 kb
Host smart-06357b9f-717b-4592-8007-d892d135f3c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078119327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1078119327
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1260881776
Short name T153
Test name
Test status
Simulation time 260083226 ps
CPU time 6.16 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:14 PM PDT 24
Peak memory 214292 kb
Host smart-067c6ccc-626f-4e2d-8451-82cde1fc22b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260881776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1260881776
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1408072331
Short name T85
Test name
Test status
Simulation time 157135128 ps
CPU time 3.08 seconds
Started Aug 12 05:03:01 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 222928 kb
Host smart-53f62374-d366-485c-91d7-7b2308e05f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408072331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1408072331
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3269709131
Short name T402
Test name
Test status
Simulation time 80974898 ps
CPU time 4.54 seconds
Started Aug 12 05:02:09 PM PDT 24
Finished Aug 12 05:02:14 PM PDT 24
Peak memory 215412 kb
Host smart-de6bff22-22e6-4053-a08e-14e65cf34c44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3269709131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3269709131
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4217294167
Short name T277
Test name
Test status
Simulation time 63424554 ps
CPU time 3.28 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:00:59 PM PDT 24
Peak memory 221232 kb
Host smart-cbb4a5f3-abb0-4f20-ad88-0fa257766a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217294167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4217294167
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.203817850
Short name T271
Test name
Test status
Simulation time 2909412302 ps
CPU time 9.38 seconds
Started Aug 12 05:02:01 PM PDT 24
Finished Aug 12 05:02:10 PM PDT 24
Peak memory 215516 kb
Host smart-bf63d90b-2c85-4183-83b4-b387107eebca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203817850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.203817850
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.209490858
Short name T827
Test name
Test status
Simulation time 54681187 ps
CPU time 2.77 seconds
Started Aug 12 05:02:12 PM PDT 24
Finished Aug 12 05:02:15 PM PDT 24
Peak memory 214740 kb
Host smart-7dd7d90f-cb34-49db-bd2b-70b76170dcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209490858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.209490858
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1378910269
Short name T218
Test name
Test status
Simulation time 3351774351 ps
CPU time 25.64 seconds
Started Aug 12 05:02:04 PM PDT 24
Finished Aug 12 05:02:30 PM PDT 24
Peak memory 222248 kb
Host smart-dbeaf968-29b6-4646-998d-bcf30e61c3c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378910269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1378910269
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.301007869
Short name T226
Test name
Test status
Simulation time 252943054 ps
CPU time 3.91 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 214856 kb
Host smart-8db6bce1-48ed-4b7f-b5a1-cf33cdbf7009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301007869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.301007869
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3121437471
Short name T146
Test name
Test status
Simulation time 31057132 ps
CPU time 2.57 seconds
Started Aug 12 05:01:54 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 223000 kb
Host smart-f7fd197f-d8f4-4bec-a36e-25280405a06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121437471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3121437471
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.747668269
Short name T259
Test name
Test status
Simulation time 335341098 ps
CPU time 7.77 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:53 PM PDT 24
Peak memory 210896 kb
Host smart-4653edf2-7039-4722-b7fb-62f96b2a7e02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747668269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.747668269
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2544452444
Short name T353
Test name
Test status
Simulation time 692076750 ps
CPU time 6.27 seconds
Started Aug 12 05:01:08 PM PDT 24
Finished Aug 12 05:01:15 PM PDT 24
Peak memory 222840 kb
Host smart-f6549834-8e30-4844-8e81-506daa03ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544452444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2544452444
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3219594468
Short name T161
Test name
Test status
Simulation time 162125097 ps
CPU time 3.55 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 206540 kb
Host smart-a6ee22fc-0824-41c5-b5c1-a4f2fcd12022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219594468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3219594468
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2488553189
Short name T147
Test name
Test status
Simulation time 51599030 ps
CPU time 1.9 seconds
Started Aug 12 05:01:54 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 216956 kb
Host smart-115d33e1-0853-43c0-b876-e2d9e453c7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488553189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2488553189
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.713699010
Short name T139
Test name
Test status
Simulation time 414668060 ps
CPU time 11.66 seconds
Started Aug 12 05:01:27 PM PDT 24
Finished Aug 12 05:01:39 PM PDT 24
Peak memory 222964 kb
Host smart-2367795e-ad5c-4ac7-811b-0c507067e067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713699010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.713699010
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1867015655
Short name T78
Test name
Test status
Simulation time 49345303 ps
CPU time 2.87 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:02:38 PM PDT 24
Peak memory 207424 kb
Host smart-fb4ce6ac-309c-45f5-be8e-352e9d913ada
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867015655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1867015655
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2877663231
Short name T206
Test name
Test status
Simulation time 17438542459 ps
CPU time 72.26 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:03:49 PM PDT 24
Peak memory 216004 kb
Host smart-626a8978-b45b-49ad-9da6-3e1ee4ff17e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877663231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2877663231
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.579272176
Short name T141
Test name
Test status
Simulation time 91228148 ps
CPU time 4.81 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:23 PM PDT 24
Peak memory 219128 kb
Host smart-dff6682d-3bc4-4ef0-a26c-fe6a997f8fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579272176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.579272176
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4227976909
Short name T172
Test name
Test status
Simulation time 118999248 ps
CPU time 1.47 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:00:57 PM PDT 24
Peak memory 210152 kb
Host smart-709af80b-ab3b-4379-8769-134eeeefd00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227976909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4227976909
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1444360818
Short name T150
Test name
Test status
Simulation time 289847354 ps
CPU time 8.91 seconds
Started Aug 12 04:59:48 PM PDT 24
Finished Aug 12 04:59:57 PM PDT 24
Peak memory 215860 kb
Host smart-4195af39-e60f-48bd-8879-513e4b9c6496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444360818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1444360818
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2443897844
Short name T163
Test name
Test status
Simulation time 435971219 ps
CPU time 3.77 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 214456 kb
Host smart-f87e002e-a5dc-4a3c-835d-f55c420a21b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443897844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2443897844
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.159057047
Short name T157
Test name
Test status
Simulation time 515432184 ps
CPU time 4.06 seconds
Started Aug 12 04:59:49 PM PDT 24
Finished Aug 12 04:59:53 PM PDT 24
Peak memory 214368 kb
Host smart-662370b4-3c96-4219-80b1-93047f6380cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159057047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
159057047
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2865329661
Short name T162
Test name
Test status
Simulation time 107637790 ps
CPU time 5.47 seconds
Started Aug 12 04:59:56 PM PDT 24
Finished Aug 12 05:00:02 PM PDT 24
Peak memory 214420 kb
Host smart-9a062a13-74dd-45cd-8aba-666dad2adf3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865329661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2865329661
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1516066413
Short name T145
Test name
Test status
Simulation time 93032185 ps
CPU time 4.12 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:02:39 PM PDT 24
Peak memory 217924 kb
Host smart-cfcc6b52-2e92-4a0b-aa60-b35d84d217f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516066413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1516066413
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3668368277
Short name T359
Test name
Test status
Simulation time 271390836 ps
CPU time 3.55 seconds
Started Aug 12 05:00:54 PM PDT 24
Finished Aug 12 05:00:57 PM PDT 24
Peak memory 209552 kb
Host smart-a9ed28e0-a9bf-48dc-b66e-860c803b9d54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668368277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3668368277
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3446141934
Short name T377
Test name
Test status
Simulation time 245836665 ps
CPU time 3.38 seconds
Started Aug 12 05:01:11 PM PDT 24
Finished Aug 12 05:01:15 PM PDT 24
Peak memory 209776 kb
Host smart-4532b936-20fe-4cda-878d-5f8a8deca133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446141934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3446141934
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3095786072
Short name T304
Test name
Test status
Simulation time 52325121 ps
CPU time 3.38 seconds
Started Aug 12 05:01:17 PM PDT 24
Finished Aug 12 05:01:20 PM PDT 24
Peak memory 216084 kb
Host smart-9d79b02c-5e60-4c7c-9747-7dbed4d51473
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095786072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3095786072
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2904970988
Short name T282
Test name
Test status
Simulation time 45380122 ps
CPU time 2.29 seconds
Started Aug 12 05:01:32 PM PDT 24
Finished Aug 12 05:01:34 PM PDT 24
Peak memory 215004 kb
Host smart-97f1343f-2e54-45be-b51e-d9a8bb8bd7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904970988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2904970988
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3919635519
Short name T299
Test name
Test status
Simulation time 63226813 ps
CPU time 4.13 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:02:01 PM PDT 24
Peak memory 215876 kb
Host smart-ee17af3e-4981-48e3-b225-8e164b08c048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919635519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3919635519
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3160902681
Short name T40
Test name
Test status
Simulation time 504374267 ps
CPU time 4.09 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:02:47 PM PDT 24
Peak memory 222036 kb
Host smart-eba0c969-f1c9-457d-85e1-3825a07c688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160902681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3160902681
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.817548743
Short name T167
Test name
Test status
Simulation time 116696178 ps
CPU time 2.57 seconds
Started Aug 12 05:02:51 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 210696 kb
Host smart-aecf9a6f-60f9-4e50-b88e-9490326ccca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817548743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.817548743
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2621710559
Short name T142
Test name
Test status
Simulation time 118713662 ps
CPU time 3.04 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 218968 kb
Host smart-524a3509-9cf5-45b8-92e1-e1e182d7781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621710559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2621710559
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.139407284
Short name T64
Test name
Test status
Simulation time 84835438 ps
CPU time 3.93 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 218644 kb
Host smart-4e83cda1-c0ae-4715-ada5-3c23fe5a735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139407284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.139407284
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1052158470
Short name T144
Test name
Test status
Simulation time 185597217 ps
CPU time 5.4 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:23 PM PDT 24
Peak memory 218232 kb
Host smart-242950a8-ebca-4f53-bf96-d82743026557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052158470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1052158470
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3698121977
Short name T403
Test name
Test status
Simulation time 70858075 ps
CPU time 4.12 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 214780 kb
Host smart-8169ea12-c414-474b-af7f-2447b9182bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698121977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3698121977
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.298111518
Short name T72
Test name
Test status
Simulation time 294210577 ps
CPU time 17.68 seconds
Started Aug 12 05:00:55 PM PDT 24
Finished Aug 12 05:01:13 PM PDT 24
Peak memory 221720 kb
Host smart-56d42301-72bf-472d-b653-05dbe4644ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298111518 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.298111518
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2629795758
Short name T316
Test name
Test status
Simulation time 278413254 ps
CPU time 3.96 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 222736 kb
Host smart-4a8defdf-d043-4131-aecc-9d39a2b959eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629795758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2629795758
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2582392180
Short name T298
Test name
Test status
Simulation time 117440985 ps
CPU time 3.02 seconds
Started Aug 12 05:01:10 PM PDT 24
Finished Aug 12 05:01:13 PM PDT 24
Peak memory 209160 kb
Host smart-d7e93c2d-b04b-40d2-8eed-79dffc3a061a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582392180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2582392180
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1173730303
Short name T192
Test name
Test status
Simulation time 102445267 ps
CPU time 2.06 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:20 PM PDT 24
Peak memory 218816 kb
Host smart-678528d4-2d93-4e57-8515-0ea1c37935ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173730303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1173730303
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1782831307
Short name T868
Test name
Test status
Simulation time 767327333 ps
CPU time 27.15 seconds
Started Aug 12 05:01:24 PM PDT 24
Finished Aug 12 05:01:51 PM PDT 24
Peak memory 221488 kb
Host smart-e080f31c-2662-40e5-98f5-1a28f43715b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782831307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1782831307
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.503484211
Short name T882
Test name
Test status
Simulation time 11596802729 ps
CPU time 55.67 seconds
Started Aug 12 05:01:35 PM PDT 24
Finished Aug 12 05:02:31 PM PDT 24
Peak memory 223036 kb
Host smart-343bc417-c508-4f81-9f72-02c8cd21e16a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503484211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.503484211
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.560502661
Short name T350
Test name
Test status
Simulation time 199126742 ps
CPU time 2.93 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 214712 kb
Host smart-1a5121fc-0712-4ab2-b31e-b1dde6401db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560502661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.560502661
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1686154100
Short name T225
Test name
Test status
Simulation time 948190369 ps
CPU time 9.77 seconds
Started Aug 12 05:02:04 PM PDT 24
Finished Aug 12 05:02:14 PM PDT 24
Peak memory 222984 kb
Host smart-8e0f3f7e-99cc-4143-8f82-aa76046304d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686154100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1686154100
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3904576362
Short name T273
Test name
Test status
Simulation time 217750257 ps
CPU time 4.05 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:40 PM PDT 24
Peak memory 215488 kb
Host smart-5be1e62c-10c0-460a-b0d7-3b126b0a4c4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3904576362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3904576362
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1314351794
Short name T258
Test name
Test status
Simulation time 47717290 ps
CPU time 3.26 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:41 PM PDT 24
Peak memory 214748 kb
Host smart-a85f84f4-9e39-495d-a0d8-b3a61bbc5113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314351794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1314351794
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.4151487166
Short name T338
Test name
Test status
Simulation time 51993788 ps
CPU time 2.35 seconds
Started Aug 12 05:02:55 PM PDT 24
Finished Aug 12 05:02:57 PM PDT 24
Peak memory 215880 kb
Host smart-00730c50-84c6-4601-b1f6-614ba9492a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151487166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4151487166
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1523478874
Short name T86
Test name
Test status
Simulation time 382961133 ps
CPU time 7.37 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:26 PM PDT 24
Peak memory 222888 kb
Host smart-092f1d80-2411-483c-8fb7-c280ba7a4e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523478874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1523478874
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1037295612
Short name T326
Test name
Test status
Simulation time 253587151 ps
CPU time 10.05 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:16 PM PDT 24
Peak memory 216824 kb
Host smart-72f507cf-7b4d-4332-96ce-5e80546f82a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037295612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1037295612
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3056145667
Short name T171
Test name
Test status
Simulation time 58404593 ps
CPU time 2.67 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 215348 kb
Host smart-9d8da669-a54d-4da2-b448-1c10f91311e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056145667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3056145667
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1633022268
Short name T151
Test name
Test status
Simulation time 249841139 ps
CPU time 4.82 seconds
Started Aug 12 05:00:07 PM PDT 24
Finished Aug 12 05:00:13 PM PDT 24
Peak memory 214508 kb
Host smart-b655564b-d6f1-40b8-b0fb-57222f5cebca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633022268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1633022268
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3086570676
Short name T158
Test name
Test status
Simulation time 689739625 ps
CPU time 8.7 seconds
Started Aug 12 05:00:24 PM PDT 24
Finished Aug 12 05:00:33 PM PDT 24
Peak memory 214384 kb
Host smart-c000f8b9-84d0-4bd1-b42b-cada7e9611f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086570676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3086570676
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2193975763
Short name T156
Test name
Test status
Simulation time 235709728 ps
CPU time 3.05 seconds
Started Aug 12 04:59:48 PM PDT 24
Finished Aug 12 04:59:52 PM PDT 24
Peak memory 214428 kb
Host smart-c25fedee-8e64-4b55-a073-4f9b25b6dc6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193975763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2193975763
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2748652813
Short name T10
Test name
Test status
Simulation time 1046205729 ps
CPU time 16.46 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:01:07 PM PDT 24
Peak memory 231312 kb
Host smart-edf4b1b4-9663-465f-adc5-0bd4f7e86224
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748652813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2748652813
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3253384442
Short name T148
Test name
Test status
Simulation time 135863085 ps
CPU time 2.79 seconds
Started Aug 12 05:03:01 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 223112 kb
Host smart-6d65cafd-b7ae-46a3-9096-405e2d0cbc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253384442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3253384442
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3374932888
Short name T126
Test name
Test status
Simulation time 814302640 ps
CPU time 5.67 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:55 PM PDT 24
Peak memory 208416 kb
Host smart-eef283f3-3af6-40c7-8f64-6424a0359993
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374932888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3374932888
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3867730813
Short name T214
Test name
Test status
Simulation time 166760910 ps
CPU time 4.83 seconds
Started Aug 12 05:01:14 PM PDT 24
Finished Aug 12 05:01:19 PM PDT 24
Peak memory 221184 kb
Host smart-88ee6f0e-c9f4-4648-9f6c-f0054116f00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867730813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3867730813
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2048614669
Short name T198
Test name
Test status
Simulation time 630313074 ps
CPU time 7.74 seconds
Started Aug 12 05:01:13 PM PDT 24
Finished Aug 12 05:01:21 PM PDT 24
Peak memory 208984 kb
Host smart-f46357ea-15bf-469d-b1e3-0b22737b4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048614669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2048614669
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1011816548
Short name T369
Test name
Test status
Simulation time 165560258 ps
CPU time 2.03 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:21 PM PDT 24
Peak memory 214672 kb
Host smart-4d6207a4-9952-48ed-bddd-1c2efd5011ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011816548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1011816548
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3778823983
Short name T216
Test name
Test status
Simulation time 11109349419 ps
CPU time 68.68 seconds
Started Aug 12 05:01:39 PM PDT 24
Finished Aug 12 05:02:48 PM PDT 24
Peak memory 209716 kb
Host smart-c7692206-b3e0-49ff-af0b-4de56eb63923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778823983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3778823983
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3622205308
Short name T220
Test name
Test status
Simulation time 178755961 ps
CPU time 3.83 seconds
Started Aug 12 05:01:51 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 217772 kb
Host smart-1e843c96-c684-4ebd-b2a9-b3fc5631b133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622205308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3622205308
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2237554179
Short name T586
Test name
Test status
Simulation time 286830944 ps
CPU time 3.01 seconds
Started Aug 12 05:01:50 PM PDT 24
Finished Aug 12 05:01:53 PM PDT 24
Peak memory 211152 kb
Host smart-4d72e29c-481c-48e0-b38c-22bdef7cf319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237554179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2237554179
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2831180429
Short name T314
Test name
Test status
Simulation time 890336083 ps
CPU time 17.4 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:02:02 PM PDT 24
Peak memory 223056 kb
Host smart-1927344b-ac5d-428d-a8f5-9ca9a0f8582a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831180429 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2831180429
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4001909921
Short name T87
Test name
Test status
Simulation time 217189492 ps
CPU time 5.68 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 210140 kb
Host smart-49c24e79-8009-4fea-85db-55f414527ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001909921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4001909921
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3139605557
Short name T456
Test name
Test status
Simulation time 4466572252 ps
CPU time 27.87 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:01:21 PM PDT 24
Peak memory 214972 kb
Host smart-898049be-e75e-42b7-92de-04de2533314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139605557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3139605557
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.631989680
Short name T215
Test name
Test status
Simulation time 1265199334 ps
CPU time 36.67 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:02:25 PM PDT 24
Peak memory 222912 kb
Host smart-298be48c-de4f-4e0e-8d7b-cedd333c6c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631989680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.631989680
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.467726001
Short name T204
Test name
Test status
Simulation time 155414564 ps
CPU time 2.05 seconds
Started Aug 12 05:01:57 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 220360 kb
Host smart-3cd342d7-1975-43d9-9e8d-40844be7e258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467726001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.467726001
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.897520701
Short name T362
Test name
Test status
Simulation time 400871277 ps
CPU time 19.69 seconds
Started Aug 12 05:02:02 PM PDT 24
Finished Aug 12 05:02:22 PM PDT 24
Peak memory 216936 kb
Host smart-84955419-1f17-4f38-8c2a-30089f079653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897520701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.897520701
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2174991519
Short name T28
Test name
Test status
Simulation time 51656711 ps
CPU time 2.62 seconds
Started Aug 12 05:02:01 PM PDT 24
Finished Aug 12 05:02:04 PM PDT 24
Peak memory 214716 kb
Host smart-b040acc7-4609-4a30-af83-9f5bb466d45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174991519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2174991519
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4069298069
Short name T212
Test name
Test status
Simulation time 115839227 ps
CPU time 3.32 seconds
Started Aug 12 05:02:04 PM PDT 24
Finished Aug 12 05:02:08 PM PDT 24
Peak memory 210684 kb
Host smart-a67221d4-c145-4d6e-8288-7688fb42aa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069298069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4069298069
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1971391870
Short name T322
Test name
Test status
Simulation time 33431883 ps
CPU time 2.7 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 214768 kb
Host smart-0f2a717e-609e-47cc-8c53-5e1eaaa2b039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971391870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1971391870
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3165200523
Short name T317
Test name
Test status
Simulation time 35243116 ps
CPU time 2.1 seconds
Started Aug 12 05:02:16 PM PDT 24
Finished Aug 12 05:02:18 PM PDT 24
Peak memory 207160 kb
Host smart-6a57106d-4e70-4f2f-94d6-ad5cd17a85e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165200523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3165200523
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3645968760
Short name T209
Test name
Test status
Simulation time 2601927424 ps
CPU time 25.34 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:38 PM PDT 24
Peak memory 222940 kb
Host smart-d1044cc0-3bc9-4f45-be32-f9df1418cf4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645968760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3645968760
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1689472960
Short name T207
Test name
Test status
Simulation time 336031821 ps
CPU time 3.78 seconds
Started Aug 12 05:02:24 PM PDT 24
Finished Aug 12 05:02:28 PM PDT 24
Peak memory 219144 kb
Host smart-ed76a44b-97b3-4f9f-ba72-ce434fd5a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689472960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1689472960
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3450745672
Short name T203
Test name
Test status
Simulation time 60847545 ps
CPU time 3.68 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:02:46 PM PDT 24
Peak memory 220820 kb
Host smart-e7db989a-1127-4312-99d2-5c76d53432d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450745672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3450745672
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1836566018
Short name T240
Test name
Test status
Simulation time 948556528 ps
CPU time 28.28 seconds
Started Aug 12 05:02:44 PM PDT 24
Finished Aug 12 05:03:12 PM PDT 24
Peak memory 215240 kb
Host smart-64894294-03c6-4c22-9fb8-55f64bfd891e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836566018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1836566018
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3694962241
Short name T969
Test name
Test status
Simulation time 963251371 ps
CPU time 8.02 seconds
Started Aug 12 04:59:46 PM PDT 24
Finished Aug 12 04:59:54 PM PDT 24
Peak memory 206056 kb
Host smart-d272b5a7-eed1-41d2-adf3-a6aeb6c1bdd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694962241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
694962241
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.481344675
Short name T1077
Test name
Test status
Simulation time 611847895 ps
CPU time 6.1 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 04:59:56 PM PDT 24
Peak memory 206144 kb
Host smart-eb0956cd-3032-462f-afa3-a1ae44af19b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481344675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.481344675
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3443548730
Short name T182
Test name
Test status
Simulation time 118128379 ps
CPU time 1.12 seconds
Started Aug 12 04:59:48 PM PDT 24
Finished Aug 12 04:59:49 PM PDT 24
Peak memory 206188 kb
Host smart-40ea6c63-0210-4d79-a76c-96df6d145e18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443548730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
443548730
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2935183514
Short name T1012
Test name
Test status
Simulation time 33401268 ps
CPU time 1.27 seconds
Started Aug 12 04:59:43 PM PDT 24
Finished Aug 12 04:59:44 PM PDT 24
Peak memory 214336 kb
Host smart-6515895d-68ca-4171-a703-6596e9df0411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935183514 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2935183514
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1228929357
Short name T1028
Test name
Test status
Simulation time 14219507 ps
CPU time 1.2 seconds
Started Aug 12 04:59:48 PM PDT 24
Finished Aug 12 04:59:49 PM PDT 24
Peak memory 206192 kb
Host smart-fb793e7b-bd6e-4525-b4c0-4afb47d4dee2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228929357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1228929357
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1064864886
Short name T932
Test name
Test status
Simulation time 24042107 ps
CPU time 0.85 seconds
Started Aug 12 04:59:43 PM PDT 24
Finished Aug 12 04:59:44 PM PDT 24
Peak memory 205796 kb
Host smart-eb3cd9f7-975a-4b3c-af97-6d7bc3db66e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064864886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1064864886
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1440074673
Short name T965
Test name
Test status
Simulation time 50210028 ps
CPU time 1.64 seconds
Started Aug 12 04:59:45 PM PDT 24
Finished Aug 12 04:59:47 PM PDT 24
Peak memory 206212 kb
Host smart-37e632e6-b6ce-4736-b638-232aaa662192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440074673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1440074673
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3565737274
Short name T1034
Test name
Test status
Simulation time 523303155 ps
CPU time 3.97 seconds
Started Aug 12 04:59:44 PM PDT 24
Finished Aug 12 04:59:48 PM PDT 24
Peak memory 214800 kb
Host smart-15dad36e-f6c8-4e80-8ea5-a3b80a02ee2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565737274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3565737274
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2500936947
Short name T997
Test name
Test status
Simulation time 1506594997 ps
CPU time 5.11 seconds
Started Aug 12 04:59:43 PM PDT 24
Finished Aug 12 04:59:48 PM PDT 24
Peak memory 220520 kb
Host smart-6d8c931f-4b45-421a-9bdb-84f776f6d590
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500936947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2500936947
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.832286825
Short name T1006
Test name
Test status
Simulation time 188299604 ps
CPU time 3.13 seconds
Started Aug 12 04:59:42 PM PDT 24
Finished Aug 12 04:59:45 PM PDT 24
Peak memory 216760 kb
Host smart-e4c310b5-504a-43f5-b8bf-c4ff96a47bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832286825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.832286825
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3869530659
Short name T381
Test name
Test status
Simulation time 403675605 ps
CPU time 5.72 seconds
Started Aug 12 04:59:43 PM PDT 24
Finished Aug 12 04:59:49 PM PDT 24
Peak memory 214344 kb
Host smart-f89843b5-674f-43a4-b720-eb40230c72ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869530659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3869530659
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.598861599
Short name T1045
Test name
Test status
Simulation time 70791300 ps
CPU time 4.22 seconds
Started Aug 12 04:59:47 PM PDT 24
Finished Aug 12 04:59:51 PM PDT 24
Peak memory 206244 kb
Host smart-8f03554e-bdec-478f-82e4-0c62b1a12523
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598861599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.598861599
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2930727301
Short name T980
Test name
Test status
Simulation time 25552480089 ps
CPU time 41.19 seconds
Started Aug 12 04:59:45 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 206268 kb
Host smart-8cb3cf4d-cb99-4045-8366-62ff10d4456b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930727301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
930727301
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1097362219
Short name T995
Test name
Test status
Simulation time 34353432 ps
CPU time 1.47 seconds
Started Aug 12 04:59:48 PM PDT 24
Finished Aug 12 04:59:50 PM PDT 24
Peak memory 206112 kb
Host smart-573eb68a-d42b-4f43-9103-2d3439d090a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097362219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
097362219
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1439940687
Short name T181
Test name
Test status
Simulation time 351821404 ps
CPU time 1.6 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 04:59:52 PM PDT 24
Peak memory 217084 kb
Host smart-9a38e7aa-5797-4ceb-8aec-691207ebcbef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439940687 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1439940687
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2638345929
Short name T1040
Test name
Test status
Simulation time 90041892 ps
CPU time 1.36 seconds
Started Aug 12 04:59:49 PM PDT 24
Finished Aug 12 04:59:51 PM PDT 24
Peak memory 206132 kb
Host smart-418450b4-7fac-4904-bee4-501484543d1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638345929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2638345929
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3467423152
Short name T1027
Test name
Test status
Simulation time 21220563 ps
CPU time 0.85 seconds
Started Aug 12 04:59:42 PM PDT 24
Finished Aug 12 04:59:43 PM PDT 24
Peak memory 205908 kb
Host smart-313c1e62-4711-448c-8475-994d39a53a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467423152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3467423152
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.99396214
Short name T954
Test name
Test status
Simulation time 302053768 ps
CPU time 1.73 seconds
Started Aug 12 04:59:51 PM PDT 24
Finished Aug 12 04:59:53 PM PDT 24
Peak memory 206136 kb
Host smart-86245538-f372-48f8-9c93-533f8b345849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99396214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same
_csr_outstanding.99396214
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1808334500
Short name T950
Test name
Test status
Simulation time 257904934 ps
CPU time 2.73 seconds
Started Aug 12 04:59:43 PM PDT 24
Finished Aug 12 04:59:46 PM PDT 24
Peak memory 214668 kb
Host smart-f51d7aca-38e4-4f12-910d-b15287ddfacb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808334500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1808334500
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2300162017
Short name T1044
Test name
Test status
Simulation time 515933920 ps
CPU time 15.26 seconds
Started Aug 12 04:59:42 PM PDT 24
Finished Aug 12 04:59:57 PM PDT 24
Peak memory 214660 kb
Host smart-c4072ef7-164a-4144-a200-5938a696222d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300162017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2300162017
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4266011555
Short name T974
Test name
Test status
Simulation time 85474382 ps
CPU time 1.3 seconds
Started Aug 12 04:59:44 PM PDT 24
Finished Aug 12 04:59:46 PM PDT 24
Peak memory 214484 kb
Host smart-3a77749b-7b64-4c0c-b5d9-c0b9d43cf841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266011555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4266011555
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1863064597
Short name T963
Test name
Test status
Simulation time 43685509 ps
CPU time 1.57 seconds
Started Aug 12 05:00:07 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 214500 kb
Host smart-77d23d19-78af-4913-a900-8ade0b57bded
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863064597 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1863064597
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.394576601
Short name T1048
Test name
Test status
Simulation time 69426861 ps
CPU time 1.23 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 206196 kb
Host smart-f3edb21e-4bca-41bc-92e3-85d5ded7520a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394576601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.394576601
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1323771981
Short name T1063
Test name
Test status
Simulation time 12638246 ps
CPU time 0.86 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:08 PM PDT 24
Peak memory 205964 kb
Host smart-75a1c9e5-ba22-4e1c-8e2b-9c82497ad87d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323771981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1323771981
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3910616883
Short name T992
Test name
Test status
Simulation time 131074464 ps
CPU time 4.19 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 206160 kb
Host smart-7b39c725-9eab-4dea-8674-adeb905cde7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910616883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3910616883
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.571955818
Short name T108
Test name
Test status
Simulation time 295726770 ps
CPU time 2.46 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 214936 kb
Host smart-b45333cd-11d2-4ba2-922f-7f52558447db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571955818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.571955818
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.4129508074
Short name T1003
Test name
Test status
Simulation time 87109644 ps
CPU time 3.86 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 214732 kb
Host smart-cff63d86-7096-4ef3-ab35-60a4597df867
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129508074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.4129508074
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2041980309
Short name T1073
Test name
Test status
Simulation time 82709800 ps
CPU time 3.21 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 214404 kb
Host smart-cc05c212-4779-4a8a-8cce-46180c8f9042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041980309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2041980309
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2697469880
Short name T1005
Test name
Test status
Simulation time 127838604 ps
CPU time 3.5 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 214292 kb
Host smart-808d7c77-fd05-46e7-82e4-6a60e19b59e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697469880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2697469880
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1416021105
Short name T957
Test name
Test status
Simulation time 45812759 ps
CPU time 1.73 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 214412 kb
Host smart-2a9d33e2-69a2-49a1-8c74-827d0b8139de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416021105 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1416021105
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2899472517
Short name T1062
Test name
Test status
Simulation time 34884963 ps
CPU time 0.96 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 205880 kb
Host smart-530712c8-bcb2-46aa-ae8c-1f4d2297403a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899472517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2899472517
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.243746672
Short name T1069
Test name
Test status
Simulation time 40561079 ps
CPU time 0.76 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:08 PM PDT 24
Peak memory 205980 kb
Host smart-9354aec7-3975-4fe9-aa81-43c0cbfd9962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243746672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.243746672
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1145198582
Short name T962
Test name
Test status
Simulation time 25569756 ps
CPU time 1.45 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 206152 kb
Host smart-25aeafb7-7948-4090-b242-9288369d527f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145198582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1145198582
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.398569906
Short name T1039
Test name
Test status
Simulation time 50988342 ps
CPU time 2.15 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 214760 kb
Host smart-32ac8ac1-b822-4892-8df6-481b0cda9e9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398569906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.398569906
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2744377115
Short name T109
Test name
Test status
Simulation time 4803281765 ps
CPU time 7.83 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:16 PM PDT 24
Peak memory 214820 kb
Host smart-ad0575ee-94ea-4ebb-87ba-5d1dcd54e029
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744377115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2744377115
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1140142317
Short name T986
Test name
Test status
Simulation time 86291908 ps
CPU time 3.16 seconds
Started Aug 12 05:00:07 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 214524 kb
Host smart-e83e4e05-f866-4fdb-8924-bdbc0f9f12aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140142317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1140142317
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4107714587
Short name T174
Test name
Test status
Simulation time 166310614 ps
CPU time 4.72 seconds
Started Aug 12 05:00:09 PM PDT 24
Finished Aug 12 05:00:14 PM PDT 24
Peak memory 206288 kb
Host smart-f2a46a8e-c399-473b-b44d-c6339de70013
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107714587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.4107714587
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1359061386
Short name T1068
Test name
Test status
Simulation time 167703947 ps
CPU time 1.27 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 206296 kb
Host smart-11593ba6-e236-4fa5-a9a3-1343777f2c4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359061386 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1359061386
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4156071116
Short name T975
Test name
Test status
Simulation time 71360266 ps
CPU time 0.93 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 205924 kb
Host smart-de3f6ffd-cff4-4ca7-8d63-f90b18538ccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156071116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4156071116
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3675013650
Short name T1011
Test name
Test status
Simulation time 36650932 ps
CPU time 0.68 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 205996 kb
Host smart-db3b139f-fc88-4879-ad78-49e3848e1519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675013650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3675013650
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2523592763
Short name T133
Test name
Test status
Simulation time 78752419 ps
CPU time 1.52 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 206148 kb
Host smart-acfb5d6d-1109-43bf-a58c-fac9ed183d2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523592763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2523592763
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1612926580
Short name T1008
Test name
Test status
Simulation time 365319779 ps
CPU time 3.49 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 214712 kb
Host smart-7770ca75-cb65-4f5f-ba48-289cc77fffab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612926580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1612926580
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1471778957
Short name T955
Test name
Test status
Simulation time 911267260 ps
CPU time 7.94 seconds
Started Aug 12 05:00:02 PM PDT 24
Finished Aug 12 05:00:16 PM PDT 24
Peak memory 214692 kb
Host smart-c5f68c9d-776f-4c76-87e8-d1d5bb78a3fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471778957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1471778957
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.572018890
Short name T917
Test name
Test status
Simulation time 90515547 ps
CPU time 2.48 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 214480 kb
Host smart-4a1f8882-e642-4ac3-85d8-017fec293c35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572018890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.572018890
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1030727646
Short name T999
Test name
Test status
Simulation time 30303360 ps
CPU time 1.25 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 214480 kb
Host smart-ce14fa4a-ab2e-4b07-b64d-36a52de0f6f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030727646 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1030727646
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.770370830
Short name T135
Test name
Test status
Simulation time 35509801 ps
CPU time 1.09 seconds
Started Aug 12 05:00:02 PM PDT 24
Finished Aug 12 05:00:08 PM PDT 24
Peak memory 206192 kb
Host smart-999a77aa-a43e-4254-97c0-8f6669101262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770370830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.770370830
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.359151003
Short name T922
Test name
Test status
Simulation time 9129501 ps
CPU time 0.73 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 205864 kb
Host smart-737c4f00-cbd0-4bcb-a6ee-4fd2274667f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359151003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.359151003
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1620174208
Short name T138
Test name
Test status
Simulation time 406746990 ps
CPU time 3.41 seconds
Started Aug 12 05:00:02 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 206152 kb
Host smart-ee9301d9-44a4-41b8-8644-bcd0a298851d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620174208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1620174208
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.866653671
Short name T953
Test name
Test status
Simulation time 183789780 ps
CPU time 4.96 seconds
Started Aug 12 05:00:02 PM PDT 24
Finished Aug 12 05:00:13 PM PDT 24
Peak memory 214708 kb
Host smart-c6a5d2e8-8860-40ce-9723-c62113c21bff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866653671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.866653671
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3215843114
Short name T1053
Test name
Test status
Simulation time 343166549 ps
CPU time 6.99 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:15 PM PDT 24
Peak memory 214864 kb
Host smart-b100f333-f762-4295-bc79-c1c458af57a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215843114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3215843114
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2888099061
Short name T935
Test name
Test status
Simulation time 58314903 ps
CPU time 1.81 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 222508 kb
Host smart-585a10f0-f424-405d-b29d-0d39b8a6796c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888099061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2888099061
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2857407904
Short name T1078
Test name
Test status
Simulation time 113125484 ps
CPU time 1.84 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 218356 kb
Host smart-13dac430-fd89-4549-9606-4dfcba94381b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857407904 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2857407904
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1339927345
Short name T1065
Test name
Test status
Simulation time 23585010 ps
CPU time 1.03 seconds
Started Aug 12 05:00:06 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 205916 kb
Host smart-3edf2402-b424-4ebc-9261-cb3a6d038785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339927345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1339927345
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.530289721
Short name T985
Test name
Test status
Simulation time 147431905 ps
CPU time 0.8 seconds
Started Aug 12 05:00:06 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 205936 kb
Host smart-481d6890-de18-4d89-9396-a6e29bd58d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530289721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.530289721
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.869441711
Short name T989
Test name
Test status
Simulation time 177911216 ps
CPU time 1.78 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 206200 kb
Host smart-5926dc3b-3e71-46ab-84b8-137e95c183d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869441711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.869441711
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1387392823
Short name T949
Test name
Test status
Simulation time 138811721 ps
CPU time 1.58 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 214724 kb
Host smart-94526260-3448-49f3-b598-236429c73bed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387392823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1387392823
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.899412433
Short name T1036
Test name
Test status
Simulation time 691616122 ps
CPU time 9.75 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:17 PM PDT 24
Peak memory 220800 kb
Host smart-446eea52-93f3-480d-8fab-92fd25e19d28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899412433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.899412433
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.201351270
Short name T1050
Test name
Test status
Simulation time 49802966 ps
CPU time 3.1 seconds
Started Aug 12 05:00:06 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 214448 kb
Host smart-1aafe3b1-670e-45dd-bed1-ab6894524f44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201351270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.201351270
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1260851472
Short name T183
Test name
Test status
Simulation time 52802892 ps
CPU time 1.22 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 206284 kb
Host smart-b0b97be2-34c4-47bc-9fc1-156b376a5781
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260851472 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1260851472
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.715552878
Short name T1007
Test name
Test status
Simulation time 67073891 ps
CPU time 1.09 seconds
Started Aug 12 05:00:02 PM PDT 24
Finished Aug 12 05:00:08 PM PDT 24
Peak memory 206028 kb
Host smart-8c084c85-cdc5-4707-b788-1a42b5891f00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715552878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.715552878
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.577543201
Short name T942
Test name
Test status
Simulation time 9893225 ps
CPU time 0.71 seconds
Started Aug 12 05:00:07 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 205784 kb
Host smart-5b43ba75-5a8f-49c1-8b47-0a42699f2588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577543201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.577543201
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2122412679
Short name T1041
Test name
Test status
Simulation time 107905104 ps
CPU time 1.9 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 206236 kb
Host smart-9b8f70d5-8cea-4f7e-aa0a-127210aa9bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122412679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2122412679
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4129404762
Short name T136
Test name
Test status
Simulation time 223710673 ps
CPU time 7.58 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:15 PM PDT 24
Peak memory 214688 kb
Host smart-e474f174-c69c-4331-8bae-153e9d667475
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129404762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4129404762
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1758081145
Short name T984
Test name
Test status
Simulation time 97733530 ps
CPU time 2.57 seconds
Started Aug 12 05:00:03 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 214476 kb
Host smart-75e911fa-9936-4685-b7ae-6bd0b4eb3ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758081145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1758081145
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4002510041
Short name T1080
Test name
Test status
Simulation time 114207745 ps
CPU time 3.67 seconds
Started Aug 12 05:00:04 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 214332 kb
Host smart-b25c8a45-6d33-4123-a65f-25e22d10cdd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002510041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4002510041
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2142880346
Short name T1024
Test name
Test status
Simulation time 118392030 ps
CPU time 1.33 seconds
Started Aug 12 05:00:09 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 214456 kb
Host smart-44f38de2-f133-4883-8740-a3cda4b2798e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142880346 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2142880346
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1271584055
Short name T137
Test name
Test status
Simulation time 27210994 ps
CPU time 1.19 seconds
Started Aug 12 05:00:06 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 206176 kb
Host smart-ceec0f25-fd93-44b5-8a46-51c7882d934e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271584055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1271584055
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1766196602
Short name T925
Test name
Test status
Simulation time 10370083 ps
CPU time 0.74 seconds
Started Aug 12 05:00:10 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 205888 kb
Host smart-0964b801-5133-4ec9-9a7a-6b3ca2f4cdf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766196602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1766196602
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3603273376
Short name T939
Test name
Test status
Simulation time 88526153 ps
CPU time 1.42 seconds
Started Aug 12 05:00:06 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 206140 kb
Host smart-4828b02d-40d9-4267-8ef3-6828521f662b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603273376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3603273376
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3653916553
Short name T1075
Test name
Test status
Simulation time 177278423 ps
CPU time 3.59 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 214712 kb
Host smart-280d7010-00cc-4d7a-9903-b7d631dbc9a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653916553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3653916553
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2293512647
Short name T1016
Test name
Test status
Simulation time 789066114 ps
CPU time 14.15 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:22 PM PDT 24
Peak memory 214784 kb
Host smart-98a3c097-8741-4f8f-bbe8-4f6cb0c728de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293512647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2293512647
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1364590455
Short name T1066
Test name
Test status
Simulation time 605853112 ps
CPU time 3.87 seconds
Started Aug 12 05:00:10 PM PDT 24
Finished Aug 12 05:00:15 PM PDT 24
Peak memory 214464 kb
Host smart-d441386c-05b2-4738-83d4-b1a7741bb69c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364590455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1364590455
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.360992770
Short name T1046
Test name
Test status
Simulation time 361324298 ps
CPU time 2.13 seconds
Started Aug 12 05:00:14 PM PDT 24
Finished Aug 12 05:00:17 PM PDT 24
Peak memory 213928 kb
Host smart-9c7c7c92-b24a-4e01-85ea-b2ed8c9dcb11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360992770 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.360992770
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2289283606
Short name T987
Test name
Test status
Simulation time 19788486 ps
CPU time 0.95 seconds
Started Aug 12 05:00:10 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 205884 kb
Host smart-57a70006-5eb9-413e-bd23-216fc8cd7326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289283606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2289283606
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.546393299
Short name T1061
Test name
Test status
Simulation time 69605954 ps
CPU time 0.74 seconds
Started Aug 12 05:00:09 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 205868 kb
Host smart-60edcd2d-9459-4335-aed5-cb6fb5dd6e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546393299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.546393299
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1481220646
Short name T960
Test name
Test status
Simulation time 22881938 ps
CPU time 1.69 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 206152 kb
Host smart-63f04b23-a716-4b27-b223-d424b8aef95b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481220646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1481220646
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3232697629
Short name T951
Test name
Test status
Simulation time 143712059 ps
CPU time 2.53 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 214708 kb
Host smart-0f2b643d-cd42-42aa-b545-bf671028ac7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232697629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3232697629
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3630158613
Short name T994
Test name
Test status
Simulation time 316697892 ps
CPU time 3.76 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 214720 kb
Host smart-b13ffea4-43a7-4865-83ca-a4e8931a9e0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630158613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3630158613
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.95644148
Short name T938
Test name
Test status
Simulation time 778586243 ps
CPU time 2.19 seconds
Started Aug 12 05:00:06 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 214392 kb
Host smart-11510116-c93a-49da-927f-ec50b5d9f35f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95644148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.95644148
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3501093354
Short name T940
Test name
Test status
Simulation time 44965511 ps
CPU time 1.37 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 214436 kb
Host smart-0b850a1d-c1a4-4c7e-af49-186425ace3b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501093354 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3501093354
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3645452703
Short name T131
Test name
Test status
Simulation time 42430517 ps
CPU time 0.96 seconds
Started Aug 12 05:00:13 PM PDT 24
Finished Aug 12 05:00:14 PM PDT 24
Peak memory 206056 kb
Host smart-df3d9c46-6331-448c-8f6b-b90e15a44c39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645452703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3645452703
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3305759789
Short name T947
Test name
Test status
Simulation time 36812066 ps
CPU time 0.71 seconds
Started Aug 12 05:00:17 PM PDT 24
Finished Aug 12 05:00:18 PM PDT 24
Peak memory 205920 kb
Host smart-a0bd9ef8-a311-4db4-9001-f69651ea67a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305759789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3305759789
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.452118344
Short name T948
Test name
Test status
Simulation time 287015940 ps
CPU time 1.53 seconds
Started Aug 12 05:00:10 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 206208 kb
Host smart-041782db-8a56-4465-ba0e-6b5e72747837
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452118344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.452118344
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.434079252
Short name T1074
Test name
Test status
Simulation time 140691786 ps
CPU time 1.92 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:13 PM PDT 24
Peak memory 214636 kb
Host smart-e1d999ea-8ce7-4fae-9e5f-5dfd48a87c4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434079252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.434079252
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2645428600
Short name T943
Test name
Test status
Simulation time 260502245 ps
CPU time 3.4 seconds
Started Aug 12 05:00:10 PM PDT 24
Finished Aug 12 05:00:13 PM PDT 24
Peak memory 221052 kb
Host smart-48dc5121-c0f6-48be-b523-416575c2fed9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645428600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2645428600
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1028433528
Short name T919
Test name
Test status
Simulation time 114675655 ps
CPU time 2.64 seconds
Started Aug 12 05:00:13 PM PDT 24
Finished Aug 12 05:00:15 PM PDT 24
Peak memory 214412 kb
Host smart-36622220-eeed-42a9-aa84-d62ca190c295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028433528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1028433528
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3110399094
Short name T1071
Test name
Test status
Simulation time 731327377 ps
CPU time 6.15 seconds
Started Aug 12 05:00:13 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 214344 kb
Host smart-bb986c90-8e50-4936-aeb8-2eb7c1ae118a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110399094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3110399094
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1753491417
Short name T968
Test name
Test status
Simulation time 106265520 ps
CPU time 1.64 seconds
Started Aug 12 05:00:12 PM PDT 24
Finished Aug 12 05:00:14 PM PDT 24
Peak memory 214488 kb
Host smart-a9881348-2233-4931-b62d-7a49fb8bd09a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753491417 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1753491417
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3252874847
Short name T1079
Test name
Test status
Simulation time 75840878 ps
CPU time 1.16 seconds
Started Aug 12 05:00:22 PM PDT 24
Finished Aug 12 05:00:23 PM PDT 24
Peak memory 206232 kb
Host smart-bcb51d5b-1af1-4c39-a5d0-d979f76f924f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252874847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3252874847
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.331949605
Short name T1035
Test name
Test status
Simulation time 18040310 ps
CPU time 0.85 seconds
Started Aug 12 05:00:12 PM PDT 24
Finished Aug 12 05:00:13 PM PDT 24
Peak memory 205984 kb
Host smart-1130e54e-d065-4316-89b1-c40583c4e78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331949605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.331949605
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3434770695
Short name T1072
Test name
Test status
Simulation time 177961704 ps
CPU time 1.52 seconds
Started Aug 12 05:00:12 PM PDT 24
Finished Aug 12 05:00:13 PM PDT 24
Peak memory 206156 kb
Host smart-aefb64f8-e78f-43f1-a915-4d5a610c1b93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434770695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3434770695
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.506633236
Short name T115
Test name
Test status
Simulation time 267017278 ps
CPU time 4.24 seconds
Started Aug 12 05:00:12 PM PDT 24
Finished Aug 12 05:00:16 PM PDT 24
Peak memory 214716 kb
Host smart-7ae2966c-0bb7-4c8c-8219-cd3a9502e338
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506633236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.506633236
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.517640128
Short name T1033
Test name
Test status
Simulation time 202698196 ps
CPU time 5.09 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:17 PM PDT 24
Peak memory 214756 kb
Host smart-580c35d5-db29-42b3-9aa8-e8af01223dad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517640128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.517640128
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1305115449
Short name T1052
Test name
Test status
Simulation time 97613773 ps
CPU time 2.98 seconds
Started Aug 12 05:00:13 PM PDT 24
Finished Aug 12 05:00:16 PM PDT 24
Peak memory 214412 kb
Host smart-dd1a0efb-4fb3-4f4e-b6cb-9ca258dee77e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305115449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1305115449
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3148566630
Short name T990
Test name
Test status
Simulation time 743470350 ps
CPU time 7.74 seconds
Started Aug 12 04:59:52 PM PDT 24
Finished Aug 12 05:00:00 PM PDT 24
Peak memory 206212 kb
Host smart-3cabb99a-3ef2-4ba8-96e5-679149b26e32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148566630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
148566630
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.732542669
Short name T191
Test name
Test status
Simulation time 2619408441 ps
CPU time 31.17 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 05:00:21 PM PDT 24
Peak memory 206252 kb
Host smart-ce3671eb-4e5c-4df9-ad88-9ac6f1c5208d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732542669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.732542669
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2366440816
Short name T941
Test name
Test status
Simulation time 15630887 ps
CPU time 1.03 seconds
Started Aug 12 04:59:52 PM PDT 24
Finished Aug 12 04:59:53 PM PDT 24
Peak memory 206068 kb
Host smart-35c3a74c-2a81-4c1d-9975-30236b8b1e0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366440816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
366440816
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2431033950
Short name T1021
Test name
Test status
Simulation time 118877297 ps
CPU time 2.11 seconds
Started Aug 12 04:59:53 PM PDT 24
Finished Aug 12 04:59:56 PM PDT 24
Peak memory 219912 kb
Host smart-5ab74a74-3935-4caa-a20e-aae362cbf2b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431033950 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2431033950
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1744224610
Short name T1037
Test name
Test status
Simulation time 118407208 ps
CPU time 1.23 seconds
Started Aug 12 04:59:53 PM PDT 24
Finished Aug 12 04:59:55 PM PDT 24
Peak memory 206212 kb
Host smart-4d65e378-b510-4bbc-8d4e-043f6c41bc04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744224610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1744224610
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2073048622
Short name T983
Test name
Test status
Simulation time 10492285 ps
CPU time 0.81 seconds
Started Aug 12 04:59:49 PM PDT 24
Finished Aug 12 04:59:50 PM PDT 24
Peak memory 205864 kb
Host smart-a2edbe40-c6c7-4c86-ae4b-effc732cd46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073048622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2073048622
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1816701769
Short name T1055
Test name
Test status
Simulation time 48662413 ps
CPU time 1.71 seconds
Started Aug 12 04:59:52 PM PDT 24
Finished Aug 12 04:59:54 PM PDT 24
Peak memory 206220 kb
Host smart-3d7f8684-27b5-4fce-874c-e8a1bfe1839c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816701769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1816701769
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.634095112
Short name T967
Test name
Test status
Simulation time 149250384 ps
CPU time 2.65 seconds
Started Aug 12 04:59:54 PM PDT 24
Finished Aug 12 04:59:57 PM PDT 24
Peak memory 214656 kb
Host smart-a4ef0642-f1ec-44b5-b695-52e92e2429e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634095112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.634095112
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3844926743
Short name T1000
Test name
Test status
Simulation time 1740425678 ps
CPU time 11.03 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 05:00:01 PM PDT 24
Peak memory 214612 kb
Host smart-9dd55287-6a30-4aa0-9f7b-5e6736b196d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844926743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3844926743
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.893216383
Short name T936
Test name
Test status
Simulation time 145947071 ps
CPU time 3.23 seconds
Started Aug 12 04:59:51 PM PDT 24
Finished Aug 12 04:59:55 PM PDT 24
Peak memory 215932 kb
Host smart-b57ac95b-9356-47d4-a7d7-80fab9617ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893216383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.893216383
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.573169492
Short name T159
Test name
Test status
Simulation time 171767533 ps
CPU time 2.89 seconds
Started Aug 12 04:59:51 PM PDT 24
Finished Aug 12 04:59:54 PM PDT 24
Peak memory 214416 kb
Host smart-51721b45-64bb-4e5c-b947-d159c6627649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573169492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
573169492
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4091335546
Short name T1032
Test name
Test status
Simulation time 20379992 ps
CPU time 0.74 seconds
Started Aug 12 05:00:10 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 205904 kb
Host smart-e16e3d71-a6f1-43eb-9c77-fced335de662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091335546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.4091335546
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.266535626
Short name T918
Test name
Test status
Simulation time 14686323 ps
CPU time 0.75 seconds
Started Aug 12 05:00:10 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 205988 kb
Host smart-ef3be7cd-140e-46bf-b704-17ec06d7ebd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266535626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.266535626
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3759903659
Short name T1056
Test name
Test status
Simulation time 13000037 ps
CPU time 0.83 seconds
Started Aug 12 05:00:09 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 205960 kb
Host smart-c107289c-69a3-4de1-adc9-280ba956dce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759903659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3759903659
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3465103081
Short name T933
Test name
Test status
Simulation time 24975861 ps
CPU time 0.71 seconds
Started Aug 12 05:00:09 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 205920 kb
Host smart-d08c62dc-83ac-432f-8d85-22306b076daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465103081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3465103081
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.581719778
Short name T924
Test name
Test status
Simulation time 17816496 ps
CPU time 0.81 seconds
Started Aug 12 05:00:13 PM PDT 24
Finished Aug 12 05:00:14 PM PDT 24
Peak memory 205968 kb
Host smart-a2a5b3a0-d19b-4441-ae8f-f3cdb6c99bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581719778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.581719778
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.850548660
Short name T1049
Test name
Test status
Simulation time 38553597 ps
CPU time 0.87 seconds
Started Aug 12 05:00:12 PM PDT 24
Finished Aug 12 05:00:13 PM PDT 24
Peak memory 205916 kb
Host smart-ebae7275-a801-40a4-9524-a8ba68504953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850548660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.850548660
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2302044030
Short name T993
Test name
Test status
Simulation time 13652932 ps
CPU time 0.7 seconds
Started Aug 12 05:00:24 PM PDT 24
Finished Aug 12 05:00:25 PM PDT 24
Peak memory 205980 kb
Host smart-d9aac451-a6bf-47ac-a7ad-5644470b7ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302044030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2302044030
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2284300724
Short name T916
Test name
Test status
Simulation time 36463041 ps
CPU time 0.83 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 205892 kb
Host smart-ed2e94b8-01c2-47f1-a7cf-7055bcbd3d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284300724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2284300724
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.315271822
Short name T1001
Test name
Test status
Simulation time 11808900 ps
CPU time 0.85 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 205972 kb
Host smart-1dfa971c-dedc-4c35-88b2-13e2ec4110be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315271822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.315271822
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4216582545
Short name T937
Test name
Test status
Simulation time 7454014 ps
CPU time 0.74 seconds
Started Aug 12 05:00:13 PM PDT 24
Finished Aug 12 05:00:14 PM PDT 24
Peak memory 205964 kb
Host smart-97e19ae5-0b21-46b6-9524-6e0c53c48988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216582545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4216582545
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.957995782
Short name T1010
Test name
Test status
Simulation time 799828500 ps
CPU time 7.53 seconds
Started Aug 12 04:59:53 PM PDT 24
Finished Aug 12 05:00:01 PM PDT 24
Peak memory 206104 kb
Host smart-7225feee-6e2f-44eb-89b4-9fccb437defa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957995782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.957995782
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.864614295
Short name T1015
Test name
Test status
Simulation time 1723318666 ps
CPU time 13.24 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 05:00:03 PM PDT 24
Peak memory 206116 kb
Host smart-44e761cc-a996-4113-9329-530093662e78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864614295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.864614295
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1191174020
Short name T991
Test name
Test status
Simulation time 23605848 ps
CPU time 1.01 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 04:59:52 PM PDT 24
Peak memory 206048 kb
Host smart-7653acd0-cd89-4da4-95f2-76f8faa684ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191174020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
191174020
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3020848516
Short name T1064
Test name
Test status
Simulation time 25402886 ps
CPU time 1.39 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 04:59:51 PM PDT 24
Peak memory 214360 kb
Host smart-38eede1e-4a87-4428-8c4f-6f3a357f50d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020848516 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3020848516
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3541357562
Short name T1023
Test name
Test status
Simulation time 151407658 ps
CPU time 0.86 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 04:59:51 PM PDT 24
Peak memory 205960 kb
Host smart-79d25f5b-fbf6-49c8-95e7-01a9e63aee90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541357562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3541357562
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2539360398
Short name T1038
Test name
Test status
Simulation time 16775257 ps
CPU time 0.78 seconds
Started Aug 12 04:59:52 PM PDT 24
Finished Aug 12 04:59:53 PM PDT 24
Peak memory 205996 kb
Host smart-9e0f64b0-7fb4-4e17-b1e8-09dc37e3b511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539360398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2539360398
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.655184812
Short name T930
Test name
Test status
Simulation time 25638943 ps
CPU time 1.33 seconds
Started Aug 12 04:59:52 PM PDT 24
Finished Aug 12 04:59:53 PM PDT 24
Peak memory 206284 kb
Host smart-b2e15ee4-b6eb-4caf-80a6-1ac5b280483e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655184812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.655184812
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2719705347
Short name T926
Test name
Test status
Simulation time 1217094593 ps
CPU time 3.3 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 04:59:54 PM PDT 24
Peak memory 214776 kb
Host smart-524facbb-c75f-4bb1-9325-9442fcd5e046
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719705347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2719705347
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2518884684
Short name T956
Test name
Test status
Simulation time 525604736 ps
CPU time 9.95 seconds
Started Aug 12 04:59:51 PM PDT 24
Finished Aug 12 05:00:01 PM PDT 24
Peak memory 214824 kb
Host smart-4b69bd42-3b1b-4f46-ba4e-6d9ba35e5174
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518884684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2518884684
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1579647617
Short name T966
Test name
Test status
Simulation time 148769526 ps
CPU time 3.39 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 04:59:53 PM PDT 24
Peak memory 214468 kb
Host smart-cff87a02-4ae1-4391-ab9f-b5f4f4d42983
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579647617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1579647617
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.173933649
Short name T972
Test name
Test status
Simulation time 33331674 ps
CPU time 0.72 seconds
Started Aug 12 05:00:18 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 205920 kb
Host smart-65cd4aec-287c-4840-8932-a9c06166e03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173933649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.173933649
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2577496593
Short name T1043
Test name
Test status
Simulation time 24260630 ps
CPU time 0.76 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 205900 kb
Host smart-4a4c1d78-ad2a-47d2-a3ce-7561585404f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577496593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2577496593
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1242869082
Short name T982
Test name
Test status
Simulation time 9664286 ps
CPU time 0.69 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 205872 kb
Host smart-cac77317-9ee5-4403-884f-1d74d8ca979d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242869082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1242869082
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3955430824
Short name T1029
Test name
Test status
Simulation time 9361302 ps
CPU time 0.84 seconds
Started Aug 12 05:00:14 PM PDT 24
Finished Aug 12 05:00:15 PM PDT 24
Peak memory 205900 kb
Host smart-759ed629-032c-4098-90a6-9f8faa0f8703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955430824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3955430824
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3985731557
Short name T928
Test name
Test status
Simulation time 25283589 ps
CPU time 0.76 seconds
Started Aug 12 05:00:10 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 205928 kb
Host smart-29a8cd69-7c8e-4cc0-90c8-d4144d84bc76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985731557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3985731557
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3873826519
Short name T1020
Test name
Test status
Simulation time 16559396 ps
CPU time 0.73 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 205996 kb
Host smart-aeed162d-4b7d-440a-a908-f20d07d881c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873826519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3873826519
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2591063127
Short name T189
Test name
Test status
Simulation time 14091953 ps
CPU time 0.68 seconds
Started Aug 12 05:00:18 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 205980 kb
Host smart-5c8ef738-2118-4d76-8794-80bf656343ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591063127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2591063127
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3925716918
Short name T921
Test name
Test status
Simulation time 24525665 ps
CPU time 0.93 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 206092 kb
Host smart-a298fd80-3a57-4439-91d2-f36866d5b5cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925716918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3925716918
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1761161715
Short name T944
Test name
Test status
Simulation time 35771581 ps
CPU time 0.72 seconds
Started Aug 12 05:00:20 PM PDT 24
Finished Aug 12 05:00:21 PM PDT 24
Peak memory 205960 kb
Host smart-30b6fcd4-c80b-4b00-97fe-dd378b3c79bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761161715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1761161715
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2920685905
Short name T1014
Test name
Test status
Simulation time 15810649 ps
CPU time 0.77 seconds
Started Aug 12 05:00:14 PM PDT 24
Finished Aug 12 05:00:15 PM PDT 24
Peak memory 205556 kb
Host smart-c4a4c3b8-eb37-44e9-8add-24cc7b37fd12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920685905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2920685905
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1640572836
Short name T971
Test name
Test status
Simulation time 1032346462 ps
CPU time 7.78 seconds
Started Aug 12 04:59:55 PM PDT 24
Finished Aug 12 05:00:03 PM PDT 24
Peak memory 206236 kb
Host smart-b766871e-1dc0-42c5-b9d8-1929dd56ac95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640572836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
640572836
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1969654216
Short name T952
Test name
Test status
Simulation time 5331099447 ps
CPU time 34.06 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 05:00:24 PM PDT 24
Peak memory 206288 kb
Host smart-b5d5c3a4-5872-4100-9319-5da5371787e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969654216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
969654216
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.141742794
Short name T958
Test name
Test status
Simulation time 19327219 ps
CPU time 0.98 seconds
Started Aug 12 04:59:52 PM PDT 24
Finished Aug 12 04:59:53 PM PDT 24
Peak memory 206128 kb
Host smart-585fa4e3-0637-41f0-ab1f-93a5935056af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141742794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.141742794
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4091320065
Short name T1026
Test name
Test status
Simulation time 169875856 ps
CPU time 2.07 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 214532 kb
Host smart-b9dd2b4f-0ca3-410b-b397-21d30ab8b3f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091320065 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4091320065
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3297316140
Short name T1058
Test name
Test status
Simulation time 10444446 ps
CPU time 1.07 seconds
Started Aug 12 04:59:53 PM PDT 24
Finished Aug 12 04:59:55 PM PDT 24
Peak memory 206192 kb
Host smart-f9055171-fc9f-4b3b-aa75-30b4b535860b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297316140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3297316140
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.244089329
Short name T1070
Test name
Test status
Simulation time 38532466 ps
CPU time 0.8 seconds
Started Aug 12 04:59:52 PM PDT 24
Finished Aug 12 04:59:53 PM PDT 24
Peak memory 205908 kb
Host smart-ef917c20-8b92-41dc-a0da-4f515e995d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244089329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.244089329
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2437883107
Short name T1076
Test name
Test status
Simulation time 74453556 ps
CPU time 1.68 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 206144 kb
Host smart-ef0e2570-cafe-451b-a821-83e6fc4c6d3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437883107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2437883107
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1781549083
Short name T934
Test name
Test status
Simulation time 697374981 ps
CPU time 3.03 seconds
Started Aug 12 04:59:50 PM PDT 24
Finished Aug 12 04:59:54 PM PDT 24
Peak memory 214624 kb
Host smart-22fe3a1e-81cf-408f-bc97-ce8def77c4de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781549083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1781549083
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3148519925
Short name T1081
Test name
Test status
Simulation time 1373170871 ps
CPU time 8.51 seconds
Started Aug 12 04:59:54 PM PDT 24
Finished Aug 12 05:00:03 PM PDT 24
Peak memory 220636 kb
Host smart-e61acf0a-3c08-4b36-a7aa-a1623c5b5554
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148519925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3148519925
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1343876827
Short name T184
Test name
Test status
Simulation time 245238224 ps
CPU time 3.09 seconds
Started Aug 12 04:59:48 PM PDT 24
Finished Aug 12 04:59:51 PM PDT 24
Peak memory 214520 kb
Host smart-f89e98c7-8067-43bb-919c-357f460c7257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343876827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1343876827
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2163797703
Short name T920
Test name
Test status
Simulation time 15222431 ps
CPU time 0.8 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 206072 kb
Host smart-9512804b-c90f-4ae2-bc9d-ec97c27058e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163797703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2163797703
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2660973693
Short name T931
Test name
Test status
Simulation time 12451275 ps
CPU time 0.86 seconds
Started Aug 12 05:00:10 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 205920 kb
Host smart-ff277381-86dd-4d99-944e-8030af54541a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660973693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2660973693
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2107102081
Short name T988
Test name
Test status
Simulation time 42904228 ps
CPU time 0.71 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 205960 kb
Host smart-9155027f-4648-4c20-a783-1b991e293cfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107102081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2107102081
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1379572632
Short name T923
Test name
Test status
Simulation time 6859970 ps
CPU time 0.69 seconds
Started Aug 12 05:00:18 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 205920 kb
Host smart-bbc4bb38-aa74-4998-8c44-0139b51b3402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379572632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1379572632
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4171394455
Short name T1018
Test name
Test status
Simulation time 244368122 ps
CPU time 0.98 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 205932 kb
Host smart-092cad77-3d75-41c3-a684-ea8400e9f811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171394455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4171394455
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.82003930
Short name T1059
Test name
Test status
Simulation time 11013348 ps
CPU time 0.7 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 205960 kb
Host smart-85cef32b-21a1-4801-b45e-8f1817781632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82003930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.82003930
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2405233764
Short name T1060
Test name
Test status
Simulation time 23235520 ps
CPU time 0.83 seconds
Started Aug 12 05:00:24 PM PDT 24
Finished Aug 12 05:00:25 PM PDT 24
Peak memory 205980 kb
Host smart-a2f48398-cfee-4e33-9ff3-ed886a4d14be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405233764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2405233764
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1597414782
Short name T959
Test name
Test status
Simulation time 26794232 ps
CPU time 0.72 seconds
Started Aug 12 05:00:13 PM PDT 24
Finished Aug 12 05:00:14 PM PDT 24
Peak memory 205820 kb
Host smart-97ba4921-dc2e-4562-949e-b9563500c9fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597414782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1597414782
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.420791647
Short name T1019
Test name
Test status
Simulation time 17667652 ps
CPU time 0.71 seconds
Started Aug 12 05:00:21 PM PDT 24
Finished Aug 12 05:00:22 PM PDT 24
Peak memory 205960 kb
Host smart-c0ee4c18-c8ee-4486-9aca-9d0c97ce2408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420791647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.420791647
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1647861051
Short name T927
Test name
Test status
Simulation time 46197556 ps
CPU time 0.73 seconds
Started Aug 12 05:00:17 PM PDT 24
Finished Aug 12 05:00:18 PM PDT 24
Peak memory 205992 kb
Host smart-32b20fde-f4f6-4205-9315-8721faa6cdcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647861051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1647861051
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2862693824
Short name T978
Test name
Test status
Simulation time 21546577 ps
CPU time 1.44 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:58 PM PDT 24
Peak memory 222612 kb
Host smart-c5ce61fc-24bc-4224-a3da-cc1b362dfa6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862693824 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2862693824
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.4107527953
Short name T1067
Test name
Test status
Simulation time 18643130 ps
CPU time 1.02 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:58 PM PDT 24
Peak memory 205940 kb
Host smart-5661e323-d09f-4ff2-900f-62f66082b6e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107527953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.4107527953
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1198192011
Short name T964
Test name
Test status
Simulation time 15100439 ps
CPU time 0.73 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:58 PM PDT 24
Peak memory 205936 kb
Host smart-48075f3e-1b9f-4c0e-a998-18c89e93df75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198192011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1198192011
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4252883301
Short name T1009
Test name
Test status
Simulation time 25714284 ps
CPU time 1.38 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 206224 kb
Host smart-6abdb003-769e-470d-a4a6-aedd5619ec5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252883301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4252883301
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.896471135
Short name T979
Test name
Test status
Simulation time 69493721 ps
CPU time 1.6 seconds
Started Aug 12 05:00:00 PM PDT 24
Finished Aug 12 05:00:01 PM PDT 24
Peak memory 214796 kb
Host smart-4ba7bd7f-56d1-42ee-9d68-99e52eb6e40a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896471135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.896471135
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1490280716
Short name T114
Test name
Test status
Simulation time 3020024246 ps
CPU time 6.54 seconds
Started Aug 12 04:59:59 PM PDT 24
Finished Aug 12 05:00:06 PM PDT 24
Peak memory 214880 kb
Host smart-1eca984b-c889-47e9-946a-5fa4fa9c88e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490280716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1490280716
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2208772177
Short name T180
Test name
Test status
Simulation time 520712484 ps
CPU time 2.45 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 215144 kb
Host smart-a12662bf-5e88-42fe-a3b1-e11bced774bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208772177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2208772177
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3430676380
Short name T155
Test name
Test status
Simulation time 85640141 ps
CPU time 2.48 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 05:00:00 PM PDT 24
Peak memory 206180 kb
Host smart-ddc1f6a1-cd11-40fa-9933-d27624eafc92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430676380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3430676380
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4168611489
Short name T1025
Test name
Test status
Simulation time 37502059 ps
CPU time 1.71 seconds
Started Aug 12 04:59:56 PM PDT 24
Finished Aug 12 04:59:58 PM PDT 24
Peak memory 214492 kb
Host smart-5ba28ff5-929e-4e80-be33-dd98b47cf1c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168611489 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4168611489
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4131778576
Short name T961
Test name
Test status
Simulation time 124194397 ps
CPU time 1.23 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 206196 kb
Host smart-e9ec8af6-2168-483f-9606-04e61891ec7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131778576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4131778576
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1083060249
Short name T1057
Test name
Test status
Simulation time 18663917 ps
CPU time 0.86 seconds
Started Aug 12 05:00:00 PM PDT 24
Finished Aug 12 05:00:01 PM PDT 24
Peak memory 205904 kb
Host smart-828f7fd7-f867-4df4-9454-3582fb64b5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083060249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1083060249
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3020199598
Short name T977
Test name
Test status
Simulation time 441486675 ps
CPU time 3.85 seconds
Started Aug 12 04:59:55 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 206092 kb
Host smart-ed7b32de-3873-489f-8615-a6696199470a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020199598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3020199598
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.988814984
Short name T1051
Test name
Test status
Simulation time 240642468 ps
CPU time 2.54 seconds
Started Aug 12 05:00:00 PM PDT 24
Finished Aug 12 05:00:03 PM PDT 24
Peak memory 214804 kb
Host smart-f067167e-0371-4917-a306-61a6d2c59c8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988814984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.988814984
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.444438616
Short name T1031
Test name
Test status
Simulation time 161673808 ps
CPU time 4.44 seconds
Started Aug 12 04:59:59 PM PDT 24
Finished Aug 12 05:00:04 PM PDT 24
Peak memory 220756 kb
Host smart-435015af-4473-4bac-a57b-116d3f426ec9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444438616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.444438616
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2171534242
Short name T973
Test name
Test status
Simulation time 75771397 ps
CPU time 1.94 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 214400 kb
Host smart-3f3bcd00-7ce1-4de0-97d4-008c65dbc9c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171534242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2171534242
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1409064216
Short name T970
Test name
Test status
Simulation time 436355405 ps
CPU time 4.24 seconds
Started Aug 12 04:59:58 PM PDT 24
Finished Aug 12 05:00:02 PM PDT 24
Peak memory 214312 kb
Host smart-fc970446-dbc0-42bf-ad4a-8086544574ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409064216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1409064216
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1574240157
Short name T946
Test name
Test status
Simulation time 54777131 ps
CPU time 1.28 seconds
Started Aug 12 05:00:02 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 206336 kb
Host smart-17d03aba-42b5-4829-927d-c2bbcbc92d49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574240157 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1574240157
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.283268789
Short name T981
Test name
Test status
Simulation time 97625759 ps
CPU time 1.26 seconds
Started Aug 12 05:00:00 PM PDT 24
Finished Aug 12 05:00:01 PM PDT 24
Peak memory 206144 kb
Host smart-2a3795f7-bd2c-4bc5-9434-7bdd38f323f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283268789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.283268789
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1122425446
Short name T976
Test name
Test status
Simulation time 38920937 ps
CPU time 0.84 seconds
Started Aug 12 05:00:02 PM PDT 24
Finished Aug 12 05:00:08 PM PDT 24
Peak memory 206016 kb
Host smart-3862c617-1754-46e4-9ba4-87475492bceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122425446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1122425446
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3545380792
Short name T1054
Test name
Test status
Simulation time 215761199 ps
CPU time 2.19 seconds
Started Aug 12 04:59:58 PM PDT 24
Finished Aug 12 05:00:00 PM PDT 24
Peak memory 206228 kb
Host smart-138e2535-679e-4fb4-af51-e0548f93d03c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545380792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3545380792
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3905931963
Short name T1047
Test name
Test status
Simulation time 137854964 ps
CPU time 2.4 seconds
Started Aug 12 04:59:59 PM PDT 24
Finished Aug 12 05:00:02 PM PDT 24
Peak memory 214792 kb
Host smart-372c1004-356c-4175-994e-5af560ae79a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905931963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3905931963
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.797189966
Short name T1022
Test name
Test status
Simulation time 774248105 ps
CPU time 12.12 seconds
Started Aug 12 04:59:56 PM PDT 24
Finished Aug 12 05:00:08 PM PDT 24
Peak memory 214704 kb
Host smart-e9973df2-756c-4a57-8d21-7f063b5fac24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797189966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.797189966
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.380358857
Short name T1002
Test name
Test status
Simulation time 78712190 ps
CPU time 3.34 seconds
Started Aug 12 04:59:58 PM PDT 24
Finished Aug 12 05:00:01 PM PDT 24
Peak memory 214408 kb
Host smart-b1a8dd97-f8be-4c71-92ab-28996d63fe43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380358857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.380358857
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1505669587
Short name T945
Test name
Test status
Simulation time 58979410 ps
CPU time 2.31 seconds
Started Aug 12 04:59:58 PM PDT 24
Finished Aug 12 05:00:00 PM PDT 24
Peak memory 214492 kb
Host smart-9f9744f7-d44f-4e2e-adf1-0e8691a74909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505669587 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1505669587
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2562678125
Short name T1017
Test name
Test status
Simulation time 98393255 ps
CPU time 1.17 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 206096 kb
Host smart-91bfe5ed-73dd-4767-aec9-2ddf90bc9a58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562678125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2562678125
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4065839452
Short name T1042
Test name
Test status
Simulation time 27909336 ps
CPU time 0.76 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:58 PM PDT 24
Peak memory 205988 kb
Host smart-52f83aab-0d74-4c42-9bb0-14ebd342e7cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065839452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4065839452
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1078186902
Short name T1013
Test name
Test status
Simulation time 60332831 ps
CPU time 1.76 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 205584 kb
Host smart-7b91fd6b-4896-47b6-9f62-f0ea3c94ce7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078186902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1078186902
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2160363745
Short name T110
Test name
Test status
Simulation time 192711934 ps
CPU time 1.72 seconds
Started Aug 12 05:00:00 PM PDT 24
Finished Aug 12 05:00:02 PM PDT 24
Peak memory 214848 kb
Host smart-a931d47a-90b9-4b45-98ba-7c3b3409b629
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160363745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2160363745
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.227289689
Short name T134
Test name
Test status
Simulation time 705221141 ps
CPU time 4.12 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 05:00:02 PM PDT 24
Peak memory 214772 kb
Host smart-3076f857-da18-44d7-bcee-77f8e0d0a8de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227289689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.227289689
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.731584165
Short name T1004
Test name
Test status
Simulation time 32525127 ps
CPU time 1.97 seconds
Started Aug 12 05:00:01 PM PDT 24
Finished Aug 12 05:00:03 PM PDT 24
Peak memory 214448 kb
Host smart-55794157-3c0b-4154-9e8b-71a5f19dd233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731584165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.731584165
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4172979917
Short name T152
Test name
Test status
Simulation time 1135326703 ps
CPU time 8.53 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 05:00:06 PM PDT 24
Peak memory 214396 kb
Host smart-2db407fa-812e-4882-bfdc-b387af036343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172979917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4172979917
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3229431929
Short name T929
Test name
Test status
Simulation time 33750536 ps
CPU time 1.66 seconds
Started Aug 12 05:00:07 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 214552 kb
Host smart-5f4f0349-d5a1-41e6-a025-4e93b3518906
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229431929 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3229431929
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3098951317
Short name T132
Test name
Test status
Simulation time 15259982 ps
CPU time 1.09 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 206312 kb
Host smart-570ce5f2-13b6-4cbe-888c-cd64e5cdb732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098951317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3098951317
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1719647261
Short name T996
Test name
Test status
Simulation time 34210852 ps
CPU time 0.8 seconds
Started Aug 12 04:59:57 PM PDT 24
Finished Aug 12 04:59:58 PM PDT 24
Peak memory 205260 kb
Host smart-067946c1-f72f-4cc7-a7e8-1759ab53d0ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719647261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1719647261
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2227286173
Short name T1030
Test name
Test status
Simulation time 425403475 ps
CPU time 3.1 seconds
Started Aug 12 05:00:05 PM PDT 24
Finished Aug 12 05:00:11 PM PDT 24
Peak memory 206320 kb
Host smart-051b01d8-2bcf-43d0-adfe-1460a34c06cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227286173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2227286173
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.115310586
Short name T111
Test name
Test status
Simulation time 57418864 ps
CPU time 1.51 seconds
Started Aug 12 05:00:00 PM PDT 24
Finished Aug 12 05:00:02 PM PDT 24
Peak memory 214808 kb
Host smart-c87eb6e3-8fa9-459f-93d6-f2a3a040fa9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115310586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.115310586
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2544210068
Short name T998
Test name
Test status
Simulation time 93338689 ps
CPU time 1.62 seconds
Started Aug 12 05:00:02 PM PDT 24
Finished Aug 12 05:00:09 PM PDT 24
Peak memory 214596 kb
Host smart-3ec8d0eb-e7a4-41d8-9711-0418dfc841d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544210068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2544210068
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2827345021
Short name T169
Test name
Test status
Simulation time 404043141 ps
CPU time 4.47 seconds
Started Aug 12 04:59:59 PM PDT 24
Finished Aug 12 05:00:04 PM PDT 24
Peak memory 214468 kb
Host smart-7c9a5d70-d015-48f0-8005-0263efd294e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827345021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2827345021
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2297039107
Short name T898
Test name
Test status
Simulation time 13734158 ps
CPU time 0.93 seconds
Started Aug 12 05:00:51 PM PDT 24
Finished Aug 12 05:00:52 PM PDT 24
Peak memory 206472 kb
Host smart-0edb5800-1ef3-444c-9e96-362c4be819c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297039107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2297039107
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.4163332394
Short name T580
Test name
Test status
Simulation time 119967082 ps
CPU time 2.71 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:00:56 PM PDT 24
Peak memory 209096 kb
Host smart-f6b81fbe-17c8-4f00-b912-5a6547c36883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163332394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4163332394
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3692870093
Short name T91
Test name
Test status
Simulation time 4421357580 ps
CPU time 60.26 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:01:54 PM PDT 24
Peak memory 214884 kb
Host smart-2ab84781-ff2a-4901-8144-d03ab25d2835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692870093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3692870093
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2171380966
Short name T506
Test name
Test status
Simulation time 132902450 ps
CPU time 2.44 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:00:59 PM PDT 24
Peak memory 214632 kb
Host smart-eedcdc95-ab9f-411a-a5ee-a1fa67245fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171380966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2171380966
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1931534690
Short name T535
Test name
Test status
Simulation time 68314552 ps
CPU time 2.39 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 214776 kb
Host smart-db6977df-8f35-4211-854d-ada2b7464e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931534690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1931534690
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3396281578
Short name T558
Test name
Test status
Simulation time 1027385089 ps
CPU time 6.1 seconds
Started Aug 12 05:00:55 PM PDT 24
Finished Aug 12 05:01:02 PM PDT 24
Peak memory 209540 kb
Host smart-c8afc28e-90b7-4fe8-9c1f-fc65a99ab04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396281578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3396281578
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.514109774
Short name T99
Test name
Test status
Simulation time 837249937 ps
CPU time 9.75 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 231512 kb
Host smart-8a790420-2dd6-4e9d-b685-caa2b368806f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514109774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.514109774
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.4136316598
Short name T462
Test name
Test status
Simulation time 222658990 ps
CPU time 6.16 seconds
Started Aug 12 05:00:54 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 207324 kb
Host smart-0b5fe34c-9809-4bdd-8e10-d49dfdcf38d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136316598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.4136316598
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4038691011
Short name T849
Test name
Test status
Simulation time 21505489 ps
CPU time 1.9 seconds
Started Aug 12 05:00:51 PM PDT 24
Finished Aug 12 05:00:53 PM PDT 24
Peak memory 208048 kb
Host smart-3d352f63-f689-43cc-ae67-31c615fbc60e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038691011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4038691011
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.39797283
Short name T360
Test name
Test status
Simulation time 180592960 ps
CPU time 2.92 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:00:59 PM PDT 24
Peak memory 210332 kb
Host smart-6ca344ba-deb1-4dd7-a7d8-06461eb7d9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39797283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.39797283
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2886436315
Short name T396
Test name
Test status
Simulation time 32968253 ps
CPU time 2.28 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:00:53 PM PDT 24
Peak memory 207000 kb
Host smart-69deb51a-667a-4899-a12f-2097cd4989c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886436315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2886436315
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.207474212
Short name T188
Test name
Test status
Simulation time 4776415510 ps
CPU time 49.34 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 216796 kb
Host smart-b141dd31-d9ac-499e-bc43-9cafbcde4447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207474212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.207474212
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2238554441
Short name T632
Test name
Test status
Simulation time 181042272 ps
CPU time 3.15 seconds
Started Aug 12 05:00:57 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 218800 kb
Host smart-21945023-c73c-483c-a183-54f499c763a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238554441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2238554441
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3438724514
Short name T122
Test name
Test status
Simulation time 137848693 ps
CPU time 1.52 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:00:59 PM PDT 24
Peak memory 210528 kb
Host smart-a8d4778e-0486-4cb3-b8eb-50e4c365da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438724514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3438724514
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4005542380
Short name T495
Test name
Test status
Simulation time 19722588 ps
CPU time 0.85 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:00:54 PM PDT 24
Peak memory 206400 kb
Host smart-5a9caa6a-60ec-4443-a9de-ee1fd208db06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005542380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4005542380
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1538307909
Short name T275
Test name
Test status
Simulation time 64694311 ps
CPU time 3.84 seconds
Started Aug 12 05:00:51 PM PDT 24
Finished Aug 12 05:00:55 PM PDT 24
Peak memory 215376 kb
Host smart-27266d0c-52f2-4964-8567-99501de5eb1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538307909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1538307909
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2367151110
Short name T567
Test name
Test status
Simulation time 1039424937 ps
CPU time 25.48 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:01:19 PM PDT 24
Peak memory 218244 kb
Host smart-66aea233-b654-4d11-a5e1-25e9444f54e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367151110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2367151110
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.109720354
Short name T794
Test name
Test status
Simulation time 526315738 ps
CPU time 10.06 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 210296 kb
Host smart-b0bbd2d8-417f-4139-8d32-791968230ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109720354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.109720354
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1681760983
Short name T325
Test name
Test status
Simulation time 310396248 ps
CPU time 4.16 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:02 PM PDT 24
Peak memory 214852 kb
Host smart-990e8585-0d3a-4ba8-a1aa-5b510fb8087f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681760983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1681760983
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2971728091
Short name T1
Test name
Test status
Simulation time 80989541 ps
CPU time 3.64 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:56 PM PDT 24
Peak memory 214616 kb
Host smart-ba395000-6be3-46f9-bd8d-63045f654ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971728091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2971728091
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1874932781
Short name T65
Test name
Test status
Simulation time 119192603 ps
CPU time 3.22 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:55 PM PDT 24
Peak memory 220968 kb
Host smart-dbd71ea5-5797-41f4-9c41-8289106201bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874932781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1874932781
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3567681269
Short name T671
Test name
Test status
Simulation time 73105698 ps
CPU time 4.38 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:56 PM PDT 24
Peak memory 214832 kb
Host smart-01cfc486-49e8-43ba-bdcd-43f49b1f64ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567681269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3567681269
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.133206501
Short name T195
Test name
Test status
Simulation time 153245614 ps
CPU time 2.73 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:55 PM PDT 24
Peak memory 209100 kb
Host smart-529edd3e-4066-4f5a-bd17-d4355da748c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133206501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.133206501
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.864468638
Short name T709
Test name
Test status
Simulation time 105733676 ps
CPU time 2.92 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:00:54 PM PDT 24
Peak memory 207040 kb
Host smart-f951d77a-e286-43fb-820c-ecf74f5babbb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864468638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.864468638
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.348392086
Short name T739
Test name
Test status
Simulation time 1420476370 ps
CPU time 17.65 seconds
Started Aug 12 05:00:54 PM PDT 24
Finished Aug 12 05:01:12 PM PDT 24
Peak memory 209176 kb
Host smart-79129632-b80f-4026-bb77-a6b60ef25cc0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348392086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.348392086
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3591288672
Short name T421
Test name
Test status
Simulation time 2270067144 ps
CPU time 33.42 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:32 PM PDT 24
Peak memory 209872 kb
Host smart-21f457c6-76fe-42d9-afcb-648115996baf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591288672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3591288672
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3923561469
Short name T609
Test name
Test status
Simulation time 684928178 ps
CPU time 5.07 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 222988 kb
Host smart-10fb5838-7ab6-4279-91bf-793bc0f933b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923561469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3923561469
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.4064032370
Short name T627
Test name
Test status
Simulation time 35493395 ps
CPU time 2.1 seconds
Started Aug 12 05:00:55 PM PDT 24
Finished Aug 12 05:00:57 PM PDT 24
Peak memory 207464 kb
Host smart-7e94aa2e-e8c1-4b47-9841-c70c7085e089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064032370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.4064032370
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1406730081
Short name T890
Test name
Test status
Simulation time 731023927 ps
CPU time 19.44 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:01:10 PM PDT 24
Peak memory 216508 kb
Host smart-03aeab62-6146-4f86-9a75-b5fa68de4302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406730081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1406730081
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3166002563
Short name T472
Test name
Test status
Simulation time 116228640 ps
CPU time 4.47 seconds
Started Aug 12 05:00:51 PM PDT 24
Finished Aug 12 05:00:56 PM PDT 24
Peak memory 214748 kb
Host smart-ab9318a8-c711-4df9-9faa-0c4b2fe2f52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166002563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3166002563
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3231791436
Short name T263
Test name
Test status
Simulation time 163876749 ps
CPU time 3.33 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:21 PM PDT 24
Peak memory 215672 kb
Host smart-4b31229d-4b0f-4f04-a634-6c11cabbe26a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231791436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3231791436
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2443557288
Short name T568
Test name
Test status
Simulation time 87116339 ps
CPU time 2.42 seconds
Started Aug 12 05:01:08 PM PDT 24
Finished Aug 12 05:01:10 PM PDT 24
Peak memory 214820 kb
Host smart-1fa5af2c-9f95-49b0-8dfd-575c75423643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443557288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2443557288
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3437640927
Short name T908
Test name
Test status
Simulation time 146577687 ps
CPU time 4.46 seconds
Started Aug 12 05:01:14 PM PDT 24
Finished Aug 12 05:01:19 PM PDT 24
Peak memory 215884 kb
Host smart-37d17dcc-532f-4bc6-ae1f-3b3bcd339ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437640927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3437640927
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1803298742
Short name T901
Test name
Test status
Simulation time 285191716 ps
CPU time 4.5 seconds
Started Aug 12 05:01:12 PM PDT 24
Finished Aug 12 05:01:17 PM PDT 24
Peak memory 209892 kb
Host smart-4b916c3d-79d6-4444-bcae-68bea470ac84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803298742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1803298742
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2995214158
Short name T357
Test name
Test status
Simulation time 2818804847 ps
CPU time 35.97 seconds
Started Aug 12 05:01:10 PM PDT 24
Finished Aug 12 05:01:46 PM PDT 24
Peak memory 209488 kb
Host smart-381b041d-3b57-4388-ad4a-8d9171fd3419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995214158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2995214158
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2356426312
Short name T332
Test name
Test status
Simulation time 110225899 ps
CPU time 2.84 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 207428 kb
Host smart-ccfc6b91-f628-4eb1-ad35-214b403ff8d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356426312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2356426312
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2454422208
Short name T742
Test name
Test status
Simulation time 81167460 ps
CPU time 3.32 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 207880 kb
Host smart-51e8d3a3-b6c3-4067-a7fe-ed6b3b09fba4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454422208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2454422208
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2891176686
Short name T305
Test name
Test status
Simulation time 148184807 ps
CPU time 2.01 seconds
Started Aug 12 05:01:24 PM PDT 24
Finished Aug 12 05:01:26 PM PDT 24
Peak memory 208748 kb
Host smart-71338f9a-c326-4430-93b1-235d457b010a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891176686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2891176686
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.88050177
Short name T494
Test name
Test status
Simulation time 133456560 ps
CPU time 4.98 seconds
Started Aug 12 05:01:11 PM PDT 24
Finished Aug 12 05:01:16 PM PDT 24
Peak memory 209020 kb
Host smart-7e797d00-7c66-4490-a7e1-a1a373f211b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88050177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.88050177
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2719120263
Short name T523
Test name
Test status
Simulation time 10361558832 ps
CPU time 72.58 seconds
Started Aug 12 05:01:13 PM PDT 24
Finished Aug 12 05:02:25 PM PDT 24
Peak memory 220268 kb
Host smart-a7b5a6cc-60ae-4e70-900d-7eb71d6780c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719120263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2719120263
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1536131245
Short name T833
Test name
Test status
Simulation time 477869794 ps
CPU time 13.01 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:32 PM PDT 24
Peak memory 219356 kb
Host smart-f7e67191-51ff-4a0b-9768-6885792730e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536131245 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1536131245
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1270088467
Short name T590
Test name
Test status
Simulation time 481628611 ps
CPU time 9.46 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:15 PM PDT 24
Peak memory 208344 kb
Host smart-987b1c1d-162e-4b9e-9ae4-45c68d0e142a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270088467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1270088467
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4152076684
Short name T383
Test name
Test status
Simulation time 61737142 ps
CPU time 1.3 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:21 PM PDT 24
Peak memory 209108 kb
Host smart-1390e5d4-cd19-4825-8c58-2bb7c8ae6fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152076684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4152076684
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.60085647
Short name T418
Test name
Test status
Simulation time 15624364 ps
CPU time 0.79 seconds
Started Aug 12 05:01:23 PM PDT 24
Finished Aug 12 05:01:24 PM PDT 24
Peak memory 206328 kb
Host smart-b4495eec-cdc2-4e4b-b40e-721347ce1870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60085647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.60085647
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1779386947
Short name T217
Test name
Test status
Simulation time 70143599 ps
CPU time 3.49 seconds
Started Aug 12 05:01:39 PM PDT 24
Finished Aug 12 05:01:43 PM PDT 24
Peak memory 209264 kb
Host smart-b04a8bf8-f7fe-4a52-b628-a2c20eea0263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779386947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1779386947
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2805836666
Short name T254
Test name
Test status
Simulation time 183586515 ps
CPU time 2.62 seconds
Started Aug 12 05:01:14 PM PDT 24
Finished Aug 12 05:01:16 PM PDT 24
Peak memory 214744 kb
Host smart-a3f7da1f-7bbc-47a7-a9f1-a37addb49e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805836666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2805836666
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2462057768
Short name T235
Test name
Test status
Simulation time 48738011 ps
CPU time 2.34 seconds
Started Aug 12 05:01:25 PM PDT 24
Finished Aug 12 05:01:28 PM PDT 24
Peak memory 221040 kb
Host smart-a55ead2d-7687-4fff-a7f9-8e661bdca5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462057768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2462057768
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2348939111
Short name T533
Test name
Test status
Simulation time 91818625 ps
CPU time 3.36 seconds
Started Aug 12 05:01:06 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 220640 kb
Host smart-5ebdd2d6-9e18-4a7a-8d9e-bb0401abcf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348939111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2348939111
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2933603537
Short name T781
Test name
Test status
Simulation time 241990303 ps
CPU time 7.48 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:12 PM PDT 24
Peak memory 219016 kb
Host smart-1083579a-61a0-4356-89e7-e0aa8ba0da6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933603537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2933603537
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2311847490
Short name T507
Test name
Test status
Simulation time 109474343 ps
CPU time 2.85 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 209220 kb
Host smart-16cfc71b-01ce-4004-b05f-355be5417b85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311847490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2311847490
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.158447294
Short name T669
Test name
Test status
Simulation time 79414877 ps
CPU time 3.21 seconds
Started Aug 12 05:01:11 PM PDT 24
Finished Aug 12 05:01:14 PM PDT 24
Peak memory 207456 kb
Host smart-4d0edb39-bf33-4ae7-a941-65098baf2ec3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158447294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.158447294
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3634976303
Short name T783
Test name
Test status
Simulation time 366668567 ps
CPU time 3.27 seconds
Started Aug 12 05:01:07 PM PDT 24
Finished Aug 12 05:01:11 PM PDT 24
Peak memory 207376 kb
Host smart-3780fe40-4e79-4147-9f47-74499f97631b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634976303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3634976303
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1672916539
Short name T623
Test name
Test status
Simulation time 25819538 ps
CPU time 1.75 seconds
Started Aug 12 05:01:23 PM PDT 24
Finished Aug 12 05:01:25 PM PDT 24
Peak memory 208196 kb
Host smart-8aa3bf39-b7f7-4e29-b721-bd056b248449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672916539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1672916539
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4081200634
Short name T553
Test name
Test status
Simulation time 492561339 ps
CPU time 5.6 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:16 PM PDT 24
Peak memory 208812 kb
Host smart-81efebed-d64c-4b99-b2a8-f5925390cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081200634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4081200634
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3308519699
Short name T365
Test name
Test status
Simulation time 1560085494 ps
CPU time 12.11 seconds
Started Aug 12 05:01:21 PM PDT 24
Finished Aug 12 05:01:33 PM PDT 24
Peak memory 223036 kb
Host smart-5e8f9e70-4d91-45b8-8c0b-670113cb5d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308519699 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3308519699
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1706537477
Short name T639
Test name
Test status
Simulation time 90725078 ps
CPU time 4.34 seconds
Started Aug 12 05:01:06 PM PDT 24
Finished Aug 12 05:01:10 PM PDT 24
Peak memory 214912 kb
Host smart-b9ae6529-4632-4850-80bd-1c9c8c19da4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706537477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1706537477
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3087960901
Short name T173
Test name
Test status
Simulation time 90594853 ps
CPU time 2.18 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:20 PM PDT 24
Peak memory 210604 kb
Host smart-c71e48f0-1a92-40af-a504-e5c4390d37df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087960901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3087960901
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.792385238
Short name T828
Test name
Test status
Simulation time 56255482 ps
CPU time 0.9 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:20 PM PDT 24
Peak memory 206380 kb
Host smart-cc69d11b-ef1d-4741-b7c5-9d758f7463cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792385238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.792385238
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.114218788
Short name T412
Test name
Test status
Simulation time 37278553 ps
CPU time 2.88 seconds
Started Aug 12 05:01:12 PM PDT 24
Finished Aug 12 05:01:15 PM PDT 24
Peak memory 214784 kb
Host smart-dc3d0dc1-d5bf-4142-ae33-d3e9d5e0945f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114218788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.114218788
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1623982192
Short name T877
Test name
Test status
Simulation time 193543662 ps
CPU time 2.02 seconds
Started Aug 12 05:01:24 PM PDT 24
Finished Aug 12 05:01:27 PM PDT 24
Peak memory 208264 kb
Host smart-a3c7b7dc-22a2-49eb-b8dc-b2c712d652fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623982192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1623982192
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1343016201
Short name T666
Test name
Test status
Simulation time 94708518 ps
CPU time 4.34 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:24 PM PDT 24
Peak memory 215044 kb
Host smart-24fefb60-fe68-43c7-9984-ccf1fd12d2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343016201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1343016201
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2110225336
Short name T673
Test name
Test status
Simulation time 105460459 ps
CPU time 3.22 seconds
Started Aug 12 05:01:42 PM PDT 24
Finished Aug 12 05:01:45 PM PDT 24
Peak memory 214684 kb
Host smart-477e8047-4f56-415d-8007-9e93fb0b9de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110225336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2110225336
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3775665456
Short name T767
Test name
Test status
Simulation time 70919164 ps
CPU time 2.73 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:21 PM PDT 24
Peak memory 220244 kb
Host smart-add290b1-4e4b-42b7-b75a-5211a7cc73ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775665456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3775665456
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.372764191
Short name T355
Test name
Test status
Simulation time 346814056 ps
CPU time 7.47 seconds
Started Aug 12 05:01:24 PM PDT 24
Finished Aug 12 05:01:32 PM PDT 24
Peak memory 209540 kb
Host smart-b63b3f13-053e-4489-acb1-1406dc6ea5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372764191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.372764191
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.790123802
Short name T820
Test name
Test status
Simulation time 142445240 ps
CPU time 4.17 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:23 PM PDT 24
Peak memory 207360 kb
Host smart-48187c6b-41e3-4aa0-a720-e426a5d2ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790123802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.790123802
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2162073311
Short name T455
Test name
Test status
Simulation time 225261562 ps
CPU time 6.2 seconds
Started Aug 12 05:01:20 PM PDT 24
Finished Aug 12 05:01:27 PM PDT 24
Peak memory 208900 kb
Host smart-fdd8315d-aac4-4ad1-b40a-5ef2bc9d5101
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162073311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2162073311
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1675894247
Short name T854
Test name
Test status
Simulation time 177015255 ps
CPU time 2.47 seconds
Started Aug 12 05:01:28 PM PDT 24
Finished Aug 12 05:01:31 PM PDT 24
Peak memory 207432 kb
Host smart-65b1c91c-b889-43ca-ad4c-3b5e742b536b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675894247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1675894247
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1911868603
Short name T559
Test name
Test status
Simulation time 78636074 ps
CPU time 1.92 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:20 PM PDT 24
Peak memory 209228 kb
Host smart-3b40ef9f-574a-403a-a132-d700a33adbb1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911868603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1911868603
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.871271203
Short name T400
Test name
Test status
Simulation time 122272044 ps
CPU time 3.23 seconds
Started Aug 12 05:01:23 PM PDT 24
Finished Aug 12 05:01:26 PM PDT 24
Peak memory 210056 kb
Host smart-281e9ad7-afd8-4c72-899f-730ad7bb43fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871271203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.871271203
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2747738556
Short name T422
Test name
Test status
Simulation time 330928658 ps
CPU time 3.28 seconds
Started Aug 12 05:01:20 PM PDT 24
Finished Aug 12 05:01:24 PM PDT 24
Peak memory 209104 kb
Host smart-b1aed9ab-1692-4371-92e2-5df2f1d239eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747738556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2747738556
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1350804281
Short name T453
Test name
Test status
Simulation time 763188226 ps
CPU time 5.69 seconds
Started Aug 12 05:01:25 PM PDT 24
Finished Aug 12 05:01:30 PM PDT 24
Peak memory 218976 kb
Host smart-5282ef0f-569c-4a1f-a50a-379362c297b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350804281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1350804281
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1361195706
Short name T819
Test name
Test status
Simulation time 45118145 ps
CPU time 2.28 seconds
Started Aug 12 05:01:24 PM PDT 24
Finished Aug 12 05:01:27 PM PDT 24
Peak memory 210756 kb
Host smart-43fa8248-3648-41fc-bf23-f0ce6e71f336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361195706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1361195706
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2913556600
Short name T420
Test name
Test status
Simulation time 9894436 ps
CPU time 0.89 seconds
Started Aug 12 05:01:24 PM PDT 24
Finished Aug 12 05:01:25 PM PDT 24
Peak memory 206368 kb
Host smart-c1b2a495-e6c4-4c5a-8258-8d388d2f2915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913556600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2913556600
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3691653597
Short name T406
Test name
Test status
Simulation time 23617356 ps
CPU time 1.68 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:20 PM PDT 24
Peak memory 209788 kb
Host smart-cd3ad8a5-268c-44dd-a8d9-7b3fe34f64c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691653597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3691653597
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.34101193
Short name T793
Test name
Test status
Simulation time 6408224447 ps
CPU time 30.18 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:48 PM PDT 24
Peak memory 222992 kb
Host smart-74cb7d03-dc8e-4575-b038-9c6f3308f5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34101193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.34101193
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2692686857
Short name T785
Test name
Test status
Simulation time 336398136 ps
CPU time 4.51 seconds
Started Aug 12 05:01:23 PM PDT 24
Finished Aug 12 05:01:28 PM PDT 24
Peak memory 210828 kb
Host smart-a3a79da0-190a-4170-93de-a3ead9105973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692686857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2692686857
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4009870104
Short name T679
Test name
Test status
Simulation time 3572267958 ps
CPU time 8.47 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:27 PM PDT 24
Peak memory 209292 kb
Host smart-4cac2a6b-7ab0-47ee-beac-dba4ddc65f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009870104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4009870104
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2996589329
Short name T244
Test name
Test status
Simulation time 128934578 ps
CPU time 2.75 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:21 PM PDT 24
Peak memory 207376 kb
Host smart-750f87bb-1fdc-44d4-bad1-9daad6ac0fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996589329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2996589329
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.4172372703
Short name T486
Test name
Test status
Simulation time 1315376205 ps
CPU time 21.99 seconds
Started Aug 12 05:01:33 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 208884 kb
Host smart-9ed41c33-af23-4a29-966e-e008f933892f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172372703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.4172372703
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3697248494
Short name T613
Test name
Test status
Simulation time 229201627 ps
CPU time 3.18 seconds
Started Aug 12 05:01:27 PM PDT 24
Finished Aug 12 05:01:30 PM PDT 24
Peak memory 209020 kb
Host smart-be6bcf50-2704-4318-a20a-3026ea28df99
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697248494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3697248494
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1983544583
Short name T825
Test name
Test status
Simulation time 2553195562 ps
CPU time 17.73 seconds
Started Aug 12 05:01:21 PM PDT 24
Finished Aug 12 05:01:39 PM PDT 24
Peak memory 209288 kb
Host smart-5ac93ddb-f673-4688-a5f5-a2c181d36f44
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983544583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1983544583
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2649508446
Short name T201
Test name
Test status
Simulation time 480939692 ps
CPU time 3.51 seconds
Started Aug 12 05:01:24 PM PDT 24
Finished Aug 12 05:01:28 PM PDT 24
Peak memory 207924 kb
Host smart-fd5beae9-d765-4ad6-bd8f-c84d59b0f295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649508446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2649508446
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2456879620
Short name T481
Test name
Test status
Simulation time 20087264 ps
CPU time 1.71 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:21 PM PDT 24
Peak memory 207496 kb
Host smart-62b33d03-03c7-4055-a06a-e3ce81b129e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456879620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2456879620
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.952645420
Short name T816
Test name
Test status
Simulation time 461681710 ps
CPU time 9.03 seconds
Started Aug 12 05:01:15 PM PDT 24
Finished Aug 12 05:01:24 PM PDT 24
Peak memory 215612 kb
Host smart-808fd0de-99b9-46db-b7e4-22c4aa20de29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952645420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.952645420
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1657329793
Short name T69
Test name
Test status
Simulation time 968882892 ps
CPU time 8.28 seconds
Started Aug 12 05:01:24 PM PDT 24
Finished Aug 12 05:01:33 PM PDT 24
Peak memory 219884 kb
Host smart-f304dde5-b102-4ccf-b544-d9d5f08b77a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657329793 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1657329793
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1072292746
Short name T710
Test name
Test status
Simulation time 187168640 ps
CPU time 5.13 seconds
Started Aug 12 05:01:26 PM PDT 24
Finished Aug 12 05:01:31 PM PDT 24
Peak memory 208596 kb
Host smart-725b4db3-8cdf-4e17-a376-4ce347418552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072292746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1072292746
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2238262103
Short name T900
Test name
Test status
Simulation time 78854094 ps
CPU time 2.81 seconds
Started Aug 12 05:01:17 PM PDT 24
Finished Aug 12 05:01:19 PM PDT 24
Peak memory 210576 kb
Host smart-72c0db8e-88aa-4ee1-9752-24c7b4fb140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238262103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2238262103
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1473200218
Short name T451
Test name
Test status
Simulation time 40328266 ps
CPU time 0.76 seconds
Started Aug 12 05:01:36 PM PDT 24
Finished Aug 12 05:01:37 PM PDT 24
Peak memory 206356 kb
Host smart-beae494a-389e-45ae-a9f5-21304276d3bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473200218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1473200218
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2486210496
Short name T374
Test name
Test status
Simulation time 127368717 ps
CPU time 2.71 seconds
Started Aug 12 05:01:37 PM PDT 24
Finished Aug 12 05:01:39 PM PDT 24
Peak memory 215348 kb
Host smart-a4521dd7-5fc8-4112-bbfa-4c87acb64947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486210496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2486210496
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2678959547
Short name T904
Test name
Test status
Simulation time 745330563 ps
CPU time 5.05 seconds
Started Aug 12 05:01:26 PM PDT 24
Finished Aug 12 05:01:31 PM PDT 24
Peak memory 210512 kb
Host smart-704808a9-5e5e-40cd-92ec-5bc76fb0926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678959547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2678959547
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4102982732
Short name T82
Test name
Test status
Simulation time 500502648 ps
CPU time 7.13 seconds
Started Aug 12 05:01:21 PM PDT 24
Finished Aug 12 05:01:29 PM PDT 24
Peak memory 209844 kb
Host smart-fc870785-1435-4581-ae09-41a0205260d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102982732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4102982732
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3118724717
Short name T336
Test name
Test status
Simulation time 47556702 ps
CPU time 1.83 seconds
Started Aug 12 05:01:31 PM PDT 24
Finished Aug 12 05:01:33 PM PDT 24
Peak memory 216924 kb
Host smart-75330514-925e-4863-bbc0-d42b5aa1622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118724717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3118724717
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3973132226
Short name T219
Test name
Test status
Simulation time 80208915 ps
CPU time 3.82 seconds
Started Aug 12 05:01:37 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 210380 kb
Host smart-ed81c137-9eda-49ad-a752-32db594e58fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973132226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3973132226
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3864525265
Short name T773
Test name
Test status
Simulation time 281062637 ps
CPU time 4.85 seconds
Started Aug 12 05:01:30 PM PDT 24
Finished Aug 12 05:01:35 PM PDT 24
Peak memory 208240 kb
Host smart-e50cd570-23b3-4d65-84cb-c1b3555bcf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864525265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3864525265
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.57504762
Short name T585
Test name
Test status
Simulation time 754716827 ps
CPU time 10.49 seconds
Started Aug 12 05:01:25 PM PDT 24
Finished Aug 12 05:01:35 PM PDT 24
Peak memory 209220 kb
Host smart-4432f42d-3f46-4e3e-b25e-f8fa014b5e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57504762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.57504762
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1678121037
Short name T432
Test name
Test status
Simulation time 854920964 ps
CPU time 9.04 seconds
Started Aug 12 05:01:27 PM PDT 24
Finished Aug 12 05:01:36 PM PDT 24
Peak memory 208768 kb
Host smart-32bbaeb7-d7f4-426e-83c4-469b2abc521b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678121037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1678121037
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.4261761335
Short name T345
Test name
Test status
Simulation time 219292220 ps
CPU time 6.34 seconds
Started Aug 12 05:01:25 PM PDT 24
Finished Aug 12 05:01:32 PM PDT 24
Peak memory 208976 kb
Host smart-797b35e6-a50e-40d6-82ea-593d847fe259
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261761335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4261761335
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.230421338
Short name T754
Test name
Test status
Simulation time 895671510 ps
CPU time 9.36 seconds
Started Aug 12 05:01:28 PM PDT 24
Finished Aug 12 05:01:38 PM PDT 24
Peak memory 207384 kb
Host smart-a8ec56e1-4da9-4685-8a54-412f9cd99f55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230421338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.230421338
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.705145759
Short name T77
Test name
Test status
Simulation time 145395510 ps
CPU time 1.98 seconds
Started Aug 12 05:01:28 PM PDT 24
Finished Aug 12 05:01:30 PM PDT 24
Peak memory 207480 kb
Host smart-22eb47e4-3eca-4f7c-9fcf-4ff0e2b14b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705145759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.705145759
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.548837049
Short name T805
Test name
Test status
Simulation time 128984190 ps
CPU time 2.13 seconds
Started Aug 12 05:01:20 PM PDT 24
Finished Aug 12 05:01:22 PM PDT 24
Peak memory 207616 kb
Host smart-4f0e3fb2-b8a0-4da0-b3e3-ceb9ca4826cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548837049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.548837049
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.101272362
Short name T121
Test name
Test status
Simulation time 117698823 ps
CPU time 6.72 seconds
Started Aug 12 05:01:27 PM PDT 24
Finished Aug 12 05:01:33 PM PDT 24
Peak memory 219892 kb
Host smart-09cd8719-e28b-4f46-ac75-5f04eb8025a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101272362 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.101272362
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1483362493
Short name T846
Test name
Test status
Simulation time 1079604429 ps
CPU time 7.99 seconds
Started Aug 12 05:01:35 PM PDT 24
Finished Aug 12 05:01:43 PM PDT 24
Peak memory 210504 kb
Host smart-439d0484-6c32-4381-ba4c-b24b6b05e5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483362493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1483362493
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.4105443205
Short name T166
Test name
Test status
Simulation time 179207572 ps
CPU time 4.02 seconds
Started Aug 12 05:01:46 PM PDT 24
Finished Aug 12 05:01:50 PM PDT 24
Peak memory 210784 kb
Host smart-8c04074b-c0d0-48a7-b89f-6335e2ce8727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105443205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4105443205
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.548939171
Short name T564
Test name
Test status
Simulation time 48005127 ps
CPU time 0.78 seconds
Started Aug 12 05:01:42 PM PDT 24
Finished Aug 12 05:01:43 PM PDT 24
Peak memory 206360 kb
Host smart-506df85e-d3fb-4eab-9cde-4afe850ee197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548939171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.548939171
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3027226744
Short name T310
Test name
Test status
Simulation time 45951416 ps
CPU time 3.12 seconds
Started Aug 12 05:01:24 PM PDT 24
Finished Aug 12 05:01:28 PM PDT 24
Peak memory 214856 kb
Host smart-522eb064-22f3-4f8e-a006-83f0cee9f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027226744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3027226744
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1783132971
Short name T239
Test name
Test status
Simulation time 67725171 ps
CPU time 4.01 seconds
Started Aug 12 05:01:30 PM PDT 24
Finished Aug 12 05:01:35 PM PDT 24
Peak memory 214856 kb
Host smart-1eb7378e-ff47-4b7e-9901-ca876b4087c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783132971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1783132971
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2411979692
Short name T337
Test name
Test status
Simulation time 277532250 ps
CPU time 6.05 seconds
Started Aug 12 05:01:30 PM PDT 24
Finished Aug 12 05:01:37 PM PDT 24
Peak memory 222788 kb
Host smart-3a7f47d1-5c68-46cf-8106-28f8540cfb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411979692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2411979692
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.178963168
Short name T391
Test name
Test status
Simulation time 258223933 ps
CPU time 5.87 seconds
Started Aug 12 05:01:35 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 222916 kb
Host smart-aeaa6a36-cab8-4920-9a55-2cfe50509e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178963168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.178963168
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.794218752
Short name T719
Test name
Test status
Simulation time 1267429066 ps
CPU time 9.75 seconds
Started Aug 12 05:01:33 PM PDT 24
Finished Aug 12 05:01:43 PM PDT 24
Peak memory 208756 kb
Host smart-369a0e9a-a3e4-4cd7-b53d-460fa4e6c415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794218752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.794218752
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.4106603863
Short name T307
Test name
Test status
Simulation time 83643385 ps
CPU time 3.88 seconds
Started Aug 12 05:01:32 PM PDT 24
Finished Aug 12 05:01:36 PM PDT 24
Peak memory 209120 kb
Host smart-7c078a3e-93e7-4147-afda-bd73f30dd1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106603863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4106603863
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1882392381
Short name T638
Test name
Test status
Simulation time 763209165 ps
CPU time 24.68 seconds
Started Aug 12 05:01:36 PM PDT 24
Finished Aug 12 05:02:01 PM PDT 24
Peak memory 209684 kb
Host smart-72547aaa-0852-46e9-bf31-6d9d03e19294
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882392381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1882392381
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1072372860
Short name T477
Test name
Test status
Simulation time 224660983 ps
CPU time 6.55 seconds
Started Aug 12 05:01:22 PM PDT 24
Finished Aug 12 05:01:29 PM PDT 24
Peak memory 209072 kb
Host smart-76e5df7d-55ff-4b01-a6ed-f8be4653a5b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072372860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1072372860
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.63604179
Short name T699
Test name
Test status
Simulation time 145785849 ps
CPU time 4.23 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:48 PM PDT 24
Peak memory 207456 kb
Host smart-6274190d-2ca9-4f1d-b5e2-9eaf4ac7c39c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63604179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.63604179
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.394543747
Short name T467
Test name
Test status
Simulation time 614684966 ps
CPU time 1.76 seconds
Started Aug 12 05:01:31 PM PDT 24
Finished Aug 12 05:01:33 PM PDT 24
Peak memory 207464 kb
Host smart-b4fb16ad-40dd-4506-be2f-256a3beb986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394543747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.394543747
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3342813422
Short name T730
Test name
Test status
Simulation time 313335856 ps
CPU time 4.19 seconds
Started Aug 12 05:01:23 PM PDT 24
Finished Aug 12 05:01:27 PM PDT 24
Peak memory 207232 kb
Host smart-f906f1b0-dfd1-4a40-be4d-fb75b7e86d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342813422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3342813422
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2288332319
Short name T66
Test name
Test status
Simulation time 1154011743 ps
CPU time 34.5 seconds
Started Aug 12 05:01:40 PM PDT 24
Finished Aug 12 05:02:15 PM PDT 24
Peak memory 221752 kb
Host smart-87a87688-3e45-44f9-a050-df0a04443568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288332319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2288332319
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.10598880
Short name T576
Test name
Test status
Simulation time 788060637 ps
CPU time 15.81 seconds
Started Aug 12 05:01:42 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 219132 kb
Host smart-09b8fa4b-1ab6-4b58-adb9-328de50cae97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10598880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.10598880
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3692057414
Short name T850
Test name
Test status
Simulation time 298199721 ps
CPU time 2.49 seconds
Started Aug 12 05:01:40 PM PDT 24
Finished Aug 12 05:01:43 PM PDT 24
Peak memory 210480 kb
Host smart-169b9200-8821-4f38-bc64-54b10610d8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692057414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3692057414
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1150392020
Short name T643
Test name
Test status
Simulation time 31304472 ps
CPU time 0.97 seconds
Started Aug 12 05:01:38 PM PDT 24
Finished Aug 12 05:01:39 PM PDT 24
Peak memory 206532 kb
Host smart-ce1a9234-56f2-428c-bd55-68bea129ae90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150392020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1150392020
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2354192488
Short name T681
Test name
Test status
Simulation time 344523022 ps
CPU time 3.29 seconds
Started Aug 12 05:01:42 PM PDT 24
Finished Aug 12 05:01:45 PM PDT 24
Peak memory 214804 kb
Host smart-43781556-7ed9-4e01-8905-ec3d3c718983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354192488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2354192488
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3264146688
Short name T517
Test name
Test status
Simulation time 99332951 ps
CPU time 2.62 seconds
Started Aug 12 05:01:33 PM PDT 24
Finished Aug 12 05:01:36 PM PDT 24
Peak memory 214692 kb
Host smart-8f6b2f8a-21a4-42bd-8c00-6f6535149bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264146688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3264146688
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_random.2638218325
Short name T634
Test name
Test status
Simulation time 75460916 ps
CPU time 3.95 seconds
Started Aug 12 05:01:36 PM PDT 24
Finished Aug 12 05:01:40 PM PDT 24
Peak memory 208728 kb
Host smart-9e629f21-f664-4fda-aac1-5c491620cb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638218325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2638218325
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.587259584
Short name T471
Test name
Test status
Simulation time 252977668 ps
CPU time 2.78 seconds
Started Aug 12 05:01:35 PM PDT 24
Finished Aug 12 05:01:38 PM PDT 24
Peak memory 207268 kb
Host smart-dd256841-3f00-401d-9046-2692f539f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587259584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.587259584
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1348295800
Short name T436
Test name
Test status
Simulation time 151183906 ps
CPU time 3.19 seconds
Started Aug 12 05:01:40 PM PDT 24
Finished Aug 12 05:01:44 PM PDT 24
Peak memory 207460 kb
Host smart-603d252d-5b16-4c3c-be8a-0b9c3683eaff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348295800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1348295800
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3043313271
Short name T746
Test name
Test status
Simulation time 34917498 ps
CPU time 2.26 seconds
Started Aug 12 05:01:30 PM PDT 24
Finished Aug 12 05:01:33 PM PDT 24
Peak memory 207612 kb
Host smart-a50011ae-051d-47ee-8dea-992308e0b8cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043313271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3043313271
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3275768707
Short name T686
Test name
Test status
Simulation time 5323852757 ps
CPU time 33.82 seconds
Started Aug 12 05:01:32 PM PDT 24
Finished Aug 12 05:02:06 PM PDT 24
Peak memory 208508 kb
Host smart-9d29f911-bf27-47b1-9efa-acf84f253849
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275768707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3275768707
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2166213884
Short name T703
Test name
Test status
Simulation time 68675512 ps
CPU time 2.62 seconds
Started Aug 12 05:01:30 PM PDT 24
Finished Aug 12 05:01:32 PM PDT 24
Peak memory 211056 kb
Host smart-f05a2db3-d4e9-4487-a029-ab5c04272852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166213884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2166213884
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3751940506
Short name T429
Test name
Test status
Simulation time 139364982 ps
CPU time 1.91 seconds
Started Aug 12 05:01:39 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 209128 kb
Host smart-9b6ac359-d97c-44ef-8df4-07bf37bc37fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751940506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3751940506
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3652772235
Short name T260
Test name
Test status
Simulation time 183782395 ps
CPU time 5.73 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 214752 kb
Host smart-02b79384-c0f4-4857-9c61-292e1af5dd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652772235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3652772235
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3162500184
Short name T165
Test name
Test status
Simulation time 136054458 ps
CPU time 2.94 seconds
Started Aug 12 05:01:38 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 211032 kb
Host smart-5aad9dcc-3e92-4649-ab84-166285673bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162500184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3162500184
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.518549334
Short name T454
Test name
Test status
Simulation time 23629465 ps
CPU time 0.91 seconds
Started Aug 12 05:01:42 PM PDT 24
Finished Aug 12 05:01:43 PM PDT 24
Peak memory 206324 kb
Host smart-c759b036-8ec0-4e9c-8bc7-405deb163de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518549334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.518549334
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1716589745
Short name T409
Test name
Test status
Simulation time 111828821 ps
CPU time 6.78 seconds
Started Aug 12 05:01:42 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 214840 kb
Host smart-b6a6e9c7-3129-4906-8aae-517d40ea2ab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1716589745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1716589745
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.992452666
Short name T30
Test name
Test status
Simulation time 136736159 ps
CPU time 2.9 seconds
Started Aug 12 05:01:37 PM PDT 24
Finished Aug 12 05:01:40 PM PDT 24
Peak memory 218148 kb
Host smart-e8596bd0-8ed0-45a0-92bc-b8be795ea554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992452666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.992452666
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3338689006
Short name T363
Test name
Test status
Simulation time 92692130 ps
CPU time 2.45 seconds
Started Aug 12 05:01:58 PM PDT 24
Finished Aug 12 05:02:00 PM PDT 24
Peak memory 207504 kb
Host smart-3bcbf546-a149-4b9b-ac49-4336343e009a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338689006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3338689006
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3635070546
Short name T665
Test name
Test status
Simulation time 759690974 ps
CPU time 3.68 seconds
Started Aug 12 05:01:39 PM PDT 24
Finished Aug 12 05:01:42 PM PDT 24
Peak memory 214936 kb
Host smart-940d3a52-28ff-4c1b-af2e-1a74db3b3403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635070546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3635070546
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.26026626
Short name T334
Test name
Test status
Simulation time 79154366 ps
CPU time 2.94 seconds
Started Aug 12 05:01:42 PM PDT 24
Finished Aug 12 05:01:45 PM PDT 24
Peak memory 211900 kb
Host smart-6145a645-3025-4303-94c7-7dbd39759dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26026626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.26026626
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.282671472
Short name T789
Test name
Test status
Simulation time 112702910 ps
CPU time 2.87 seconds
Started Aug 12 05:01:43 PM PDT 24
Finished Aug 12 05:01:46 PM PDT 24
Peak memory 207296 kb
Host smart-a45a09e1-5eb2-4c89-8f2d-e60756f85239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282671472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.282671472
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3673890518
Short name T297
Test name
Test status
Simulation time 138795564 ps
CPU time 5.39 seconds
Started Aug 12 05:01:39 PM PDT 24
Finished Aug 12 05:01:45 PM PDT 24
Peak memory 208164 kb
Host smart-38f213d3-5b06-470c-9894-0b1533396db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673890518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3673890518
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1455321136
Short name T856
Test name
Test status
Simulation time 165555041 ps
CPU time 2.43 seconds
Started Aug 12 05:01:46 PM PDT 24
Finished Aug 12 05:01:48 PM PDT 24
Peak memory 207208 kb
Host smart-dd769738-1475-41c7-bd13-4afd6986479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455321136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1455321136
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.743292451
Short name T526
Test name
Test status
Simulation time 77884337 ps
CPU time 2.93 seconds
Started Aug 12 05:01:38 PM PDT 24
Finished Aug 12 05:01:46 PM PDT 24
Peak memory 208020 kb
Host smart-564711f3-5536-48ba-bf79-429fb6e0ce8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743292451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.743292451
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2849317812
Short name T512
Test name
Test status
Simulation time 407912193 ps
CPU time 7.27 seconds
Started Aug 12 05:01:47 PM PDT 24
Finished Aug 12 05:01:54 PM PDT 24
Peak memory 207464 kb
Host smart-d4e1ac46-bf2b-4415-a69a-ec5a54800503
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849317812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2849317812
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2228674505
Short name T588
Test name
Test status
Simulation time 39731708 ps
CPU time 2.36 seconds
Started Aug 12 05:01:37 PM PDT 24
Finished Aug 12 05:01:40 PM PDT 24
Peak memory 208536 kb
Host smart-c532ac84-f881-4718-acb5-288416479e9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228674505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2228674505
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1415890378
Short name T599
Test name
Test status
Simulation time 483047935 ps
CPU time 8.95 seconds
Started Aug 12 05:01:42 PM PDT 24
Finished Aug 12 05:01:51 PM PDT 24
Peak memory 216320 kb
Host smart-004fe575-0a37-4e97-bb05-9278fbe2306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415890378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1415890378
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2925395115
Short name T414
Test name
Test status
Simulation time 1024539960 ps
CPU time 3.51 seconds
Started Aug 12 05:01:48 PM PDT 24
Finished Aug 12 05:01:52 PM PDT 24
Peak memory 207448 kb
Host smart-27bbb0fb-1c24-4139-8f5a-08b23a6334f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925395115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2925395115
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1348486890
Short name T584
Test name
Test status
Simulation time 825571356 ps
CPU time 6.77 seconds
Started Aug 12 05:01:35 PM PDT 24
Finished Aug 12 05:01:42 PM PDT 24
Peak memory 207820 kb
Host smart-5aa3e4c6-0118-475b-bc87-1d80629f79d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348486890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1348486890
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2390306047
Short name T485
Test name
Test status
Simulation time 197870488 ps
CPU time 2.68 seconds
Started Aug 12 05:01:43 PM PDT 24
Finished Aug 12 05:01:46 PM PDT 24
Peak memory 210448 kb
Host smart-73b2365a-900c-46d9-9e3e-f14f3e3c99a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390306047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2390306047
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.431082367
Short name T899
Test name
Test status
Simulation time 56414676 ps
CPU time 0.96 seconds
Started Aug 12 05:01:51 PM PDT 24
Finished Aug 12 05:01:52 PM PDT 24
Peak memory 206512 kb
Host smart-cf4289e8-1418-4dbf-bc74-19a336c033e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431082367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.431082367
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.171034699
Short name T376
Test name
Test status
Simulation time 267318973 ps
CPU time 7.65 seconds
Started Aug 12 05:01:32 PM PDT 24
Finished Aug 12 05:01:39 PM PDT 24
Peak memory 214928 kb
Host smart-527b7b59-a6cd-4093-9351-1b32f00a7e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171034699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.171034699
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3851786353
Short name T29
Test name
Test status
Simulation time 3168564198 ps
CPU time 12.59 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:02:09 PM PDT 24
Peak memory 210564 kb
Host smart-bdc9e317-31ae-4e42-8122-7a707ffdc749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851786353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3851786353
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1469593102
Short name T698
Test name
Test status
Simulation time 353407298 ps
CPU time 5.19 seconds
Started Aug 12 05:01:31 PM PDT 24
Finished Aug 12 05:01:36 PM PDT 24
Peak memory 209028 kb
Host smart-c98ff4ed-ca2d-4388-afce-282a83623e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469593102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1469593102
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3163267992
Short name T862
Test name
Test status
Simulation time 217382505 ps
CPU time 3.28 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 222848 kb
Host smart-6f799f6a-48ac-4f07-99c3-de1eb48c3bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163267992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3163267992
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1171550592
Short name T733
Test name
Test status
Simulation time 90049067 ps
CPU time 2.55 seconds
Started Aug 12 05:01:40 PM PDT 24
Finished Aug 12 05:01:43 PM PDT 24
Peak memory 209652 kb
Host smart-44707ee7-8bcc-4bbd-bc04-dbd3960b4442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171550592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1171550592
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2991318014
Short name T797
Test name
Test status
Simulation time 216270010 ps
CPU time 6.28 seconds
Started Aug 12 05:01:34 PM PDT 24
Finished Aug 12 05:01:40 PM PDT 24
Peak memory 207856 kb
Host smart-422b2377-e8e6-4269-a30a-5656ca166cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991318014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2991318014
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3069194931
Short name T251
Test name
Test status
Simulation time 191743059 ps
CPU time 2.91 seconds
Started Aug 12 05:01:38 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 207296 kb
Host smart-df867382-8388-4659-b594-e293728d0b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069194931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3069194931
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1781483897
Short name T688
Test name
Test status
Simulation time 38592501 ps
CPU time 2.44 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:48 PM PDT 24
Peak memory 209196 kb
Host smart-434b41eb-ecab-4768-9b01-f0baac4bd5e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781483897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1781483897
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3000154571
Short name T745
Test name
Test status
Simulation time 367709864 ps
CPU time 5.58 seconds
Started Aug 12 05:01:43 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 208964 kb
Host smart-44fd8004-af53-484d-8d01-12560b6612c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000154571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3000154571
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2978632410
Short name T320
Test name
Test status
Simulation time 203261654 ps
CPU time 7.33 seconds
Started Aug 12 05:01:38 PM PDT 24
Finished Aug 12 05:01:45 PM PDT 24
Peak memory 209404 kb
Host smart-27db3c78-ecd2-40aa-81ef-52ed19f30e64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978632410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2978632410
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.648679256
Short name T824
Test name
Test status
Simulation time 105381169 ps
CPU time 2 seconds
Started Aug 12 05:01:54 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 208436 kb
Host smart-ae5ed27e-79fa-43c8-82d4-f027b9315e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648679256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.648679256
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.936176515
Short name T765
Test name
Test status
Simulation time 270206046 ps
CPU time 5.62 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:50 PM PDT 24
Peak memory 207132 kb
Host smart-9fdeca4f-b209-460f-bd8e-b3eaf4d8f080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936176515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.936176515
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1020114726
Short name T674
Test name
Test status
Simulation time 122390344 ps
CPU time 4.11 seconds
Started Aug 12 05:01:30 PM PDT 24
Finished Aug 12 05:01:34 PM PDT 24
Peak memory 214776 kb
Host smart-6bb8254b-78f9-4f41-85cf-689871c77b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020114726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1020114726
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3920827026
Short name T863
Test name
Test status
Simulation time 15883746 ps
CPU time 0.76 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:50 PM PDT 24
Peak memory 206376 kb
Host smart-0b065456-325d-483b-8aa7-75274ec33cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920827026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3920827026
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1717823873
Short name T749
Test name
Test status
Simulation time 267898525 ps
CPU time 2.98 seconds
Started Aug 12 05:01:54 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 215584 kb
Host smart-9bc5cce7-30e5-4192-8300-c7e6b984e2eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1717823873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1717823873
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1906948572
Short name T32
Test name
Test status
Simulation time 342551505 ps
CPU time 2.94 seconds
Started Aug 12 05:01:39 PM PDT 24
Finished Aug 12 05:01:42 PM PDT 24
Peak memory 209536 kb
Host smart-83b0b682-78de-4734-83ce-a09d2f288bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906948572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1906948572
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4269262656
Short name T224
Test name
Test status
Simulation time 674979240 ps
CPU time 3.08 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:48 PM PDT 24
Peak memory 208368 kb
Host smart-93d094d4-aa34-4e99-97f0-84de429c4bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269262656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4269262656
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.770066869
Short name T286
Test name
Test status
Simulation time 137126808 ps
CPU time 2.81 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 214840 kb
Host smart-acaa3c9f-f044-4cc5-954e-e0ee1e29aa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770066869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.770066869
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3054153432
Short name T847
Test name
Test status
Simulation time 35354678 ps
CPU time 2.59 seconds
Started Aug 12 05:01:46 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 222328 kb
Host smart-e5dcb75c-5936-4787-bc74-fc14ca25a6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054153432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3054153432
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2636380140
Short name T473
Test name
Test status
Simulation time 477346467 ps
CPU time 5.34 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:02:00 PM PDT 24
Peak memory 220280 kb
Host smart-2ffc7c60-4ea1-400c-a135-cdb29d089162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636380140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2636380140
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3105969965
Short name T815
Test name
Test status
Simulation time 378560159 ps
CPU time 4.2 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:54 PM PDT 24
Peak memory 208060 kb
Host smart-6941fbde-4b00-4fa9-a7d2-aa67d786d147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105969965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3105969965
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1012605234
Short name T300
Test name
Test status
Simulation time 70229745 ps
CPU time 2.68 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 209044 kb
Host smart-ac3b828c-b5d6-4a6f-bf6a-497db3bfddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012605234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1012605234
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3621503242
Short name T468
Test name
Test status
Simulation time 73254612 ps
CPU time 2.28 seconds
Started Aug 12 05:01:46 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 207488 kb
Host smart-f1efce57-348a-499b-9382-795d548519c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621503242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3621503242
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3723697896
Short name T399
Test name
Test status
Simulation time 114037998 ps
CPU time 2.54 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 209100 kb
Host smart-b5680827-c776-41a0-9231-66687cc676cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723697896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3723697896
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3534066525
Short name T344
Test name
Test status
Simulation time 32830514 ps
CPU time 2.41 seconds
Started Aug 12 05:01:48 PM PDT 24
Finished Aug 12 05:01:51 PM PDT 24
Peak memory 207520 kb
Host smart-d5bef2f7-ee24-40e3-83a7-3f30a68585e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534066525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3534066525
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1013157627
Short name T779
Test name
Test status
Simulation time 43886461 ps
CPU time 2.56 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 216660 kb
Host smart-e2e5c3ab-f77d-4b0b-968d-653ed642bdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013157627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1013157627
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.762988557
Short name T837
Test name
Test status
Simulation time 86777512 ps
CPU time 2.84 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:51 PM PDT 24
Peak memory 208988 kb
Host smart-57e9022b-0eed-438d-bb37-0caf2d7541fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762988557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.762988557
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1870963442
Short name T60
Test name
Test status
Simulation time 1023982118 ps
CPU time 27.74 seconds
Started Aug 12 05:01:50 PM PDT 24
Finished Aug 12 05:02:18 PM PDT 24
Peak memory 216788 kb
Host smart-a184f862-90cc-4f69-a4d5-c4e01cc28ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870963442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1870963442
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3628626971
Short name T437
Test name
Test status
Simulation time 246695303 ps
CPU time 3.53 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:48 PM PDT 24
Peak memory 208008 kb
Host smart-fb60d99b-8a7f-42e8-a8b9-f5fe9eb43b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628626971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3628626971
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3883188515
Short name T529
Test name
Test status
Simulation time 72254277 ps
CPU time 2.55 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 210484 kb
Host smart-0867a965-f330-4e44-81e1-742d72145e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883188515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3883188515
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4178573380
Short name T658
Test name
Test status
Simulation time 51077603 ps
CPU time 0.92 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:00:57 PM PDT 24
Peak memory 206336 kb
Host smart-adb21f25-b45e-42a3-a634-c84124c745ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178573380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4178573380
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.906407678
Short name T565
Test name
Test status
Simulation time 258939799 ps
CPU time 2.46 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:00:53 PM PDT 24
Peak memory 220216 kb
Host smart-39eabddc-ca05-4fbb-b4ad-d0420536136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906407678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.906407678
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.4188762238
Short name T769
Test name
Test status
Simulation time 960541217 ps
CPU time 3.59 seconds
Started Aug 12 05:00:54 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 208500 kb
Host smart-ab8b1604-57d6-4155-b088-edd48c0784d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188762238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.4188762238
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.966054709
Short name T59
Test name
Test status
Simulation time 459435411 ps
CPU time 4.6 seconds
Started Aug 12 05:00:55 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 214448 kb
Host smart-5fbbec16-c871-47b6-848c-518952ad5434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966054709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.966054709
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3226278454
Short name T521
Test name
Test status
Simulation time 104485974 ps
CPU time 2.06 seconds
Started Aug 12 05:01:00 PM PDT 24
Finished Aug 12 05:01:03 PM PDT 24
Peak memory 214780 kb
Host smart-bcf99b6a-4797-4805-9f8a-5bacfea583fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226278454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3226278454
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.919147694
Short name T591
Test name
Test status
Simulation time 86582987 ps
CPU time 4.19 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 210316 kb
Host smart-c3fb9a60-fa43-42d0-891b-cbe22f11c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919147694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.919147694
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1514512214
Short name T98
Test name
Test status
Simulation time 5657299232 ps
CPU time 7.41 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 231116 kb
Host smart-96f4a86b-400f-4747-9696-9d82cde84664
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514512214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1514512214
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.473409230
Short name T478
Test name
Test status
Simulation time 44241139 ps
CPU time 2.25 seconds
Started Aug 12 05:00:51 PM PDT 24
Finished Aug 12 05:00:53 PM PDT 24
Peak memory 207616 kb
Host smart-bc66ed9d-2e26-4e45-b6ad-c22bce7d98b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473409230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.473409230
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2466339744
Short name T516
Test name
Test status
Simulation time 343434178 ps
CPU time 2.86 seconds
Started Aug 12 05:00:55 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 207344 kb
Host smart-a7338868-a0f8-4504-963c-7c686c9d28a7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466339744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2466339744
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.438874201
Short name T425
Test name
Test status
Simulation time 1242793259 ps
CPU time 27.39 seconds
Started Aug 12 05:01:01 PM PDT 24
Finished Aug 12 05:01:28 PM PDT 24
Peak memory 208704 kb
Host smart-40f55634-c546-4532-ba82-80467c0fafe0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438874201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.438874201
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.103891577
Short name T892
Test name
Test status
Simulation time 797576382 ps
CPU time 6.29 seconds
Started Aug 12 05:00:51 PM PDT 24
Finished Aug 12 05:00:57 PM PDT 24
Peak memory 209124 kb
Host smart-dab7be94-dff9-473d-a0bb-7ee01dbfe957
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103891577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.103891577
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2059870414
Short name T855
Test name
Test status
Simulation time 2084377107 ps
CPU time 4.69 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:57 PM PDT 24
Peak memory 209316 kb
Host smart-b286601a-445a-43ba-b650-fd7ad321a521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059870414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2059870414
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2681328880
Short name T881
Test name
Test status
Simulation time 9606481469 ps
CPU time 66.98 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 216884 kb
Host smart-2f96617e-0352-42d7-9824-a257fd0c591e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681328880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2681328880
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1505698248
Short name T811
Test name
Test status
Simulation time 1229322517 ps
CPU time 13.13 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:12 PM PDT 24
Peak memory 222996 kb
Host smart-66fab4bc-4e98-47cf-90bc-79cee5299074
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505698248 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1505698248
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2114130414
Short name T579
Test name
Test status
Simulation time 134519591 ps
CPU time 5.25 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 210696 kb
Host smart-28653618-88a3-486d-96f7-b2b437407f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114130414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2114130414
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.960310948
Short name T149
Test name
Test status
Simulation time 192714099 ps
CPU time 1.88 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:00:55 PM PDT 24
Peak memory 210436 kb
Host smart-47d9edf6-67e0-4674-a4bb-6abcac8a710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960310948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.960310948
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3776693110
Short name T575
Test name
Test status
Simulation time 12199556 ps
CPU time 0.9 seconds
Started Aug 12 05:01:48 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 206316 kb
Host smart-9ab48843-f4fc-4428-827d-c28473257925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776693110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3776693110
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.463382504
Short name T346
Test name
Test status
Simulation time 217110534 ps
CPU time 4.55 seconds
Started Aug 12 05:01:58 PM PDT 24
Finished Aug 12 05:02:02 PM PDT 24
Peak memory 215980 kb
Host smart-ae9cb778-30a9-4c6d-8281-0dca4a658b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=463382504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.463382504
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2488792424
Short name T676
Test name
Test status
Simulation time 134317842 ps
CPU time 2.86 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 218932 kb
Host smart-75c52ce8-8b35-4d0b-94c8-9fda0d6a88c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488792424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2488792424
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2279006375
Short name T888
Test name
Test status
Simulation time 1580496641 ps
CPU time 7.45 seconds
Started Aug 12 05:01:40 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 221300 kb
Host smart-4203bae3-78af-453f-a316-2feceb764e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279006375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2279006375
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.504077521
Short name T484
Test name
Test status
Simulation time 80076723 ps
CPU time 3.39 seconds
Started Aug 12 05:01:39 PM PDT 24
Finished Aug 12 05:01:43 PM PDT 24
Peak memory 221840 kb
Host smart-7b593e3f-12a3-4ce9-8e4d-b8eaa9f0b0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504077521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.504077521
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.680220379
Short name T438
Test name
Test status
Simulation time 126222184 ps
CPU time 2.06 seconds
Started Aug 12 05:01:47 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 214984 kb
Host smart-bc0fb103-8075-447a-b7df-8d0b611eb39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680220379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.680220379
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.432679565
Short name T706
Test name
Test status
Simulation time 406562978 ps
CPU time 4.94 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 208112 kb
Host smart-3da8e0fd-ab7d-4b41-b5a7-b9fcb2c0806d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432679565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.432679565
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.4087923457
Short name T884
Test name
Test status
Simulation time 50088869 ps
CPU time 2.54 seconds
Started Aug 12 05:01:46 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 208480 kb
Host smart-7cabe08b-d46a-489c-9f83-b2176ab3fbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087923457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.4087923457
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2186398052
Short name T741
Test name
Test status
Simulation time 942310989 ps
CPU time 7.23 seconds
Started Aug 12 05:01:43 PM PDT 24
Finished Aug 12 05:01:51 PM PDT 24
Peak memory 208688 kb
Host smart-36f963ed-f349-4ad2-bb04-b50682925f00
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186398052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2186398052
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.832310492
Short name T312
Test name
Test status
Simulation time 77106362 ps
CPU time 2.63 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 207348 kb
Host smart-e2b40dae-7490-4f0b-af78-e771eddf9ea4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832310492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.832310492
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1276195249
Short name T818
Test name
Test status
Simulation time 95892256 ps
CPU time 1.8 seconds
Started Aug 12 05:01:39 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 207428 kb
Host smart-bda114eb-6220-438c-95a0-b14810ce72c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276195249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1276195249
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4284680335
Short name T242
Test name
Test status
Simulation time 85721829 ps
CPU time 2.74 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 218828 kb
Host smart-61b25cb5-372b-4d1d-bcba-a5dad6c02938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284680335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4284680335
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.988661457
Short name T705
Test name
Test status
Simulation time 200236410 ps
CPU time 4.03 seconds
Started Aug 12 05:01:47 PM PDT 24
Finished Aug 12 05:01:51 PM PDT 24
Peak memory 208756 kb
Host smart-e3fa31f9-8d2d-4bbc-80b8-a6b9edd47f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988661457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.988661457
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2343993034
Short name T428
Test name
Test status
Simulation time 56658666 ps
CPU time 2.77 seconds
Started Aug 12 05:01:51 PM PDT 24
Finished Aug 12 05:01:54 PM PDT 24
Peak memory 207776 kb
Host smart-696a72bd-6b01-4179-8818-f752abbf6ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343993034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2343993034
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2000977000
Short name T75
Test name
Test status
Simulation time 499257829 ps
CPU time 11.66 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:02:04 PM PDT 24
Peak memory 223076 kb
Host smart-b9674dab-f481-4c6f-8e7b-ef56c4fb6eb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000977000 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2000977000
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3975140940
Short name T356
Test name
Test status
Simulation time 829085807 ps
CPU time 6.97 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:53 PM PDT 24
Peak memory 214840 kb
Host smart-5c3fe1d9-3bc7-43ce-90ef-de96fe7b9987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975140940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3975140940
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3644734697
Short name T175
Test name
Test status
Simulation time 39479185 ps
CPU time 2.07 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:46 PM PDT 24
Peak memory 210860 kb
Host smart-9bdf1b2f-f226-47fd-a693-a096711bbe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644734697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3644734697
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1123994095
Short name T786
Test name
Test status
Simulation time 13151631 ps
CPU time 0.78 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:46 PM PDT 24
Peak memory 206404 kb
Host smart-5446daff-3dc3-4e42-9e54-10075ce22d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123994095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1123994095
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.330114662
Short name T140
Test name
Test status
Simulation time 125525136 ps
CPU time 4.5 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 215900 kb
Host smart-a2089e6b-3516-4f6e-8876-c4e28f332160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330114662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.330114662
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1007505104
Short name T26
Test name
Test status
Simulation time 67685018 ps
CPU time 3.26 seconds
Started Aug 12 05:01:43 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 221796 kb
Host smart-e9e7e763-d2aa-450c-b684-30a2c5c664c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007505104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1007505104
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3338169637
Short name T652
Test name
Test status
Simulation time 192141921 ps
CPU time 1.8 seconds
Started Aug 12 05:01:46 PM PDT 24
Finished Aug 12 05:01:48 PM PDT 24
Peak memory 208136 kb
Host smart-9086795f-e6cb-4929-9863-738e3d32f67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338169637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3338169637
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.570126809
Short name T670
Test name
Test status
Simulation time 88807264 ps
CPU time 4.36 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:54 PM PDT 24
Peak memory 214884 kb
Host smart-ea855d35-d332-4608-b8a2-589e1fb90913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570126809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.570126809
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2394040093
Short name T233
Test name
Test status
Simulation time 106607172 ps
CPU time 2.39 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 214952 kb
Host smart-bf782bba-59f4-41ce-9b51-d0b5c425fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394040093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2394040093
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.4184188747
Short name T738
Test name
Test status
Simulation time 76294558 ps
CPU time 2.48 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 207704 kb
Host smart-6958b4b8-ff03-415d-8a6e-6405d5c3cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184188747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4184188747
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2634526353
Short name T413
Test name
Test status
Simulation time 1090891217 ps
CPU time 6.4 seconds
Started Aug 12 05:01:50 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 208088 kb
Host smart-619a8375-9469-41c9-b894-d3da0b031dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634526353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2634526353
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3821059882
Short name T762
Test name
Test status
Simulation time 198354069 ps
CPU time 5.5 seconds
Started Aug 12 05:01:43 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 209528 kb
Host smart-c0fcf004-1250-43fd-adfb-07bc00aa1728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821059882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3821059882
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.141675486
Short name T443
Test name
Test status
Simulation time 618020313 ps
CPU time 9.15 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 209132 kb
Host smart-c3c61a94-db88-4271-b7ce-1aeda83b7906
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141675486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.141675486
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1333125255
Short name T433
Test name
Test status
Simulation time 76078163 ps
CPU time 3.53 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 209232 kb
Host smart-2b03b9f1-bd72-48f9-8ea9-0973c8def081
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333125255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1333125255
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2905606085
Short name T615
Test name
Test status
Simulation time 1319797683 ps
CPU time 10.37 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:02:00 PM PDT 24
Peak memory 209396 kb
Host smart-545737a4-4047-49c1-954d-2d4fff2af37d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905606085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2905606085
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3481768664
Short name T654
Test name
Test status
Simulation time 94153512 ps
CPU time 2.57 seconds
Started Aug 12 05:01:41 PM PDT 24
Finished Aug 12 05:01:44 PM PDT 24
Peak memory 216604 kb
Host smart-483770bd-020f-4b77-98bd-354c5ba8f73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481768664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3481768664
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4003114467
Short name T489
Test name
Test status
Simulation time 443927844 ps
CPU time 7.48 seconds
Started Aug 12 05:01:38 PM PDT 24
Finished Aug 12 05:01:45 PM PDT 24
Peak memory 208952 kb
Host smart-bce5cd87-531e-4d7d-9bb7-e78c68ddbe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003114467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4003114467
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3802562013
Short name T549
Test name
Test status
Simulation time 98804490 ps
CPU time 3 seconds
Started Aug 12 05:01:46 PM PDT 24
Finished Aug 12 05:01:50 PM PDT 24
Peak memory 207392 kb
Host smart-8c7356b4-09b1-4592-ae5d-dcf0666ba232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802562013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3802562013
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1905019024
Short name T644
Test name
Test status
Simulation time 480091145 ps
CPU time 18.26 seconds
Started Aug 12 05:01:52 PM PDT 24
Finished Aug 12 05:02:10 PM PDT 24
Peak memory 223024 kb
Host smart-a6a66597-bd9e-4e2c-8d9d-d460d6434053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905019024 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1905019024
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3267359416
Short name T562
Test name
Test status
Simulation time 459754203 ps
CPU time 4.61 seconds
Started Aug 12 05:01:52 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 209460 kb
Host smart-463d5ccd-d53a-4851-8709-63089fb91d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267359416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3267359416
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1691858806
Short name T515
Test name
Test status
Simulation time 39348322 ps
CPU time 1.7 seconds
Started Aug 12 05:01:42 PM PDT 24
Finished Aug 12 05:01:44 PM PDT 24
Peak memory 210160 kb
Host smart-36128da0-5b6c-463d-90f7-448f09b43227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691858806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1691858806
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.221527150
Short name T650
Test name
Test status
Simulation time 29325798 ps
CPU time 0.78 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 206332 kb
Host smart-c1222213-83f7-4daa-afa2-dd3c7238e972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221527150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.221527150
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1925048447
Short name T407
Test name
Test status
Simulation time 360316595 ps
CPU time 3.85 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 214852 kb
Host smart-be642a30-074c-4ea6-a47b-d5271198c667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1925048447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1925048447
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2038817820
Short name T777
Test name
Test status
Simulation time 18947465 ps
CPU time 1.47 seconds
Started Aug 12 05:01:50 PM PDT 24
Finished Aug 12 05:01:52 PM PDT 24
Peak memory 207984 kb
Host smart-3b960877-48f3-4cd0-b00f-d568e4ad6d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038817820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2038817820
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3260813921
Short name T89
Test name
Test status
Simulation time 132156397 ps
CPU time 2.87 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 222988 kb
Host smart-19481c0a-fe39-4686-a4d9-03752e78e05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260813921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3260813921
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2354293531
Short name T234
Test name
Test status
Simulation time 4353724750 ps
CPU time 5.3 seconds
Started Aug 12 05:02:00 PM PDT 24
Finished Aug 12 05:02:05 PM PDT 24
Peak memory 222804 kb
Host smart-0f357856-1333-44e5-b15d-7db8e015fc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354293531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2354293531
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3291024225
Short name T211
Test name
Test status
Simulation time 553000110 ps
CPU time 14.6 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 210468 kb
Host smart-14f71f62-ed2e-4ccb-bd7c-8ea683ccc3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291024225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3291024225
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2409629533
Short name T367
Test name
Test status
Simulation time 4445784313 ps
CPU time 50.61 seconds
Started Aug 12 05:01:54 PM PDT 24
Finished Aug 12 05:02:44 PM PDT 24
Peak memory 218720 kb
Host smart-bbbf328e-5165-462c-8fa2-17d8c922dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409629533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2409629533
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3803994888
Short name T804
Test name
Test status
Simulation time 129169780 ps
CPU time 1.82 seconds
Started Aug 12 05:01:50 PM PDT 24
Finished Aug 12 05:01:52 PM PDT 24
Peak memory 206552 kb
Host smart-33624e3c-c150-453f-90cc-1ebbe45682cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803994888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3803994888
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2417252949
Short name T361
Test name
Test status
Simulation time 62277306 ps
CPU time 3.16 seconds
Started Aug 12 05:01:48 PM PDT 24
Finished Aug 12 05:01:51 PM PDT 24
Peak memory 207396 kb
Host smart-8d6e2948-5434-419e-84ba-e25247162812
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417252949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2417252949
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2711593277
Short name T556
Test name
Test status
Simulation time 117335903 ps
CPU time 4 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 207408 kb
Host smart-d8b3f0db-b08c-4c3b-9b52-873e14b6117b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711593277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2711593277
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2248238975
Short name T340
Test name
Test status
Simulation time 65241375 ps
CPU time 3.26 seconds
Started Aug 12 05:01:45 PM PDT 24
Finished Aug 12 05:01:49 PM PDT 24
Peak memory 209056 kb
Host smart-1b330a0e-a60a-4a05-a4ad-e1fffd735b7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248238975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2248238975
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.886367252
Short name T347
Test name
Test status
Simulation time 124681943 ps
CPU time 3.77 seconds
Started Aug 12 05:01:57 PM PDT 24
Finished Aug 12 05:02:01 PM PDT 24
Peak memory 216148 kb
Host smart-ae52e700-9818-42c5-bef4-e9a680660604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886367252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.886367252
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3626305425
Short name T711
Test name
Test status
Simulation time 1118445473 ps
CPU time 19.94 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:02:17 PM PDT 24
Peak memory 208568 kb
Host smart-4784de6c-4968-4d49-bce6-07107064dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626305425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3626305425
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1724618127
Short name T869
Test name
Test status
Simulation time 293041013 ps
CPU time 8.05 seconds
Started Aug 12 05:01:44 PM PDT 24
Finished Aug 12 05:01:52 PM PDT 24
Peak memory 210684 kb
Host smart-090d7570-44e8-420b-9533-750ab04c9c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724618127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1724618127
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1030110798
Short name T712
Test name
Test status
Simulation time 175931082 ps
CPU time 2.32 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 210456 kb
Host smart-7a7146c6-23b5-4e5c-b8fd-8bc411eaddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030110798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1030110798
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1176196413
Short name T790
Test name
Test status
Simulation time 42521559 ps
CPU time 0.74 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 206344 kb
Host smart-b87e23b2-ff1a-408f-90fd-1a1fc1e051b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176196413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1176196413
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.241911248
Short name T687
Test name
Test status
Simulation time 149519963 ps
CPU time 2.29 seconds
Started Aug 12 05:01:52 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 214796 kb
Host smart-f6c313eb-a364-451e-b375-889a2f33ce6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241911248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.241911248
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1817526034
Short name T52
Test name
Test status
Simulation time 430731141 ps
CPU time 4.78 seconds
Started Aug 12 05:01:51 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 214812 kb
Host smart-746034a2-29e4-4eec-b090-d3022cf9556b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817526034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1817526034
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1527847960
Short name T279
Test name
Test status
Simulation time 504917735 ps
CPU time 3.41 seconds
Started Aug 12 05:01:52 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 215184 kb
Host smart-46411619-87b6-4a1d-a088-cb94687e15aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527847960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1527847960
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3968266746
Short name T697
Test name
Test status
Simulation time 62083820 ps
CPU time 2.04 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 208604 kb
Host smart-d4de0540-de66-40a2-a5dc-f5cdadc484cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968266746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3968266746
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2356986430
Short name T79
Test name
Test status
Simulation time 80653573 ps
CPU time 3.85 seconds
Started Aug 12 05:01:54 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 210600 kb
Host smart-1106a3e0-7e74-4075-b3be-773d3899fc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356986430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2356986430
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2057407497
Short name T778
Test name
Test status
Simulation time 165376871 ps
CPU time 4.68 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:54 PM PDT 24
Peak memory 207324 kb
Host smart-a0870739-9f6f-414a-8c45-0357765c6f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057407497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2057407497
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1669946114
Short name T439
Test name
Test status
Simulation time 363678739 ps
CPU time 4.08 seconds
Started Aug 12 05:01:48 PM PDT 24
Finished Aug 12 05:01:52 PM PDT 24
Peak memory 207584 kb
Host smart-f985db30-9e7a-4080-8215-5ed1ed762241
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669946114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1669946114
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3821731484
Short name T758
Test name
Test status
Simulation time 153416183 ps
CPU time 4.78 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 209096 kb
Host smart-5b9160f3-fd56-42df-a3f6-7fed6e18e19b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821731484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3821731484
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1207977850
Short name T469
Test name
Test status
Simulation time 601026955 ps
CPU time 3.26 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 207412 kb
Host smart-d1ae22b4-8886-4afe-a6d9-d05f2b346df8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207977850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1207977850
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2253204080
Short name T691
Test name
Test status
Simulation time 88378460 ps
CPU time 3.05 seconds
Started Aug 12 05:01:47 PM PDT 24
Finished Aug 12 05:01:50 PM PDT 24
Peak memory 218712 kb
Host smart-ddbca95f-36ff-45c2-8edb-0fddde92d404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253204080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2253204080
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.70009141
Short name T502
Test name
Test status
Simulation time 40528602 ps
CPU time 2.32 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 207428 kb
Host smart-25f54c75-5d3c-4eff-8bde-9bb138f11841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70009141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.70009141
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3611817167
Short name T47
Test name
Test status
Simulation time 7124195237 ps
CPU time 23.42 seconds
Started Aug 12 05:01:47 PM PDT 24
Finished Aug 12 05:02:11 PM PDT 24
Peak memory 216076 kb
Host smart-1660e55c-a464-4e61-8536-8d1ea134e5aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611817167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3611817167
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.106751226
Short name T120
Test name
Test status
Simulation time 263745311 ps
CPU time 9.66 seconds
Started Aug 12 05:01:54 PM PDT 24
Finished Aug 12 05:02:04 PM PDT 24
Peak memory 222924 kb
Host smart-a523ca64-13f8-4651-bbe3-a3a353759f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106751226 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.106751226
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1987316358
Short name T460
Test name
Test status
Simulation time 153941454 ps
CPU time 6.77 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:02:02 PM PDT 24
Peak memory 210904 kb
Host smart-67ecc4fb-ab64-4b92-9376-a0b5a96ce452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987316358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1987316358
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2447481049
Short name T830
Test name
Test status
Simulation time 115898777 ps
CPU time 3.6 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 211340 kb
Host smart-074871d4-f7a7-4b32-a832-8b01db904ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447481049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2447481049
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2015089280
Short name T729
Test name
Test status
Simulation time 93640004 ps
CPU time 0.73 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 206376 kb
Host smart-d537b43c-89b1-4a29-bcd9-fc75929de6fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015089280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2015089280
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3754550198
Short name T405
Test name
Test status
Simulation time 495432227 ps
CPU time 26.65 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 214748 kb
Host smart-7ff338dc-6ae6-4ebd-b842-1a0620562594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754550198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3754550198
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.912427245
Short name T232
Test name
Test status
Simulation time 427442466 ps
CPU time 3.17 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 208324 kb
Host smart-7365da26-aa0b-48f4-aa52-0b28429bdda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912427245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.912427245
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.4232454857
Short name T24
Test name
Test status
Simulation time 8688019767 ps
CPU time 41.89 seconds
Started Aug 12 05:01:50 PM PDT 24
Finished Aug 12 05:02:32 PM PDT 24
Peak memory 214840 kb
Host smart-a196bb3b-79ed-4d4f-ae1b-c5b170651269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232454857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.4232454857
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.755326902
Short name T90
Test name
Test status
Simulation time 106874504 ps
CPU time 4 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:02:00 PM PDT 24
Peak memory 214676 kb
Host smart-1af1fac6-84fa-43e4-a467-3d37eeb9dede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755326902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.755326902
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1497159285
Short name T874
Test name
Test status
Simulation time 338371168 ps
CPU time 3.8 seconds
Started Aug 12 05:01:54 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 219064 kb
Host smart-cca6c6d4-b93c-45f8-b480-36f65d2e857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497159285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1497159285
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1780904112
Short name T474
Test name
Test status
Simulation time 284983550 ps
CPU time 6.01 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 209352 kb
Host smart-f352c305-145b-480d-8f7d-a46d4efacf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780904112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1780904112
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1284740015
Short name T102
Test name
Test status
Simulation time 219660958 ps
CPU time 5.45 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 209016 kb
Host smart-acf51fc2-bf25-4ffc-9cf1-e17a35024ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284740015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1284740015
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.435143069
Short name T914
Test name
Test status
Simulation time 1257889771 ps
CPU time 32.41 seconds
Started Aug 12 05:01:52 PM PDT 24
Finished Aug 12 05:02:25 PM PDT 24
Peak memory 209648 kb
Host smart-2335b79b-9b8b-44ab-bf2d-30af791aa07a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435143069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.435143069
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1549323118
Short name T845
Test name
Test status
Simulation time 130707269 ps
CPU time 2.41 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 207392 kb
Host smart-ea8925c3-3068-427a-a301-d0638c2280a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549323118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1549323118
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1797901029
Short name T810
Test name
Test status
Simulation time 301181366 ps
CPU time 3.93 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:53 PM PDT 24
Peak memory 207432 kb
Host smart-443d7486-3868-4093-9e36-cc7e873e0feb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797901029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1797901029
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2068906835
Short name T514
Test name
Test status
Simulation time 1446853987 ps
CPU time 13.75 seconds
Started Aug 12 05:01:59 PM PDT 24
Finished Aug 12 05:02:13 PM PDT 24
Peak memory 219096 kb
Host smart-ff85da72-9ef4-4da9-b3e8-0652353cb4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068906835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2068906835
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1129899965
Short name T622
Test name
Test status
Simulation time 496342347 ps
CPU time 2.77 seconds
Started Aug 12 05:01:47 PM PDT 24
Finished Aug 12 05:01:50 PM PDT 24
Peak memory 207504 kb
Host smart-bff96cc4-2344-4bc5-8376-b61b5b40f7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129899965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1129899965
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1066238470
Short name T513
Test name
Test status
Simulation time 1996623746 ps
CPU time 32.67 seconds
Started Aug 12 05:01:48 PM PDT 24
Finished Aug 12 05:02:21 PM PDT 24
Peak memory 220104 kb
Host smart-78150d7d-b987-4cf0-a258-70799912cac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066238470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1066238470
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3843740232
Short name T750
Test name
Test status
Simulation time 205794783 ps
CPU time 4.7 seconds
Started Aug 12 05:01:58 PM PDT 24
Finished Aug 12 05:02:03 PM PDT 24
Peak memory 207712 kb
Host smart-a952f297-3d43-4d73-bfab-f6ab932edb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843740232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3843740232
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2522723826
Short name T672
Test name
Test status
Simulation time 95736466 ps
CPU time 1.59 seconds
Started Aug 12 05:01:49 PM PDT 24
Finished Aug 12 05:01:51 PM PDT 24
Peak memory 210296 kb
Host smart-3a1981fa-bf16-403e-8ab1-b46c55abfe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522723826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2522723826
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.368890691
Short name T753
Test name
Test status
Simulation time 53133179 ps
CPU time 0.8 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 206352 kb
Host smart-8a5e0644-85b9-419e-aa10-cdc9c5aae4a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368890691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.368890691
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.457864414
Short name T266
Test name
Test status
Simulation time 61541395 ps
CPU time 4.37 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 215108 kb
Host smart-2359e85d-3042-4b63-b9b4-dcde3a7b36e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457864414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.457864414
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1990731315
Short name T35
Test name
Test status
Simulation time 142442438 ps
CPU time 3.3 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 215884 kb
Host smart-03ea9ab3-0bf4-4b14-ba6f-428a3e1bfc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990731315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1990731315
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.215455104
Short name T897
Test name
Test status
Simulation time 35920946 ps
CPU time 1.94 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 209724 kb
Host smart-0977934e-ee76-4712-95bc-95135611395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215455104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.215455104
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3865126929
Short name T339
Test name
Test status
Simulation time 616528473 ps
CPU time 3.7 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 209460 kb
Host smart-5f08e8ad-ca00-4d0c-b60f-e5e36f657897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865126929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3865126929
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3278697149
Short name T352
Test name
Test status
Simulation time 111906530 ps
CPU time 4.03 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 222788 kb
Host smart-f8b79c74-c51b-40ad-bc12-f60064f3bfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278697149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3278697149
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1072800707
Short name T771
Test name
Test status
Simulation time 458987357 ps
CPU time 4.13 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 223040 kb
Host smart-ee38a160-dcb1-4319-94c0-1f0ab4c24979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072800707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1072800707
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1471854304
Short name T323
Test name
Test status
Simulation time 64755823 ps
CPU time 3.98 seconds
Started Aug 12 05:01:53 PM PDT 24
Finished Aug 12 05:01:57 PM PDT 24
Peak memory 210644 kb
Host smart-918afe1b-78cb-4325-8dfb-b70422f89fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471854304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1471854304
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1207385140
Short name T713
Test name
Test status
Simulation time 53469782 ps
CPU time 2.69 seconds
Started Aug 12 05:01:51 PM PDT 24
Finished Aug 12 05:01:54 PM PDT 24
Peak memory 208600 kb
Host smart-c39d5add-c8b9-49cc-a0aa-3bef874293db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207385140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1207385140
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.319522280
Short name T631
Test name
Test status
Simulation time 208654173 ps
CPU time 3.12 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 207332 kb
Host smart-fa884146-c750-4810-97ce-bf93d6189f7e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319522280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.319522280
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.731466539
Short name T324
Test name
Test status
Simulation time 361333961 ps
CPU time 3.57 seconds
Started Aug 12 05:01:52 PM PDT 24
Finished Aug 12 05:01:56 PM PDT 24
Peak memory 209492 kb
Host smart-f898f6fd-62b4-455e-a447-129c8a8b6f5e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731466539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.731466539
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1911369625
Short name T808
Test name
Test status
Simulation time 152846799 ps
CPU time 2.69 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 209208 kb
Host smart-7c86ae50-be0c-4413-9422-638d3194577d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911369625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1911369625
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1929279164
Short name T912
Test name
Test status
Simulation time 18367824 ps
CPU time 1.74 seconds
Started Aug 12 05:01:57 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 207456 kb
Host smart-20ce73aa-e80a-469a-ad3b-c416ef07a10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929279164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1929279164
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2386166095
Short name T434
Test name
Test status
Simulation time 48173368 ps
CPU time 2.51 seconds
Started Aug 12 05:01:47 PM PDT 24
Finished Aug 12 05:01:50 PM PDT 24
Peak memory 208932 kb
Host smart-3ebeb346-5821-41c7-a5b7-0f07f2029602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386166095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2386166095
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2689128628
Short name T702
Test name
Test status
Simulation time 226204303 ps
CPU time 7.8 seconds
Started Aug 12 05:01:57 PM PDT 24
Finished Aug 12 05:02:05 PM PDT 24
Peak memory 223072 kb
Host smart-28840f27-7456-48cc-b84d-22717f41d57c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689128628 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2689128628
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.934957631
Short name T327
Test name
Test status
Simulation time 252107635 ps
CPU time 3.92 seconds
Started Aug 12 05:01:51 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 210476 kb
Host smart-27e9a0cb-22b3-46c1-9232-fc7b7b5282e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934957631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.934957631
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1227181262
Short name T496
Test name
Test status
Simulation time 119513873 ps
CPU time 1.79 seconds
Started Aug 12 05:01:50 PM PDT 24
Finished Aug 12 05:01:52 PM PDT 24
Peak memory 210308 kb
Host smart-7c40d722-535b-42ec-8edc-fe65ec6702e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227181262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1227181262
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1813433905
Short name T630
Test name
Test status
Simulation time 24474656 ps
CPU time 0.78 seconds
Started Aug 12 05:02:07 PM PDT 24
Finished Aug 12 05:02:08 PM PDT 24
Peak memory 206400 kb
Host smart-64b15fb2-c435-453f-bdfe-97566d909cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813433905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1813433905
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3260637832
Short name T411
Test name
Test status
Simulation time 717349051 ps
CPU time 9.69 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:02:05 PM PDT 24
Peak memory 216320 kb
Host smart-1b544f0f-5ce4-4259-a5e3-11291d102e53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260637832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3260637832
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1079775812
Short name T813
Test name
Test status
Simulation time 258784535 ps
CPU time 3.94 seconds
Started Aug 12 05:02:00 PM PDT 24
Finished Aug 12 05:02:04 PM PDT 24
Peak memory 214656 kb
Host smart-1da1543b-30ee-4988-a2f3-79b0ccd55a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079775812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1079775812
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.49027308
Short name T368
Test name
Test status
Simulation time 3540741898 ps
CPU time 19.85 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 209600 kb
Host smart-b619fa86-d68d-45b8-a8f7-69088ee68c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49027308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.49027308
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4245905500
Short name T803
Test name
Test status
Simulation time 332999631 ps
CPU time 8.43 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:02:04 PM PDT 24
Peak memory 214832 kb
Host smart-49a50696-cc44-44a1-973e-37da6daa3149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245905500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4245905500
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1450060159
Short name T280
Test name
Test status
Simulation time 124125672 ps
CPU time 2.97 seconds
Started Aug 12 05:02:09 PM PDT 24
Finished Aug 12 05:02:12 PM PDT 24
Peak memory 214868 kb
Host smart-b3557e0a-4f4c-41a1-b5c4-b01657cccb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450060159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1450060159
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.2999360342
Short name T757
Test name
Test status
Simulation time 164610476 ps
CPU time 3.62 seconds
Started Aug 12 05:01:54 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 207908 kb
Host smart-7491a44e-33e2-4090-b930-c5db85ce7b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999360342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2999360342
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.123382077
Short name T124
Test name
Test status
Simulation time 49288788 ps
CPU time 2.68 seconds
Started Aug 12 05:01:52 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 207368 kb
Host smart-c441ee48-094e-4a0b-9d7e-f47ca262f5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123382077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.123382077
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.4071199468
Short name T604
Test name
Test status
Simulation time 353701898 ps
CPU time 3.53 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:02:00 PM PDT 24
Peak memory 207292 kb
Host smart-83ad4e4d-060f-437c-8603-97ca90286243
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071199468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.4071199468
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3886426887
Short name T647
Test name
Test status
Simulation time 169006448 ps
CPU time 4.94 seconds
Started Aug 12 05:01:59 PM PDT 24
Finished Aug 12 05:02:04 PM PDT 24
Peak memory 208680 kb
Host smart-0cfad388-5a4c-4845-85c5-26676d90ccd3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886426887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3886426887
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2120460448
Short name T607
Test name
Test status
Simulation time 966883313 ps
CPU time 32.12 seconds
Started Aug 12 05:01:58 PM PDT 24
Finished Aug 12 05:02:30 PM PDT 24
Peak memory 208760 kb
Host smart-66c84ae0-b451-4f45-84bd-a0951b3335d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120460448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2120460448
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3712396215
Short name T707
Test name
Test status
Simulation time 227199643 ps
CPU time 2.27 seconds
Started Aug 12 05:02:10 PM PDT 24
Finished Aug 12 05:02:12 PM PDT 24
Peak memory 209624 kb
Host smart-6952c126-c1fe-4061-8ee6-b287ce1a5e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712396215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3712396215
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3510815874
Short name T774
Test name
Test status
Simulation time 31610470 ps
CPU time 2.06 seconds
Started Aug 12 05:02:02 PM PDT 24
Finished Aug 12 05:02:04 PM PDT 24
Peak memory 207608 kb
Host smart-92aaccc4-4642-4b34-87f6-6be4d94eaf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510815874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3510815874
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.674190630
Short name T6
Test name
Test status
Simulation time 4910119324 ps
CPU time 27.74 seconds
Started Aug 12 05:02:08 PM PDT 24
Finished Aug 12 05:02:36 PM PDT 24
Peak memory 222952 kb
Host smart-e13fcb89-c680-4bf1-9297-774a109970de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674190630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.674190630
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1282617080
Short name T578
Test name
Test status
Simulation time 1575435258 ps
CPU time 17.86 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:02:14 PM PDT 24
Peak memory 219888 kb
Host smart-ab5c7284-edd7-4939-be1d-5aeb98e714f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282617080 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1282617080
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3541340519
Short name T756
Test name
Test status
Simulation time 706399645 ps
CPU time 8.1 seconds
Started Aug 12 05:02:09 PM PDT 24
Finished Aug 12 05:02:17 PM PDT 24
Peak memory 220524 kb
Host smart-ed8ee69e-df37-4682-a753-270c8fee8438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541340519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3541340519
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1432504612
Short name T379
Test name
Test status
Simulation time 87390165 ps
CPU time 1.89 seconds
Started Aug 12 05:02:00 PM PDT 24
Finished Aug 12 05:02:02 PM PDT 24
Peak memory 211208 kb
Host smart-9659a40a-eaee-4306-b35f-12902ae66e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432504612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1432504612
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.242847099
Short name T592
Test name
Test status
Simulation time 12976027 ps
CPU time 0.83 seconds
Started Aug 12 05:02:01 PM PDT 24
Finished Aug 12 05:02:02 PM PDT 24
Peak memory 206360 kb
Host smart-aa347533-d1ef-4ef2-8856-a9259b4223dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242847099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.242847099
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.757347243
Short name T36
Test name
Test status
Simulation time 80829581 ps
CPU time 1.84 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 208992 kb
Host smart-f9e6da4f-e58d-4f8f-b9bb-df681749ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757347243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.757347243
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1833097695
Short name T689
Test name
Test status
Simulation time 50926999 ps
CPU time 2.37 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 214748 kb
Host smart-abd9eb73-8d23-4a06-969b-49e00a7259d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833097695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1833097695
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1657574672
Short name T743
Test name
Test status
Simulation time 135414800 ps
CPU time 5.45 seconds
Started Aug 12 05:01:58 PM PDT 24
Finished Aug 12 05:02:03 PM PDT 24
Peak memory 209492 kb
Host smart-8bb106f1-6b22-4d6c-a95d-b32ac698c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657574672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1657574672
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.718133619
Short name T354
Test name
Test status
Simulation time 423913882 ps
CPU time 3.67 seconds
Started Aug 12 05:01:56 PM PDT 24
Finished Aug 12 05:02:00 PM PDT 24
Peak memory 214688 kb
Host smart-d472c0e1-dc1d-46be-aca6-ea4d089e82f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718133619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.718133619
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.356026899
Short name T392
Test name
Test status
Simulation time 179149837 ps
CPU time 4.33 seconds
Started Aug 12 05:01:57 PM PDT 24
Finished Aug 12 05:02:02 PM PDT 24
Peak memory 209264 kb
Host smart-b0ce16a6-10b9-4f8a-b7dd-0ad92baff73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356026899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.356026899
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1765330545
Short name T274
Test name
Test status
Simulation time 367620362 ps
CPU time 7.49 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:20 PM PDT 24
Peak memory 214836 kb
Host smart-95d08ba9-c9a9-42dd-875d-fc6ec0c73851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765330545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1765330545
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3720457356
Short name T886
Test name
Test status
Simulation time 1128704474 ps
CPU time 8.66 seconds
Started Aug 12 05:01:59 PM PDT 24
Finished Aug 12 05:02:08 PM PDT 24
Peak memory 208840 kb
Host smart-49320819-8b5b-43a4-82d0-bdeff49f1b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720457356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3720457356
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.969865845
Short name T487
Test name
Test status
Simulation time 64550684 ps
CPU time 2.56 seconds
Started Aug 12 05:02:00 PM PDT 24
Finished Aug 12 05:02:03 PM PDT 24
Peak memory 209100 kb
Host smart-a8f14f5c-2342-4edb-aa4d-994df31734c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969865845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.969865845
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1957968480
Short name T544
Test name
Test status
Simulation time 128451479 ps
CPU time 4.4 seconds
Started Aug 12 05:02:05 PM PDT 24
Finished Aug 12 05:02:10 PM PDT 24
Peak memory 209360 kb
Host smart-0c4e6fd6-403d-45da-874a-9d1b9f740def
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957968480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1957968480
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.267534371
Short name T246
Test name
Test status
Simulation time 123104702 ps
CPU time 3.55 seconds
Started Aug 12 05:02:11 PM PDT 24
Finished Aug 12 05:02:15 PM PDT 24
Peak memory 207356 kb
Host smart-1808d618-09a1-4490-88d3-531dfbecdbaa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267534371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.267534371
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2899955461
Short name T873
Test name
Test status
Simulation time 183398747 ps
CPU time 2.23 seconds
Started Aug 12 05:02:19 PM PDT 24
Finished Aug 12 05:02:22 PM PDT 24
Peak memory 218976 kb
Host smart-9daf4fb0-3be8-4243-9213-420137626706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899955461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2899955461
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.217699610
Short name T563
Test name
Test status
Simulation time 1305752333 ps
CPU time 3.99 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 208644 kb
Host smart-ba7563a3-4060-49c9-ad05-4e348902a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217699610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.217699610
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1585749545
Short name T542
Test name
Test status
Simulation time 952298415 ps
CPU time 19.23 seconds
Started Aug 12 05:02:10 PM PDT 24
Finished Aug 12 05:02:30 PM PDT 24
Peak memory 209188 kb
Host smart-4d2b8a22-6a49-4143-9af0-c54c113a21a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585749545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1585749545
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1883141147
Short name T545
Test name
Test status
Simulation time 464123239 ps
CPU time 2.13 seconds
Started Aug 12 05:01:57 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 210320 kb
Host smart-d0d0aa5d-f2ba-4a41-b58a-4d5ddbf53eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883141147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1883141147
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2220725260
Short name T520
Test name
Test status
Simulation time 16584602 ps
CPU time 0.71 seconds
Started Aug 12 05:01:58 PM PDT 24
Finished Aug 12 05:01:59 PM PDT 24
Peak memory 206332 kb
Host smart-67c4f73c-0736-434e-b171-aa1848dc4294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220725260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2220725260
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1318037194
Short name T252
Test name
Test status
Simulation time 125079585 ps
CPU time 2.14 seconds
Started Aug 12 05:02:02 PM PDT 24
Finished Aug 12 05:02:04 PM PDT 24
Peak memory 209912 kb
Host smart-c078ea58-f236-4862-87bb-bd0651030988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318037194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1318037194
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3448749132
Short name T92
Test name
Test status
Simulation time 640863430 ps
CPU time 5.26 seconds
Started Aug 12 05:02:10 PM PDT 24
Finished Aug 12 05:02:15 PM PDT 24
Peak memory 209584 kb
Host smart-629c4960-ecf5-4841-89c2-09dbecb9a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448749132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3448749132
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3383227533
Short name T255
Test name
Test status
Simulation time 119224380 ps
CPU time 3.74 seconds
Started Aug 12 05:01:55 PM PDT 24
Finished Aug 12 05:01:58 PM PDT 24
Peak memory 222876 kb
Host smart-8c69d74f-da78-4cb7-bdb3-1fb8b33c953e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383227533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3383227533
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2935654760
Short name T12
Test name
Test status
Simulation time 123292253 ps
CPU time 2.67 seconds
Started Aug 12 05:01:59 PM PDT 24
Finished Aug 12 05:02:02 PM PDT 24
Peak memory 216540 kb
Host smart-54cc45fd-4d91-445e-a0ea-33643da20582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935654760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2935654760
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3216148316
Short name T398
Test name
Test status
Simulation time 4358642475 ps
CPU time 51.2 seconds
Started Aug 12 05:01:59 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 210044 kb
Host smart-f2356d70-73ea-4d59-a725-327b3bfb3ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216148316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3216148316
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1730664024
Short name T574
Test name
Test status
Simulation time 70583194 ps
CPU time 3.21 seconds
Started Aug 12 05:02:03 PM PDT 24
Finished Aug 12 05:02:06 PM PDT 24
Peak memory 209108 kb
Host smart-40c78247-ea9c-42f0-9fc6-123f3b771b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730664024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1730664024
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2516726965
Short name T885
Test name
Test status
Simulation time 48626569 ps
CPU time 2.81 seconds
Started Aug 12 05:02:06 PM PDT 24
Finished Aug 12 05:02:09 PM PDT 24
Peak memory 209052 kb
Host smart-f6361ccd-33cf-4137-a889-78f5475a704d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516726965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2516726965
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4168360873
Short name T394
Test name
Test status
Simulation time 581128844 ps
CPU time 4.35 seconds
Started Aug 12 05:02:02 PM PDT 24
Finished Aug 12 05:02:06 PM PDT 24
Peak memory 207448 kb
Host smart-fe0e4e17-856d-4857-bbb1-98e79ebdaba7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168360873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4168360873
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2274606592
Short name T611
Test name
Test status
Simulation time 323514094 ps
CPU time 2.2 seconds
Started Aug 12 05:02:15 PM PDT 24
Finished Aug 12 05:02:17 PM PDT 24
Peak memory 209268 kb
Host smart-abe1230f-8375-4fcd-a074-9227c0ffe042
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274606592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2274606592
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3545901303
Short name T807
Test name
Test status
Simulation time 33861360 ps
CPU time 1.54 seconds
Started Aug 12 05:02:01 PM PDT 24
Finished Aug 12 05:02:02 PM PDT 24
Peak memory 208104 kb
Host smart-c98c552d-7835-4aff-9961-49008ed796f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545901303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3545901303
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3531186967
Short name T561
Test name
Test status
Simulation time 693276939 ps
CPU time 6.06 seconds
Started Aug 12 05:02:09 PM PDT 24
Finished Aug 12 05:02:15 PM PDT 24
Peak memory 207356 kb
Host smart-106e0493-84ac-457b-a4d5-0ada14a80ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531186967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3531186967
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1600876768
Short name T306
Test name
Test status
Simulation time 431060130 ps
CPU time 8.93 seconds
Started Aug 12 05:02:00 PM PDT 24
Finished Aug 12 05:02:09 PM PDT 24
Peak memory 214864 kb
Host smart-1bbdf629-286d-4c6c-ba0b-afa66ce5849e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600876768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1600876768
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2786897087
Short name T823
Test name
Test status
Simulation time 1047225071 ps
CPU time 18.09 seconds
Started Aug 12 05:02:02 PM PDT 24
Finished Aug 12 05:02:21 PM PDT 24
Peak memory 222952 kb
Host smart-339f61ac-4330-43e7-8a65-142a5dc2ff02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786897087 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2786897087
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1900093467
Short name T287
Test name
Test status
Simulation time 171622365 ps
CPU time 2.96 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 210548 kb
Host smart-f2cd51b0-431c-40b5-8eee-c9788246af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900093467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1900093467
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3880635829
Short name T566
Test name
Test status
Simulation time 249553525 ps
CPU time 4.93 seconds
Started Aug 12 05:02:08 PM PDT 24
Finished Aug 12 05:02:13 PM PDT 24
Peak memory 211592 kb
Host smart-16868768-c495-4a33-b4b4-8025d5a34cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880635829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3880635829
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2380481403
Short name T595
Test name
Test status
Simulation time 8885026 ps
CPU time 0.83 seconds
Started Aug 12 05:02:18 PM PDT 24
Finished Aug 12 05:02:19 PM PDT 24
Peak memory 206316 kb
Host smart-01932e4a-8604-4665-a7c2-e31b87fbcda0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380481403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2380481403
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1090545886
Short name T401
Test name
Test status
Simulation time 2162960370 ps
CPU time 101.62 seconds
Started Aug 12 05:02:11 PM PDT 24
Finished Aug 12 05:03:53 PM PDT 24
Peak memory 214944 kb
Host smart-9e7b738b-eb67-4c89-869f-688b15082605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090545886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1090545886
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.736443054
Short name T848
Test name
Test status
Simulation time 60617728 ps
CPU time 2.36 seconds
Started Aug 12 05:02:03 PM PDT 24
Finished Aug 12 05:02:05 PM PDT 24
Peak memory 210244 kb
Host smart-00e3bd44-0d59-4f6a-93de-e23019fe69a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736443054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.736443054
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.965539380
Short name T74
Test name
Test status
Simulation time 112747624 ps
CPU time 2.67 seconds
Started Aug 12 05:02:12 PM PDT 24
Finished Aug 12 05:02:15 PM PDT 24
Peak memory 209324 kb
Host smart-b69cf1e1-959b-4676-8667-61dbea1014fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965539380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.965539380
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3769384432
Short name T839
Test name
Test status
Simulation time 80563927 ps
CPU time 2.61 seconds
Started Aug 12 05:02:10 PM PDT 24
Finished Aug 12 05:02:13 PM PDT 24
Peak memory 215000 kb
Host smart-fa452b45-d8da-4306-bb9e-c4eecfeb750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769384432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3769384432
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2070871977
Short name T726
Test name
Test status
Simulation time 536784925 ps
CPU time 3.1 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 213588 kb
Host smart-eb82d29a-8ec6-4d68-80fe-b537a9fe8c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070871977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2070871977
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2472888910
Short name T772
Test name
Test status
Simulation time 115180590 ps
CPU time 2.92 seconds
Started Aug 12 05:02:09 PM PDT 24
Finished Aug 12 05:02:12 PM PDT 24
Peak memory 222912 kb
Host smart-ca807f92-cbc6-4ffc-b3af-fb77a401cb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472888910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2472888910
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1211288936
Short name T315
Test name
Test status
Simulation time 265084731 ps
CPU time 6.79 seconds
Started Aug 12 05:02:12 PM PDT 24
Finished Aug 12 05:02:19 PM PDT 24
Peak memory 209500 kb
Host smart-d50cec61-d9a7-4183-a96a-c4ca156a55f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211288936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1211288936
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3527529454
Short name T656
Test name
Test status
Simulation time 112788916 ps
CPU time 2.71 seconds
Started Aug 12 05:02:08 PM PDT 24
Finished Aug 12 05:02:10 PM PDT 24
Peak memory 207480 kb
Host smart-89306efc-f290-4d26-ae28-b5fbba712b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527529454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3527529454
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2456111104
Short name T296
Test name
Test status
Simulation time 38320738 ps
CPU time 2.74 seconds
Started Aug 12 05:02:08 PM PDT 24
Finished Aug 12 05:02:11 PM PDT 24
Peak memory 209040 kb
Host smart-6a929ee1-b6c1-4121-a32a-7f527572913d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456111104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2456111104
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.163123829
Short name T876
Test name
Test status
Simulation time 144650304 ps
CPU time 2.5 seconds
Started Aug 12 05:02:00 PM PDT 24
Finished Aug 12 05:02:03 PM PDT 24
Peak memory 207488 kb
Host smart-642d0e7a-897e-4b85-802d-9d175155ef0c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163123829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.163123829
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.192226027
Short name T834
Test name
Test status
Simulation time 134009613 ps
CPU time 3.49 seconds
Started Aug 12 05:02:15 PM PDT 24
Finished Aug 12 05:02:18 PM PDT 24
Peak memory 209344 kb
Host smart-fe3ebfdd-9bc8-4029-bad0-e8c23f138e80
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192226027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.192226027
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2352099894
Short name T657
Test name
Test status
Simulation time 706101033 ps
CPU time 5 seconds
Started Aug 12 05:02:06 PM PDT 24
Finished Aug 12 05:02:11 PM PDT 24
Peak memory 219012 kb
Host smart-6628a848-58dd-47a8-bc4f-fcc2d84bc2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352099894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2352099894
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.124031610
Short name T608
Test name
Test status
Simulation time 2182024306 ps
CPU time 4.72 seconds
Started Aug 12 05:02:04 PM PDT 24
Finished Aug 12 05:02:08 PM PDT 24
Peak memory 207452 kb
Host smart-9e760d2f-df78-4884-9bbb-c4ba9d26839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124031610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.124031610
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2527538849
Short name T684
Test name
Test status
Simulation time 1087541970 ps
CPU time 11.89 seconds
Started Aug 12 05:02:17 PM PDT 24
Finished Aug 12 05:02:29 PM PDT 24
Peak memory 208004 kb
Host smart-f74c00d4-97ad-4c97-b521-c93159cccbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527538849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2527538849
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2200870004
Short name T45
Test name
Test status
Simulation time 100761680 ps
CPU time 3.39 seconds
Started Aug 12 05:02:19 PM PDT 24
Finished Aug 12 05:02:23 PM PDT 24
Peak memory 210680 kb
Host smart-22d734f5-d2dd-4b77-afe9-8c5d81ae3313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200870004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2200870004
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3575625084
Short name T491
Test name
Test status
Simulation time 29295045 ps
CPU time 0.71 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:00:57 PM PDT 24
Peak memory 206400 kb
Host smart-e47a5e27-fd58-43a3-b974-935ed82a09c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575625084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3575625084
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2926315002
Short name T385
Test name
Test status
Simulation time 99623024 ps
CPU time 2.74 seconds
Started Aug 12 05:00:55 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 214720 kb
Host smart-b91f646b-fc87-463c-b4b9-fad9faf13447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926315002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2926315002
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3180533608
Short name T695
Test name
Test status
Simulation time 88407589 ps
CPU time 1.86 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:00:55 PM PDT 24
Peak memory 217596 kb
Host smart-d5a2bd98-bd26-4d8f-90ac-7f2e316cdec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180533608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3180533608
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1061011391
Short name T348
Test name
Test status
Simulation time 128552012 ps
CPU time 2.05 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:54 PM PDT 24
Peak memory 208132 kb
Host smart-485d6d88-dd9e-47ef-9d61-c16a9ed66f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061011391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1061011391
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2614199102
Short name T285
Test name
Test status
Simulation time 61102722 ps
CPU time 2.53 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 214960 kb
Host smart-d6c264fd-a67c-4493-a614-d4778a7d8857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614199102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2614199102
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_random.3678172946
Short name T791
Test name
Test status
Simulation time 1010793910 ps
CPU time 5.5 seconds
Started Aug 12 05:01:01 PM PDT 24
Finished Aug 12 05:01:07 PM PDT 24
Peak memory 207956 kb
Host smart-689c58c8-fb6d-4c7c-8857-1346a55db0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678172946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3678172946
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.813648190
Short name T11
Test name
Test status
Simulation time 840527944 ps
CPU time 17.69 seconds
Started Aug 12 05:01:01 PM PDT 24
Finished Aug 12 05:01:18 PM PDT 24
Peak memory 239876 kb
Host smart-3c806998-bd67-4d00-b5ed-b52d27a6f3ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813648190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.813648190
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3517393587
Short name T775
Test name
Test status
Simulation time 127308437 ps
CPU time 2.36 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:00:59 PM PDT 24
Peak memory 207580 kb
Host smart-cb398ecb-5756-44ab-bbc0-67f1937d9009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517393587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3517393587
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.295617708
Short name T329
Test name
Test status
Simulation time 6800464000 ps
CPU time 42.37 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:01:39 PM PDT 24
Peak memory 208976 kb
Host smart-92eaad68-fa7c-45cd-b57b-38bdfa2ea4e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295617708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.295617708
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1294094204
Short name T887
Test name
Test status
Simulation time 39284402 ps
CPU time 2.37 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 207380 kb
Host smart-99a3e4de-5d7a-42be-8240-ca2c0b44140e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294094204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1294094204
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2478418220
Short name T853
Test name
Test status
Simulation time 87239750 ps
CPU time 4.13 seconds
Started Aug 12 05:00:55 PM PDT 24
Finished Aug 12 05:00:59 PM PDT 24
Peak memory 209372 kb
Host smart-52191788-b9d6-43f8-a434-ab28f7688ea8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478418220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2478418220
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2165300067
Short name T896
Test name
Test status
Simulation time 39668601 ps
CPU time 2.72 seconds
Started Aug 12 05:00:55 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 210444 kb
Host smart-8d3e54bc-c960-417d-8279-89951b2f90d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165300067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2165300067
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1213024958
Short name T782
Test name
Test status
Simulation time 47186477 ps
CPU time 2.2 seconds
Started Aug 12 05:00:54 PM PDT 24
Finished Aug 12 05:00:56 PM PDT 24
Peak memory 208612 kb
Host smart-ac0a2cea-c5fd-4ba0-99f7-ef0213ecb885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213024958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1213024958
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2301056977
Short name T806
Test name
Test status
Simulation time 214279181 ps
CPU time 9.36 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:13 PM PDT 24
Peak memory 220336 kb
Host smart-1b93178e-f8e8-4285-9a14-d15a2f2e11a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301056977 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2301056977
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1958711945
Short name T199
Test name
Test status
Simulation time 924840873 ps
CPU time 7.08 seconds
Started Aug 12 05:00:54 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 210428 kb
Host smart-c4871b1c-7d95-4ec6-bfce-e7e28fd55857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958711945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1958711945
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1834471660
Short name T160
Test name
Test status
Simulation time 49221132 ps
CPU time 2.54 seconds
Started Aug 12 05:00:55 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 214768 kb
Host smart-951e754b-8547-4dcd-a8b0-ef9db1032e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834471660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1834471660
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1751283294
Short name T15
Test name
Test status
Simulation time 37997815 ps
CPU time 0.8 seconds
Started Aug 12 05:02:15 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 205248 kb
Host smart-b3620d13-fbb2-417c-8eab-0f67eba1b1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751283294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1751283294
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1763623923
Short name T490
Test name
Test status
Simulation time 144422309 ps
CPU time 3.42 seconds
Started Aug 12 05:02:15 PM PDT 24
Finished Aug 12 05:02:19 PM PDT 24
Peak memory 209312 kb
Host smart-a34a14d7-6916-45c9-8efb-1afd8adede89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763623923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1763623923
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1669446668
Short name T872
Test name
Test status
Simulation time 25097488 ps
CPU time 1.71 seconds
Started Aug 12 05:02:12 PM PDT 24
Finished Aug 12 05:02:14 PM PDT 24
Peak memory 214708 kb
Host smart-095bde64-74df-4271-9f8d-79a119f894d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669446668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1669446668
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3802720069
Short name T589
Test name
Test status
Simulation time 211672299 ps
CPU time 2 seconds
Started Aug 12 05:02:12 PM PDT 24
Finished Aug 12 05:02:14 PM PDT 24
Peak memory 209296 kb
Host smart-d1671735-eb4d-4eff-bdc8-8f48b322d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802720069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3802720069
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.388889139
Short name T227
Test name
Test status
Simulation time 46210111 ps
CPU time 3.18 seconds
Started Aug 12 05:02:19 PM PDT 24
Finished Aug 12 05:02:23 PM PDT 24
Peak memory 210132 kb
Host smart-a3a2415d-3636-47ac-806b-c0f6a666502a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388889139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.388889139
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2098759463
Short name T626
Test name
Test status
Simulation time 341012355 ps
CPU time 4.42 seconds
Started Aug 12 05:02:04 PM PDT 24
Finished Aug 12 05:02:09 PM PDT 24
Peak memory 208532 kb
Host smart-63224fa3-fa58-4aa9-b016-cdd4299c2939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098759463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2098759463
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.953325124
Short name T328
Test name
Test status
Simulation time 147211222 ps
CPU time 5.49 seconds
Started Aug 12 05:02:04 PM PDT 24
Finished Aug 12 05:02:10 PM PDT 24
Peak memory 209176 kb
Host smart-88d18576-c17b-4340-9792-dcabc4068ebd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953325124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.953325124
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1275913816
Short name T661
Test name
Test status
Simulation time 97739606 ps
CPU time 2.88 seconds
Started Aug 12 05:02:17 PM PDT 24
Finished Aug 12 05:02:20 PM PDT 24
Peak memory 209180 kb
Host smart-aed3d8ed-50b6-42d8-a27a-dbdec3675dd7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275913816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1275913816
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.76810459
Short name T860
Test name
Test status
Simulation time 81653852 ps
CPU time 1.8 seconds
Started Aug 12 05:02:04 PM PDT 24
Finished Aug 12 05:02:06 PM PDT 24
Peak memory 207364 kb
Host smart-75bcc98d-b8f4-4199-bf28-4a61888820d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76810459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.76810459
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2738564645
Short name T645
Test name
Test status
Simulation time 86635255 ps
CPU time 3.81 seconds
Started Aug 12 05:02:12 PM PDT 24
Finished Aug 12 05:02:21 PM PDT 24
Peak memory 209708 kb
Host smart-131cec45-54f7-4377-b9d5-51cd3e216ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738564645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2738564645
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3942237884
Short name T660
Test name
Test status
Simulation time 396493665 ps
CPU time 7.59 seconds
Started Aug 12 05:02:06 PM PDT 24
Finished Aug 12 05:02:14 PM PDT 24
Peak memory 208388 kb
Host smart-0078f5f8-4433-4a23-8762-34bda9286787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942237884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3942237884
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3359762068
Short name T612
Test name
Test status
Simulation time 1205288530 ps
CPU time 10.83 seconds
Started Aug 12 05:02:05 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 207252 kb
Host smart-687c6c63-ab9f-4e6f-ac02-05479bcb9b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359762068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3359762068
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1516412707
Short name T241
Test name
Test status
Simulation time 429585234 ps
CPU time 6.38 seconds
Started Aug 12 05:02:06 PM PDT 24
Finished Aug 12 05:02:13 PM PDT 24
Peak memory 209432 kb
Host smart-2c7cf8c6-4759-47b0-8faf-1788b3ecaff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516412707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1516412707
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.4087444418
Short name T154
Test name
Test status
Simulation time 42034273 ps
CPU time 1.64 seconds
Started Aug 12 05:02:03 PM PDT 24
Finished Aug 12 05:02:05 PM PDT 24
Peak memory 210464 kb
Host smart-fb12acd8-3215-429d-b03a-4ba458672bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087444418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.4087444418
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1781416172
Short name T879
Test name
Test status
Simulation time 13596227 ps
CPU time 0.83 seconds
Started Aug 12 05:02:15 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 206344 kb
Host smart-160a4cb6-29b9-431e-9c9c-ba1eacaae681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781416172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1781416172
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4048663551
Short name T178
Test name
Test status
Simulation time 58186535 ps
CPU time 2.19 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:15 PM PDT 24
Peak memory 215740 kb
Host smart-d52f1fef-8b77-477c-9249-d639dad60bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048663551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4048663551
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.826353109
Short name T552
Test name
Test status
Simulation time 266124239 ps
CPU time 5.83 seconds
Started Aug 12 05:02:04 PM PDT 24
Finished Aug 12 05:02:10 PM PDT 24
Peak memory 209520 kb
Host smart-4a91fbe2-efed-4a89-a117-48e71dfd493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826353109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.826353109
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1154713969
Short name T640
Test name
Test status
Simulation time 109576018 ps
CPU time 2.94 seconds
Started Aug 12 05:02:18 PM PDT 24
Finished Aug 12 05:02:21 PM PDT 24
Peak memory 222884 kb
Host smart-28eae333-2f61-4b45-b22a-d53308d094a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154713969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1154713969
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2709878680
Short name T624
Test name
Test status
Simulation time 91872669 ps
CPU time 3 seconds
Started Aug 12 05:02:16 PM PDT 24
Finished Aug 12 05:02:19 PM PDT 24
Peak memory 209116 kb
Host smart-42415df0-056d-4b25-baac-401c3f1e55df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709878680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2709878680
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2790180256
Short name T531
Test name
Test status
Simulation time 120505599 ps
CPU time 5.18 seconds
Started Aug 12 05:02:03 PM PDT 24
Finished Aug 12 05:02:08 PM PDT 24
Peak memory 209632 kb
Host smart-c3ebbdeb-5a72-4a27-b85b-04af022e1f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790180256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2790180256
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4144393884
Short name T829
Test name
Test status
Simulation time 420338390 ps
CPU time 5.14 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:18 PM PDT 24
Peak memory 208924 kb
Host smart-97907be2-31b9-4f75-bfb9-cb6e549b8d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144393884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4144393884
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3459581562
Short name T865
Test name
Test status
Simulation time 181120540 ps
CPU time 5.08 seconds
Started Aug 12 05:02:14 PM PDT 24
Finished Aug 12 05:02:19 PM PDT 24
Peak memory 208388 kb
Host smart-81274db7-da3c-4fd0-b7a6-4a83a85eef54
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459581562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3459581562
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1130785793
Short name T480
Test name
Test status
Simulation time 61155150 ps
CPU time 3.2 seconds
Started Aug 12 05:02:15 PM PDT 24
Finished Aug 12 05:02:18 PM PDT 24
Peak memory 208532 kb
Host smart-d7adaeb1-6f93-4abe-ac3c-01843abdd017
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130785793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1130785793
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.695384369
Short name T14
Test name
Test status
Simulation time 88921683 ps
CPU time 3.34 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 207404 kb
Host smart-2ee6aef6-3af4-4406-ad9a-37918cbe3a08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695384369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.695384369
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3610347496
Short name T708
Test name
Test status
Simulation time 142249369 ps
CPU time 3.78 seconds
Started Aug 12 05:02:16 PM PDT 24
Finished Aug 12 05:02:20 PM PDT 24
Peak memory 210472 kb
Host smart-2d68c2d8-d645-4b66-8345-82e3d82e1258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610347496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3610347496
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3110920174
Short name T718
Test name
Test status
Simulation time 115593890 ps
CPU time 2.64 seconds
Started Aug 12 05:02:05 PM PDT 24
Finished Aug 12 05:02:08 PM PDT 24
Peak memory 206164 kb
Host smart-71fd6802-8ad5-4031-b189-46b6bc06672b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110920174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3110920174
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.4155767335
Short name T187
Test name
Test status
Simulation time 706675269 ps
CPU time 26.51 seconds
Started Aug 12 05:02:25 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 220972 kb
Host smart-c8ea320b-8102-4097-b96a-d1bff9449c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155767335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.4155767335
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2005860168
Short name T202
Test name
Test status
Simulation time 1532579090 ps
CPU time 4.78 seconds
Started Aug 12 05:02:14 PM PDT 24
Finished Aug 12 05:02:19 PM PDT 24
Peak memory 214844 kb
Host smart-176cb32e-2289-4131-8388-68d99ce6e7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005860168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2005860168
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.985739960
Short name T164
Test name
Test status
Simulation time 51262718 ps
CPU time 1.71 seconds
Started Aug 12 05:02:22 PM PDT 24
Finished Aug 12 05:02:24 PM PDT 24
Peak memory 210556 kb
Host smart-f254d8b4-b680-46fd-8628-88f73001787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985739960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.985739960
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.536946336
Short name T649
Test name
Test status
Simulation time 14835915 ps
CPU time 0.94 seconds
Started Aug 12 05:02:17 PM PDT 24
Finished Aug 12 05:02:18 PM PDT 24
Peak memory 206532 kb
Host smart-620dbb6f-4147-48bc-a378-244b29012165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536946336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.536946336
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1328457868
Short name T128
Test name
Test status
Simulation time 45091713 ps
CPU time 3.42 seconds
Started Aug 12 05:02:29 PM PDT 24
Finished Aug 12 05:02:33 PM PDT 24
Peak memory 214868 kb
Host smart-890ae278-11a0-4f46-a9d1-d28f543bc219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328457868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1328457868
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3244393560
Short name T31
Test name
Test status
Simulation time 1188793251 ps
CPU time 10.12 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:23 PM PDT 24
Peak memory 215068 kb
Host smart-7fac955d-313f-47d2-ad57-791470773a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244393560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3244393560
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3404607564
Short name T450
Test name
Test status
Simulation time 73352826 ps
CPU time 2.49 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:15 PM PDT 24
Peak memory 209796 kb
Host smart-43cb2c85-5412-4db3-b960-7d92c17036d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404607564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3404607564
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.334479911
Short name T601
Test name
Test status
Simulation time 325800953 ps
CPU time 3.55 seconds
Started Aug 12 05:02:17 PM PDT 24
Finished Aug 12 05:02:21 PM PDT 24
Peak memory 214744 kb
Host smart-6df8d4e8-eba6-476c-906b-b2ae26c3734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334479911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.334479911
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1693792095
Short name T373
Test name
Test status
Simulation time 49454901 ps
CPU time 3.23 seconds
Started Aug 12 05:02:10 PM PDT 24
Finished Aug 12 05:02:14 PM PDT 24
Peak memory 222816 kb
Host smart-c763525d-8aca-4da6-b38f-ffa9bcf73048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693792095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1693792095
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.190742995
Short name T54
Test name
Test status
Simulation time 156145726 ps
CPU time 3.59 seconds
Started Aug 12 05:02:14 PM PDT 24
Finished Aug 12 05:02:17 PM PDT 24
Peak memory 207684 kb
Host smart-5cdbcc0f-460e-40d4-8b72-a87908bdc079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190742995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.190742995
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2354840463
Short name T616
Test name
Test status
Simulation time 121262737 ps
CPU time 4.51 seconds
Started Aug 12 05:02:23 PM PDT 24
Finished Aug 12 05:02:27 PM PDT 24
Peak memory 214916 kb
Host smart-215a919f-98f8-4278-ae49-80e3b9db8450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354840463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2354840463
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4122227952
Short name T272
Test name
Test status
Simulation time 3254115937 ps
CPU time 32.94 seconds
Started Aug 12 05:02:16 PM PDT 24
Finished Aug 12 05:02:49 PM PDT 24
Peak memory 209012 kb
Host smart-87587e69-7586-43a7-8f54-31f50e61be49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122227952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4122227952
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.481696333
Short name T776
Test name
Test status
Simulation time 217529189 ps
CPU time 4 seconds
Started Aug 12 05:02:14 PM PDT 24
Finished Aug 12 05:02:18 PM PDT 24
Peak memory 209496 kb
Host smart-2b3a3aea-e2dc-4b3e-adb0-4e9cf1301ef1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481696333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.481696333
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2141956777
Short name T500
Test name
Test status
Simulation time 233469761 ps
CPU time 3.09 seconds
Started Aug 12 05:02:15 PM PDT 24
Finished Aug 12 05:02:19 PM PDT 24
Peak memory 207308 kb
Host smart-4499006e-0203-47ab-aede-db1898fb4d87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141956777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2141956777
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2581572871
Short name T910
Test name
Test status
Simulation time 125634984 ps
CPU time 2.44 seconds
Started Aug 12 05:02:12 PM PDT 24
Finished Aug 12 05:02:15 PM PDT 24
Peak memory 207496 kb
Host smart-4e28861f-d93d-45a4-aa8d-7d6248e7a620
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581572871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2581572871
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2235146692
Short name T2
Test name
Test status
Simulation time 57211628 ps
CPU time 2.64 seconds
Started Aug 12 05:02:17 PM PDT 24
Finished Aug 12 05:02:19 PM PDT 24
Peak memory 210008 kb
Host smart-b6d18ac9-9025-45a4-8aad-4ccaff1338ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235146692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2235146692
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4111655536
Short name T602
Test name
Test status
Simulation time 654430536 ps
CPU time 4.36 seconds
Started Aug 12 05:02:14 PM PDT 24
Finished Aug 12 05:02:18 PM PDT 24
Peak memory 207156 kb
Host smart-528c03f8-ba94-4379-b8f1-40e431d1e85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111655536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4111655536
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1713033077
Short name T728
Test name
Test status
Simulation time 489588630 ps
CPU time 8.35 seconds
Started Aug 12 05:02:13 PM PDT 24
Finished Aug 12 05:02:22 PM PDT 24
Peak memory 222992 kb
Host smart-48d616cf-7308-4f74-bd25-246ac9070954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713033077 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1713033077
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1237204702
Short name T889
Test name
Test status
Simulation time 355047251 ps
CPU time 4.06 seconds
Started Aug 12 05:02:17 PM PDT 24
Finished Aug 12 05:02:22 PM PDT 24
Peak memory 218612 kb
Host smart-560c7087-c9b1-4f59-9110-30f5dcd6b86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237204702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1237204702
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1039567671
Short name T653
Test name
Test status
Simulation time 190080289 ps
CPU time 2.48 seconds
Started Aug 12 05:02:17 PM PDT 24
Finished Aug 12 05:02:19 PM PDT 24
Peak memory 210536 kb
Host smart-b4ebea2c-c804-4409-8639-d84ba7dbf742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039567671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1039567671
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3931822339
Short name T906
Test name
Test status
Simulation time 21998006 ps
CPU time 0.76 seconds
Started Aug 12 05:02:23 PM PDT 24
Finished Aug 12 05:02:24 PM PDT 24
Peak memory 206404 kb
Host smart-d5eab8c1-5da6-4636-a041-edb8d49ca695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931822339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3931822339
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.565615190
Short name T221
Test name
Test status
Simulation time 333822216 ps
CPU time 14 seconds
Started Aug 12 05:02:23 PM PDT 24
Finished Aug 12 05:02:37 PM PDT 24
Peak memory 216292 kb
Host smart-6efea9c6-e555-4158-95a4-de28c9a75cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565615190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.565615190
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2845093288
Short name T71
Test name
Test status
Simulation time 124353453 ps
CPU time 3.75 seconds
Started Aug 12 05:02:26 PM PDT 24
Finished Aug 12 05:02:30 PM PDT 24
Peak memory 210536 kb
Host smart-cb25ccfc-35f5-48a6-906d-d3504210017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845093288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2845093288
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.331809309
Short name T694
Test name
Test status
Simulation time 139013869 ps
CPU time 4.07 seconds
Started Aug 12 05:02:24 PM PDT 24
Finished Aug 12 05:02:28 PM PDT 24
Peak memory 214684 kb
Host smart-8a49f2eb-3fa3-473d-8fd7-d34ef10c015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331809309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.331809309
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1440291805
Short name T610
Test name
Test status
Simulation time 130959697 ps
CPU time 6.1 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:42 PM PDT 24
Peak memory 222836 kb
Host smart-04fbb8f0-47d4-4b46-bcc9-72b47b2ae708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440291805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1440291805
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1718393934
Short name T582
Test name
Test status
Simulation time 1012604493 ps
CPU time 5.95 seconds
Started Aug 12 05:02:23 PM PDT 24
Finished Aug 12 05:02:29 PM PDT 24
Peak memory 208516 kb
Host smart-0fd12b47-7ee5-4365-8023-944230fda406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718393934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1718393934
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.720850024
Short name T264
Test name
Test status
Simulation time 1174063953 ps
CPU time 3.45 seconds
Started Aug 12 05:02:17 PM PDT 24
Finished Aug 12 05:02:21 PM PDT 24
Peak memory 209088 kb
Host smart-eb03d513-e86a-48c4-b6f6-1f6e69f536ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720850024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.720850024
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4041254876
Short name T736
Test name
Test status
Simulation time 426513853 ps
CPU time 3.72 seconds
Started Aug 12 05:02:28 PM PDT 24
Finished Aug 12 05:02:32 PM PDT 24
Peak memory 209344 kb
Host smart-9499180b-cae4-4f87-bde9-5afb464b667f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041254876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4041254876
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3129281042
Short name T759
Test name
Test status
Simulation time 205266572 ps
CPU time 4.93 seconds
Started Aug 12 05:02:31 PM PDT 24
Finished Aug 12 05:02:41 PM PDT 24
Peak memory 207500 kb
Host smart-7983355e-1ae5-4174-b6d3-c7a016cfbe20
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129281042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3129281042
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2028618523
Short name T716
Test name
Test status
Simulation time 1603512101 ps
CPU time 47.1 seconds
Started Aug 12 05:02:14 PM PDT 24
Finished Aug 12 05:03:01 PM PDT 24
Peak memory 209476 kb
Host smart-3aa13fec-1702-4063-8fcf-2da13af49516
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028618523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2028618523
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3347192479
Short name T618
Test name
Test status
Simulation time 23542287 ps
CPU time 1.66 seconds
Started Aug 12 05:02:30 PM PDT 24
Finished Aug 12 05:02:32 PM PDT 24
Peak memory 214828 kb
Host smart-ee0aa064-87ca-4921-ad07-3fe203b664d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347192479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3347192479
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2690063528
Short name T466
Test name
Test status
Simulation time 121581568 ps
CPU time 2.96 seconds
Started Aug 12 05:02:17 PM PDT 24
Finished Aug 12 05:02:20 PM PDT 24
Peak memory 207472 kb
Host smart-fb1b9bb3-5485-4962-9828-ce763cc600d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690063528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2690063528
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2082853642
Short name T343
Test name
Test status
Simulation time 65349959 ps
CPU time 2.6 seconds
Started Aug 12 05:02:23 PM PDT 24
Finished Aug 12 05:02:26 PM PDT 24
Peak memory 209808 kb
Host smart-a448e1cc-e661-4d1e-a9e6-23eb6e941982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082853642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2082853642
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2054842389
Short name T168
Test name
Test status
Simulation time 289280779 ps
CPU time 2.52 seconds
Started Aug 12 05:02:29 PM PDT 24
Finished Aug 12 05:02:32 PM PDT 24
Peak memory 210812 kb
Host smart-709ec1f6-80a5-41f7-91c2-57e483641371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054842389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2054842389
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2420401438
Short name T751
Test name
Test status
Simulation time 50615831 ps
CPU time 0.75 seconds
Started Aug 12 05:02:24 PM PDT 24
Finished Aug 12 05:02:25 PM PDT 24
Peak memory 206384 kb
Host smart-add2202d-8d54-4b1c-8048-6e660925ec7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420401438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2420401438
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4215002799
Short name T915
Test name
Test status
Simulation time 454342630 ps
CPU time 3.55 seconds
Started Aug 12 05:02:33 PM PDT 24
Finished Aug 12 05:02:37 PM PDT 24
Peak memory 215072 kb
Host smart-d4e25104-bcef-41c2-a24b-5ac2e5313571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215002799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4215002799
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3730720546
Short name T56
Test name
Test status
Simulation time 77978568 ps
CPU time 2.1 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:02:39 PM PDT 24
Peak memory 208932 kb
Host smart-55a5575f-e2e7-48d5-9e4e-a364bf22accd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730720546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3730720546
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3534565977
Short name T593
Test name
Test status
Simulation time 695992371 ps
CPU time 10.53 seconds
Started Aug 12 05:02:19 PM PDT 24
Finished Aug 12 05:02:30 PM PDT 24
Peak memory 214844 kb
Host smart-d4d90884-0d34-479a-b6aa-88dde0f4d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534565977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3534565977
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.306588541
Short name T278
Test name
Test status
Simulation time 132780090 ps
CPU time 5.49 seconds
Started Aug 12 05:02:24 PM PDT 24
Finished Aug 12 05:02:30 PM PDT 24
Peak memory 206396 kb
Host smart-c4ec3a25-84ac-4950-ba33-5d0eb68999e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306588541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.306588541
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2360456888
Short name T859
Test name
Test status
Simulation time 323597554 ps
CPU time 2.65 seconds
Started Aug 12 05:02:24 PM PDT 24
Finished Aug 12 05:02:27 PM PDT 24
Peak memory 210088 kb
Host smart-a44fa423-1055-4c65-a6e0-ef19908b9207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360456888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2360456888
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3598811251
Short name T250
Test name
Test status
Simulation time 38576385 ps
CPU time 2.67 seconds
Started Aug 12 05:02:22 PM PDT 24
Finished Aug 12 05:02:24 PM PDT 24
Peak memory 210580 kb
Host smart-add026a9-3800-4353-9b71-490beda4b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598811251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3598811251
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3238019286
Short name T594
Test name
Test status
Simulation time 34551383 ps
CPU time 2.23 seconds
Started Aug 12 05:02:23 PM PDT 24
Finished Aug 12 05:02:25 PM PDT 24
Peak memory 207356 kb
Host smart-a5b5d953-b614-4cbb-bea0-a6d8cb4c260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238019286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3238019286
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2153216976
Short name T426
Test name
Test status
Simulation time 70654310 ps
CPU time 3.34 seconds
Started Aug 12 05:02:29 PM PDT 24
Finished Aug 12 05:02:33 PM PDT 24
Peak memory 208584 kb
Host smart-a29a665a-caea-4454-b69a-130823e45736
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153216976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2153216976
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.712788452
Short name T685
Test name
Test status
Simulation time 306153384 ps
CPU time 4.15 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:41 PM PDT 24
Peak memory 208904 kb
Host smart-34a43b83-e898-4298-8761-418bccd182fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712788452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.712788452
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2426349444
Short name T483
Test name
Test status
Simulation time 58721228 ps
CPU time 1.75 seconds
Started Aug 12 05:02:22 PM PDT 24
Finished Aug 12 05:02:24 PM PDT 24
Peak memory 207424 kb
Host smart-9e8fa6d6-bb1b-4fe2-8e17-9e0b7db41303
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426349444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2426349444
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3675338457
Short name T261
Test name
Test status
Simulation time 24656335 ps
CPU time 2.08 seconds
Started Aug 12 05:02:23 PM PDT 24
Finished Aug 12 05:02:25 PM PDT 24
Peak memory 210912 kb
Host smart-614eaea3-103a-44c2-bfbf-21370399babb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675338457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3675338457
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1150176872
Short name T539
Test name
Test status
Simulation time 806069577 ps
CPU time 14.12 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 208688 kb
Host smart-a14f26d5-3867-4553-882c-a51e9cf2864b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150176872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1150176872
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2028073651
Short name T73
Test name
Test status
Simulation time 2245265192 ps
CPU time 36.74 seconds
Started Aug 12 05:02:25 PM PDT 24
Finished Aug 12 05:03:02 PM PDT 24
Peak memory 216908 kb
Host smart-26f88fa6-672a-47a2-98f1-060d97e4a9f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028073651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2028073651
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2197619783
Short name T842
Test name
Test status
Simulation time 397598491 ps
CPU time 10.03 seconds
Started Aug 12 05:02:24 PM PDT 24
Finished Aug 12 05:02:34 PM PDT 24
Peak memory 209424 kb
Host smart-4285baab-3202-4d7a-9411-060f261a19de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197619783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2197619783
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3597351961
Short name T498
Test name
Test status
Simulation time 43376263 ps
CPU time 0.77 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:37 PM PDT 24
Peak memory 206352 kb
Host smart-6195f746-35f4-499b-8e5d-ee6171beb637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597351961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3597351961
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.919401668
Short name T725
Test name
Test status
Simulation time 46666009 ps
CPU time 2.15 seconds
Started Aug 12 05:02:20 PM PDT 24
Finished Aug 12 05:02:22 PM PDT 24
Peak memory 214780 kb
Host smart-363b8769-c728-42de-bc45-31e224695eae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919401668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.919401668
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1733642264
Short name T27
Test name
Test status
Simulation time 386316437 ps
CPU time 3.56 seconds
Started Aug 12 05:02:21 PM PDT 24
Finished Aug 12 05:02:25 PM PDT 24
Peak memory 223276 kb
Host smart-6944c25d-8eb6-4b70-b4d2-935c7a5ac7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733642264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1733642264
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2846116295
Short name T534
Test name
Test status
Simulation time 1025205923 ps
CPU time 7.51 seconds
Started Aug 12 05:02:21 PM PDT 24
Finished Aug 12 05:02:28 PM PDT 24
Peak memory 214824 kb
Host smart-163b9c1b-2b66-4200-a742-6efdf2073bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846116295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2846116295
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3433325018
Short name T253
Test name
Test status
Simulation time 452782488 ps
CPU time 5.1 seconds
Started Aug 12 05:02:28 PM PDT 24
Finished Aug 12 05:02:33 PM PDT 24
Peak memory 223080 kb
Host smart-6a73f0ea-be60-4cc4-b531-332ca111068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433325018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3433325018
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.854200208
Short name T176
Test name
Test status
Simulation time 66170032 ps
CPU time 2.93 seconds
Started Aug 12 05:02:30 PM PDT 24
Finished Aug 12 05:02:33 PM PDT 24
Peak memory 208460 kb
Host smart-4444b991-ff35-4f33-9bf1-7dd944dc63f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854200208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.854200208
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1906765830
Short name T690
Test name
Test status
Simulation time 3032542479 ps
CPU time 68.75 seconds
Started Aug 12 05:02:32 PM PDT 24
Finished Aug 12 05:03:41 PM PDT 24
Peak memory 209920 kb
Host smart-229f7ad3-3233-445d-8831-0bce26b0742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906765830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1906765830
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1197042410
Short name T465
Test name
Test status
Simulation time 168718521 ps
CPU time 2.37 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:43 PM PDT 24
Peak memory 207264 kb
Host smart-444ffa31-ebaf-41dc-b751-38b0d9738beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197042410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1197042410
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.594924197
Short name T548
Test name
Test status
Simulation time 434703900 ps
CPU time 13.86 seconds
Started Aug 12 05:02:24 PM PDT 24
Finished Aug 12 05:02:38 PM PDT 24
Peak memory 208968 kb
Host smart-38477c4d-2678-4bd4-ae05-d7bb718f59b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594924197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.594924197
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.4171579164
Short name T655
Test name
Test status
Simulation time 314624985 ps
CPU time 5.19 seconds
Started Aug 12 05:02:31 PM PDT 24
Finished Aug 12 05:02:36 PM PDT 24
Peak memory 209156 kb
Host smart-0d1f12a4-5256-4557-89f1-c166d227e17e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171579164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.4171579164
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1304754659
Short name T801
Test name
Test status
Simulation time 89922217 ps
CPU time 1.93 seconds
Started Aug 12 05:02:27 PM PDT 24
Finished Aug 12 05:02:29 PM PDT 24
Peak memory 209296 kb
Host smart-9400ae5e-8262-44c3-96ce-1c9aea3a6af5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304754659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1304754659
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.725359713
Short name T891
Test name
Test status
Simulation time 132932716 ps
CPU time 1.88 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:02:37 PM PDT 24
Peak memory 209556 kb
Host smart-2586f3a6-e8b9-4d27-b40a-7bc6601c34c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725359713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.725359713
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2057634592
Short name T387
Test name
Test status
Simulation time 55964854 ps
CPU time 2.13 seconds
Started Aug 12 05:02:26 PM PDT 24
Finished Aug 12 05:02:28 PM PDT 24
Peak memory 207416 kb
Host smart-d9ba1249-7e91-4b8d-96eb-1f56befd2d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057634592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2057634592
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3948279751
Short name T907
Test name
Test status
Simulation time 1042637509 ps
CPU time 10.17 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:49 PM PDT 24
Peak memory 223148 kb
Host smart-b66a84d5-2cad-4af4-ace2-54142ac01017
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948279751 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3948279751
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.175686469
Short name T678
Test name
Test status
Simulation time 175869472 ps
CPU time 2.76 seconds
Started Aug 12 05:02:26 PM PDT 24
Finished Aug 12 05:02:29 PM PDT 24
Peak memory 207776 kb
Host smart-8bfef244-bee7-48da-a4a4-6215577dbbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175686469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.175686469
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2980167735
Short name T606
Test name
Test status
Simulation time 875303862 ps
CPU time 3.08 seconds
Started Aug 12 05:02:32 PM PDT 24
Finished Aug 12 05:02:36 PM PDT 24
Peak memory 211364 kb
Host smart-e91d45ca-d849-47d8-9af4-7ffaac523698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980167735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2980167735
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.539999582
Short name T464
Test name
Test status
Simulation time 49470553 ps
CPU time 0.89 seconds
Started Aug 12 05:02:40 PM PDT 24
Finished Aug 12 05:02:41 PM PDT 24
Peak memory 206304 kb
Host smart-8b2adc20-a5fc-4930-830a-a49945c14c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539999582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.539999582
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1323138610
Short name T127
Test name
Test status
Simulation time 67193032 ps
CPU time 2.72 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:02:38 PM PDT 24
Peak memory 214760 kb
Host smart-bf054d7a-61a5-4c9a-8500-30da1916039d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323138610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1323138610
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1714619070
Short name T664
Test name
Test status
Simulation time 53101580 ps
CPU time 1.97 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:02:39 PM PDT 24
Peak memory 208240 kb
Host smart-8f948621-3f6b-4503-8e62-336aaaf8c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714619070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1714619070
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.285959282
Short name T393
Test name
Test status
Simulation time 154455617 ps
CPU time 1.95 seconds
Started Aug 12 05:02:40 PM PDT 24
Finished Aug 12 05:02:42 PM PDT 24
Peak memory 214776 kb
Host smart-6bd9ebae-26ca-4451-b372-a20055297023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285959282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.285959282
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.951770886
Short name T236
Test name
Test status
Simulation time 52087860 ps
CPU time 2.08 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:02:38 PM PDT 24
Peak memory 214756 kb
Host smart-f3b9b616-cda8-4637-a4af-cd347c185741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951770886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.951770886
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3722472923
Short name T130
Test name
Test status
Simulation time 57934937 ps
CPU time 3.52 seconds
Started Aug 12 05:02:40 PM PDT 24
Finished Aug 12 05:02:44 PM PDT 24
Peak memory 211316 kb
Host smart-2871c7a8-56b2-4290-bf90-ecf8d11ec928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722472923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3722472923
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.399957707
Short name T475
Test name
Test status
Simulation time 293611138 ps
CPU time 9.85 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:02:47 PM PDT 24
Peak memory 208712 kb
Host smart-87b2c1c0-b943-4387-b1fc-efd2318dacba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399957707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.399957707
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.895142051
Short name T81
Test name
Test status
Simulation time 23467682 ps
CPU time 1.88 seconds
Started Aug 12 05:02:34 PM PDT 24
Finished Aug 12 05:02:36 PM PDT 24
Peak memory 208940 kb
Host smart-c3089e83-bac8-459b-9cb0-40e610457b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895142051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.895142051
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3031779469
Short name T814
Test name
Test status
Simulation time 529324696 ps
CPU time 4.24 seconds
Started Aug 12 05:02:33 PM PDT 24
Finished Aug 12 05:02:37 PM PDT 24
Peak memory 209248 kb
Host smart-f74c84f4-601c-46b3-afd8-717c7dee5144
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031779469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3031779469
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2076673270
Short name T642
Test name
Test status
Simulation time 594010516 ps
CPU time 4.44 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:02:39 PM PDT 24
Peak memory 208656 kb
Host smart-b81f2f97-800e-474c-a935-f2dc610d210c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076673270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2076673270
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2054892250
Short name T448
Test name
Test status
Simulation time 7406746357 ps
CPU time 24.78 seconds
Started Aug 12 05:02:34 PM PDT 24
Finished Aug 12 05:02:58 PM PDT 24
Peak memory 214788 kb
Host smart-67b77223-84eb-44ac-93ab-3db8c76ab7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054892250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2054892250
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.722712923
Short name T194
Test name
Test status
Simulation time 170362754 ps
CPU time 4.21 seconds
Started Aug 12 05:02:32 PM PDT 24
Finished Aug 12 05:02:37 PM PDT 24
Peak memory 207272 kb
Host smart-ab15a9f5-40d5-4793-bda0-09b7fc121a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722712923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.722712923
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4068707259
Short name T894
Test name
Test status
Simulation time 1353853718 ps
CPU time 4.27 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:42 PM PDT 24
Peak memory 214904 kb
Host smart-83408fb7-811d-4c01-9c9a-1fd7e929c24b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068707259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4068707259
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.570893688
Short name T503
Test name
Test status
Simulation time 1515212474 ps
CPU time 35.75 seconds
Started Aug 12 05:02:43 PM PDT 24
Finished Aug 12 05:03:18 PM PDT 24
Peak memory 214832 kb
Host smart-65506f39-4bee-45a4-8eca-3be08bce2d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570893688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.570893688
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2409534044
Short name T497
Test name
Test status
Simulation time 347333593 ps
CPU time 8.64 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 210872 kb
Host smart-4ea99e72-1964-434c-b9ec-3553dfa0b5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409534044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2409534044
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.344657416
Short name T527
Test name
Test status
Simulation time 21713017 ps
CPU time 0.94 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:47 PM PDT 24
Peak memory 206336 kb
Host smart-0a3f3d45-3933-484f-ba75-d7357f2eef99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344657416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.344657416
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.736693184
Short name T96
Test name
Test status
Simulation time 1660369159 ps
CPU time 23.16 seconds
Started Aug 12 05:02:34 PM PDT 24
Finished Aug 12 05:02:57 PM PDT 24
Peak memory 221332 kb
Host smart-c916a226-8c28-4798-ba21-97a927e58e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736693184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.736693184
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4129222280
Short name T570
Test name
Test status
Simulation time 74845325 ps
CPU time 3.22 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:44 PM PDT 24
Peak memory 208176 kb
Host smart-f00983a7-103d-4e17-ba31-363af700f477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129222280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4129222280
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.44567413
Short name T256
Test name
Test status
Simulation time 128263100 ps
CPU time 5.88 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:44 PM PDT 24
Peak memory 222860 kb
Host smart-6c64a65f-ccb5-4c9a-bb86-fa1fa3806c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44567413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.44567413
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3397632484
Short name T696
Test name
Test status
Simulation time 290142006 ps
CPU time 2.32 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:38 PM PDT 24
Peak memory 216724 kb
Host smart-5d2cd920-aa76-4b87-aaa4-28fef795f795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397632484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3397632484
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2332721450
Short name T331
Test name
Test status
Simulation time 2029875389 ps
CPU time 24.04 seconds
Started Aug 12 05:02:33 PM PDT 24
Finished Aug 12 05:02:58 PM PDT 24
Peak memory 209376 kb
Host smart-8c0262c4-7bd2-4e3a-b17a-1d209844cb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332721450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2332721450
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.299719003
Short name T243
Test name
Test status
Simulation time 100944004 ps
CPU time 2.54 seconds
Started Aug 12 05:02:32 PM PDT 24
Finished Aug 12 05:02:35 PM PDT 24
Peak memory 209000 kb
Host smart-890a5ebc-1d0f-450b-8327-4dd035922610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299719003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.299719003
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3120015448
Short name T682
Test name
Test status
Simulation time 2360142363 ps
CPU time 24.31 seconds
Started Aug 12 05:02:31 PM PDT 24
Finished Aug 12 05:02:55 PM PDT 24
Peak memory 209440 kb
Host smart-474df137-9c44-4361-af22-7fdabdc8af9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120015448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3120015448
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.963796456
Short name T493
Test name
Test status
Simulation time 84672960 ps
CPU time 1.93 seconds
Started Aug 12 05:02:48 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 207936 kb
Host smart-7efd380c-3617-44b8-9a2e-cdc6f3f0f723
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963796456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.963796456
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3126268299
Short name T479
Test name
Test status
Simulation time 43211531 ps
CPU time 1.88 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:02:37 PM PDT 24
Peak memory 207828 kb
Host smart-93a9b2cc-d07d-404e-b72d-9067ca29d30f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126268299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3126268299
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.894908550
Short name T38
Test name
Test status
Simulation time 88397321 ps
CPU time 1.92 seconds
Started Aug 12 05:02:34 PM PDT 24
Finished Aug 12 05:02:36 PM PDT 24
Peak memory 208008 kb
Host smart-38872661-90eb-48cd-89d2-8c64c697339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894908550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.894908550
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1693922275
Short name T614
Test name
Test status
Simulation time 411889697 ps
CPU time 2.3 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:39 PM PDT 24
Peak memory 207276 kb
Host smart-ab3e7456-969f-4535-9f5d-3e24274dd9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693922275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1693922275
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.474128581
Short name T179
Test name
Test status
Simulation time 1080325454 ps
CPU time 9.57 seconds
Started Aug 12 05:02:43 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 219320 kb
Host smart-6633d226-e664-41e8-a336-103433424d7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474128581 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.474128581
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3189429019
Short name T197
Test name
Test status
Simulation time 1077680281 ps
CPU time 11.05 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:02:48 PM PDT 24
Peak memory 209720 kb
Host smart-286bb8f6-3f0a-4fca-ac60-ddb8701c41ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189429019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3189429019
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.226592052
Short name T883
Test name
Test status
Simulation time 92633095 ps
CPU time 1.74 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:44 PM PDT 24
Peak memory 210500 kb
Host smart-c4c3037e-f224-4477-bda6-a30323cae1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226592052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.226592052
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3584663423
Short name T600
Test name
Test status
Simulation time 13424833 ps
CPU time 0.9 seconds
Started Aug 12 05:02:33 PM PDT 24
Finished Aug 12 05:02:34 PM PDT 24
Peak memory 206344 kb
Host smart-42c9b7ae-d7af-48d1-97cd-3df0ba1ea9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584663423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3584663423
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.340185226
Short name T247
Test name
Test status
Simulation time 92099673 ps
CPU time 3.61 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:02:38 PM PDT 24
Peak memory 214832 kb
Host smart-2366cf3d-e010-409e-9324-207247a30ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340185226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.340185226
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.838854991
Short name T4
Test name
Test status
Simulation time 114539152 ps
CPU time 1.74 seconds
Started Aug 12 05:02:31 PM PDT 24
Finished Aug 12 05:02:33 PM PDT 24
Peak memory 214880 kb
Host smart-e073dd08-8232-4a66-b125-fb77bf6f7ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838854991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.838854991
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3361779893
Short name T835
Test name
Test status
Simulation time 334299593 ps
CPU time 2.47 seconds
Started Aug 12 05:02:40 PM PDT 24
Finished Aug 12 05:02:42 PM PDT 24
Peak memory 215632 kb
Host smart-a26cadf0-0fe4-436c-a4ab-9d8bc1f45904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361779893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3361779893
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.196428339
Short name T864
Test name
Test status
Simulation time 217782632 ps
CPU time 2.37 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:02:39 PM PDT 24
Peak memory 220972 kb
Host smart-da6eec66-a241-48db-a728-361f22463757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196428339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.196428339
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_random.1948215248
Short name T683
Test name
Test status
Simulation time 231856849 ps
CPU time 6.6 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 209960 kb
Host smart-a1905415-8317-41c8-8656-93d778a936a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948215248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1948215248
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3085779990
Short name T625
Test name
Test status
Simulation time 197660574 ps
CPU time 3.27 seconds
Started Aug 12 05:02:29 PM PDT 24
Finished Aug 12 05:02:33 PM PDT 24
Peak memory 207340 kb
Host smart-a4e05933-4fde-4fda-912f-129307fed990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085779990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3085779990
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4090082258
Short name T866
Test name
Test status
Simulation time 1654893037 ps
CPU time 34.42 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:03:12 PM PDT 24
Peak memory 208972 kb
Host smart-779eae2e-94da-4584-8d66-c230c23857a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090082258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4090082258
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.170365694
Short name T737
Test name
Test status
Simulation time 1430395856 ps
CPU time 35.17 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:03:10 PM PDT 24
Peak memory 209408 kb
Host smart-381feb46-1a54-4f62-ad60-ef9f02e7d687
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170365694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.170365694
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3501342334
Short name T476
Test name
Test status
Simulation time 57438860 ps
CPU time 3.11 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:02:40 PM PDT 24
Peak memory 208780 kb
Host smart-8356cb9e-d707-4210-9b08-00dc08266f08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501342334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3501342334
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.112474959
Short name T628
Test name
Test status
Simulation time 281469776 ps
CPU time 4.3 seconds
Started Aug 12 05:02:33 PM PDT 24
Finished Aug 12 05:02:38 PM PDT 24
Peak memory 210324 kb
Host smart-e54b71cd-565c-4e0f-8e6e-cbf8917b5ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112474959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.112474959
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1895670285
Short name T416
Test name
Test status
Simulation time 120645578 ps
CPU time 2.77 seconds
Started Aug 12 05:02:28 PM PDT 24
Finished Aug 12 05:02:31 PM PDT 24
Peak memory 207280 kb
Host smart-59fb53dd-d29d-4c0a-9fdb-2542d527002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895670285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1895670285
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.329337175
Short name T205
Test name
Test status
Simulation time 25851847760 ps
CPU time 252.13 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:06:51 PM PDT 24
Peak memory 217204 kb
Host smart-f7bce145-8285-4654-baa8-f0a0f6646718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329337175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.329337175
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1227796847
Short name T118
Test name
Test status
Simulation time 783410200 ps
CPU time 11.08 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 222956 kb
Host smart-d884310a-b8ae-44df-826e-7e30e9f95f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227796847 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1227796847
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2667009596
Short name T722
Test name
Test status
Simulation time 3668695350 ps
CPU time 25.49 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:03:05 PM PDT 24
Peak memory 210192 kb
Host smart-595a9d48-d902-4414-8678-71f0124986b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667009596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2667009596
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1671642606
Short name T700
Test name
Test status
Simulation time 79368648 ps
CPU time 1.33 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:02:41 PM PDT 24
Peak memory 210684 kb
Host smart-3a40727a-1a27-4350-b24d-408733cea256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671642606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1671642606
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2928265414
Short name T430
Test name
Test status
Simulation time 22294605 ps
CPU time 0.75 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:02:38 PM PDT 24
Peak memory 206304 kb
Host smart-08c013ad-a897-4200-b69b-0a36cbab78ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928265414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2928265414
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1248361675
Short name T112
Test name
Test status
Simulation time 2407017514 ps
CPU time 28.25 seconds
Started Aug 12 05:02:45 PM PDT 24
Finished Aug 12 05:03:13 PM PDT 24
Peak memory 214828 kb
Host smart-33db250b-b862-417d-823f-3f1cf27f94ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248361675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1248361675
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2405214041
Short name T858
Test name
Test status
Simulation time 396425013 ps
CPU time 4.99 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:46 PM PDT 24
Peak memory 210768 kb
Host smart-c3bd19e3-efef-4131-997d-be6870f7bba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405214041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2405214041
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.465254074
Short name T349
Test name
Test status
Simulation time 7214345892 ps
CPU time 27.5 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:03:03 PM PDT 24
Peak memory 210076 kb
Host smart-dfc7be77-323b-4452-9171-74a5020120c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465254074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.465254074
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1736692173
Short name T748
Test name
Test status
Simulation time 230235309 ps
CPU time 6.57 seconds
Started Aug 12 05:02:35 PM PDT 24
Finished Aug 12 05:02:42 PM PDT 24
Peak memory 214740 kb
Host smart-763e300f-00d6-46e6-b326-ce0dbc49f714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736692173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1736692173
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3823676758
Short name T875
Test name
Test status
Simulation time 133247630 ps
CPU time 3.76 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:40 PM PDT 24
Peak memory 220296 kb
Host smart-68f33266-1837-4a5b-8a83-cad9fcf51335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823676758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3823676758
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3160008416
Short name T667
Test name
Test status
Simulation time 58189429 ps
CPU time 3.04 seconds
Started Aug 12 05:02:36 PM PDT 24
Finished Aug 12 05:02:39 PM PDT 24
Peak memory 209940 kb
Host smart-75253874-45b0-4dd8-838d-ef3ea94c251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160008416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3160008416
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3749546424
Short name T636
Test name
Test status
Simulation time 654274386 ps
CPU time 7.49 seconds
Started Aug 12 05:02:28 PM PDT 24
Finished Aug 12 05:02:35 PM PDT 24
Peak memory 208408 kb
Host smart-b2f03e9a-061e-4eb2-ac81-1d21a76bd915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749546424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3749546424
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3603138148
Short name T518
Test name
Test status
Simulation time 97796062 ps
CPU time 2.74 seconds
Started Aug 12 05:02:43 PM PDT 24
Finished Aug 12 05:02:46 PM PDT 24
Peak memory 207356 kb
Host smart-fb3e4208-4bf4-4a3c-8577-5142f4ce180d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603138148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3603138148
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2416502005
Short name T633
Test name
Test status
Simulation time 1135612962 ps
CPU time 29.38 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:03:08 PM PDT 24
Peak memory 208588 kb
Host smart-27e46460-1065-46da-93b9-81f8fd829f46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416502005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2416502005
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2705390266
Short name T458
Test name
Test status
Simulation time 121217193 ps
CPU time 4.01 seconds
Started Aug 12 05:02:47 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 209312 kb
Host smart-72260587-a3cb-46da-90fe-e0f2b00c2788
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705390266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2705390266
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.4121226040
Short name T100
Test name
Test status
Simulation time 1046966043 ps
CPU time 2.77 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:41 PM PDT 24
Peak memory 209304 kb
Host smart-ede86ae2-a6f4-409f-8029-f1afaf9baa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121226040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4121226040
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1539698090
Short name T424
Test name
Test status
Simulation time 139614675 ps
CPU time 1.96 seconds
Started Aug 12 05:02:29 PM PDT 24
Finished Aug 12 05:02:31 PM PDT 24
Peak memory 207388 kb
Host smart-bc82d34e-d2a1-4f15-ad4e-d798bff66ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539698090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1539698090
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3177250211
Short name T809
Test name
Test status
Simulation time 884472270 ps
CPU time 6.69 seconds
Started Aug 12 05:02:34 PM PDT 24
Finished Aug 12 05:02:40 PM PDT 24
Peak memory 214776 kb
Host smart-4dc924ac-ed7b-4789-a338-3908cee19c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177250211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3177250211
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3326570614
Short name T724
Test name
Test status
Simulation time 308490560 ps
CPU time 2.47 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:41 PM PDT 24
Peak memory 210712 kb
Host smart-7feadb08-a0b6-46d7-8a73-e8534a8c6eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326570614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3326570614
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3078742523
Short name T569
Test name
Test status
Simulation time 44504189 ps
CPU time 0.81 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 206380 kb
Host smart-1ff8a541-b497-456b-b717-3ed96b2f097f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078742523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3078742523
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2356129976
Short name T410
Test name
Test status
Simulation time 1242479842 ps
CPU time 56.81 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:55 PM PDT 24
Peak memory 214828 kb
Host smart-f02b5a06-e8dd-4867-b52a-fdbf4341af3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2356129976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2356129976
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3558364743
Short name T237
Test name
Test status
Simulation time 64538815 ps
CPU time 2.74 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 210632 kb
Host smart-d3f8c0c5-d053-488e-a735-694573638724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558364743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3558364743
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.206973359
Short name T25
Test name
Test status
Simulation time 210905430 ps
CPU time 4.81 seconds
Started Aug 12 05:01:03 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 214804 kb
Host smart-a2ea203d-7ee8-4e9e-9c99-a1a034a9f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206973359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.206973359
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1286432701
Short name T550
Test name
Test status
Simulation time 162571977 ps
CPU time 2.29 seconds
Started Aug 12 05:01:03 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 206548 kb
Host smart-342b4df7-9ea2-492a-b00b-42e3795656fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286432701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1286432701
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.164975230
Short name T510
Test name
Test status
Simulation time 1145979817 ps
CPU time 4.36 seconds
Started Aug 12 05:01:00 PM PDT 24
Finished Aug 12 05:01:04 PM PDT 24
Peak memory 209112 kb
Host smart-5beb3882-c7e9-45f0-9ed1-14641074abc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164975230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.164975230
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.617106534
Short name T619
Test name
Test status
Simulation time 1014994118 ps
CPU time 3.25 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 207340 kb
Host smart-387ecd85-9a86-4dc5-8508-4ddc626bccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617106534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.617106534
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3140559144
Short name T397
Test name
Test status
Simulation time 63538630 ps
CPU time 3.31 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:56 PM PDT 24
Peak memory 207440 kb
Host smart-6f8b73cd-b4a8-4c9e-8f33-6ee7e07fde10
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140559144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3140559144
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1441327875
Short name T740
Test name
Test status
Simulation time 651066946 ps
CPU time 6.96 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 208584 kb
Host smart-90bf24e4-f5b3-4621-9f43-d5781a31aac6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441327875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1441327875
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2168801393
Short name T770
Test name
Test status
Simulation time 76190214 ps
CPU time 3.46 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:00:59 PM PDT 24
Peak memory 207504 kb
Host smart-21c7d77e-0244-43f9-8b96-b06dc67775ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168801393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2168801393
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.237912196
Short name T101
Test name
Test status
Simulation time 145969343 ps
CPU time 1.97 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:02 PM PDT 24
Peak memory 208112 kb
Host smart-a99bf17b-eb26-4132-aeee-15fc46993e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237912196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.237912196
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3184742940
Short name T390
Test name
Test status
Simulation time 214121051 ps
CPU time 2.95 seconds
Started Aug 12 05:01:01 PM PDT 24
Finished Aug 12 05:01:04 PM PDT 24
Peak memory 207316 kb
Host smart-985d0089-c3e3-4ddb-bdf4-c43cda2ef831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184742940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3184742940
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1276447888
Short name T787
Test name
Test status
Simulation time 1317407148 ps
CPU time 20.98 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:19 PM PDT 24
Peak memory 216056 kb
Host smart-452cc43d-90c4-4025-b28a-b6ab86bde657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276447888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1276447888
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3744926390
Short name T651
Test name
Test status
Simulation time 616074809 ps
CPU time 5.71 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:05 PM PDT 24
Peak memory 218864 kb
Host smart-216b9f78-6404-4774-beef-1cdfb2305466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744926390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3744926390
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1999549392
Short name T41
Test name
Test status
Simulation time 41431157 ps
CPU time 1.67 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 210752 kb
Host smart-fde6af14-7e29-422d-9bf8-9ae14783b72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999549392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1999549392
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1554873780
Short name T488
Test name
Test status
Simulation time 29414478 ps
CPU time 0.96 seconds
Started Aug 12 05:02:40 PM PDT 24
Finished Aug 12 05:02:42 PM PDT 24
Peak memory 206528 kb
Host smart-5c111af6-7602-4d02-96b8-91c67774170c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554873780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1554873780
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3721912499
Short name T893
Test name
Test status
Simulation time 66417047 ps
CPU time 2.93 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 214848 kb
Host smart-42509ec7-1434-4c1e-a019-224101269d72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721912499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3721912499
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1654077046
Short name T780
Test name
Test status
Simulation time 50346299 ps
CPU time 2.85 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:02:42 PM PDT 24
Peak memory 223172 kb
Host smart-8a179fba-4cb8-4efd-9614-a4f076415964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654077046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1654077046
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.624821182
Short name T560
Test name
Test status
Simulation time 211014413 ps
CPU time 3.19 seconds
Started Aug 12 05:02:51 PM PDT 24
Finished Aug 12 05:02:54 PM PDT 24
Peak memory 209064 kb
Host smart-1ec4e765-7f75-480e-af79-4d2d36f10fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624821182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.624821182
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1687144750
Short name T351
Test name
Test status
Simulation time 38732081 ps
CPU time 2.96 seconds
Started Aug 12 05:02:49 PM PDT 24
Finished Aug 12 05:02:52 PM PDT 24
Peak memory 221692 kb
Host smart-c3d01565-1cec-4a3f-bbda-23600285f949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687144750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1687144750
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2436655147
Short name T371
Test name
Test status
Simulation time 433940037 ps
CPU time 4.41 seconds
Started Aug 12 05:02:50 PM PDT 24
Finished Aug 12 05:02:55 PM PDT 24
Peak memory 214700 kb
Host smart-5db05241-6f23-4cf4-82c7-899187122554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436655147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2436655147
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3339505052
Short name T735
Test name
Test status
Simulation time 131559196 ps
CPU time 2.75 seconds
Started Aug 12 05:02:49 PM PDT 24
Finished Aug 12 05:02:52 PM PDT 24
Peak memory 220492 kb
Host smart-e31aed3a-6c5b-4f63-8bfa-05a8b6cc155e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339505052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3339505052
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.740643438
Short name T125
Test name
Test status
Simulation time 250912128 ps
CPU time 7.05 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:48 PM PDT 24
Peak memory 209820 kb
Host smart-9ffb4fdf-27f7-426e-b1b6-ab1a99f682f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740643438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.740643438
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1568545906
Short name T249
Test name
Test status
Simulation time 3031768882 ps
CPU time 32.16 seconds
Started Aug 12 05:02:31 PM PDT 24
Finished Aug 12 05:03:03 PM PDT 24
Peak memory 208844 kb
Host smart-3729a0b7-ff04-4a60-ba68-d61b50bf1d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568545906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1568545906
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1016922635
Short name T836
Test name
Test status
Simulation time 3109332772 ps
CPU time 40.82 seconds
Started Aug 12 05:02:59 PM PDT 24
Finished Aug 12 05:03:40 PM PDT 24
Peak memory 208868 kb
Host smart-c62838b5-022d-40ea-ae8a-08fde050a948
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016922635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1016922635
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2100770718
Short name T662
Test name
Test status
Simulation time 2081459113 ps
CPU time 8.4 seconds
Started Aug 12 05:02:44 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 208416 kb
Host smart-5571c049-95bf-4cc8-a791-7938375f9ff2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100770718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2100770718
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.229938352
Short name T415
Test name
Test status
Simulation time 36193815 ps
CPU time 2.4 seconds
Started Aug 12 05:02:50 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 207596 kb
Host smart-68d01ad0-8cd4-4d3f-a0a4-8ddfc3c6674d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229938352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.229938352
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1311081123
Short name T519
Test name
Test status
Simulation time 258035667 ps
CPU time 3.15 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 209244 kb
Host smart-9522b846-bc7b-43cc-a222-22ee61aedc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311081123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1311081123
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.180477546
Short name T547
Test name
Test status
Simulation time 399457289 ps
CPU time 3.58 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:02:42 PM PDT 24
Peak memory 209296 kb
Host smart-10a180e4-32c8-49da-a695-417c2cd73e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180477546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.180477546
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2842066108
Short name T213
Test name
Test status
Simulation time 3657161330 ps
CPU time 47.98 seconds
Started Aug 12 05:02:49 PM PDT 24
Finished Aug 12 05:03:37 PM PDT 24
Peak memory 215564 kb
Host smart-cedec357-d547-4a3f-af9d-bee7357d0e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842066108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2842066108
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.4148730257
Short name T288
Test name
Test status
Simulation time 141832457 ps
CPU time 8.23 seconds
Started Aug 12 05:02:44 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 217992 kb
Host smart-7e1f737c-dbb6-4b53-a505-757fb917f290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148730257 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.4148730257
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3607173435
Short name T717
Test name
Test status
Simulation time 286815662 ps
CPU time 5.13 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:02:47 PM PDT 24
Peak memory 214748 kb
Host smart-1ae57b04-56de-41b5-bcb9-917cee149c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607173435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3607173435
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3988557362
Short name T470
Test name
Test status
Simulation time 41234146 ps
CPU time 0.85 seconds
Started Aug 12 05:02:47 PM PDT 24
Finished Aug 12 05:02:48 PM PDT 24
Peak memory 206316 kb
Host smart-658efb27-4947-4f5a-bb18-8e82429766f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988557362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3988557362
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1709921762
Short name T677
Test name
Test status
Simulation time 120798185 ps
CPU time 2.57 seconds
Started Aug 12 05:03:04 PM PDT 24
Finished Aug 12 05:03:07 PM PDT 24
Peak memory 214740 kb
Host smart-c07c29e4-d6f3-4e3b-ad05-edd17e3854e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709921762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1709921762
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1095653725
Short name T34
Test name
Test status
Simulation time 2040558006 ps
CPU time 5.57 seconds
Started Aug 12 05:02:50 PM PDT 24
Finished Aug 12 05:02:56 PM PDT 24
Peak memory 214780 kb
Host smart-86b84837-96d3-4b53-b219-e4d12a862392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095653725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1095653725
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.250871609
Short name T692
Test name
Test status
Simulation time 70953983 ps
CPU time 1.74 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:43 PM PDT 24
Peak memory 207704 kb
Host smart-2c6baa13-5a2c-410f-ad89-337c4e51b60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250871609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.250871609
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2958463764
Short name T291
Test name
Test status
Simulation time 698947205 ps
CPU time 4.62 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:02:47 PM PDT 24
Peak memory 214820 kb
Host smart-b25042eb-0d7a-4439-bbf3-54e7b703e9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958463764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2958463764
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.283911807
Short name T319
Test name
Test status
Simulation time 68410190 ps
CPU time 3.23 seconds
Started Aug 12 05:02:40 PM PDT 24
Finished Aug 12 05:02:44 PM PDT 24
Peak memory 214732 kb
Host smart-0fe872ec-383b-47fd-a823-49ebd695c3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283911807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.283911807
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1050238275
Short name T629
Test name
Test status
Simulation time 268275973 ps
CPU time 3.45 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 220984 kb
Host smart-84215b4a-ba5b-49bf-8e2d-45139077b4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050238275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1050238275
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2504890496
Short name T449
Test name
Test status
Simulation time 5415727857 ps
CPU time 34.6 seconds
Started Aug 12 05:02:57 PM PDT 24
Finished Aug 12 05:03:32 PM PDT 24
Peak memory 214848 kb
Host smart-453bfd80-a301-44fa-a921-487ecea543c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504890496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2504890496
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3289017727
Short name T536
Test name
Test status
Simulation time 608975910 ps
CPU time 2.68 seconds
Started Aug 12 05:02:45 PM PDT 24
Finished Aug 12 05:02:48 PM PDT 24
Peak memory 207196 kb
Host smart-1590caeb-3e02-4e62-823e-d0d7fe75b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289017727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3289017727
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3356673316
Short name T812
Test name
Test status
Simulation time 91026520 ps
CPU time 3.78 seconds
Started Aug 12 05:02:47 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 209388 kb
Host smart-1a954acb-759b-4649-b73e-c269d309b87d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356673316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3356673316
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.557867125
Short name T832
Test name
Test status
Simulation time 83969144 ps
CPU time 3.69 seconds
Started Aug 12 05:02:50 PM PDT 24
Finished Aug 12 05:02:54 PM PDT 24
Peak memory 207440 kb
Host smart-8ee6788a-85d8-4c55-a71e-39990dc98aa7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557867125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.557867125
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1674565881
Short name T431
Test name
Test status
Simulation time 22501103 ps
CPU time 1.99 seconds
Started Aug 12 05:02:53 PM PDT 24
Finished Aug 12 05:02:55 PM PDT 24
Peak memory 207504 kb
Host smart-c0e0462f-f6c3-4a5c-a324-e368eba22592
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674565881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1674565881
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2551658658
Short name T313
Test name
Test status
Simulation time 551619501 ps
CPU time 6.36 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 214752 kb
Host smart-a9e6ff32-0b92-451b-a82a-02cd3081c744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551658658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2551658658
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1866608056
Short name T543
Test name
Test status
Simulation time 185770842 ps
CPU time 3.43 seconds
Started Aug 12 05:02:58 PM PDT 24
Finished Aug 12 05:03:02 PM PDT 24
Peak memory 209464 kb
Host smart-89f60e42-e041-46ab-883d-ae7a7d458f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866608056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1866608056
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1674520813
Short name T792
Test name
Test status
Simulation time 150804889 ps
CPU time 6.87 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 215700 kb
Host smart-6c3767c1-bf92-4fff-aa91-7543b6003f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674520813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1674520813
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.945665118
Short name T270
Test name
Test status
Simulation time 90092824 ps
CPU time 4.37 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:02:43 PM PDT 24
Peak memory 208568 kb
Host smart-f068151a-0fae-4354-96d6-1afdefe052fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945665118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.945665118
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2922310727
Short name T170
Test name
Test status
Simulation time 333697579 ps
CPU time 2.24 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:06 PM PDT 24
Peak memory 210240 kb
Host smart-d0f3e8dd-6005-4b73-936a-a14d5f61560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922310727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2922310727
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.191605596
Short name T509
Test name
Test status
Simulation time 20363545 ps
CPU time 0.87 seconds
Started Aug 12 05:02:50 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 206320 kb
Host smart-5ea568d1-d752-4035-b557-d51084b78288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191605596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.191605596
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3461905197
Short name T375
Test name
Test status
Simulation time 155812728 ps
CPU time 8.97 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 216184 kb
Host smart-c74b3086-5724-4c74-8fdc-d26e6c942853
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461905197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3461905197
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2620338303
Short name T68
Test name
Test status
Simulation time 4252749642 ps
CPU time 23.71 seconds
Started Aug 12 05:02:48 PM PDT 24
Finished Aug 12 05:03:12 PM PDT 24
Peak memory 223304 kb
Host smart-8f0f3009-c8d9-46a1-b086-1bed600fde9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620338303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2620338303
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1514025002
Short name T895
Test name
Test status
Simulation time 909078636 ps
CPU time 2.56 seconds
Started Aug 12 05:02:50 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 207956 kb
Host smart-634325a8-2f42-4d77-9285-98c45ddacf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514025002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1514025002
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.978551731
Short name T210
Test name
Test status
Simulation time 235876474 ps
CPU time 5.64 seconds
Started Aug 12 05:02:44 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 210912 kb
Host smart-3b973faa-6080-4094-93c8-10c8273fdc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978551731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.978551731
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1487334855
Short name T551
Test name
Test status
Simulation time 2384090096 ps
CPU time 29.98 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:03:13 PM PDT 24
Peak memory 210016 kb
Host smart-251714a5-8546-4bb5-b55e-789b9cdfd996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487334855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1487334855
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3202800059
Short name T577
Test name
Test status
Simulation time 250261489 ps
CPU time 3.34 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 209196 kb
Host smart-5d984ae5-a9cf-480e-8571-28cb41194402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202800059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3202800059
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2314952429
Short name T798
Test name
Test status
Simulation time 115984890 ps
CPU time 3.7 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:02:43 PM PDT 24
Peak memory 209360 kb
Host smart-9101b0fe-7ac2-4f37-90c5-d7e0a5369ddf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314952429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2314952429
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1275646289
Short name T554
Test name
Test status
Simulation time 42588657 ps
CPU time 2.42 seconds
Started Aug 12 05:02:54 PM PDT 24
Finished Aug 12 05:02:57 PM PDT 24
Peak memory 207840 kb
Host smart-4bc04ef9-8e6b-418e-9e51-6d72eb819b44
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275646289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1275646289
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2167103945
Short name T541
Test name
Test status
Simulation time 118755799 ps
CPU time 3.31 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 209496 kb
Host smart-8a5cb857-8623-4feb-afbb-694656a2ade7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167103945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2167103945
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1545424233
Short name T302
Test name
Test status
Simulation time 132098101 ps
CPU time 2.79 seconds
Started Aug 12 05:02:47 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 210348 kb
Host smart-db6ddbb0-f6e7-42d6-9d77-3c5cdc35010a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545424233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1545424233
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3220351193
Short name T763
Test name
Test status
Simulation time 1421348169 ps
CPU time 3.53 seconds
Started Aug 12 05:02:48 PM PDT 24
Finished Aug 12 05:02:52 PM PDT 24
Peak memory 207140 kb
Host smart-8f374570-9ba2-4a59-adfa-0592bc566ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220351193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3220351193
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3572830909
Short name T802
Test name
Test status
Simulation time 3737356698 ps
CPU time 42.57 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:03:22 PM PDT 24
Peak memory 214824 kb
Host smart-85c623b1-f371-49be-8d94-29fe44dcb5f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572830909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3572830909
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.697347933
Short name T663
Test name
Test status
Simulation time 235668327 ps
CPU time 5.9 seconds
Started Aug 12 05:02:49 PM PDT 24
Finished Aug 12 05:02:55 PM PDT 24
Peak memory 210260 kb
Host smart-5e94339b-771b-45fb-a7c8-8e3b5cc6f4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697347933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.697347933
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.4048980544
Short name T123
Test name
Test status
Simulation time 4552976577 ps
CPU time 23.58 seconds
Started Aug 12 05:02:37 PM PDT 24
Finished Aug 12 05:03:01 PM PDT 24
Peak memory 211560 kb
Host smart-2d3311a8-ae81-4753-8f05-1574e9c20561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048980544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.4048980544
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3029974824
Short name T641
Test name
Test status
Simulation time 43936531 ps
CPU time 0.9 seconds
Started Aug 12 05:02:52 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 206444 kb
Host smart-8ed718f0-d682-45f6-ba0e-aa6b66b5fc33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029974824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3029974824
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2017499385
Short name T248
Test name
Test status
Simulation time 2705442454 ps
CPU time 73.07 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:03:55 PM PDT 24
Peak memory 215788 kb
Host smart-c5dd6bb2-53fc-47d8-bc1e-87510541ff18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017499385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2017499385
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2858912826
Short name T761
Test name
Test status
Simulation time 305388905 ps
CPU time 3.95 seconds
Started Aug 12 05:02:49 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 218868 kb
Host smart-dbd84dc6-cc97-4a8a-8c94-c71ef67647f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858912826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2858912826
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2916675509
Short name T620
Test name
Test status
Simulation time 171306793 ps
CPU time 4.69 seconds
Started Aug 12 05:02:45 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 222908 kb
Host smart-b3496351-0807-40e5-8154-29a94adacd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916675509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2916675509
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2672390381
Short name T603
Test name
Test status
Simulation time 358216801 ps
CPU time 6.77 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:15 PM PDT 24
Peak memory 209580 kb
Host smart-68b059ad-3c75-42f0-b10a-6b49bb9e83a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672390381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2672390381
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2270605497
Short name T532
Test name
Test status
Simulation time 211656773 ps
CPU time 2.4 seconds
Started Aug 12 05:02:56 PM PDT 24
Finished Aug 12 05:02:59 PM PDT 24
Peak memory 207372 kb
Host smart-81b2a80f-f056-445b-8d43-c245746b5060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270605497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2270605497
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2426393614
Short name T911
Test name
Test status
Simulation time 66477932 ps
CPU time 3.32 seconds
Started Aug 12 05:02:44 PM PDT 24
Finished Aug 12 05:02:48 PM PDT 24
Peak memory 209444 kb
Host smart-a949376b-0ee8-4615-805e-c446f573c0ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426393614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2426393614
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1089365636
Short name T245
Test name
Test status
Simulation time 24004575 ps
CPU time 1.89 seconds
Started Aug 12 05:02:49 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 209236 kb
Host smart-3e4f5766-6689-4df9-b922-3ad69cc7c0e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089365636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1089365636
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1617301249
Short name T852
Test name
Test status
Simulation time 474525331 ps
CPU time 13.31 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:55 PM PDT 24
Peak memory 209008 kb
Host smart-7b5ff757-f3cf-42b0-8f97-0d43ceceedc0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617301249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1617301249
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2854221008
Short name T704
Test name
Test status
Simulation time 39833211 ps
CPU time 2.34 seconds
Started Aug 12 05:02:41 PM PDT 24
Finished Aug 12 05:02:43 PM PDT 24
Peak memory 210460 kb
Host smart-d33bdcfa-99b0-4979-a2d9-5b756bb33628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854221008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2854221008
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1387128686
Short name T675
Test name
Test status
Simulation time 313552304 ps
CPU time 3.62 seconds
Started Aug 12 05:02:50 PM PDT 24
Finished Aug 12 05:02:54 PM PDT 24
Peak memory 209084 kb
Host smart-14cacbcf-5e78-4058-8ac4-64a71f9660ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387128686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1387128686
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.297008730
Short name T309
Test name
Test status
Simulation time 2702560385 ps
CPU time 26.67 seconds
Started Aug 12 05:02:43 PM PDT 24
Finished Aug 12 05:03:10 PM PDT 24
Peak memory 223104 kb
Host smart-37b91a9a-1d8c-4344-a87c-5a8478dc1e69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297008730 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.297008730
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.168329391
Short name T265
Test name
Test status
Simulation time 68747347 ps
CPU time 3.83 seconds
Started Aug 12 05:02:46 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 210704 kb
Host smart-efe87c67-b9e5-4ecc-9f4c-36e88dfe7bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168329391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.168329391
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3372915435
Short name T537
Test name
Test status
Simulation time 306038547 ps
CPU time 3.5 seconds
Started Aug 12 05:02:45 PM PDT 24
Finished Aug 12 05:02:49 PM PDT 24
Peak memory 211236 kb
Host smart-8868395c-9648-4b82-aa49-5b465986160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372915435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3372915435
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1050813123
Short name T482
Test name
Test status
Simulation time 37471557 ps
CPU time 0.82 seconds
Started Aug 12 05:03:00 PM PDT 24
Finished Aug 12 05:03:01 PM PDT 24
Peak memory 206432 kb
Host smart-288a76bc-3abe-40aa-8b60-a075a4191f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050813123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1050813123
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2141968062
Short name T262
Test name
Test status
Simulation time 517587537 ps
CPU time 7.33 seconds
Started Aug 12 05:02:56 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 214844 kb
Host smart-fe03f173-e8a8-4422-a018-e5e45dc4968b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141968062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2141968062
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1125410857
Short name T784
Test name
Test status
Simulation time 346497218 ps
CPU time 3.33 seconds
Started Aug 12 05:02:47 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 214836 kb
Host smart-766c04d0-d060-424d-826e-dfaf4f5676bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125410857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1125410857
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.143850958
Short name T378
Test name
Test status
Simulation time 1698601586 ps
CPU time 10.92 seconds
Started Aug 12 05:02:43 PM PDT 24
Finished Aug 12 05:02:54 PM PDT 24
Peak memory 221424 kb
Host smart-11f84391-b9a7-4a15-89c2-9f183e7edfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143850958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.143850958
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2495539249
Short name T283
Test name
Test status
Simulation time 65163497 ps
CPU time 3.58 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:02:46 PM PDT 24
Peak memory 222844 kb
Host smart-a2cf24ae-98ef-4465-825b-e7d2cf959706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495539249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2495539249
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.4088045794
Short name T62
Test name
Test status
Simulation time 532470369 ps
CPU time 5.13 seconds
Started Aug 12 05:02:45 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 222916 kb
Host smart-b04a41d2-72b6-4f19-be1e-e8f7ba5e1d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088045794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.4088045794
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2164134049
Short name T795
Test name
Test status
Simulation time 1359878134 ps
CPU time 7.98 seconds
Started Aug 12 05:02:52 PM PDT 24
Finished Aug 12 05:03:00 PM PDT 24
Peak memory 209028 kb
Host smart-07fc79ee-cd05-4a61-abcf-231f47af19fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164134049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2164134049
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2042412446
Short name T276
Test name
Test status
Simulation time 117960038 ps
CPU time 2.18 seconds
Started Aug 12 05:02:48 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 207480 kb
Host smart-e60dbd87-d7ab-42d4-b237-44fa9166d6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042412446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2042412446
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.719232866
Short name T538
Test name
Test status
Simulation time 64255849 ps
CPU time 3.09 seconds
Started Aug 12 05:02:44 PM PDT 24
Finished Aug 12 05:02:47 PM PDT 24
Peak memory 209304 kb
Host smart-cfb705ef-3c37-4ad0-ae86-096edf25499f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719232866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.719232866
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.23176562
Short name T659
Test name
Test status
Simulation time 2171444852 ps
CPU time 7.59 seconds
Started Aug 12 05:02:45 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 209124 kb
Host smart-a5d2fdd3-bf17-444c-a613-890ae56edd12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23176562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.23176562
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1328057292
Short name T880
Test name
Test status
Simulation time 146174828 ps
CPU time 2.41 seconds
Started Aug 12 05:02:38 PM PDT 24
Finished Aug 12 05:02:41 PM PDT 24
Peak memory 207432 kb
Host smart-2633bfe3-f197-4a7c-b0a9-2cab6f8a0e92
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328057292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1328057292
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.4025928453
Short name T528
Test name
Test status
Simulation time 129990937 ps
CPU time 2.14 seconds
Started Aug 12 05:02:49 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 214824 kb
Host smart-cb9431f4-a062-4a0b-bbb7-410096885e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025928453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4025928453
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2993394180
Short name T572
Test name
Test status
Simulation time 345326227 ps
CPU time 2.13 seconds
Started Aug 12 05:02:39 PM PDT 24
Finished Aug 12 05:02:42 PM PDT 24
Peak memory 207496 kb
Host smart-13f598a7-ec46-4497-a730-4a4b3708222d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993394180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2993394180
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.399451212
Short name T119
Test name
Test status
Simulation time 154873288 ps
CPU time 6.82 seconds
Started Aug 12 05:03:04 PM PDT 24
Finished Aug 12 05:03:11 PM PDT 24
Peak memory 222992 kb
Host smart-d36ee2e7-7b38-4df8-9cf9-7d95e7650dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399451212 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.399451212
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1535385993
Short name T386
Test name
Test status
Simulation time 159091508 ps
CPU time 3.77 seconds
Started Aug 12 05:02:50 PM PDT 24
Finished Aug 12 05:02:54 PM PDT 24
Peak memory 207440 kb
Host smart-bf893aee-c685-4a74-a757-fe26dd3e3f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535385993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1535385993
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2097897502
Short name T530
Test name
Test status
Simulation time 248824222 ps
CPU time 7.51 seconds
Started Aug 12 05:02:42 PM PDT 24
Finished Aug 12 05:02:50 PM PDT 24
Peak memory 211020 kb
Host smart-16c995cc-0715-4eac-bc73-0bdd91eca781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097897502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2097897502
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3932741417
Short name T752
Test name
Test status
Simulation time 86919165 ps
CPU time 0.87 seconds
Started Aug 12 05:03:01 PM PDT 24
Finished Aug 12 05:03:02 PM PDT 24
Peak memory 206352 kb
Host smart-da2de10d-687c-44be-8352-3c8eabb327a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932741417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3932741417
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.137013610
Short name T95
Test name
Test status
Simulation time 163623160 ps
CPU time 2.82 seconds
Started Aug 12 05:03:01 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 208884 kb
Host smart-cb925cee-b1b2-43ea-8d22-dd18a530a404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137013610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.137013610
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1325276280
Short name T196
Test name
Test status
Simulation time 948601869 ps
CPU time 13.82 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:20 PM PDT 24
Peak memory 210936 kb
Host smart-eacda673-2058-43d2-8790-75255a89bdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325276280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1325276280
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3229152357
Short name T84
Test name
Test status
Simulation time 464755704 ps
CPU time 5.69 seconds
Started Aug 12 05:02:56 PM PDT 24
Finished Aug 12 05:03:01 PM PDT 24
Peak memory 214824 kb
Host smart-1b44fb80-996f-4a50-9dc1-0eeb6c52d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229152357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3229152357
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.274310716
Short name T281
Test name
Test status
Simulation time 81615217 ps
CPU time 2.45 seconds
Started Aug 12 05:02:57 PM PDT 24
Finished Aug 12 05:02:59 PM PDT 24
Peak memory 214676 kb
Host smart-c755916a-6ce7-4a3b-8929-76d87a728287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274310716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.274310716
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.4186801643
Short name T61
Test name
Test status
Simulation time 74251828 ps
CPU time 3.38 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:10 PM PDT 24
Peak memory 210856 kb
Host smart-003a0ba8-c2b8-44fe-8958-b22b1dd20aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186801643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.4186801643
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.690178724
Short name T905
Test name
Test status
Simulation time 32266245 ps
CPU time 2.1 seconds
Started Aug 12 05:03:02 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 209148 kb
Host smart-23da1e6d-0df5-4797-8577-46a4921c05c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690178724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.690178724
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.282302638
Short name T228
Test name
Test status
Simulation time 114670878 ps
CPU time 3.88 seconds
Started Aug 12 05:03:02 PM PDT 24
Finished Aug 12 05:03:06 PM PDT 24
Peak memory 209036 kb
Host smart-4ddcec7a-f427-467f-8235-7176b08e9bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282302638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.282302638
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2164412503
Short name T364
Test name
Test status
Simulation time 150405615 ps
CPU time 4.67 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:13 PM PDT 24
Peak memory 209408 kb
Host smart-59d6cec3-bc40-4192-b9f0-5d96401a41f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164412503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2164412503
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2928735841
Short name T635
Test name
Test status
Simulation time 70615180 ps
CPU time 3.51 seconds
Started Aug 12 05:02:58 PM PDT 24
Finished Aug 12 05:03:02 PM PDT 24
Peak memory 208796 kb
Host smart-9437af10-bf18-4a07-8b62-7177cc8f2e39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928735841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2928735841
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.612087187
Short name T555
Test name
Test status
Simulation time 26888455 ps
CPU time 1.82 seconds
Started Aug 12 05:03:00 PM PDT 24
Finished Aug 12 05:03:02 PM PDT 24
Peak memory 209136 kb
Host smart-3cc9e8b0-dda2-41af-b534-94fb1d43c98d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612087187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.612087187
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.772505474
Short name T721
Test name
Test status
Simulation time 425820057 ps
CPU time 5.11 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:11 PM PDT 24
Peak memory 210860 kb
Host smart-a3ebedb0-8edb-465b-8fc8-ebfc6b203a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772505474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.772505474
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2703709150
Short name T388
Test name
Test status
Simulation time 375955197 ps
CPU time 2.91 seconds
Started Aug 12 05:03:02 PM PDT 24
Finished Aug 12 05:03:05 PM PDT 24
Peak memory 206040 kb
Host smart-7612c601-de96-4528-a0fd-c7713e4e7b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703709150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2703709150
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2873905848
Short name T230
Test name
Test status
Simulation time 1615445717 ps
CPU time 23.63 seconds
Started Aug 12 05:02:59 PM PDT 24
Finished Aug 12 05:03:22 PM PDT 24
Peak memory 215464 kb
Host smart-b7be33b1-052c-4a23-9935-90117c894c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873905848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2873905848
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2137143656
Short name T55
Test name
Test status
Simulation time 604562106 ps
CPU time 22.41 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:03:27 PM PDT 24
Peak memory 222984 kb
Host smart-894099f6-d00a-4890-b492-595ed9454ee9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137143656 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2137143656
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.739136333
Short name T268
Test name
Test status
Simulation time 43908358 ps
CPU time 3.31 seconds
Started Aug 12 05:02:57 PM PDT 24
Finished Aug 12 05:03:01 PM PDT 24
Peak memory 214904 kb
Host smart-91d107bf-fee0-484d-bba6-0a38dabfc1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739136333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.739136333
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.310094723
Short name T461
Test name
Test status
Simulation time 228637215 ps
CPU time 2.53 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:03:07 PM PDT 24
Peak memory 210756 kb
Host smart-7c051fe6-1b0f-48fd-8ae3-b6fb69ffda33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310094723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.310094723
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.699138556
Short name T419
Test name
Test status
Simulation time 172740446 ps
CPU time 0.88 seconds
Started Aug 12 05:03:02 PM PDT 24
Finished Aug 12 05:03:03 PM PDT 24
Peak memory 205232 kb
Host smart-cd218999-9e6d-44c3-b1e0-b95500f4e019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699138556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.699138556
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.149258384
Short name T878
Test name
Test status
Simulation time 212611576 ps
CPU time 4.47 seconds
Started Aug 12 05:02:59 PM PDT 24
Finished Aug 12 05:03:03 PM PDT 24
Peak memory 214856 kb
Host smart-af084219-d0c4-416b-9e4d-793a6ba87bd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149258384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.149258384
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1391360441
Short name T744
Test name
Test status
Simulation time 29761089 ps
CPU time 1.74 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:05 PM PDT 24
Peak memory 207984 kb
Host smart-4ea8a3e7-2e6f-4869-a327-aadeabc09699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391360441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1391360441
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.237411239
Short name T88
Test name
Test status
Simulation time 151629824 ps
CPU time 4.98 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:08 PM PDT 24
Peak memory 210136 kb
Host smart-c31de274-0cc5-47a9-a6fb-1f44a660e40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237411239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.237411239
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.324324198
Short name T284
Test name
Test status
Simulation time 771478208 ps
CPU time 3.48 seconds
Started Aug 12 05:03:04 PM PDT 24
Finished Aug 12 05:03:07 PM PDT 24
Peak memory 222876 kb
Host smart-f5d019e6-70e9-4b6f-8020-e43114757d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324324198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.324324198
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3337943950
Short name T734
Test name
Test status
Simulation time 182765436 ps
CPU time 2.85 seconds
Started Aug 12 05:02:56 PM PDT 24
Finished Aug 12 05:02:59 PM PDT 24
Peak memory 214744 kb
Host smart-4b82154a-8d95-4518-ba0e-273393f27313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337943950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3337943950
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.353432457
Short name T693
Test name
Test status
Simulation time 297437989 ps
CPU time 8.58 seconds
Started Aug 12 05:02:59 PM PDT 24
Finished Aug 12 05:03:08 PM PDT 24
Peak memory 208360 kb
Host smart-d04ba2d5-a0df-4479-8e74-69c4b62ceb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353432457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.353432457
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2108754861
Short name T799
Test name
Test status
Simulation time 256506440 ps
CPU time 3.19 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:03:08 PM PDT 24
Peak memory 207388 kb
Host smart-2ec3320d-da2c-4d95-9917-3469f4fa5e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108754861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2108754861
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.379568566
Short name T200
Test name
Test status
Simulation time 193251075 ps
CPU time 6.68 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:03:11 PM PDT 24
Peak memory 209044 kb
Host smart-04d5c39d-a476-45f3-9ad8-dd55f7dc552f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379568566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.379568566
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3256339073
Short name T909
Test name
Test status
Simulation time 231615667 ps
CPU time 5 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:03:10 PM PDT 24
Peak memory 209152 kb
Host smart-90d28c0a-869c-4896-885d-0466ccb15f2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256339073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3256339073
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.796409723
Short name T731
Test name
Test status
Simulation time 70806740 ps
CPU time 3.24 seconds
Started Aug 12 05:03:01 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 209172 kb
Host smart-f3ea417e-6671-4d70-b4d3-09af87140feb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796409723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.796409723
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4175873287
Short name T583
Test name
Test status
Simulation time 498628804 ps
CPU time 2.66 seconds
Started Aug 12 05:02:50 PM PDT 24
Finished Aug 12 05:02:53 PM PDT 24
Peak memory 216456 kb
Host smart-2d33d225-6276-459c-bb5b-922c0f105753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175873287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4175873287
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1745303206
Short name T766
Test name
Test status
Simulation time 72363319 ps
CPU time 2.03 seconds
Started Aug 12 05:02:56 PM PDT 24
Finished Aug 12 05:02:58 PM PDT 24
Peak memory 207196 kb
Host smart-5751e61d-b42a-4897-bf85-417aaaef850e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745303206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1745303206
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1243419023
Short name T817
Test name
Test status
Simulation time 4847598062 ps
CPU time 42.44 seconds
Started Aug 12 05:02:57 PM PDT 24
Finished Aug 12 05:03:39 PM PDT 24
Peak memory 215560 kb
Host smart-1a2e9144-364e-4bf4-b650-d9feeda54068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243419023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1243419023
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2980881820
Short name T540
Test name
Test status
Simulation time 98083056 ps
CPU time 2.8 seconds
Started Aug 12 05:03:04 PM PDT 24
Finished Aug 12 05:03:07 PM PDT 24
Peak memory 207876 kb
Host smart-32777d79-2472-4ef6-8998-0911bd24ca4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980881820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2980881820
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3424549661
Short name T637
Test name
Test status
Simulation time 48054908 ps
CPU time 1.85 seconds
Started Aug 12 05:02:55 PM PDT 24
Finished Aug 12 05:02:57 PM PDT 24
Peak memory 210640 kb
Host smart-7e58ca12-98cd-45c9-a1d3-362a1b66ab8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424549661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3424549661
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.142897119
Short name T505
Test name
Test status
Simulation time 12470789 ps
CPU time 0.74 seconds
Started Aug 12 05:03:01 PM PDT 24
Finished Aug 12 05:03:02 PM PDT 24
Peak memory 206348 kb
Host smart-5767d8f8-edc4-499d-946a-b2ee98125127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142897119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.142897119
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.955281746
Short name T292
Test name
Test status
Simulation time 104856734 ps
CPU time 3.74 seconds
Started Aug 12 05:02:47 PM PDT 24
Finished Aug 12 05:02:51 PM PDT 24
Peak memory 214808 kb
Host smart-f2c1cd61-0f44-4c67-bb4b-8f518c59f999
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955281746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.955281746
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1151769014
Short name T107
Test name
Test status
Simulation time 111239732 ps
CPU time 3.13 seconds
Started Aug 12 05:03:02 PM PDT 24
Finished Aug 12 05:03:05 PM PDT 24
Peak memory 218768 kb
Host smart-f3d184e9-91b2-4dc3-b453-6fb32238029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151769014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1151769014
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3442789386
Short name T747
Test name
Test status
Simulation time 207824677 ps
CPU time 2.43 seconds
Started Aug 12 05:03:00 PM PDT 24
Finished Aug 12 05:03:03 PM PDT 24
Peak memory 209532 kb
Host smart-33789b7f-0910-43d1-83cd-6ef373ce3f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442789386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3442789386
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1463745862
Short name T97
Test name
Test status
Simulation time 304848255 ps
CPU time 2.63 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:08 PM PDT 24
Peak memory 215980 kb
Host smart-9be6d2b8-920f-45ba-9c25-713b1643ba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463745862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1463745862
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4150173692
Short name T701
Test name
Test status
Simulation time 224854379 ps
CPU time 4.45 seconds
Started Aug 12 05:02:54 PM PDT 24
Finished Aug 12 05:02:59 PM PDT 24
Peak memory 222720 kb
Host smart-9c1df9b5-5fa5-4d3c-86a3-78bf4a058615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150173692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4150173692
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2260143817
Short name T57
Test name
Test status
Simulation time 76805290 ps
CPU time 2.24 seconds
Started Aug 12 05:02:58 PM PDT 24
Finished Aug 12 05:03:00 PM PDT 24
Peak memory 215460 kb
Host smart-bf66dee8-242c-427e-a686-6bda4ded052e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260143817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2260143817
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3806925784
Short name T80
Test name
Test status
Simulation time 370272317 ps
CPU time 4.54 seconds
Started Aug 12 05:02:59 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 210216 kb
Host smart-f100dff9-4ef8-446d-836c-727f2a2ec511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806925784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3806925784
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2839371043
Short name T621
Test name
Test status
Simulation time 25246215 ps
CPU time 1.81 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:05 PM PDT 24
Peak memory 207464 kb
Host smart-afd81fb0-6fd0-467d-875e-0d210a16401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839371043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2839371043
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4168903704
Short name T843
Test name
Test status
Simulation time 4279137187 ps
CPU time 46.95 seconds
Started Aug 12 05:03:00 PM PDT 24
Finished Aug 12 05:03:47 PM PDT 24
Peak memory 208784 kb
Host smart-687e54da-eea7-4288-8bf2-e8fe428c5f9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168903704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4168903704
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1530081631
Short name T838
Test name
Test status
Simulation time 25995868 ps
CPU time 1.97 seconds
Started Aug 12 05:02:58 PM PDT 24
Finished Aug 12 05:03:00 PM PDT 24
Peak memory 209228 kb
Host smart-55134b63-769e-444c-b649-3d3a047ed2b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530081631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1530081631
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2715619321
Short name T441
Test name
Test status
Simulation time 236757023 ps
CPU time 4.21 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:10 PM PDT 24
Peak memory 207388 kb
Host smart-7a0a605b-bf39-44b5-84a4-717ee7b5aae1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715619321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2715619321
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3665839638
Short name T295
Test name
Test status
Simulation time 387174992 ps
CPU time 2.65 seconds
Started Aug 12 05:02:56 PM PDT 24
Finished Aug 12 05:02:59 PM PDT 24
Peak memory 207772 kb
Host smart-df13d858-4fc4-4562-a8ad-6f4cf1149ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665839638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3665839638
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1497791732
Short name T423
Test name
Test status
Simulation time 122728715 ps
CPU time 2.32 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:08 PM PDT 24
Peak memory 206640 kb
Host smart-e7320bd6-5edf-4347-aca8-79dc0aa1a9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497791732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1497791732
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1967311768
Short name T573
Test name
Test status
Simulation time 554000097 ps
CPU time 4.35 seconds
Started Aug 12 05:03:04 PM PDT 24
Finished Aug 12 05:03:08 PM PDT 24
Peak memory 208884 kb
Host smart-99202360-7b30-49d9-bfd6-e14f83a211ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967311768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1967311768
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2925754122
Short name T395
Test name
Test status
Simulation time 2395453206 ps
CPU time 32.05 seconds
Started Aug 12 05:02:59 PM PDT 24
Finished Aug 12 05:03:31 PM PDT 24
Peak memory 208908 kb
Host smart-001f097f-fadf-485f-a957-0ad3ec3e8fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925754122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2925754122
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2560875064
Short name T382
Test name
Test status
Simulation time 117352663 ps
CPU time 2.95 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:09 PM PDT 24
Peak memory 210828 kb
Host smart-38fc688d-c8c8-4642-94d3-a68904c2d231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560875064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2560875064
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.876420229
Short name T617
Test name
Test status
Simulation time 161273079 ps
CPU time 1.13 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 206492 kb
Host smart-89dc7cd7-aa8b-4730-a064-9e1c8c21c3be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876420229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.876420229
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1214747315
Short name T42
Test name
Test status
Simulation time 2847202984 ps
CPU time 24.59 seconds
Started Aug 12 05:02:56 PM PDT 24
Finished Aug 12 05:03:21 PM PDT 24
Peak memory 218540 kb
Host smart-47e2a667-0255-45bd-8eba-3b858716644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214747315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1214747315
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.857876687
Short name T452
Test name
Test status
Simulation time 66247907 ps
CPU time 2.77 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:09 PM PDT 24
Peak memory 210300 kb
Host smart-6856f087-3d7c-4c14-a51d-7bedb49586a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857876687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.857876687
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2735157003
Short name T571
Test name
Test status
Simulation time 1342007857 ps
CPU time 3.23 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:10 PM PDT 24
Peak memory 215152 kb
Host smart-f4e07f92-73a3-4720-9ffa-343b31a9525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735157003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2735157003
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1811942641
Short name T318
Test name
Test status
Simulation time 448634845 ps
CPU time 10.27 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:14 PM PDT 24
Peak memory 222816 kb
Host smart-33690e01-bf96-4bf2-9fb3-c248a2c9cf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811942641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1811942641
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3548574237
Short name T668
Test name
Test status
Simulation time 40799804 ps
CPU time 3.04 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:09 PM PDT 24
Peak memory 220948 kb
Host smart-27fe7755-1a0d-4e3b-b01d-bfd535b1e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548574237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3548574237
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1692110850
Short name T366
Test name
Test status
Simulation time 1172480227 ps
CPU time 24.42 seconds
Started Aug 12 05:03:02 PM PDT 24
Finished Aug 12 05:03:27 PM PDT 24
Peak memory 209152 kb
Host smart-9bf9ffd1-822f-4e4c-9e22-1d92a9ab3cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692110850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1692110850
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1251074661
Short name T720
Test name
Test status
Simulation time 393959466 ps
CPU time 4.29 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:07 PM PDT 24
Peak memory 208568 kb
Host smart-4b582b73-0946-434e-869e-b5233f16cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251074661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1251074661
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2284153676
Short name T822
Test name
Test status
Simulation time 5845038544 ps
CPU time 26.48 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:34 PM PDT 24
Peak memory 209732 kb
Host smart-ad070f1a-904d-432b-99f9-44bb80bf9900
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284153676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2284153676
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3399735355
Short name T844
Test name
Test status
Simulation time 22828776 ps
CPU time 1.92 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:09 PM PDT 24
Peak memory 209188 kb
Host smart-e2a67054-0597-47b8-8e08-c7273f7c4043
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399735355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3399735355
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.664490948
Short name T342
Test name
Test status
Simulation time 175831826 ps
CPU time 2.68 seconds
Started Aug 12 05:02:59 PM PDT 24
Finished Aug 12 05:03:02 PM PDT 24
Peak memory 209344 kb
Host smart-fd16ec14-b7ea-404e-9901-f09cd0cdd292
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664490948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.664490948
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4161522031
Short name T788
Test name
Test status
Simulation time 215513228 ps
CPU time 2.88 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:11 PM PDT 24
Peak memory 214832 kb
Host smart-dbd41707-c93f-4c18-b0ec-84f8f1af7310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161522031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4161522031
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3441147787
Short name T389
Test name
Test status
Simulation time 518243083 ps
CPU time 2.44 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:03:08 PM PDT 24
Peak memory 207288 kb
Host smart-d1cb8062-b2a1-468a-9d0b-0517b22da9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441147787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3441147787
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1013590588
Short name T871
Test name
Test status
Simulation time 498126125 ps
CPU time 26.76 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:34 PM PDT 24
Peak memory 216408 kb
Host smart-98675140-bf37-462c-b24b-b1584a64610c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013590588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1013590588
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1918404229
Short name T117
Test name
Test status
Simulation time 2025914519 ps
CPU time 21.38 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:28 PM PDT 24
Peak memory 223028 kb
Host smart-46cb61f0-22fd-48bd-8a94-ecb73f9291d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918404229 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1918404229
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2750524256
Short name T597
Test name
Test status
Simulation time 519009593 ps
CPU time 7.79 seconds
Started Aug 12 05:03:04 PM PDT 24
Finished Aug 12 05:03:12 PM PDT 24
Peak memory 214904 kb
Host smart-db2bb74e-3673-4bb4-ab24-ffd6678ef516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750524256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2750524256
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1753806028
Short name T43
Test name
Test status
Simulation time 35104704 ps
CPU time 2 seconds
Started Aug 12 05:02:59 PM PDT 24
Finished Aug 12 05:03:02 PM PDT 24
Peak memory 210800 kb
Host smart-f6d49f94-1974-45d0-87d3-d18db0ba0a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753806028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1753806028
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2823793211
Short name T598
Test name
Test status
Simulation time 41841260 ps
CPU time 0.75 seconds
Started Aug 12 05:03:24 PM PDT 24
Finished Aug 12 05:03:25 PM PDT 24
Peak memory 206404 kb
Host smart-676b4dae-7d05-4ed1-87ad-ba8828bf9b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823793211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2823793211
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.119248814
Short name T223
Test name
Test status
Simulation time 37359199 ps
CPU time 2.72 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:09 PM PDT 24
Peak memory 214924 kb
Host smart-7f26ec10-1fd7-49ea-a0b7-ea7cf3e7b7e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119248814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.119248814
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3969108887
Short name T440
Test name
Test status
Simulation time 217649991 ps
CPU time 3.16 seconds
Started Aug 12 05:03:06 PM PDT 24
Finished Aug 12 05:03:10 PM PDT 24
Peak memory 209832 kb
Host smart-a7113724-a21b-4ed4-aafc-1f0640b0aaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969108887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3969108887
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.319512543
Short name T851
Test name
Test status
Simulation time 170583452 ps
CPU time 2.95 seconds
Started Aug 12 05:03:01 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 218852 kb
Host smart-536bb73e-2fcc-453a-868a-9499a03eaf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319512543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.319512543
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1203174875
Short name T22
Test name
Test status
Simulation time 5023778817 ps
CPU time 7.92 seconds
Started Aug 12 05:03:02 PM PDT 24
Finished Aug 12 05:03:10 PM PDT 24
Peak memory 214888 kb
Host smart-112c6926-de96-46a5-a418-62107c05eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203174875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1203174875
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1892685665
Short name T727
Test name
Test status
Simulation time 34613394 ps
CPU time 2.33 seconds
Started Aug 12 05:03:07 PM PDT 24
Finished Aug 12 05:03:09 PM PDT 24
Peak memory 214672 kb
Host smart-be055b45-ebc6-4a4e-a169-47821599da83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892685665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1892685665
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1756786624
Short name T796
Test name
Test status
Simulation time 127704370 ps
CPU time 3.75 seconds
Started Aug 12 05:03:11 PM PDT 24
Finished Aug 12 05:03:15 PM PDT 24
Peak memory 214788 kb
Host smart-c1528731-bc49-43c0-9100-2c89fdb7dabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756786624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1756786624
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.418034771
Short name T16
Test name
Test status
Simulation time 135808339 ps
CPU time 6.09 seconds
Started Aug 12 05:02:58 PM PDT 24
Finished Aug 12 05:03:04 PM PDT 24
Peak memory 210888 kb
Host smart-2d68e77a-52e0-4062-9dcf-8cf8be23be2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418034771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.418034771
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3916849101
Short name T301
Test name
Test status
Simulation time 475858317 ps
CPU time 6.45 seconds
Started Aug 12 05:03:05 PM PDT 24
Finished Aug 12 05:03:11 PM PDT 24
Peak memory 209488 kb
Host smart-21917e8d-2b55-4132-937f-5e8ef8f1cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916849101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3916849101
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4117436483
Short name T238
Test name
Test status
Simulation time 167903788 ps
CPU time 3.76 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:07 PM PDT 24
Peak memory 209064 kb
Host smart-9492bb8f-e329-4e1b-98b0-e34f11f400be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117436483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4117436483
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2156371910
Short name T867
Test name
Test status
Simulation time 70055043 ps
CPU time 2.99 seconds
Started Aug 12 05:02:57 PM PDT 24
Finished Aug 12 05:03:00 PM PDT 24
Peak memory 209500 kb
Host smart-05f97b70-e5f9-4eaf-b3b8-c212b1990c26
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156371910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2156371910
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.565192168
Short name T861
Test name
Test status
Simulation time 143244401 ps
CPU time 1.87 seconds
Started Aug 12 05:02:58 PM PDT 24
Finished Aug 12 05:03:00 PM PDT 24
Peak memory 207448 kb
Host smart-350bda6a-91a2-45e8-9ecd-8ea61f2f9312
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565192168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.565192168
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1809241389
Short name T321
Test name
Test status
Simulation time 97292582 ps
CPU time 1.98 seconds
Started Aug 12 05:03:04 PM PDT 24
Finished Aug 12 05:03:07 PM PDT 24
Peak memory 218788 kb
Host smart-78c3194f-a677-4a10-83f7-503ed565bb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809241389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1809241389
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1059437303
Short name T581
Test name
Test status
Simulation time 55431399 ps
CPU time 2.62 seconds
Started Aug 12 05:03:08 PM PDT 24
Finished Aug 12 05:03:11 PM PDT 24
Peak memory 208608 kb
Host smart-1ae27743-e3ee-452d-8b9c-7cad2b9291e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059437303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1059437303
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2315312894
Short name T289
Test name
Test status
Simulation time 2987195099 ps
CPU time 81 seconds
Started Aug 12 05:03:11 PM PDT 24
Finished Aug 12 05:04:32 PM PDT 24
Peak memory 221400 kb
Host smart-2ceb6e02-46fe-4a93-ab74-5da68b8ed88e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315312894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2315312894
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.345384650
Short name T293
Test name
Test status
Simulation time 91396027 ps
CPU time 4.43 seconds
Started Aug 12 05:03:02 PM PDT 24
Finished Aug 12 05:03:07 PM PDT 24
Peak memory 214844 kb
Host smart-7c2760fb-e564-42b0-b163-f7c05dba06af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345384650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.345384650
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1328972718
Short name T821
Test name
Test status
Simulation time 195272959 ps
CPU time 3.49 seconds
Started Aug 12 05:03:03 PM PDT 24
Finished Aug 12 05:03:07 PM PDT 24
Peak memory 210940 kb
Host smart-db600e20-bbc3-4a9e-a75f-465beb1cc9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328972718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1328972718
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.471934443
Short name T94
Test name
Test status
Simulation time 23413506 ps
CPU time 0.88 seconds
Started Aug 12 05:01:03 PM PDT 24
Finished Aug 12 05:01:04 PM PDT 24
Peak memory 206368 kb
Host smart-c39a7505-fc22-4b22-9344-7e1693748a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471934443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.471934443
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2101214483
Short name T913
Test name
Test status
Simulation time 3433199215 ps
CPU time 28.78 seconds
Started Aug 12 05:01:02 PM PDT 24
Finished Aug 12 05:01:31 PM PDT 24
Peak memory 223316 kb
Host smart-17881bfe-9de1-49a5-9a0f-f3f833197a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101214483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2101214483
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3684888260
Short name T457
Test name
Test status
Simulation time 253480810 ps
CPU time 2.89 seconds
Started Aug 12 05:00:57 PM PDT 24
Finished Aug 12 05:01:00 PM PDT 24
Peak memory 207760 kb
Host smart-09de0769-68a5-4046-a206-3a8644ea28d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684888260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3684888260
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2168955573
Short name T370
Test name
Test status
Simulation time 263100160 ps
CPU time 2.6 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:07 PM PDT 24
Peak memory 214708 kb
Host smart-411b7b85-d775-4f8f-b613-0b2a1e62ef7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168955573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2168955573
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.332199865
Short name T7
Test name
Test status
Simulation time 93587292 ps
CPU time 3.08 seconds
Started Aug 12 05:01:03 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 223004 kb
Host smart-09d4e981-85d2-44ab-8298-75ee0a337758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332199865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.332199865
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1618395099
Short name T723
Test name
Test status
Simulation time 62615756 ps
CPU time 3 seconds
Started Aug 12 05:01:03 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 207884 kb
Host smart-a8ac43da-87ed-44f9-95a1-40c8705fca9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618395099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1618395099
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.637856617
Short name T508
Test name
Test status
Simulation time 22207196 ps
CPU time 1.69 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 207388 kb
Host smart-c671649e-7e13-4a6e-a567-9e9f17c1f29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637856617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.637856617
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1258330087
Short name T800
Test name
Test status
Simulation time 478773502 ps
CPU time 4.14 seconds
Started Aug 12 05:00:56 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 209168 kb
Host smart-c8463071-9ed9-4094-b2f1-ba179c2c200a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258330087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1258330087
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2467563873
Short name T764
Test name
Test status
Simulation time 41556399 ps
CPU time 2.4 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 207584 kb
Host smart-d4fd5681-0d44-4bce-b459-6797d0502b48
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467563873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2467563873
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.4260093480
Short name T522
Test name
Test status
Simulation time 470737889 ps
CPU time 6.52 seconds
Started Aug 12 05:01:00 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 208668 kb
Host smart-c943767c-82e7-430d-977a-ce57b99ad027
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260093480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.4260093480
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.953283170
Short name T446
Test name
Test status
Simulation time 56511990 ps
CPU time 2.06 seconds
Started Aug 12 05:01:03 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 209032 kb
Host smart-5dd203f4-f1a4-49ed-be94-ab3edf147be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953283170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.953283170
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1250909640
Short name T768
Test name
Test status
Simulation time 173398674 ps
CPU time 3.97 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:00:57 PM PDT 24
Peak memory 208948 kb
Host smart-466464b4-ca17-4acd-81e0-0b569ad4e82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250909640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1250909640
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1832614296
Short name T840
Test name
Test status
Simulation time 376620942 ps
CPU time 3.01 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 207436 kb
Host smart-63cc61d3-9b48-48e9-9364-736c72eb89f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832614296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1832614296
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2209914672
Short name T311
Test name
Test status
Simulation time 573663137 ps
CPU time 21.27 seconds
Started Aug 12 05:01:01 PM PDT 24
Finished Aug 12 05:01:23 PM PDT 24
Peak memory 223044 kb
Host smart-a3be730b-b2ef-409a-b9d3-d73c31488499
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209914672 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2209914672
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.936115186
Short name T330
Test name
Test status
Simulation time 892347795 ps
CPU time 5.13 seconds
Started Aug 12 05:01:08 PM PDT 24
Finished Aug 12 05:01:14 PM PDT 24
Peak memory 218776 kb
Host smart-7ac368ce-8703-4e5c-b071-83af01b1f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936115186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.936115186
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.843091475
Short name T557
Test name
Test status
Simulation time 203232334 ps
CPU time 2.52 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 210692 kb
Host smart-b487b330-6874-4ab6-a992-5c9d1f411d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843091475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.843091475
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1336816399
Short name T648
Test name
Test status
Simulation time 36346512 ps
CPU time 0.75 seconds
Started Aug 12 05:00:57 PM PDT 24
Finished Aug 12 05:00:58 PM PDT 24
Peak memory 206360 kb
Host smart-d88ed800-f04d-4b4b-9b55-703d7d3f6633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336816399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1336816399
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2179156752
Short name T445
Test name
Test status
Simulation time 105539896 ps
CPU time 4.56 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:04 PM PDT 24
Peak memory 210600 kb
Host smart-5cfd87dc-5d86-4c24-861d-640246b3e346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179156752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2179156752
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2599692811
Short name T587
Test name
Test status
Simulation time 43067349 ps
CPU time 2.11 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 208656 kb
Host smart-6cb41db2-d34e-4582-b911-d22b7d8cc5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599692811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2599692811
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.117774862
Short name T303
Test name
Test status
Simulation time 190614521 ps
CPU time 5.12 seconds
Started Aug 12 05:01:16 PM PDT 24
Finished Aug 12 05:01:21 PM PDT 24
Peak memory 209748 kb
Host smart-62d13d29-f617-4c9c-8773-4b714bcb2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117774862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.117774862
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2377007752
Short name T372
Test name
Test status
Simulation time 245376159 ps
CPU time 2.54 seconds
Started Aug 12 05:01:16 PM PDT 24
Finished Aug 12 05:01:19 PM PDT 24
Peak memory 207744 kb
Host smart-e126148b-cee8-45d3-ab9f-1da2ab2c0360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377007752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2377007752
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1780719511
Short name T680
Test name
Test status
Simulation time 113524346 ps
CPU time 2 seconds
Started Aug 12 05:01:03 PM PDT 24
Finished Aug 12 05:01:05 PM PDT 24
Peak memory 214928 kb
Host smart-1872b0e2-96ec-4dfc-b9f3-351e6585f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780719511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1780719511
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.629164743
Short name T106
Test name
Test status
Simulation time 184110148 ps
CPU time 6.46 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:12 PM PDT 24
Peak memory 208020 kb
Host smart-d8b18535-add3-4f29-927c-eefaa2a690e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629164743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.629164743
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3577496860
Short name T459
Test name
Test status
Simulation time 106504458 ps
CPU time 4.23 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 209204 kb
Host smart-042d7b7c-334e-440c-9f9f-acc88f77bdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577496860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3577496860
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3557251768
Short name T463
Test name
Test status
Simulation time 35808768 ps
CPU time 2.39 seconds
Started Aug 12 05:01:14 PM PDT 24
Finished Aug 12 05:01:16 PM PDT 24
Peak memory 207432 kb
Host smart-e6d54b75-0182-4363-b00a-8e98b2c255a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557251768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3557251768
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.747582894
Short name T501
Test name
Test status
Simulation time 412824466 ps
CPU time 5.3 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:07 PM PDT 24
Peak memory 207444 kb
Host smart-23599c26-ce52-4472-9d3b-98feb47509ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747582894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.747582894
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.961622608
Short name T18
Test name
Test status
Simulation time 54947005 ps
CPU time 2.96 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:02 PM PDT 24
Peak memory 208908 kb
Host smart-e98a7fcb-e3b3-439a-89cd-3672ad32d863
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961622608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.961622608
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4123931844
Short name T903
Test name
Test status
Simulation time 1081579753 ps
CPU time 23.76 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:29 PM PDT 24
Peak memory 218872 kb
Host smart-e90f64f7-aef3-435b-87aa-4a67c6ad2aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123931844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4123931844
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.217721320
Short name T435
Test name
Test status
Simulation time 1410481343 ps
CPU time 7.21 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:12 PM PDT 24
Peak memory 209072 kb
Host smart-118f82d6-b1a4-4ae1-97d9-5f7ec2c4e122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217721320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.217721320
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3940882431
Short name T186
Test name
Test status
Simulation time 2592673231 ps
CPU time 26.09 seconds
Started Aug 12 05:01:13 PM PDT 24
Finished Aug 12 05:01:39 PM PDT 24
Peak memory 214872 kb
Host smart-7af3e66a-efab-4c44-817b-46e86c7058d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940882431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3940882431
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3219708818
Short name T358
Test name
Test status
Simulation time 302859025 ps
CPU time 11.84 seconds
Started Aug 12 05:01:02 PM PDT 24
Finished Aug 12 05:01:14 PM PDT 24
Peak memory 222924 kb
Host smart-f96f2c1b-f68b-4b4c-9d11-83c929f42b13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219708818 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3219708818
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.594032710
Short name T524
Test name
Test status
Simulation time 137369218 ps
CPU time 6.26 seconds
Started Aug 12 05:01:03 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 214808 kb
Host smart-97dada4e-42fe-4215-9a5c-fa5566d86b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594032710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.594032710
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3214593590
Short name T39
Test name
Test status
Simulation time 90425351 ps
CPU time 1.19 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:05 PM PDT 24
Peak memory 210020 kb
Host smart-88fcdb53-146e-41e0-add9-da085ae9ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214593590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3214593590
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2675420459
Short name T831
Test name
Test status
Simulation time 9687001 ps
CPU time 0.75 seconds
Started Aug 12 05:01:08 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 206268 kb
Host smart-109f18cc-d481-4f5d-b18f-2efc40a0b118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675420459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2675420459
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2669860704
Short name T384
Test name
Test status
Simulation time 136749211 ps
CPU time 4.65 seconds
Started Aug 12 05:01:08 PM PDT 24
Finished Aug 12 05:01:13 PM PDT 24
Peak memory 216020 kb
Host smart-3840af68-4779-4b3c-a926-f43f14b9b93a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669860704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2669860704
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.801928920
Short name T20
Test name
Test status
Simulation time 161401114 ps
CPU time 6.29 seconds
Started Aug 12 05:00:57 PM PDT 24
Finished Aug 12 05:01:04 PM PDT 24
Peak memory 222116 kb
Host smart-050d0ec2-4e28-4b00-97d5-6c4cabaf211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801928920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.801928920
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3929178891
Short name T755
Test name
Test status
Simulation time 70113553 ps
CPU time 1.68 seconds
Started Aug 12 05:01:01 PM PDT 24
Finished Aug 12 05:01:03 PM PDT 24
Peak memory 208232 kb
Host smart-ce8f033e-56e4-44b6-a15f-a3825ec3f3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929178891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3929178891
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1856043093
Short name T335
Test name
Test status
Simulation time 60847473 ps
CPU time 2.24 seconds
Started Aug 12 05:01:01 PM PDT 24
Finished Aug 12 05:01:04 PM PDT 24
Peak memory 221208 kb
Host smart-57558060-cf34-479d-938d-d21efb1436ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856043093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1856043093
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.811600479
Short name T546
Test name
Test status
Simulation time 65925002 ps
CPU time 2.95 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 221264 kb
Host smart-022df138-5d0a-4e71-a127-2563eac4ab4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811600479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.811600479
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3820610954
Short name T499
Test name
Test status
Simulation time 349322575 ps
CPU time 3.55 seconds
Started Aug 12 05:01:12 PM PDT 24
Finished Aug 12 05:01:15 PM PDT 24
Peak memory 220552 kb
Host smart-6d38e6b3-1bba-42b2-b6ff-b0baa75c88c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820610954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3820610954
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4243684223
Short name T104
Test name
Test status
Simulation time 328048734 ps
CPU time 5.05 seconds
Started Aug 12 05:01:18 PM PDT 24
Finished Aug 12 05:01:24 PM PDT 24
Peak memory 214824 kb
Host smart-d94f0322-4c02-4cc8-97dc-a85a38fa93fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243684223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4243684223
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1028030769
Short name T511
Test name
Test status
Simulation time 341665688 ps
CPU time 2.82 seconds
Started Aug 12 05:01:03 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 207924 kb
Host smart-c9b52586-8579-41ae-b760-d8a03df6cb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028030769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1028030769
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2045150169
Short name T229
Test name
Test status
Simulation time 153598366 ps
CPU time 5.56 seconds
Started Aug 12 05:01:08 PM PDT 24
Finished Aug 12 05:01:13 PM PDT 24
Peak memory 208344 kb
Host smart-db139343-0556-4fe8-8273-7995a3c9aea4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045150169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2045150169
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3471272994
Short name T732
Test name
Test status
Simulation time 337677434 ps
CPU time 9.3 seconds
Started Aug 12 05:00:59 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 209300 kb
Host smart-d2582d20-3abd-4cec-9fc5-f914e5e6909a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471272994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3471272994
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.371454980
Short name T308
Test name
Test status
Simulation time 70451640 ps
CPU time 3.35 seconds
Started Aug 12 05:01:09 PM PDT 24
Finished Aug 12 05:01:13 PM PDT 24
Peak memory 209036 kb
Host smart-6190c747-cb2a-4734-84e9-e094dce51202
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371454980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.371454980
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3551695431
Short name T76
Test name
Test status
Simulation time 87495459 ps
CPU time 2.24 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 210064 kb
Host smart-8aa90b48-fbd5-4bbd-aa65-b40ed1935103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551695431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3551695431
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.940401916
Short name T444
Test name
Test status
Simulation time 1107313254 ps
CPU time 2.68 seconds
Started Aug 12 05:01:06 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 207320 kb
Host smart-6bbd5a51-3d88-4c5c-bb61-14afc5d846f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940401916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.940401916
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2924590598
Short name T646
Test name
Test status
Simulation time 181400621 ps
CPU time 7.21 seconds
Started Aug 12 05:00:58 PM PDT 24
Finished Aug 12 05:01:05 PM PDT 24
Peak memory 209184 kb
Host smart-bb695dcf-7f46-4695-b693-27099063c59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924590598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2924590598
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1776773451
Short name T190
Test name
Test status
Simulation time 52900724 ps
CPU time 2.31 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:07 PM PDT 24
Peak memory 210576 kb
Host smart-7d5e9a46-288c-4723-8ee6-466d06422b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776773451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1776773451
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3024555983
Short name T447
Test name
Test status
Simulation time 13781433 ps
CPU time 0.77 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:05 PM PDT 24
Peak memory 206356 kb
Host smart-30207c78-40f7-49df-8193-576d437b4701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024555983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3024555983
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1814019605
Short name T596
Test name
Test status
Simulation time 90714871 ps
CPU time 2.18 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 217340 kb
Host smart-596c6691-a7b3-4fb3-9b97-6ee759601ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814019605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1814019605
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3072678437
Short name T841
Test name
Test status
Simulation time 159849103 ps
CPU time 2.05 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 207372 kb
Host smart-b70a7c2d-5ff5-4eb0-8414-70da440886cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072678437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3072678437
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1446525437
Short name T257
Test name
Test status
Simulation time 29312164 ps
CPU time 1.81 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 214656 kb
Host smart-5906e9a7-396c-4b8d-b8e6-f090c6d5551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446525437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1446525437
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3287709124
Short name T760
Test name
Test status
Simulation time 272438712 ps
CPU time 6.13 seconds
Started Aug 12 05:01:12 PM PDT 24
Finished Aug 12 05:01:18 PM PDT 24
Peak memory 220524 kb
Host smart-c6486237-67d1-465d-a2a5-bbd85621ffdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287709124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3287709124
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4057863607
Short name T193
Test name
Test status
Simulation time 227856948 ps
CPU time 5.52 seconds
Started Aug 12 05:01:14 PM PDT 24
Finished Aug 12 05:01:19 PM PDT 24
Peak memory 214736 kb
Host smart-05c77982-65ad-4c27-9c9f-4d4d74bbe2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057863607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4057863607
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.521582182
Short name T826
Test name
Test status
Simulation time 148918231 ps
CPU time 3.81 seconds
Started Aug 12 05:01:01 PM PDT 24
Finished Aug 12 05:01:05 PM PDT 24
Peak memory 209220 kb
Host smart-34e8192c-625c-4b6c-8af4-d5902244d4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521582182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.521582182
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3724069489
Short name T442
Test name
Test status
Simulation time 66905928 ps
CPU time 3.3 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:07 PM PDT 24
Peak memory 207380 kb
Host smart-ec8934a1-6d7e-476c-a338-27db85cbcdf9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724069489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3724069489
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3591977732
Short name T525
Test name
Test status
Simulation time 126411041 ps
CPU time 4.42 seconds
Started Aug 12 05:01:12 PM PDT 24
Finished Aug 12 05:01:16 PM PDT 24
Peak memory 208980 kb
Host smart-7ea3d4bf-40e6-429b-afad-6ba07eec10ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591977732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3591977732
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1702946103
Short name T427
Test name
Test status
Simulation time 177862365 ps
CPU time 4.16 seconds
Started Aug 12 05:01:12 PM PDT 24
Finished Aug 12 05:01:16 PM PDT 24
Peak memory 209132 kb
Host smart-28c0ef5a-3a69-4ad9-b5b2-5d4a50ed249a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702946103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1702946103
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2237117062
Short name T103
Test name
Test status
Simulation time 256210177 ps
CPU time 3.77 seconds
Started Aug 12 05:01:09 PM PDT 24
Finished Aug 12 05:01:13 PM PDT 24
Peak memory 210228 kb
Host smart-29ed05e7-d2e9-47d9-9e9b-510ce303feae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237117062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2237117062
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3463768174
Short name T417
Test name
Test status
Simulation time 30109646 ps
CPU time 1.76 seconds
Started Aug 12 05:01:13 PM PDT 24
Finished Aug 12 05:01:15 PM PDT 24
Peak memory 208496 kb
Host smart-dfbc4e2a-0604-4328-b0bd-ddef63ad24b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463768174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3463768174
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3804466103
Short name T294
Test name
Test status
Simulation time 293859863 ps
CPU time 4.29 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 218760 kb
Host smart-b5822357-297a-4964-a330-08454c86a58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804466103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3804466103
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1139860932
Short name T504
Test name
Test status
Simulation time 107578050 ps
CPU time 2.47 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 210908 kb
Host smart-9d0947d7-8ecd-4e0c-802c-ad01d19088f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139860932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1139860932
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1812326438
Short name T870
Test name
Test status
Simulation time 113932727 ps
CPU time 0.95 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:06 PM PDT 24
Peak memory 206328 kb
Host smart-3a80a06d-b5c2-48e5-ab92-78da22f86f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812326438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1812326438
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1035905357
Short name T70
Test name
Test status
Simulation time 21171656 ps
CPU time 1.74 seconds
Started Aug 12 05:01:11 PM PDT 24
Finished Aug 12 05:01:13 PM PDT 24
Peak memory 208692 kb
Host smart-ea838946-c32c-419b-9337-5d13a5d29aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035905357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1035905357
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3253553856
Short name T714
Test name
Test status
Simulation time 32893233 ps
CPU time 2.34 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:07 PM PDT 24
Peak memory 214760 kb
Host smart-6c5d7ad2-1956-42ed-a51a-433d3901680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253553856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3253553856
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2303887529
Short name T715
Test name
Test status
Simulation time 88109320 ps
CPU time 3.46 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 214732 kb
Host smart-0cf51bc4-4f4b-44d8-94de-77c7c8d0d3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303887529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2303887529
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2226964945
Short name T58
Test name
Test status
Simulation time 100030606 ps
CPU time 4.52 seconds
Started Aug 12 05:01:04 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 214852 kb
Host smart-476da586-5a4d-4f34-9917-5ffccf3ac7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226964945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2226964945
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.746996003
Short name T902
Test name
Test status
Simulation time 545648020 ps
CPU time 6.61 seconds
Started Aug 12 05:01:19 PM PDT 24
Finished Aug 12 05:01:26 PM PDT 24
Peak memory 209948 kb
Host smart-3b8d497c-2507-4fe4-9154-c7f88dade62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746996003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.746996003
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3689357846
Short name T857
Test name
Test status
Simulation time 1199352433 ps
CPU time 12.44 seconds
Started Aug 12 05:01:12 PM PDT 24
Finished Aug 12 05:01:24 PM PDT 24
Peak memory 208484 kb
Host smart-383b8239-b620-48f2-877d-3b1017e04834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689357846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3689357846
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.842736089
Short name T17
Test name
Test status
Simulation time 123246039 ps
CPU time 2.62 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 209084 kb
Host smart-fc26b346-a6d3-4a71-820f-da75961f773c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842736089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.842736089
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.268579805
Short name T37
Test name
Test status
Simulation time 46188984 ps
CPU time 2.56 seconds
Started Aug 12 05:01:16 PM PDT 24
Finished Aug 12 05:01:18 PM PDT 24
Peak memory 209272 kb
Host smart-29b407c8-6018-4dd9-bb83-60a937b38bf8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268579805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.268579805
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3497408648
Short name T605
Test name
Test status
Simulation time 86370307 ps
CPU time 3.65 seconds
Started Aug 12 05:01:11 PM PDT 24
Finished Aug 12 05:01:14 PM PDT 24
Peak memory 209280 kb
Host smart-7f1f2f17-9220-41c0-9083-b13b05625181
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497408648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3497408648
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1822873299
Short name T269
Test name
Test status
Simulation time 260430979 ps
CPU time 3.88 seconds
Started Aug 12 05:01:05 PM PDT 24
Finished Aug 12 05:01:09 PM PDT 24
Peak memory 210132 kb
Host smart-8b495867-5a77-4eb2-b790-0bc77c016637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822873299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1822873299
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1998474988
Short name T492
Test name
Test status
Simulation time 145616113 ps
CPU time 2.18 seconds
Started Aug 12 05:01:00 PM PDT 24
Finished Aug 12 05:01:04 PM PDT 24
Peak memory 206604 kb
Host smart-fd62c28f-1f22-4399-865c-4b8fd0276501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998474988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1998474988
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3544266679
Short name T177
Test name
Test status
Simulation time 2279033184 ps
CPU time 23.1 seconds
Started Aug 12 05:01:07 PM PDT 24
Finished Aug 12 05:01:30 PM PDT 24
Peak memory 221172 kb
Host smart-19f3b742-e580-43dd-be36-b01fa3082ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544266679 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3544266679
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1000807444
Short name T290
Test name
Test status
Simulation time 580715656 ps
CPU time 10.51 seconds
Started Aug 12 05:01:08 PM PDT 24
Finished Aug 12 05:01:19 PM PDT 24
Peak memory 218856 kb
Host smart-373a1781-059f-444a-a0b5-621e4be24864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000807444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1000807444
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1690041134
Short name T380
Test name
Test status
Simulation time 33989246 ps
CPU time 2.05 seconds
Started Aug 12 05:01:11 PM PDT 24
Finished Aug 12 05:01:13 PM PDT 24
Peak memory 210784 kb
Host smart-dad9e9c0-0a4b-4a31-a7c9-a751439b76b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690041134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1690041134
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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