| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 87.50 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 8 | 1 | 7 | 87.50 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| invalid_hw_input_cp | 8 | 1 | 7 | 87.50 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 8 | 1 | 7 | 87.50 | 
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| auto[OtpRootKeyValidLow] | 0 | 1 | 1 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[OtpRootKeyInvalid] | 5 | 1 | T61 | 1 | T77 | 1 | T174 | 1 | ||||
| auto[LcStateInvalid] | 192 | 1 | T271 | 12 | T286 | 36 | T368 | 84 | ||||
| auto[OtpDevIdInvalid] | 180 | 1 | T24 | 12 | T86 | 24 | T271 | 48 | ||||
| auto[RomDigestInvalid] | 168 | 1 | T22 | 36 | T24 | 12 | T330 | 36 | ||||
| auto[RomDigestValidLow] | 84 | 1 | T23 | 12 | T233 | 60 | T369 | 12 | ||||
| auto[FlashCreatorSeedInvalid] | 72 | 1 | T86 | 12 | T271 | 12 | T330 | 48 | ||||
| auto[FlashOwnerSeedInvalid] | 106 | 1 | T23 | 36 | T89 | 22 | T90 | 24 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |