Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	43	1			T5	2		T43	1		T44	3
auto[OpGenId]	14	1			T56	1		T5	1		T194	1
auto[OpGenSwOut]	23	1			T52	3		T61	1		T73	1
auto[OpGenHwOut]	25	1			T5	2		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1720	1			T6	1		T52	3		T7	2
auto[StInit]	107	1			T5	3		T52	2		T43	1
auto[StCreatorRootKey]	64	1			T34	1		T5	2		T53	1
auto[StOwnerIntKey]	42	1			T56	1		T58	1		T28	1
auto[StOwnerKey]	35	1			T47	1		T35	1		T44	1
auto[StDisabled]	475	1			T46	1		T5	13		T6	2
auto[StInvalid]	50	1			T4	1		T48	1		T195	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3473

1

T1

1

T2

1

T3

1

auto[1]

105

1

T56

1

T5

5

T6

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1716	1			T6	1		T52	3		T7	2
auto[StReset]	auto[1]	4	1			T50	1		T30	1		T51	1
auto[StInit]	auto[0]	56	1			T37	1		T61	1		T57	1
auto[StInit]	auto[1]	51	1			T5	3		T52	2		T43	1
auto[StCreatorRootKey]	auto[0]	42	1			T34	1		T53	1		T61	1
auto[StCreatorRootKey]	auto[1]	22	1			T5	2		T6	1		T52	1
auto[StOwnerIntKey]	auto[0]	29	1			T58	1		T28	1		T59	1
auto[StOwnerIntKey]	auto[1]	13	1			T56	1		T60	1		T196	1
auto[StOwnerKey]	auto[0]	29	1			T47	1		T35	1		T61	2
auto[StOwnerKey]	auto[1]	6	1			T44	1		T19	1		T197	1
auto[StDisabled]	auto[0]	466	1			T46	1		T5	13		T6	2
auto[StDisabled]	auto[1]	9	1			T7	1		T61	1		T173	1
auto[StInvalid]	auto[0]	50	1			T4	1		T48	1		T195	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StDisabled]]	[auto[OpGenId]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	3	1			T50	1		T51	1		T198	1
auto[StReset]	auto[OpGenSwOut]	1	1			T30	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	26	1			T5	1		T43	1		T44	2
auto[StInit]	auto[OpGenId]	7	1			T194	1		T199	1		T200	2
auto[StInit]	auto[OpGenSwOut]	7	1			T52	2		T20	1		T201	1
auto[StInit]	auto[OpGenHwOut]	11	1			T5	2		T202	1		T203	1
auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T5	1		T204	1		T205	1
auto[StCreatorRootKey]	auto[OpGenId]	4	1			T5	1		T206	1		T207	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T52	1		T73	1		T117	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	6	1			T6	1		T208	1		T199	1
auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T196	1		T209	1		-	-
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T56	1		T64	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T60	1		T210	1		T211	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	5	1			T212	1		T213	1		T201	1
auto[StOwnerKey]	auto[OpAdvance]	4	1			T44	1		T19	1		T213	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T214	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T197	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	3	1			T168	1		T215	1		T216	1
auto[StDisabled]	auto[OpGenSwOut]	3	1			T61	1		T173	1		T217	1
auto[StDisabled]	auto[OpGenHwOut]	3	1			T7	1		T218	1		T219	1