Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4862

1

T1

8

T2

9

T3

3

auto[1]

619

1

T2

2

T13

6

T32

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4862

1

T1

8

T2

9

T3

3

auto[1]

619

1

T2

2

T13

6

T32

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4907

1

T1

2

T2

11

T3

3

auto[1]

574

1

T1

6

T13

6

T14

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4907

1

T1

2

T2

11

T3

3

auto[1]

574

1

T1

6

T13

6

T14

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	437	1			T1	4		T4	1		T13	3
auto[OpGenId]	1163	1			T1	2		T3	1		T4	2
auto[OpGenSwOut]	1189	1			T3	2		T4	1		T13	1
auto[OpGenHwOut]	2625	1			T1	2		T2	11		T4	3
auto[OpDisable]	67	1			T45	1		T5	1		T6	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	437	1			T1	4		T4	1		T13	3
auto[OpGenId]	1163	1			T1	2		T3	1		T4	2
auto[OpGenSwOut]	1189	1			T3	2		T4	1		T13	1
auto[OpGenHwOut]	2625	1			T1	2		T2	11		T4	3
auto[OpDisable]	67	1			T45	1		T5	1		T6	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4944

1

T1

2

T2

11

T3

3

auto[1]

537

1

T1

6

T15

1

T33

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4944

1

T1

2

T2

11

T3

3

auto[1]

537

1

T1

6

T15

1

T33

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5246

1

T1

2

T2

11

T3

3

auto[1]

235

1

T1

6

T13

5

T110

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1899	1			T1	5		T2	3		T3	2
auto[1]	700	1			T1	3		T2	1		T4	2
auto[2]	671	1			T32	2		T47	1		T130	1
auto[3]	756	1			T2	1		T3	1		T4	2
auto[4]	411	1			T2	1		T4	1		T14	3
auto[5]	347	1			T2	4		T16	1		T33	1
auto[6]	374	1			T2	1		T14	3		T16	1
auto[7]	323	1			T14	1		T32	1		T33	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1455	1			T2	6		T4	1		T14	7
clear_one[1]	700	1			T1	3		T2	1		T4	2
clear_one[2]	671	1			T32	2		T47	1		T130	1
clear_one[3]	756	1			T2	1		T3	1		T4	2
clear_none	1899	1			T1	5		T2	3		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1118	1			T2	3		T3	2		T4	3
auto[StInit]	685	1			T2	1		T13	1		T14	1
auto[StCreatorRootKey]	560	1			T1	1		T2	1		T13	1
auto[StOwnerIntKey]	536	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	474	1			T2	1		T13	1		T14	1
auto[StDisabled]	1840	1			T1	6		T2	4		T13	3
auto[StInvalid]	268	1			T4	4		T36	4		T48	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1118	1			T2	3		T3	2		T4	3
auto[StInit]	685	1			T2	1		T13	1		T14	1
auto[StCreatorRootKey]	560	1			T1	1		T2	1		T13	1
auto[StOwnerIntKey]	536	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	474	1			T2	1		T13	1		T14	1
auto[StDisabled]	1840	1			T1	6		T2	4		T13	3
auto[StInvalid]	268	1			T4	4		T36	4		T48	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	7
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	7
[auto[1] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	28
[auto[1] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	7

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T220	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	173	1			T3	1		T4	2		T15	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	186	1			T3	1		T83	1		T47	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	277	1			T2	2		T13	1		T14	1
auto[0]	auto[StInit]	auto[OpAdvance]	50	1			T56	1		T79	1		T5	2
auto[0]	auto[StInit]	auto[OpGenId]	74	1			T32	1		T33	1		T5	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	100	1			T5	4		T52	1		T110	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	179	1			T16	1		T81	1		T191	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	20	1			T1	1		T52	1		T61	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T103	1		T5	1		T140	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	46	1			T62	1		T72	1		T221	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	64	1			T130	1		T81	1		T191	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	20	1			T1	1		T5	1		T222	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	24	1			T104	1		T52	1		T192	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	33	1			T190	1		T102	1		T71	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	60	1			T5	1		T52	1		T223	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	14	1			T110	1		T224	1		T182	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	16	1			T5	1		T61	2		T196	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T84	1		T5	1		T6	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	52	1			T130	1		T119	1		T7	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	29	1			T33	1		T5	1		T110	1
auto[0]	auto[StDisabled]	auto[OpGenId]	75	1			T1	1		T13	1		T83	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T5	1		T52	2		T110	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T1	2		T2	1		T32	1
auto[0]	auto[StDisabled]	auto[OpDisable]	18	1			T6	1		T52	1		T68	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T49	1		T225	2		T226	1
auto[0]	auto[StInvalid]	auto[OpGenId]	33	1			T49	2		T195	1		T227	2
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	17	1			T228	1		T229	1		T226	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	22	1			T227	1		T230	1		T55	1
auto[1]	auto[StReset]	auto[OpGenId]	27	1			T71	1		T72	1		T231	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	18	1			T44	1		T73	1		T232	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	40	1			T4	1		T52	1		T97	1
auto[1]	auto[StInit]	auto[OpAdvance]	12	1			T5	1		T73	1		T233	1
auto[1]	auto[StInit]	auto[OpGenId]	18	1			T44	1		T71	1		T234	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	5	1			T72	1		T235	1		T78	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T14	1		T5	1		T236	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T61	1		T237	2		T238	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T5	1		T224	1		T204	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T5	1		T239	1		T235	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T14	1		T53	1		T100	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T240	3		T241	1		T242	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T243	1		T244	1		T245	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T243	1		T246	1		T247	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T122	2		T248	1		T177	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T243	1		T63	1		T237	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	14	1			T190	1		T140	1		T7	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T140	1		T249	1		T240	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T33	1		T71	1		T250	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	29	1			T1	2		T103	1		T224	1
auto[1]	auto[StDisabled]	auto[OpGenId]	44	1			T1	1		T6	1		T71	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T5	4		T52	1		T44	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T2	1		T15	1		T5	2
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T5	1		T73	1		T182	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T221	1		T89	1		T251	1
auto[1]	auto[StInvalid]	auto[OpGenId]	7	1			T36	1		T227	1		T55	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T48	2		T195	2		T231	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T4	1		T49	1		T55	1
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T52	1		T124	1		T188	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	21	1			T243	1		T61	1		T71	2
auto[2]	auto[StReset]	auto[OpGenHwOut]	41	1			T80	1		T52	1		T178	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T131	1		T252	1		T220	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T116	1		T196	1		T76	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	12	1			T5	1		T44	1		T75	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	21	1			T22	1		T69	1		T250	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T253	1		T254	1		T213	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T32	1		T243	1		T126	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T52	1		T44	1		T73	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T80	1		T6	1		T119	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T32	1		T7	1		T182	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T47	1		T5	1		T72	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T110	1		T182	1		T255	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	32	1			T191	1		T71	1		T256	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T240	1		T213	1		T257	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	21	1			T22	1		T258	1		T247	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T259	1		T197	1		T260	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T52	1		T192	1		T191	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	27	1			T5	1		T188	1		T140	1
auto[2]	auto[StDisabled]	auto[OpGenId]	51	1			T5	2		T52	2		T192	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T52	2		T140	1		T7	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	145	1			T130	1		T5	1		T80	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T121	1		T261	1		T199	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T262	1		T263	1		T264	1
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T265	1		T266	1		T267	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T227	1		T231	1		T85	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T36	1		T268	1		T267	1
auto[3]	auto[StReset]	auto[OpGenId]	29	1			T52	1		T188	1		T231	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	34	1			T5	1		T52	1		T44	2
auto[3]	auto[StReset]	auto[OpGenHwOut]	54	1			T14	1		T52	1		T57	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T13	1		T134	2		T269	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T117	1		T270	1		T212	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	17	1			T71	1		T271	1		T272	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	29	1			T65	1		T97	1		T193	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T13	1		T273	1		T274	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T5	1		T110	1		T7	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T16	1		T6	1		T23	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T97	1		T23	1		T73	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T13	1		T273	1		T134	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T273	1		T77	1		T197	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T3	1		T52	1		T188	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	32	1			T2	1		T81	1		T6	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T122	1		T223	1		T134	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T52	1		T98	1		T73	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T52	1		T275	1		T276	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T13	1		T180	1		T244	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	19	1			T5	1		T122	1		T102	2
auto[3]	auto[StDisabled]	auto[OpGenId]	55	1			T16	1		T32	1		T104	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	48	1			T13	1		T103	2		T5	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	171	1			T13	1		T104	1		T130	1
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T69	1		T232	1		T277	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T4	1		T278	1		T265	1
auto[3]	auto[StInvalid]	auto[OpGenId]	5	1			T262	1		T279	1		T280	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T4	1		T48	1		T227	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T231	1		T281	1		T282	1
auto[4]	auto[StReset]	auto[OpGenId]	13	1			T43	1		T124	1		T7	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	15	1			T43	1		T61	1		T23	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T15	1		T46	1		T97	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T254	1		T283	1		T284	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T285	1		T78	1		T209	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T24	1		T286	1		T213	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	14	1			T130	1		T61	1		T115	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T197	1		T89	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T7	1		T287	1		T118	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T247	1		T118	1		T288	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T2	1		T61	1		T71	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T289	1		T182	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T5	1		T290	1		T291	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T69	1		T118	1		T292	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T14	1		T119	1		T69	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T293	1		T212	1		T208	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	10	1			T7	1		T115	1		T196	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T5	1		T294	1		T208	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T14	1		T5	1		T295	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	14	1			T7	1		T273	1		T237	1
auto[4]	auto[StDisabled]	auto[OpGenId]	32	1			T7	2		T61	1		T296	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T52	1		T187	1		T44	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	110	1			T14	1		T83	1		T81	2
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T196	1		T297	1		T298	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T278	1		T299	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T36	1		T278	1		T282	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T231	1		T300	1		T262	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T4	1		T301	1		T89	1
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T53	1		T115	1		T269	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T302	1		T92	1		T303	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	26	1			T2	1		T48	1		T188	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T304	1		T208	1		T305	1
auto[5]	auto[StInit]	auto[OpGenId]	2	1			T46	1		T233	1		-	-
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T73	1		T287	1		T306	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T45	1		T224	1		T307	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T308	2		T216	1		T200	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T7	1		T44	1		T73	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T244	1		T294	1		T64	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T256	1		T309	1		T310	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T57	1		T254	1		T201	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T33	1		T80	1		T125	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T311	1		T312	1		T252	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T313	1		T314	1		T315	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T316	1		T317	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	12	1			T189	1		T71	1		T254	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T318	1		T290	1		T319	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T2	1		T193	1		T177	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T320	1		T321	1		T212	2
auto[5]	auto[StDisabled]	auto[OpGenId]	34	1			T16	1		T52	1		T224	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T84	1		T5	1		T259	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T2	2		T97	1		T193	2
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T45	1		T62	1		T322	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T226	1		T323	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T324	1		T325	1		T326	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T48	1		T266	1		T263	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T36	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	6	1			T281	1		T208	1		T210	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T205	1		T327	1		T274	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	33	1			T14	1		T45	1		T52	1
auto[6]	auto[StInit]	auto[OpAdvance]	6	1			T328	1		T329	1		T321	1
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T6	1		T330	1		T233	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T69	1		T212	1		T331	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T2	1		T22	1		T332	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T329	1		T333	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T71	1		T334	1		T298	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T249	1		T196	1		T335	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T56	1		T189	1		T248	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T140	1		T72	1		T209	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T23	1		T329	1		T336	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T44	1		T61	1		T182	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T130	1		T7	1		T337	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T243	1		T72	1		T118	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T32	1		T72	1		T338	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T73	1		T196	1		T183	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T126	1		T178	1		T315	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T224	1		T328	2		T304	1
auto[6]	auto[StDisabled]	auto[OpGenId]	23	1			T243	1		T296	1		T73	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T16	1		T140	1		T7	2
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T14	2		T130	1		T52	1
auto[6]	auto[StDisabled]	auto[OpDisable]	7	1			T7	1		T179	1		T183	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T339	1		T340	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	8	1			T227	1		T278	1		T265	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T266	1		T341	1		T339	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T195	1		T281	1		T85	1
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T6	1		T69	1		T342	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T343	1		T182	2		T125	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T344	1		T231	1		T256	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T345	1		T209	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T346	1		T197	1		T347	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T183	1		T348	1		T349	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	15	1			T177	1		T350	1		T309	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T83	1		T7	1		T351	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T69	1		T352	1		T353	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T354	1		T116	1		T318	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T52	1		T355	1		T196	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T61	1		T100	1		T356	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T61	1		T334	1		T78	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T287	1		T125	1		T357	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T180	1		T332	1		T355	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T358	1		T359	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	10	1			T187	1		T69	1		T183	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T360	1		T361	1		T362	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T81	1		T97	1		T363	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T7	1		T289	1		T239	1
auto[7]	auto[StDisabled]	auto[OpGenId]	29	1			T33	1		T188	1		T7	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	18	1			T83	1		T44	1		T182	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	66	1			T14	1		T32	1		T52	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T270	1		T336	1		T364	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	7	1			T225	1		T365	1		T266	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T55	1		T85	2		T89	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T230	1		T300	1		T366	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T282	1		T367	1		T263	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1455

1

T2

6

T4

1

T14

7

clear_one[1]

auto[0]

auto[0]

auto[0]

406

1

T2

1

T4

2

T14

1

clear_one[1]

auto[0]

auto[0]

auto[1]

113

1

T5

1

T190

1

T44

1

clear_one[1]

auto[0]

auto[1]

auto[0]

134

1

T14

1

T103

1

T5

2

clear_one[1]

auto[0]

auto[1]

auto[1]

47

1

T1

3

T15

1

T33

1

clear_one[2]

auto[0]

auto[0]

auto[0]

386

1

T130

1

T5

5

T80

1

clear_one[2]

auto[0]

auto[0]

auto[1]

108

1

T80

1

T7

2

T44

1

clear_one[2]

auto[1]

auto[0]

auto[0]

132

1

T32

2

T47

1

T80

1

clear_one[2]

auto[1]

auto[0]

auto[1]

45

1

T5

1

T52

2

T192

1

clear_one[3]

auto[0]

auto[0]

auto[0]

447

1

T3

1

T4

2

T13

1

clear_one[3]

auto[0]

auto[1]

auto[0]

129

1

T103

2

T130

1

T52

2

clear_one[3]

auto[1]

auto[0]

auto[0]

127

1

T2

1

T104

2

T119

1

clear_one[3]

auto[1]

auto[1]

auto[0]

53

1

T13

5

T5

2

T80

1

clear_none

auto[0]

auto[0]

auto[0]

1369

1

T1

2

T2

2

T3

2

clear_none

auto[0]

auto[0]

auto[1]

127

1

T5

2

T81

3

T6

1

clear_none

auto[0]

auto[1]

auto[0]

108

1

T130

3

T5

1

T122

1

clear_none

auto[0]

auto[1]

auto[1]

33

1

T1

3

T33

1

T6

1

clear_none

auto[1]

auto[0]

auto[0]

162

1

T2

1

T104

1

T5

1

clear_none

auto[1]

auto[0]

auto[1]

30

1

T5

1

T102

1

T69

1

clear_none

auto[1]

auto[1]

auto[0]

36

1

T13

1

T32

1

T46

1

clear_none

auto[1]

auto[1]

auto[1]

34

1

T5

1

T52

1

T123

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1405	1			T2	6		T4	1		T14	7
clear_all	auto[1]	50	1			T243	1		T328	4		T308	2
clear_one[1]	auto[0]	652	1			T1	1		T2	1		T4	2
clear_one[1]	auto[1]	48	1			T1	2		T122	1		T140	1
clear_one[2]	auto[0]	639	1			T32	2		T47	1		T130	1
clear_one[2]	auto[1]	32	1			T110	1		T140	2		T131	1
clear_one[3]	auto[0]	717	1			T2	1		T3	1		T4	2
clear_one[3]	auto[1]	39	1			T13	5		T122	3		T102	3
clear_none	auto[0]	1833	1			T1	1		T2	3		T3	2
clear_none	auto[1]	66	1			T1	4		T110	2		T140	1