Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11444

1

T1

8

T2

11

T3

23

auto[Attestation]

8210

1

T1

12

T2

4

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2853	1			T1	2		T3	3		T4	4
auto[Aes]	3635	1			T1	2		T2	15		T3	3
auto[Kmac]	3453	1			T1	8		T3	4		T4	5
auto[Otbn]	3610	1			T1	2		T3	7		T4	6

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7872	1			T1	8		T2	8		T3	4
auto[OpGenId]	6103	1			T1	6		T3	12		T4	9
auto[OpGenSwOut]	6240	1			T1	7		T3	7		T4	6
auto[OpGenHwOut]	7311	1			T1	7		T2	15		T3	10
auto[OpDisable]	134	1			T45	1		T5	3		T6	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10848

1

T1

13

T2

8

T3

15

auto[OpDoneFail]

16812

1

T1

15

T2

15

T3

18

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6817	1			T1	1		T2	8		T3	15
auto[StInit]	3957	1			T1	4		T2	2		T3	5
auto[StCreatorRootKey]	3278	1			T1	3		T2	2		T3	3
auto[StOwnerIntKey]	2771	1			T1	4		T2	2		T3	4
auto[StOwnerKey]	2594	1			T1	4		T2	2		T3	6
auto[StDisabled]	8243	1			T1	12		T2	7		T13	8

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	324	1			T3	1		T4	1		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	127	1			T5	3		T6	2		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	93	1			T5	4		T80	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	65	1			T5	1		T82	1		T187	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T5	5		T82	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	196	1			T13	1		T5	2		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	347	1			T3	2		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T1	1		T15	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	62	1			T16	1		T32	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	77	1			T3	1		T15	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	66	1			T83	1		T104	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	226	1			T15	1		T84	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	350	1			T3	1		T4	2		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	104	1			T13	1		T16	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T13	1		T79	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T33	1		T52	1		T65	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	69	1			T83	1		T52	2		T188	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	216	1			T33	1		T103	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	346	1			T3	1		T4	2		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	118	1			T1	1		T5	2		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T84	1		T5	2		T52	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	76	1			T5	2		T110	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	64	1			T103	1		T5	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	255	1			T15	1		T84	1		T5	8
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	101	1			T5	1		T52	4		T7	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	116	1			T13	1		T15	2		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T34	1		T5	1		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T16	1		T7	2		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	72	1			T84	1		T5	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	220	1			T83	1		T5	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	91	1			T5	1		T52	4		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	111	1			T1	1		T84	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	89	1			T33	1		T45	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	83	1			T52	1		T7	1		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	64	1			T5	1		T122	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	243	1			T104	1		T46	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	105	1			T5	2		T52	4		T7	7
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	104	1			T5	1		T65	1		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T1	1		T79	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T1	2		T6	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	53	1			T5	1		T52	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	221	1			T1	1		T83	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	93	1			T7	5		T44	2		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T3	1		T103	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T5	1		T23	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T33	1		T52	2		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	72	1			T16	1		T83	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	208	1			T15	1		T16	1		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	260	1			T4	3		T15	3		T46	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T104	1		T46	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T1	1		T56	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T33	1		T103	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	53	1			T16	2		T104	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	188	1			T1	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	545	1			T2	7		T13	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	133	1			T2	1		T15	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	102	1			T32	1		T104	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	87	1			T2	1		T5	2		T191	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	87	1			T83	1		T46	3		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	272	1			T2	2		T83	1		T104	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	481	1			T3	2		T4	2		T14	6
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T14	1		T16	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T14	1		T16	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T14	1		T130	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	97	1			T1	1		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	281	1			T14	2		T32	2		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	487	1			T3	1		T4	4		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	130	1			T81	1		T6	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	119	1			T13	1		T5	4		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T5	1		T6	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	93	1			T3	3		T13	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	298	1			T13	1		T32	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	67	1			T52	4		T7	7		T44	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	98	1			T83	1		T5	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T16	1		T47	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	51	1			T3	1		T16	2		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	71	1			T3	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	221	1			T32	1		T84	3		T103	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	71	1			T5	2		T52	3		T44	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	125	1			T34	1		T5	3		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	137	1			T2	1		T13	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T16	1		T52	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	114	1			T2	1		T103	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	304	1			T2	2		T32	2		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	67	1			T52	4		T44	2		T71	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	113	1			T4	1		T104	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T13	1		T130	1		T79	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	103	1			T35	1		T57	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	92	1			T1	1		T33	1		T5	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	278	1			T1	2		T14	2		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	76	1			T5	1		T52	5		T7	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T32	1		T5	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T45	1		T79	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T5	1		T81	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T1	1		T3	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	315	1			T15	1		T16	2		T103	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	196	1			T5	10		T80	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	670	1			T3	1		T4	1		T13	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	189	1			T3	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	698	1			T1	1		T3	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	207	1			T13	1		T33	1		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	690	1			T3	1		T4	2		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	221	1			T84	1		T5	5		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	743	1			T1	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	208	1			T16	1		T84	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	453	1			T13	1		T15	2		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	217	1			T33	1		T45	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	464	1			T1	1		T84	1		T104	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	184	1			T1	3		T79	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	449	1			T1	1		T83	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	214	1			T16	1		T33	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	437	1			T3	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	170	1			T1	1		T16	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	574	1			T1	1		T4	3		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	265	1			T2	1		T32	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	961	1			T2	10		T13	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T1	1		T3	1		T14	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	902	1			T3	2		T4	2		T14	9
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	278	1			T3	3		T13	2		T5	6
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	928	1			T3	1		T4	4		T13	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	174	1			T3	2		T13	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	408	1			T16	2		T32	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	316	1			T2	2		T13	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	525	1			T2	2		T16	1		T32	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	278	1			T1	1		T13	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	475	1			T1	2		T4	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	263	1			T1	1		T3	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	526	1			T15	1		T16	2		T32	1