Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33736

1

T1

31

T2

27

T3

33

auto[1]

263

1

T1

5

T13

6

T122

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33747	1			T1	31		T2	27		T3	33
auto[134217728:268435455]	11	1			T140	1		T131	1		T134	1
auto[268435456:402653183]	11	1			T13	1		T243	1		T240	2
auto[402653184:536870911]	5	1			T302	1		T362	1		T390	1
auto[536870912:671088639]	9	1			T1	1		T140	1		T391	2
auto[671088640:805306367]	3	1			T243	1		T392	1		T393	1
auto[805306368:939524095]	10	1			T122	1		T140	1		T243	1
auto[939524096:1073741823]	10	1			T243	1		T273	1		T134	1
auto[1073741824:1207959551]	16	1			T140	1		T243	1		T132	1
auto[1207959552:1342177279]	11	1			T1	1		T240	1		T391	1
auto[1342177280:1476395007]	4	1			T237	1		T394	1		T390	1
auto[1476395008:1610612735]	6	1			T122	1		T140	1		T391	1
auto[1610612736:1744830463]	6	1			T134	1		T391	2		T395	1
auto[1744830464:1879048191]	4	1			T102	1		T362	1		T220	1
auto[1879048192:2013265919]	7	1			T13	1		T308	1		T396	1
auto[2013265920:2147483647]	7	1			T134	1		T328	1		T308	2
auto[2147483648:2281701375]	7	1			T1	1		T122	1		T237	1
auto[2281701376:2415919103]	3	1			T133	1		T396	1		T393	1
auto[2415919104:2550136831]	10	1			T13	1		T273	2		T134	1
auto[2550136832:2684354559]	9	1			T328	2		T391	1		T275	1
auto[2684354560:2818572287]	5	1			T102	1		T133	1		T391	1
auto[2818572288:2952790015]	13	1			T1	1		T240	2		T328	1
auto[2952790016:3087007743]	10	1			T140	1		T394	1		T319	2
auto[3087007744:3221225471]	15	1			T122	1		T102	1		T328	1
auto[3221225472:3355443199]	4	1			T134	1		T274	1		T362	1
auto[3355443200:3489660927]	8	1			T13	1		T131	1		T358	1
auto[3489660928:3623878655]	9	1			T328	1		T391	1		T292	1
auto[3623878656:3758096383]	9	1			T1	1		T391	1		T275	1
auto[3758096384:3892314111]	3	1			T240	1		T275	1		T397	1
auto[3892314112:4026531839]	7	1			T122	1		T302	1		T242	1
auto[4026531840:4160749567]	9	1			T13	1		T243	1		T240	1
auto[4160749568:4294967295]	11	1			T13	1		T131	1		T273	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33736	1			T1	31		T2	27		T3	33
auto[0:134217727]	auto[1]	11	1			T243	1		T133	1		T134	1
auto[134217728:268435455]	auto[1]	11	1			T140	1		T131	1		T134	1
auto[268435456:402653183]	auto[1]	11	1			T13	1		T243	1		T240	2
auto[402653184:536870911]	auto[1]	5	1			T302	1		T362	1		T390	1
auto[536870912:671088639]	auto[1]	9	1			T1	1		T140	1		T391	2
auto[671088640:805306367]	auto[1]	3	1			T243	1		T392	1		T393	1
auto[805306368:939524095]	auto[1]	10	1			T122	1		T140	1		T243	1
auto[939524096:1073741823]	auto[1]	10	1			T243	1		T273	1		T134	1
auto[1073741824:1207959551]	auto[1]	16	1			T140	1		T243	1		T132	1
auto[1207959552:1342177279]	auto[1]	11	1			T1	1		T240	1		T391	1
auto[1342177280:1476395007]	auto[1]	4	1			T237	1		T394	1		T390	1
auto[1476395008:1610612735]	auto[1]	6	1			T122	1		T140	1		T391	1
auto[1610612736:1744830463]	auto[1]	6	1			T134	1		T391	2		T395	1
auto[1744830464:1879048191]	auto[1]	4	1			T102	1		T362	1		T220	1
auto[1879048192:2013265919]	auto[1]	7	1			T13	1		T308	1		T396	1
auto[2013265920:2147483647]	auto[1]	7	1			T134	1		T328	1		T308	2
auto[2147483648:2281701375]	auto[1]	7	1			T1	1		T122	1		T237	1
auto[2281701376:2415919103]	auto[1]	3	1			T133	1		T396	1		T393	1
auto[2415919104:2550136831]	auto[1]	10	1			T13	1		T273	2		T134	1
auto[2550136832:2684354559]	auto[1]	9	1			T328	2		T391	1		T275	1
auto[2684354560:2818572287]	auto[1]	5	1			T102	1		T133	1		T391	1
auto[2818572288:2952790015]	auto[1]	13	1			T1	1		T240	2		T328	1
auto[2952790016:3087007743]	auto[1]	10	1			T140	1		T394	1		T319	2
auto[3087007744:3221225471]	auto[1]	15	1			T122	1		T102	1		T328	1
auto[3221225472:3355443199]	auto[1]	4	1			T134	1		T274	1		T362	1
auto[3355443200:3489660927]	auto[1]	8	1			T13	1		T131	1		T358	1
auto[3489660928:3623878655]	auto[1]	9	1			T328	1		T391	1		T292	1
auto[3623878656:3758096383]	auto[1]	9	1			T1	1		T391	1		T275	1
auto[3758096384:3892314111]	auto[1]	3	1			T240	1		T275	1		T397	1
auto[3892314112:4026531839]	auto[1]	7	1			T122	1		T302	1		T242	1
auto[4026531840:4160749567]	auto[1]	9	1			T13	1		T243	1		T240	1
auto[4160749568:4294967295]	auto[1]	11	1			T13	1		T131	1		T273	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1699

1

T3

1

T4

3

T13

3

auto[1]

1874

1

T1

5

T3

2

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T1	1		T3	1		T45	1
auto[134217728:268435455]	126	1			T16	1		T84	1		T104	1
auto[268435456:402653183]	112	1			T83	1		T46	1		T5	2
auto[402653184:536870911]	99	1			T4	1		T13	1		T5	1
auto[536870912:671088639]	103	1			T3	1		T13	1		T16	1
auto[671088640:805306367]	101	1			T13	1		T33	1		T5	3
auto[805306368:939524095]	111	1			T83	1		T46	1		T5	4
auto[939524096:1073741823]	130	1			T3	1		T46	2		T47	1
auto[1073741824:1207959551]	115	1			T15	1		T5	2		T6	3
auto[1207959552:1342177279]	111	1			T5	3		T53	1		T6	1
auto[1342177280:1476395007]	122	1			T13	1		T16	1		T33	1
auto[1476395008:1610612735]	124	1			T83	1		T104	1		T5	4
auto[1610612736:1744830463]	138	1			T47	1		T45	1		T5	3
auto[1744830464:1879048191]	111	1			T5	1		T6	1		T52	2
auto[1879048192:2013265919]	96	1			T13	1		T5	1		T36	2
auto[2013265920:2147483647]	106	1			T84	2		T103	1		T104	1
auto[2147483648:2281701375]	112	1			T104	1		T45	1		T5	1
auto[2281701376:2415919103]	102	1			T47	1		T5	3		T80	1
auto[2415919104:2550136831]	111	1			T84	1		T47	1		T5	2
auto[2550136832:2684354559]	127	1			T13	1		T15	1		T16	1
auto[2684354560:2818572287]	125	1			T4	1		T13	1		T16	1
auto[2818572288:2952790015]	112	1			T32	1		T83	1		T43	2
auto[2952790016:3087007743]	96	1			T15	1		T32	1		T5	2
auto[3087007744:3221225471]	115	1			T5	2		T6	1		T52	3
auto[3221225472:3355443199]	123	1			T1	1		T15	1		T83	1
auto[3355443200:3489660927]	106	1			T1	1		T4	1		T103	1
auto[3489660928:3623878655]	114	1			T33	1		T5	1		T110	1
auto[3623878656:3758096383]	100	1			T47	1		T5	2		T52	3
auto[3758096384:3892314111]	101	1			T5	3		T6	1		T52	1
auto[3892314112:4026531839]	99	1			T4	1		T46	1		T5	5
auto[4026531840:4160749567]	117	1			T1	2		T83	1		T46	1
auto[4160749568:4294967295]	100	1			T46	1		T47	1		T45	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T5	1		T52	2		T195	1
auto[0:134217727]	auto[1]	49	1			T1	1		T3	1		T45	1
auto[134217728:268435455]	auto[0]	63	1			T16	1		T5	2		T48	1
auto[134217728:268435455]	auto[1]	63	1			T84	1		T104	1		T56	1
auto[268435456:402653183]	auto[0]	61	1			T83	1		T5	2		T52	1
auto[268435456:402653183]	auto[1]	51	1			T46	1		T48	1		T122	1
auto[402653184:536870911]	auto[0]	53	1			T4	1		T13	1		T5	1
auto[402653184:536870911]	auto[1]	46	1			T6	1		T43	1		T190	1
auto[536870912:671088639]	auto[0]	52	1			T5	2		T44	2		T99	1
auto[536870912:671088639]	auto[1]	51	1			T3	1		T13	1		T16	1
auto[671088640:805306367]	auto[0]	54	1			T13	1		T5	2		T52	2
auto[671088640:805306367]	auto[1]	47	1			T33	1		T5	1		T53	1
auto[805306368:939524095]	auto[0]	56	1			T83	1		T5	3		T53	1
auto[805306368:939524095]	auto[1]	55	1			T46	1		T5	1		T6	2
auto[939524096:1073741823]	auto[0]	62	1			T3	1		T5	1		T80	1
auto[939524096:1073741823]	auto[1]	68	1			T46	2		T47	1		T80	1
auto[1073741824:1207959551]	auto[0]	61	1			T15	1		T5	1		T6	1
auto[1073741824:1207959551]	auto[1]	54	1			T5	1		T6	2		T140	1
auto[1207959552:1342177279]	auto[0]	61	1			T5	1		T53	1		T122	1
auto[1207959552:1342177279]	auto[1]	50	1			T5	2		T6	1		T52	1
auto[1342177280:1476395007]	auto[0]	58	1			T5	1		T53	1		T6	1
auto[1342177280:1476395007]	auto[1]	64	1			T13	1		T16	1		T33	1
auto[1476395008:1610612735]	auto[0]	59	1			T104	1		T5	3		T52	1
auto[1476395008:1610612735]	auto[1]	65	1			T83	1		T5	1		T52	1
auto[1610612736:1744830463]	auto[0]	74	1			T47	1		T45	1		T52	3
auto[1610612736:1744830463]	auto[1]	64	1			T5	3		T6	1		T52	2
auto[1744830464:1879048191]	auto[0]	41	1			T52	1		T190	1		T44	1
auto[1744830464:1879048191]	auto[1]	70	1			T5	1		T6	1		T52	1
auto[1879048192:2013265919]	auto[0]	40	1			T5	1		T36	1		T7	1
auto[1879048192:2013265919]	auto[1]	56	1			T13	1		T36	1		T48	1
auto[2013265920:2147483647]	auto[0]	49	1			T84	1		T5	1		T36	1
auto[2013265920:2147483647]	auto[1]	57	1			T84	1		T103	1		T104	1
auto[2147483648:2281701375]	auto[0]	48	1			T104	1		T5	1		T7	3
auto[2147483648:2281701375]	auto[1]	64	1			T45	1		T120	1		T124	1
auto[2281701376:2415919103]	auto[0]	46	1			T47	1		T5	2		T52	2
auto[2281701376:2415919103]	auto[1]	56	1			T5	1		T80	1		T52	2
auto[2415919104:2550136831]	auto[0]	49	1			T47	1		T5	1		T43	1
auto[2415919104:2550136831]	auto[1]	62	1			T84	1		T5	1		T6	1
auto[2550136832:2684354559]	auto[0]	62	1			T13	1		T16	1		T58	1
auto[2550136832:2684354559]	auto[1]	65	1			T15	1		T46	1		T52	1
auto[2684354560:2818572287]	auto[0]	61	1			T52	1		T7	1		T57	1
auto[2684354560:2818572287]	auto[1]	64	1			T4	1		T13	1		T16	1
auto[2818572288:2952790015]	auto[0]	41	1			T83	1		T43	1		T7	1
auto[2818572288:2952790015]	auto[1]	71	1			T32	1		T43	1		T7	1
auto[2952790016:3087007743]	auto[0]	42	1			T15	1		T7	1		T49	1
auto[2952790016:3087007743]	auto[1]	54	1			T32	1		T5	2		T52	2
auto[3087007744:3221225471]	auto[0]	64	1			T5	2		T52	3		T36	1
auto[3087007744:3221225471]	auto[1]	51	1			T6	1		T122	1		T7	1
auto[3221225472:3355443199]	auto[0]	53	1			T83	1		T47	1		T48	1
auto[3221225472:3355443199]	auto[1]	70	1			T1	1		T15	1		T5	1
auto[3355443200:3489660927]	auto[0]	43	1			T4	1		T53	1		T7	3
auto[3355443200:3489660927]	auto[1]	63	1			T1	1		T103	1		T104	1
auto[3489660928:3623878655]	auto[0]	49	1			T202	1		T38	1		T59	1
auto[3489660928:3623878655]	auto[1]	65	1			T33	1		T5	1		T110	1
auto[3623878656:3758096383]	auto[0]	51	1			T47	1		T5	1		T52	1
auto[3623878656:3758096383]	auto[1]	49	1			T5	1		T52	2		T120	1
auto[3758096384:3892314111]	auto[0]	49	1			T5	2		T52	1		T7	1
auto[3758096384:3892314111]	auto[1]	52	1			T5	1		T6	1		T7	2
auto[3892314112:4026531839]	auto[0]	42	1			T4	1		T398	1		T227	1
auto[3892314112:4026531839]	auto[1]	57	1			T46	1		T5	5		T80	1
auto[4026531840:4160749567]	auto[0]	59	1			T83	1		T46	1		T5	1
auto[4026531840:4160749567]	auto[1]	58	1			T1	2		T56	1		T52	1
auto[4160749568:4294967295]	auto[0]	37	1			T45	1		T52	1		T61	2
auto[4160749568:4294967295]	auto[1]	63	1			T46	1		T47	1		T5	3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1740

1

T3

1

T4

2

T13

3

auto[1]

1833

1

T1

5

T3

2

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T15	1		T33	1		T83	1
auto[134217728:268435455]	118	1			T1	1		T13	1		T84	1
auto[268435456:402653183]	109	1			T33	1		T103	1		T104	1
auto[402653184:536870911]	107	1			T13	1		T5	2		T53	1
auto[536870912:671088639]	111	1			T4	1		T16	1		T47	1
auto[671088640:805306367]	116	1			T3	1		T4	1		T83	1
auto[805306368:939524095]	124	1			T32	1		T46	1		T5	5
auto[939524096:1073741823]	116	1			T79	1		T5	1		T52	4
auto[1073741824:1207959551]	117	1			T15	1		T80	1		T52	1
auto[1207959552:1342177279]	107	1			T83	1		T84	1		T103	1
auto[1342177280:1476395007]	93	1			T1	1		T16	1		T104	1
auto[1476395008:1610612735]	117	1			T15	1		T46	1		T47	1
auto[1610612736:1744830463]	104	1			T1	1		T13	1		T52	2
auto[1744830464:1879048191]	105	1			T13	2		T15	1		T84	1
auto[1879048192:2013265919]	103	1			T47	1		T5	3		T6	1
auto[2013265920:2147483647]	112	1			T3	1		T4	1		T5	5
auto[2147483648:2281701375]	114	1			T32	1		T45	1		T5	2
auto[2281701376:2415919103]	123	1			T4	1		T16	1		T84	1
auto[2415919104:2550136831]	106	1			T103	1		T5	2		T53	1
auto[2550136832:2684354559]	122	1			T46	2		T5	1		T53	1
auto[2684354560:2818572287]	96	1			T16	1		T46	1		T5	1
auto[2818572288:2952790015]	124	1			T3	1		T56	1		T5	2
auto[2952790016:3087007743]	131	1			T13	1		T48	1		T122	1
auto[3087007744:3221225471]	115	1			T33	1		T46	1		T47	2
auto[3221225472:3355443199]	115	1			T1	1		T83	1		T124	1
auto[3355443200:3489660927]	96	1			T45	1		T5	2		T65	1
auto[3489660928:3623878655]	114	1			T16	1		T47	1		T56	1
auto[3623878656:3758096383]	111	1			T5	3		T52	3		T43	1
auto[3758096384:3892314111]	110	1			T83	1		T5	2		T124	1
auto[3892314112:4026531839]	127	1			T13	1		T104	1		T46	1
auto[4026531840:4160749567]	93	1			T1	1		T83	1		T47	1
auto[4160749568:4294967295]	108	1			T104	1		T47	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T15	1		T83	1		T104	1
auto[0:134217727]	auto[1]	51	1			T33	1		T47	1		T5	1
auto[134217728:268435455]	auto[0]	58	1			T52	1		T48	1		T243	1
auto[134217728:268435455]	auto[1]	60	1			T1	1		T13	1		T84	1
auto[268435456:402653183]	auto[0]	52	1			T104	1		T52	1		T192	1
auto[268435456:402653183]	auto[1]	57	1			T33	1		T103	1		T192	1
auto[402653184:536870911]	auto[0]	47	1			T53	1		T43	1		T7	3
auto[402653184:536870911]	auto[1]	60	1			T13	1		T5	2		T6	1
auto[536870912:671088639]	auto[0]	51	1			T4	1		T47	1		T43	1
auto[536870912:671088639]	auto[1]	60	1			T16	1		T5	1		T53	1
auto[671088640:805306367]	auto[0]	61	1			T3	1		T4	1		T83	1
auto[671088640:805306367]	auto[1]	55	1			T45	1		T5	3		T6	1
auto[805306368:939524095]	auto[0]	50	1			T5	1		T230	1		T342	1
auto[805306368:939524095]	auto[1]	74	1			T32	1		T46	1		T5	4
auto[939524096:1073741823]	auto[0]	49	1			T79	1		T52	1		T7	1
auto[939524096:1073741823]	auto[1]	67	1			T5	1		T52	3		T7	5
auto[1073741824:1207959551]	auto[0]	65	1			T15	1		T80	1		T52	1
auto[1073741824:1207959551]	auto[1]	52	1			T48	1		T120	1		T7	2
auto[1207959552:1342177279]	auto[0]	58	1			T83	1		T84	1		T5	1
auto[1207959552:1342177279]	auto[1]	49	1			T103	1		T52	1		T7	1
auto[1342177280:1476395007]	auto[0]	50	1			T16	1		T5	1		T52	1
auto[1342177280:1476395007]	auto[1]	43	1			T1	1		T104	1		T80	1
auto[1476395008:1610612735]	auto[0]	54	1			T5	1		T243	1		T61	1
auto[1476395008:1610612735]	auto[1]	63	1			T15	1		T46	1		T47	1
auto[1610612736:1744830463]	auto[0]	48	1			T52	1		T43	1		T7	2
auto[1610612736:1744830463]	auto[1]	56	1			T1	1		T13	1		T52	1
auto[1744830464:1879048191]	auto[0]	47	1			T13	2		T15	1		T5	1
auto[1744830464:1879048191]	auto[1]	58	1			T84	1		T52	2		T120	1
auto[1879048192:2013265919]	auto[0]	44	1			T47	1		T5	1		T227	1
auto[1879048192:2013265919]	auto[1]	59	1			T5	2		T6	1		T36	1
auto[2013265920:2147483647]	auto[0]	55	1			T5	3		T36	1		T122	1
auto[2013265920:2147483647]	auto[1]	57	1			T3	1		T4	1		T5	2
auto[2147483648:2281701375]	auto[0]	60	1			T45	1		T5	2		T44	1
auto[2147483648:2281701375]	auto[1]	54	1			T32	1		T110	1		T190	1
auto[2281701376:2415919103]	auto[0]	60	1			T84	1		T5	2		T80	1
auto[2281701376:2415919103]	auto[1]	63	1			T4	1		T16	1		T46	1
auto[2415919104:2550136831]	auto[0]	50	1			T53	1		T52	1		T122	1
auto[2415919104:2550136831]	auto[1]	56	1			T103	1		T5	2		T52	2
auto[2550136832:2684354559]	auto[0]	59	1			T53	1		T6	1		T243	1
auto[2550136832:2684354559]	auto[1]	63	1			T46	2		T5	1		T121	1
auto[2684354560:2818572287]	auto[0]	44	1			T46	1		T5	1		T52	2
auto[2684354560:2818572287]	auto[1]	52	1			T16	1		T6	1		T224	1
auto[2818572288:2952790015]	auto[0]	59	1			T6	1		T52	1		T7	3
auto[2818572288:2952790015]	auto[1]	65	1			T3	1		T56	1		T5	2
auto[2952790016:3087007743]	auto[0]	60	1			T7	1		T223	1		T102	1
auto[2952790016:3087007743]	auto[1]	71	1			T13	1		T48	1		T122	1
auto[3087007744:3221225471]	auto[0]	65	1			T33	1		T46	1		T47	2
auto[3087007744:3221225471]	auto[1]	50	1			T5	1		T80	1		T52	1
auto[3221225472:3355443199]	auto[0]	57	1			T83	1		T7	1		T61	4
auto[3221225472:3355443199]	auto[1]	58	1			T1	1		T124	1		T398	1
auto[3355443200:3489660927]	auto[0]	58	1			T45	1		T5	2		T7	1
auto[3355443200:3489660927]	auto[1]	38	1			T65	1		T120	1		T124	1
auto[3489660928:3623878655]	auto[0]	44	1			T16	1		T5	2		T43	1
auto[3489660928:3623878655]	auto[1]	70	1			T47	1		T56	1		T45	1
auto[3623878656:3758096383]	auto[0]	59	1			T5	3		T52	2		T65	1
auto[3623878656:3758096383]	auto[1]	52	1			T52	1		T43	1		T61	1
auto[3758096384:3892314111]	auto[0]	47	1			T83	1		T44	1		T69	1
auto[3758096384:3892314111]	auto[1]	63	1			T5	2		T124	1		T61	1
auto[3892314112:4026531839]	auto[0]	67	1			T13	1		T46	1		T5	2
auto[3892314112:4026531839]	auto[1]	60	1			T104	1		T5	2		T6	1
auto[4026531840:4160749567]	auto[0]	44	1			T83	1		T47	1		T5	3
auto[4026531840:4160749567]	auto[1]	49	1			T1	1		T5	1		T6	1
auto[4160749568:4294967295]	auto[0]	60	1			T47	1		T53	1		T44	3
auto[4160749568:4294967295]	auto[1]	48	1			T104	1		T5	1		T48	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1738

1

T3

1

T4

3

T13

3

auto[1]

1834

1

T1

5

T3

2

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T5	2		T43	2		T192	1
auto[134217728:268435455]	117	1			T1	1		T5	1		T6	1
auto[268435456:402653183]	104	1			T13	1		T104	1		T46	1
auto[402653184:536870911]	104	1			T13	1		T83	1		T104	1
auto[536870912:671088639]	114	1			T104	1		T47	1		T5	5
auto[671088640:805306367]	116	1			T15	1		T16	1		T103	1
auto[805306368:939524095]	132	1			T32	1		T83	1		T5	5
auto[939524096:1073741823]	124	1			T46	1		T5	2		T80	1
auto[1073741824:1207959551]	99	1			T16	1		T47	1		T5	2
auto[1207959552:1342177279]	112	1			T33	1		T84	1		T5	3
auto[1342177280:1476395007]	102	1			T15	1		T6	1		T52	1
auto[1476395008:1610612735]	119	1			T3	1		T33	1		T104	1
auto[1610612736:1744830463]	100	1			T16	1		T84	1		T46	2
auto[1744830464:1879048191]	116	1			T1	1		T4	1		T83	2
auto[1879048192:2013265919]	108	1			T53	1		T52	1		T122	1
auto[2013265920:2147483647]	115	1			T5	1		T6	1		T110	1
auto[2147483648:2281701375]	129	1			T13	1		T15	1		T16	1
auto[2281701376:2415919103]	117	1			T1	1		T13	1		T104	1
auto[2415919104:2550136831]	111	1			T46	1		T80	1		T52	3
auto[2550136832:2684354559]	105	1			T3	1		T5	2		T52	2
auto[2684354560:2818572287]	102	1			T4	1		T13	1		T84	1
auto[2818572288:2952790015]	121	1			T13	1		T32	1		T5	4
auto[2952790016:3087007743]	108	1			T47	1		T5	2		T52	2
auto[3087007744:3221225471]	118	1			T3	1		T16	1		T83	1
auto[3221225472:3355443199]	104	1			T46	1		T45	1		T5	2
auto[3355443200:3489660927]	104	1			T15	1		T5	3		T52	1
auto[3489660928:3623878655]	113	1			T33	1		T47	1		T45	1
auto[3623878656:3758096383]	128	1			T1	1		T13	1		T5	1
auto[3758096384:3892314111]	102	1			T4	1		T47	2		T5	2
auto[3892314112:4026531839]	114	1			T4	1		T5	2		T80	1
auto[4026531840:4160749567]	105	1			T1	1		T83	1		T80	1
auto[4160749568:4294967295]	108	1			T47	1		T79	1		T5	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T5	2		T43	2		T7	1
auto[0:134217727]	auto[1]	49	1			T192	1		T243	1		T61	2
auto[134217728:268435455]	auto[0]	56	1			T5	1		T43	1		T36	1
auto[134217728:268435455]	auto[1]	61	1			T1	1		T6	1		T7	2
auto[268435456:402653183]	auto[0]	57	1			T13	1		T5	2		T6	2
auto[268435456:402653183]	auto[1]	47	1			T104	1		T46	1		T5	1
auto[402653184:536870911]	auto[0]	52	1			T83	1		T7	1		T227	1
auto[402653184:536870911]	auto[1]	52	1			T13	1		T104	1		T5	2
auto[536870912:671088639]	auto[0]	51	1			T104	1		T47	1		T5	2
auto[536870912:671088639]	auto[1]	63	1			T5	3		T80	1		T6	1
auto[671088640:805306367]	auto[0]	49	1			T16	1		T5	1		T49	1
auto[671088640:805306367]	auto[1]	67	1			T15	1		T103	1		T56	1
auto[805306368:939524095]	auto[0]	60	1			T83	1		T5	3		T224	1
auto[805306368:939524095]	auto[1]	72	1			T32	1		T5	2		T6	1
auto[939524096:1073741823]	auto[0]	61	1			T5	2		T80	1		T52	2
auto[939524096:1073741823]	auto[1]	63	1			T46	1		T124	1		T7	1
auto[1073741824:1207959551]	auto[0]	51	1			T16	1		T47	1		T7	1
auto[1073741824:1207959551]	auto[1]	48	1			T5	2		T6	1		T36	1
auto[1207959552:1342177279]	auto[0]	49	1			T33	1		T5	2		T52	1
auto[1207959552:1342177279]	auto[1]	63	1			T84	1		T5	1		T7	1
auto[1342177280:1476395007]	auto[0]	59	1			T15	1		T6	1		T7	1
auto[1342177280:1476395007]	auto[1]	43	1			T52	1		T7	2		T73	1
auto[1476395008:1610612735]	auto[0]	57	1			T3	1		T5	1		T52	1
auto[1476395008:1610612735]	auto[1]	62	1			T33	1		T104	1		T46	1
auto[1610612736:1744830463]	auto[0]	49	1			T84	1		T46	1		T5	1
auto[1610612736:1744830463]	auto[1]	51	1			T16	1		T46	1		T5	1
auto[1744830464:1879048191]	auto[0]	52	1			T4	1		T83	2		T46	1
auto[1744830464:1879048191]	auto[1]	64	1			T1	1		T103	1		T7	1
auto[1879048192:2013265919]	auto[0]	50	1			T52	1		T22	1		T202	1
auto[1879048192:2013265919]	auto[1]	58	1			T53	1		T122	1		T188	1
auto[2013265920:2147483647]	auto[0]	68	1			T190	1		T44	1		T67	1
auto[2013265920:2147483647]	auto[1]	47	1			T5	1		T6	1		T110	1
auto[2147483648:2281701375]	auto[0]	66	1			T15	1		T36	1		T7	1
auto[2147483648:2281701375]	auto[1]	63	1			T13	1		T16	1		T56	1
auto[2281701376:2415919103]	auto[0]	73	1			T13	1		T104	1		T47	1
auto[2281701376:2415919103]	auto[1]	44	1			T1	1		T5	1		T52	1
auto[2415919104:2550136831]	auto[0]	53	1			T52	1		T190	1		T7	2
auto[2415919104:2550136831]	auto[1]	58	1			T46	1		T80	1		T52	2
auto[2550136832:2684354559]	auto[0]	50	1			T7	2		T243	1		T23	1
auto[2550136832:2684354559]	auto[1]	55	1			T3	1		T5	2		T52	2
auto[2684354560:2818572287]	auto[0]	47	1			T4	1		T5	2		T52	1
auto[2684354560:2818572287]	auto[1]	55	1			T13	1		T84	1		T45	1
auto[2818572288:2952790015]	auto[0]	47	1			T13	1		T5	1		T52	2
auto[2818572288:2952790015]	auto[1]	74	1			T32	1		T5	3		T52	2
auto[2952790016:3087007743]	auto[0]	61	1			T47	1		T5	2		T52	2
auto[2952790016:3087007743]	auto[1]	47	1			T224	1		T7	2		T131	1
auto[3087007744:3221225471]	auto[0]	56	1			T83	1		T5	2		T52	1
auto[3087007744:3221225471]	auto[1]	62	1			T3	1		T16	1		T84	1
auto[3221225472:3355443199]	auto[0]	53	1			T46	1		T5	1		T52	1
auto[3221225472:3355443199]	auto[1]	51	1			T45	1		T5	1		T6	1
auto[3355443200:3489660927]	auto[0]	43	1			T15	1		T5	1		T52	1
auto[3355443200:3489660927]	auto[1]	61	1			T5	2		T190	1		T195	1
auto[3489660928:3623878655]	auto[0]	63	1			T45	1		T53	1		T7	1
auto[3489660928:3623878655]	auto[1]	50	1			T33	1		T47	1		T5	1
auto[3623878656:3758096383]	auto[0]	61	1			T53	1		T61	1		T49	1
auto[3623878656:3758096383]	auto[1]	67	1			T1	1		T13	1		T5	1
auto[3758096384:3892314111]	auto[0]	49	1			T4	1		T47	1		T5	2
auto[3758096384:3892314111]	auto[1]	53	1			T47	1		T52	1		T120	1
auto[3892314112:4026531839]	auto[0]	54	1			T5	2		T80	1		T53	2
auto[3892314112:4026531839]	auto[1]	60	1			T4	1		T52	1		T110	1
auto[4026531840:4160749567]	auto[0]	44	1			T7	2		T230	1		T334	1
auto[4026531840:4160749567]	auto[1]	61	1			T1	1		T83	1		T80	1
auto[4160749568:4294967295]	auto[0]	45	1			T5	1		T192	1		T36	2
auto[4160749568:4294967295]	auto[1]	63	1			T47	1		T79	1		T5	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1737

1

T3

1

T4

2

T13

3

auto[1]

1837

1

T1

5

T3

2

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	122	1			T5	3		T52	2		T110	1
auto[134217728:268435455]	116	1			T83	1		T5	1		T6	1
auto[268435456:402653183]	104	1			T15	1		T46	1		T5	3
auto[402653184:536870911]	116	1			T83	1		T47	1		T5	2
auto[536870912:671088639]	106	1			T5	1		T65	1		T120	1
auto[671088640:805306367]	103	1			T13	1		T83	2		T84	1
auto[805306368:939524095]	121	1			T13	1		T32	1		T5	3
auto[939524096:1073741823]	114	1			T15	1		T5	3		T6	2
auto[1073741824:1207959551]	107	1			T1	1		T4	2		T13	1
auto[1207959552:1342177279]	112	1			T16	1		T5	3		T52	1
auto[1342177280:1476395007]	96	1			T45	1		T5	1		T6	1
auto[1476395008:1610612735]	130	1			T45	1		T5	2		T53	1
auto[1610612736:1744830463]	124	1			T16	1		T104	1		T46	2
auto[1744830464:1879048191]	117	1			T103	1		T47	2		T56	1
auto[1879048192:2013265919]	92	1			T46	1		T52	2		T124	1
auto[2013265920:2147483647]	102	1			T5	2		T53	1		T6	1
auto[2147483648:2281701375]	122	1			T1	1		T13	1		T104	1
auto[2281701376:2415919103]	96	1			T13	1		T15	1		T5	1
auto[2415919104:2550136831]	128	1			T1	1		T4	1		T84	1
auto[2550136832:2684354559]	107	1			T3	1		T103	1		T5	6
auto[2684354560:2818572287]	105	1			T5	4		T52	2		T48	2
auto[2818572288:2952790015]	109	1			T33	1		T5	6		T6	1
auto[2952790016:3087007743]	118	1			T47	1		T5	2		T80	3
auto[3087007744:3221225471]	124	1			T33	1		T83	1		T47	1
auto[3221225472:3355443199]	107	1			T83	1		T79	1		T5	1
auto[3355443200:3489660927]	135	1			T15	1		T16	1		T46	1
auto[3489660928:3623878655]	93	1			T4	1		T13	1		T16	1
auto[3623878656:3758096383]	115	1			T1	1		T3	1		T5	3
auto[3758096384:3892314111]	104	1			T1	1		T84	1		T104	1
auto[3892314112:4026531839]	111	1			T13	1		T16	1		T32	1
auto[4026531840:4160749567]	108	1			T104	1		T5	4		T52	5
auto[4160749568:4294967295]	110	1			T3	1		T45	1		T5	2