Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4760

1

T1

10

T3

4

T4

2

auto[1]

2384

1

T3

2

T4

6

T13

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	218	1			T4	2		T83	2		T5	4
auto[134217728:268435455]	226	1			T4	2		T46	2		T45	2
auto[268435456:402653183]	222	1			T13	2		T83	4		T5	4
auto[402653184:536870911]	208	1			T1	2		T16	2		T46	2
auto[536870912:671088639]	224	1			T1	2		T104	4		T5	6
auto[671088640:805306367]	228	1			T1	2		T45	2		T5	2
auto[805306368:939524095]	222	1			T47	2		T5	10		T6	2
auto[939524096:1073741823]	228	1			T5	6		T53	2		T6	2
auto[1073741824:1207959551]	230	1			T46	2		T47	2		T52	2
auto[1207959552:1342177279]	212	1			T56	2		T5	2		T80	2
auto[1342177280:1476395007]	248	1			T13	2		T15	2		T16	2
auto[1476395008:1610612735]	208	1			T83	2		T84	4		T5	6
auto[1610612736:1744830463]	242	1			T13	4		T103	2		T104	2
auto[1744830464:1879048191]	232	1			T3	2		T47	2		T5	2
auto[1879048192:2013265919]	226	1			T1	2		T3	2		T16	2
auto[2013265920:2147483647]	220	1			T13	2		T33	2		T5	4
auto[2147483648:2281701375]	222	1			T4	2		T15	2		T84	2
auto[2281701376:2415919103]	234	1			T103	4		T5	4		T80	2
auto[2415919104:2550136831]	218	1			T33	2		T47	2		T5	8
auto[2550136832:2684354559]	230	1			T46	2		T190	2		T7	2
auto[2684354560:2818572287]	190	1			T52	4		T124	2		T7	2
auto[2818572288:2952790015]	226	1			T47	2		T5	2		T52	6
auto[2952790016:3087007743]	208	1			T47	2		T56	2		T5	6
auto[3087007744:3221225471]	268	1			T3	2		T16	2		T5	6
auto[3221225472:3355443199]	200	1			T1	2		T33	2		T84	2
auto[3355443200:3489660927]	210	1			T13	2		T47	2		T45	2
auto[3489660928:3623878655]	230	1			T83	4		T5	4		T6	2
auto[3623878656:3758096383]	244	1			T13	2		T32	2		T5	4
auto[3758096384:3892314111]	226	1			T16	2		T47	2		T5	8
auto[3892314112:4026531839]	206	1			T15	2		T5	4		T53	2
auto[4026531840:4160749567]	236	1			T4	2		T104	2		T46	2
auto[4160749568:4294967295]	202	1			T15	2		T46	4		T5	6

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	118	1			T5	2		T6	2		T7	6
auto[0:134217727]	auto[1]	100	1			T4	2		T83	2		T5	2
auto[134217728:268435455]	auto[0]	140	1			T4	2		T46	2		T52	2
auto[134217728:268435455]	auto[1]	86	1			T45	2		T43	2		T120	4
auto[268435456:402653183]	auto[0]	142	1			T13	2		T83	2		T5	2
auto[268435456:402653183]	auto[1]	80	1			T83	2		T5	2		T52	6
auto[402653184:536870911]	auto[0]	142	1			T1	2		T16	2		T46	2
auto[402653184:536870911]	auto[1]	66	1			T7	2		T44	2		T28	2
auto[536870912:671088639]	auto[0]	140	1			T1	2		T104	4		T5	4
auto[536870912:671088639]	auto[1]	84	1			T5	2		T43	2		T122	2
auto[671088640:805306367]	auto[0]	144	1			T1	2		T5	2		T52	2
auto[671088640:805306367]	auto[1]	84	1			T45	2		T43	2		T122	2
auto[805306368:939524095]	auto[0]	152	1			T47	2		T5	6		T6	2
auto[805306368:939524095]	auto[1]	70	1			T5	4		T52	2		T188	2
auto[939524096:1073741823]	auto[0]	146	1			T5	4		T53	2		T52	2
auto[939524096:1073741823]	auto[1]	82	1			T5	2		T6	2		T52	2
auto[1073741824:1207959551]	auto[0]	154	1			T46	2		T47	2		T52	2
auto[1073741824:1207959551]	auto[1]	76	1			T43	2		T48	2		T202	2
auto[1207959552:1342177279]	auto[0]	140	1			T56	2		T80	2		T52	2
auto[1207959552:1342177279]	auto[1]	72	1			T5	2		T99	2		T227	2
auto[1342177280:1476395007]	auto[0]	168	1			T15	2		T16	2		T46	2
auto[1342177280:1476395007]	auto[1]	80	1			T13	2		T32	2		T65	2
auto[1476395008:1610612735]	auto[0]	144	1			T84	4		T5	4		T6	4
auto[1476395008:1610612735]	auto[1]	64	1			T83	2		T5	2		T7	4
auto[1610612736:1744830463]	auto[0]	156	1			T13	4		T103	2		T5	2
auto[1610612736:1744830463]	auto[1]	86	1			T104	2		T45	2		T7	4
auto[1744830464:1879048191]	auto[0]	158	1			T3	2		T47	2		T5	2
auto[1744830464:1879048191]	auto[1]	74	1			T52	2		T43	2		T48	2
auto[1879048192:2013265919]	auto[0]	164	1			T1	2		T16	2		T5	2
auto[1879048192:2013265919]	auto[1]	62	1			T3	2		T188	2		T185	2
auto[2013265920:2147483647]	auto[0]	150	1			T5	2		T53	4		T52	2
auto[2013265920:2147483647]	auto[1]	70	1			T13	2		T33	2		T5	2
auto[2147483648:2281701375]	auto[0]	154	1			T15	2		T84	2		T47	2
auto[2147483648:2281701375]	auto[1]	68	1			T4	2		T52	2		T61	2
auto[2281701376:2415919103]	auto[0]	156	1			T103	2		T5	4		T52	2
auto[2281701376:2415919103]	auto[1]	78	1			T103	2		T80	2		T6	2
auto[2415919104:2550136831]	auto[0]	156	1			T47	2		T5	6		T52	2
auto[2415919104:2550136831]	auto[1]	62	1			T33	2		T5	2		T6	2
auto[2550136832:2684354559]	auto[0]	168	1			T46	2		T190	2		T7	2
auto[2550136832:2684354559]	auto[1]	62	1			T61	4		T59	2		T69	2
auto[2684354560:2818572287]	auto[0]	130	1			T52	4		T124	2		T7	2
auto[2684354560:2818572287]	auto[1]	60	1			T23	2		T383	2		T258	2
auto[2818572288:2952790015]	auto[0]	150	1			T47	2		T52	6		T190	2
auto[2818572288:2952790015]	auto[1]	76	1			T5	2		T43	2		T61	2
auto[2952790016:3087007743]	auto[0]	134	1			T47	2		T56	2		T5	6
auto[2952790016:3087007743]	auto[1]	74	1			T36	2		T7	2		T398	2
auto[3087007744:3221225471]	auto[0]	168	1			T3	2		T16	2		T5	2
auto[3087007744:3221225471]	auto[1]	100	1			T5	4		T124	2		T57	2
auto[3221225472:3355443199]	auto[0]	130	1			T1	2		T84	2		T5	2
auto[3221225472:3355443199]	auto[1]	70	1			T33	2		T104	2		T79	2
auto[3355443200:3489660927]	auto[0]	140	1			T13	2		T5	2		T52	2
auto[3355443200:3489660927]	auto[1]	70	1			T47	2		T45	2		T5	8
auto[3489660928:3623878655]	auto[0]	144	1			T83	2		T5	4		T6	2
auto[3489660928:3623878655]	auto[1]	86	1			T83	2		T140	2		T58	2
auto[3623878656:3758096383]	auto[0]	164	1			T13	2		T32	2		T5	2
auto[3623878656:3758096383]	auto[1]	80	1			T5	2		T122	2		T7	2
auto[3758096384:3892314111]	auto[0]	150	1			T16	2		T47	2		T5	2
auto[3758096384:3892314111]	auto[1]	76	1			T5	6		T140	2		T7	4
auto[3892314112:4026531839]	auto[0]	144	1			T15	2		T5	4		T53	2
auto[3892314112:4026531839]	auto[1]	62	1			T52	4		T124	2		T188	2
auto[4026531840:4160749567]	auto[0]	166	1			T104	2		T46	2		T52	2
auto[4026531840:4160749567]	auto[1]	70	1			T4	2		T44	2		T61	2
auto[4160749568:4294967295]	auto[0]	148	1			T15	2		T46	4		T5	4
auto[4160749568:4294967295]	auto[1]	54	1			T5	2		T52	2		T7	2