Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3124

1

T1

5

T3

3

T4

4

auto[1]

276

1

T1

8

T13

1

T122

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	122	1			T16	1		T84	1		T52	3
auto[134217728:268435455]	114	1			T16	1		T83	2		T47	1
auto[268435456:402653183]	97	1			T4	1		T13	1		T15	1
auto[402653184:536870911]	102	1			T1	1		T4	1		T46	1
auto[536870912:671088639]	100	1			T1	2		T5	2		T140	1
auto[671088640:805306367]	112	1			T3	1		T5	2		T140	2
auto[805306368:939524095]	98	1			T1	2		T16	2		T5	1
auto[939524096:1073741823]	100	1			T3	1		T47	1		T6	1
auto[1073741824:1207959551]	115	1			T3	1		T32	1		T5	3
auto[1207959552:1342177279]	121	1			T15	1		T83	1		T84	1
auto[1342177280:1476395007]	104	1			T1	1		T15	1		T104	1
auto[1476395008:1610612735]	104	1			T1	1		T5	2		T6	2
auto[1610612736:1744830463]	113	1			T45	1		T5	2		T6	1
auto[1744830464:1879048191]	112	1			T56	1		T53	1		T6	1
auto[1879048192:2013265919]	116	1			T13	1		T103	1		T45	1
auto[2013265920:2147483647]	92	1			T83	1		T5	3		T52	1
auto[2147483648:2281701375]	104	1			T5	3		T6	1		T36	1
auto[2281701376:2415919103]	96	1			T84	1		T5	3		T6	1
auto[2415919104:2550136831]	95	1			T1	1		T45	1		T52	2
auto[2550136832:2684354559]	107	1			T1	1		T5	3		T36	1
auto[2684354560:2818572287]	95	1			T1	1		T4	1		T13	1
auto[2818572288:2952790015]	93	1			T15	1		T47	1		T6	1
auto[2952790016:3087007743]	100	1			T4	1		T13	2		T52	1
auto[3087007744:3221225471]	127	1			T46	1		T5	1		T52	1
auto[3221225472:3355443199]	126	1			T1	1		T5	3		T48	1
auto[3355443200:3489660927]	94	1			T1	1		T103	1		T5	2
auto[3489660928:3623878655]	107	1			T80	1		T122	1		T7	1
auto[3623878656:3758096383]	123	1			T13	1		T16	1		T5	2
auto[3758096384:3892314111]	88	1			T83	1		T104	1		T5	1
auto[3892314112:4026531839]	115	1			T1	1		T32	1		T84	1
auto[4026531840:4160749567]	106	1			T13	2		T104	2		T140	1
auto[4160749568:4294967295]	102	1			T33	2		T83	1		T104	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	116	1			T16	1		T84	1		T52	3
auto[0:134217727]	auto[1]	6	1			T122	1		T243	1		T274	1
auto[134217728:268435455]	auto[0]	102	1			T16	1		T83	2		T47	1
auto[134217728:268435455]	auto[1]	12	1			T328	1		T391	1		T308	1
auto[268435456:402653183]	auto[0]	91	1			T4	1		T13	1		T15	1
auto[268435456:402653183]	auto[1]	6	1			T240	1		T391	1		T237	1
auto[402653184:536870911]	auto[0]	91	1			T1	1		T4	1		T46	1
auto[402653184:536870911]	auto[1]	11	1			T102	1		T131	1		T275	1
auto[536870912:671088639]	auto[0]	95	1			T1	1		T5	2		T7	3
auto[536870912:671088639]	auto[1]	5	1			T1	1		T140	1		T220	1
auto[671088640:805306367]	auto[0]	104	1			T3	1		T5	2		T7	1
auto[671088640:805306367]	auto[1]	8	1			T140	2		T133	1		T134	1
auto[805306368:939524095]	auto[0]	89	1			T1	1		T16	2		T5	1
auto[805306368:939524095]	auto[1]	9	1			T1	1		T243	1		T134	1
auto[939524096:1073741823]	auto[0]	94	1			T3	1		T47	1		T6	1
auto[939524096:1073741823]	auto[1]	6	1			T243	2		T329	1		T292	1
auto[1073741824:1207959551]	auto[0]	102	1			T3	1		T32	1		T5	3
auto[1073741824:1207959551]	auto[1]	13	1			T133	1		T273	1		T240	1
auto[1207959552:1342177279]	auto[0]	113	1			T15	1		T83	1		T84	1
auto[1207959552:1342177279]	auto[1]	8	1			T243	1		T102	1		T131	1
auto[1342177280:1476395007]	auto[0]	99	1			T15	1		T104	1		T46	1
auto[1342177280:1476395007]	auto[1]	5	1			T1	1		T140	1		T308	1
auto[1476395008:1610612735]	auto[0]	96	1			T5	2		T6	2		T52	3
auto[1476395008:1610612735]	auto[1]	8	1			T1	1		T140	1		T273	1
auto[1610612736:1744830463]	auto[0]	105	1			T45	1		T5	2		T6	1
auto[1610612736:1744830463]	auto[1]	8	1			T131	1		T240	1		T391	1
auto[1744830464:1879048191]	auto[0]	100	1			T56	1		T53	1		T6	1
auto[1744830464:1879048191]	auto[1]	12	1			T140	1		T134	1		T240	1
auto[1879048192:2013265919]	auto[0]	108	1			T13	1		T103	1		T45	1
auto[1879048192:2013265919]	auto[1]	8	1			T131	1		T378	1		T395	1
auto[2013265920:2147483647]	auto[0]	80	1			T83	1		T5	3		T52	1
auto[2013265920:2147483647]	auto[1]	12	1			T122	1		T140	1		T102	2
auto[2147483648:2281701375]	auto[0]	96	1			T5	3		T6	1		T36	1
auto[2147483648:2281701375]	auto[1]	8	1			T358	1		T328	1		T403	2
auto[2281701376:2415919103]	auto[0]	89	1			T84	1		T5	3		T6	1
auto[2281701376:2415919103]	auto[1]	7	1			T134	2		T240	1		T391	1
auto[2415919104:2550136831]	auto[0]	87	1			T45	1		T52	2		T190	1
auto[2415919104:2550136831]	auto[1]	8	1			T1	1		T122	1		T292	1
auto[2550136832:2684354559]	auto[0]	96	1			T5	3		T36	1		T120	1
auto[2550136832:2684354559]	auto[1]	11	1			T1	1		T122	1		T237	2
auto[2684354560:2818572287]	auto[0]	87	1			T4	1		T13	1		T46	1
auto[2684354560:2818572287]	auto[1]	8	1			T1	1		T304	1		T405	2
auto[2818572288:2952790015]	auto[0]	87	1			T15	1		T47	1		T6	1
auto[2818572288:2952790015]	auto[1]	6	1			T237	1		T362	1		T390	1
auto[2952790016:3087007743]	auto[0]	96	1			T4	1		T13	2		T52	1
auto[2952790016:3087007743]	auto[1]	4	1			T328	2		T397	1		T401	1
auto[3087007744:3221225471]	auto[0]	121	1			T46	1		T5	1		T52	1
auto[3087007744:3221225471]	auto[1]	6	1			T140	1		T240	3		T394	1
auto[3221225472:3355443199]	auto[0]	119	1			T1	1		T5	3		T48	1
auto[3221225472:3355443199]	auto[1]	7	1			T140	1		T102	1		T237	1
auto[3355443200:3489660927]	auto[0]	83	1			T1	1		T103	1		T5	2
auto[3355443200:3489660927]	auto[1]	11	1			T122	2		T140	1		T102	1
auto[3489660928:3623878655]	auto[0]	93	1			T80	1		T122	1		T7	1
auto[3489660928:3623878655]	auto[1]	14	1			T243	1		T391	1		T237	1
auto[3623878656:3758096383]	auto[0]	113	1			T13	1		T16	1		T5	2
auto[3623878656:3758096383]	auto[1]	10	1			T240	1		T308	1		T378	1
auto[3758096384:3892314111]	auto[0]	81	1			T83	1		T104	1		T5	1
auto[3758096384:3892314111]	auto[1]	7	1			T122	1		T102	1		T240	1
auto[3892314112:4026531839]	auto[0]	106	1			T32	1		T84	1		T36	1
auto[3892314112:4026531839]	auto[1]	9	1			T1	1		T122	1		T140	1
auto[4026531840:4160749567]	auto[0]	95	1			T13	1		T104	2		T7	1
auto[4026531840:4160749567]	auto[1]	11	1			T13	1		T140	1		T243	1
auto[4160749568:4294967295]	auto[0]	90	1			T33	2		T83	1		T104	1
auto[4160749568:4294967295]	auto[1]	12	1			T134	1		T328	1		T308	1