Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3120

1

T1

5

T3

3

T4

4

auto[1]

271

1

T1

8

T13

6

T110

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	81	1			T1	1		T46	1		T5	2
auto[134217728:268435455]	112	1			T1	1		T4	1		T103	1
auto[268435456:402653183]	118	1			T1	1		T13	2		T83	1
auto[402653184:536870911]	109	1			T13	1		T5	1		T52	4
auto[536870912:671088639]	94	1			T15	1		T47	1		T45	1
auto[671088640:805306367]	113	1			T1	1		T13	1		T5	3
auto[805306368:939524095]	93	1			T47	1		T5	1		T48	1
auto[939524096:1073741823]	95	1			T33	1		T104	1		T79	1
auto[1073741824:1207959551]	117	1			T1	1		T83	1		T5	1
auto[1207959552:1342177279]	110	1			T1	2		T4	1		T15	1
auto[1342177280:1476395007]	119	1			T1	1		T4	1		T5	2
auto[1476395008:1610612735]	111	1			T4	1		T84	1		T5	2
auto[1610612736:1744830463]	101	1			T5	1		T36	1		T7	1
auto[1744830464:1879048191]	102	1			T46	1		T45	2		T5	1
auto[1879048192:2013265919]	110	1			T13	1		T83	1		T45	1
auto[2013265920:2147483647]	111	1			T13	1		T5	2		T80	1
auto[2147483648:2281701375]	99	1			T103	1		T52	1		T65	1
auto[2281701376:2415919103]	109	1			T16	1		T7	2		T398	1
auto[2415919104:2550136831]	116	1			T1	1		T3	1		T13	1
auto[2550136832:2684354559]	103	1			T84	1		T5	2		T6	1
auto[2684354560:2818572287]	95	1			T5	2		T140	1		T224	1
auto[2818572288:2952790015]	111	1			T3	1		T13	2		T16	1
auto[2952790016:3087007743]	111	1			T13	1		T33	1		T5	4
auto[3087007744:3221225471]	92	1			T84	1		T104	1		T5	3
auto[3221225472:3355443199]	109	1			T13	1		T16	1		T83	1
auto[3355443200:3489660927]	103	1			T83	1		T6	1		T52	2
auto[3489660928:3623878655]	100	1			T13	2		T52	1		T43	1
auto[3623878656:3758096383]	106	1			T1	2		T16	1		T5	3
auto[3758096384:3892314111]	136	1			T1	1		T15	1		T5	2
auto[3892314112:4026531839]	97	1			T32	1		T47	1		T5	2
auto[4026531840:4160749567]	92	1			T33	1		T56	1		T5	1
auto[4160749568:4294967295]	116	1			T1	1		T3	1		T15	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	75	1			T1	1		T46	1		T5	2
auto[0:134217727]	auto[1]	6	1			T133	1		T273	1		T308	1
auto[134217728:268435455]	auto[0]	101	1			T1	1		T4	1		T103	1
auto[134217728:268435455]	auto[1]	11	1			T122	1		T243	1		T133	1
auto[268435456:402653183]	auto[0]	109	1			T1	1		T13	1		T83	1
auto[268435456:402653183]	auto[1]	9	1			T13	1		T122	1		T102	1
auto[402653184:536870911]	auto[0]	103	1			T5	1		T52	4		T122	1
auto[402653184:536870911]	auto[1]	6	1			T13	1		T122	1		T132	1
auto[536870912:671088639]	auto[0]	91	1			T15	1		T47	1		T45	1
auto[536870912:671088639]	auto[1]	3	1			T132	1		T133	1		T319	1
auto[671088640:805306367]	auto[0]	105	1			T1	1		T5	3		T52	1
auto[671088640:805306367]	auto[1]	8	1			T13	1		T243	1		T131	1
auto[805306368:939524095]	auto[0]	82	1			T47	1		T5	1		T48	1
auto[805306368:939524095]	auto[1]	11	1			T140	1		T243	1		T131	1
auto[939524096:1073741823]	auto[0]	85	1			T33	1		T104	1		T79	1
auto[939524096:1073741823]	auto[1]	10	1			T243	1		T391	1		T304	1
auto[1073741824:1207959551]	auto[0]	102	1			T83	1		T5	1		T80	1
auto[1073741824:1207959551]	auto[1]	15	1			T1	1		T110	1		T243	2
auto[1207959552:1342177279]	auto[0]	104	1			T4	1		T15	1		T104	1
auto[1207959552:1342177279]	auto[1]	6	1			T1	2		T140	1		T131	1
auto[1342177280:1476395007]	auto[0]	111	1			T4	1		T5	2		T52	1
auto[1342177280:1476395007]	auto[1]	8	1			T1	1		T243	1		T391	1
auto[1476395008:1610612735]	auto[0]	103	1			T4	1		T84	1		T5	2
auto[1476395008:1610612735]	auto[1]	8	1			T358	1		T237	1		T378	1
auto[1610612736:1744830463]	auto[0]	97	1			T5	1		T36	1		T7	1
auto[1610612736:1744830463]	auto[1]	4	1			T394	1		T403	1		T402	1
auto[1744830464:1879048191]	auto[0]	94	1			T46	1		T45	2		T5	1
auto[1744830464:1879048191]	auto[1]	8	1			T243	2		T275	1		T395	1
auto[1879048192:2013265919]	auto[0]	103	1			T83	1		T45	1		T5	3
auto[1879048192:2013265919]	auto[1]	7	1			T13	1		T237	1		T378	1
auto[2013265920:2147483647]	auto[0]	103	1			T13	1		T5	2		T80	1
auto[2013265920:2147483647]	auto[1]	8	1			T243	1		T102	1		T240	1
auto[2147483648:2281701375]	auto[0]	94	1			T103	1		T52	1		T65	1
auto[2147483648:2281701375]	auto[1]	5	1			T140	1		T329	1		T395	1
auto[2281701376:2415919103]	auto[0]	99	1			T16	1		T7	2		T398	1
auto[2281701376:2415919103]	auto[1]	10	1			T273	1		T240	1		T391	1
auto[2415919104:2550136831]	auto[0]	105	1			T1	1		T3	1		T16	1
auto[2415919104:2550136831]	auto[1]	11	1			T13	1		T132	1		T240	1
auto[2550136832:2684354559]	auto[0]	91	1			T84	1		T5	2		T6	1
auto[2550136832:2684354559]	auto[1]	12	1			T140	2		T131	1		T391	1
auto[2684354560:2818572287]	auto[0]	82	1			T5	2		T224	1		T7	1
auto[2684354560:2818572287]	auto[1]	13	1			T140	1		T237	1		T292	1
auto[2818572288:2952790015]	auto[0]	101	1			T3	1		T13	1		T16	1
auto[2818572288:2952790015]	auto[1]	10	1			T13	1		T122	1		T391	1
auto[2952790016:3087007743]	auto[0]	105	1			T13	1		T33	1		T5	4
auto[2952790016:3087007743]	auto[1]	6	1			T240	1		T304	1		T378	2
auto[3087007744:3221225471]	auto[0]	85	1			T84	1		T104	1		T5	3
auto[3087007744:3221225471]	auto[1]	7	1			T132	1		T134	1		T275	1
auto[3221225472:3355443199]	auto[0]	98	1			T13	1		T16	1		T83	1
auto[3221225472:3355443199]	auto[1]	11	1			T391	1		T237	1		T292	2
auto[3355443200:3489660927]	auto[0]	100	1			T83	1		T6	1		T52	2
auto[3355443200:3489660927]	auto[1]	3	1			T406	1		T396	1		T257	1
auto[3489660928:3623878655]	auto[0]	91	1			T13	2		T52	1		T43	1
auto[3489660928:3623878655]	auto[1]	9	1			T140	1		T243	1		T240	1
auto[3623878656:3758096383]	auto[0]	95	1			T16	1		T5	3		T6	1
auto[3623878656:3758096383]	auto[1]	11	1			T1	2		T237	1		T403	1
auto[3758096384:3892314111]	auto[0]	124	1			T15	1		T5	2		T52	1
auto[3758096384:3892314111]	auto[1]	12	1			T1	1		T140	1		T131	1
auto[3892314112:4026531839]	auto[0]	91	1			T32	1		T47	1		T5	2
auto[3892314112:4026531839]	auto[1]	6	1			T140	1		T131	1		T133	1
auto[4026531840:4160749567]	auto[0]	87	1			T33	1		T56	1		T5	1
auto[4026531840:4160749567]	auto[1]	5	1			T235	1		T394	2		T402	2
auto[4160749568:4294967295]	auto[0]	104	1			T3	1		T15	1		T46	1
auto[4160749568:4294967295]	auto[1]	12	1			T1	1		T243	1		T391	1