Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1752

1

T3

2

T4

3

T13

3

auto[1]

1822

1

T1

5

T3

1

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T56	1		T5	2		T53	1
auto[134217728:268435455]	105	1			T5	1		T80	1		T53	1
auto[268435456:402653183]	99	1			T13	1		T32	1		T104	1
auto[402653184:536870911]	121	1			T3	1		T15	1		T83	1
auto[536870912:671088639]	108	1			T1	1		T13	1		T84	1
auto[671088640:805306367]	124	1			T3	1		T16	1		T47	1
auto[805306368:939524095]	119	1			T5	2		T110	2		T43	1
auto[939524096:1073741823]	125	1			T4	1		T84	1		T47	1
auto[1073741824:1207959551]	118	1			T46	1		T5	3		T52	2
auto[1207959552:1342177279]	121	1			T15	1		T83	2		T46	2
auto[1342177280:1476395007]	102	1			T4	1		T47	1		T79	1
auto[1476395008:1610612735]	106	1			T53	1		T52	1		T43	1
auto[1610612736:1744830463]	94	1			T5	1		T52	1		T190	1
auto[1744830464:1879048191]	112	1			T1	2		T33	1		T46	1
auto[1879048192:2013265919]	106	1			T13	2		T104	1		T46	1
auto[2013265920:2147483647]	101	1			T4	1		T104	1		T5	4
auto[2147483648:2281701375]	118	1			T83	1		T84	1		T46	1
auto[2281701376:2415919103]	124	1			T52	5		T192	1		T36	1
auto[2415919104:2550136831]	120	1			T16	2		T5	2		T6	1
auto[2550136832:2684354559]	116	1			T3	1		T83	1		T47	2
auto[2684354560:2818572287]	82	1			T32	1		T103	1		T124	1
auto[2818572288:2952790015]	115	1			T56	1		T5	2		T6	2
auto[2952790016:3087007743]	117	1			T1	1		T15	1		T16	1
auto[3087007744:3221225471]	110	1			T5	6		T52	1		T124	1
auto[3221225472:3355443199]	119	1			T33	1		T46	1		T5	1
auto[3355443200:3489660927]	112	1			T104	1		T5	2		T52	5
auto[3489660928:3623878655]	123	1			T16	1		T84	1		T5	1
auto[3623878656:3758096383]	89	1			T104	1		T46	1		T5	2
auto[3758096384:3892314111]	111	1			T1	1		T4	1		T47	1
auto[3892314112:4026531839]	103	1			T33	1		T83	1		T5	2
auto[4026531840:4160749567]	143	1			T13	3		T15	1		T45	1
auto[4160749568:4294967295]	94	1			T103	1		T45	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	66	1			T5	1		T43	1		T65	1
auto[0:134217727]	auto[1]	51	1			T56	1		T5	1		T53	1
auto[134217728:268435455]	auto[0]	52	1			T53	1		T52	1		T44	1
auto[134217728:268435455]	auto[1]	53	1			T5	1		T80	1		T120	1
auto[268435456:402653183]	auto[0]	49	1			T47	1		T5	1		T43	1
auto[268435456:402653183]	auto[1]	50	1			T13	1		T32	1		T104	1
auto[402653184:536870911]	auto[0]	61	1			T3	1		T83	1		T45	1
auto[402653184:536870911]	auto[1]	60	1			T15	1		T103	1		T47	1
auto[536870912:671088639]	auto[0]	49	1			T13	1		T84	1		T5	1
auto[536870912:671088639]	auto[1]	59	1			T1	1		T5	1		T52	1
auto[671088640:805306367]	auto[0]	52	1			T3	1		T47	1		T80	1
auto[671088640:805306367]	auto[1]	72	1			T16	1		T45	1		T5	3
auto[805306368:939524095]	auto[0]	56	1			T5	2		T43	1		T36	1
auto[805306368:939524095]	auto[1]	63	1			T110	2		T65	1		T188	1
auto[939524096:1073741823]	auto[0]	56	1			T47	1		T5	1		T6	1
auto[939524096:1073741823]	auto[1]	69	1			T4	1		T84	1		T5	2
auto[1073741824:1207959551]	auto[0]	53	1			T5	2		T52	1		T48	1
auto[1073741824:1207959551]	auto[1]	65	1			T46	1		T5	1		T52	1
auto[1207959552:1342177279]	auto[0]	72	1			T15	1		T83	1		T47	1
auto[1207959552:1342177279]	auto[1]	49	1			T83	1		T46	2		T5	2
auto[1342177280:1476395007]	auto[0]	47	1			T4	1		T47	1		T52	2
auto[1342177280:1476395007]	auto[1]	55	1			T79	1		T6	2		T140	1
auto[1476395008:1610612735]	auto[0]	56	1			T53	1		T7	1		T44	1
auto[1476395008:1610612735]	auto[1]	50	1			T52	1		T43	1		T398	1
auto[1610612736:1744830463]	auto[0]	47	1			T5	1		T52	1		T7	4
auto[1610612736:1744830463]	auto[1]	47	1			T190	1		T189	1		T222	1
auto[1744830464:1879048191]	auto[0]	55	1			T5	2		T52	1		T36	1
auto[1744830464:1879048191]	auto[1]	57	1			T1	2		T33	1		T46	1
auto[1879048192:2013265919]	auto[0]	61	1			T13	1		T46	1		T53	1
auto[1879048192:2013265919]	auto[1]	45	1			T13	1		T104	1		T5	1
auto[2013265920:2147483647]	auto[0]	53	1			T4	1		T104	1		T5	1
auto[2013265920:2147483647]	auto[1]	48	1			T5	3		T52	2		T122	1
auto[2147483648:2281701375]	auto[0]	57	1			T83	1		T84	1		T5	1
auto[2147483648:2281701375]	auto[1]	61	1			T46	1		T5	1		T80	1
auto[2281701376:2415919103]	auto[0]	60	1			T52	5		T48	1		T190	1
auto[2281701376:2415919103]	auto[1]	64	1			T192	1		T36	1		T48	1
auto[2415919104:2550136831]	auto[0]	65	1			T5	1		T7	1		T49	1
auto[2415919104:2550136831]	auto[1]	55	1			T16	2		T5	1		T6	1
auto[2550136832:2684354559]	auto[0]	52	1			T83	1		T5	1		T52	1
auto[2550136832:2684354559]	auto[1]	64	1			T3	1		T47	2		T5	2
auto[2684354560:2818572287]	auto[0]	36	1			T243	2		T222	1		T73	1
auto[2684354560:2818572287]	auto[1]	46	1			T32	1		T103	1		T124	1
auto[2818572288:2952790015]	auto[0]	48	1			T52	1		T192	1		T224	1
auto[2818572288:2952790015]	auto[1]	67	1			T56	1		T5	2		T6	2
auto[2952790016:3087007743]	auto[0]	64	1			T15	1		T16	1		T5	2
auto[2952790016:3087007743]	auto[1]	53	1			T1	1		T5	2		T6	1
auto[3087007744:3221225471]	auto[0]	55	1			T5	5		T7	1		T44	1
auto[3087007744:3221225471]	auto[1]	55	1			T5	1		T52	1		T124	1
auto[3221225472:3355443199]	auto[0]	58	1			T5	1		T80	1		T6	1
auto[3221225472:3355443199]	auto[1]	61	1			T33	1		T46	1		T36	1
auto[3355443200:3489660927]	auto[0]	55	1			T52	2		T122	1		T44	1
auto[3355443200:3489660927]	auto[1]	57	1			T104	1		T5	2		T52	3
auto[3489660928:3623878655]	auto[0]	60	1			T16	1		T5	1		T100	1
auto[3489660928:3623878655]	auto[1]	63	1			T84	1		T6	2		T52	1
auto[3623878656:3758096383]	auto[0]	42	1			T5	1		T52	1		T7	1
auto[3623878656:3758096383]	auto[1]	47	1			T104	1		T46	1		T5	1
auto[3758096384:3892314111]	auto[0]	50	1			T4	1		T47	1		T5	3
auto[3758096384:3892314111]	auto[1]	61	1			T1	1		T6	1		T122	1
auto[3892314112:4026531839]	auto[0]	41	1			T83	1		T5	2		T7	1
auto[3892314112:4026531839]	auto[1]	62	1			T33	1		T52	2		T61	1
auto[4026531840:4160749567]	auto[0]	81	1			T13	1		T5	3		T53	1
auto[4026531840:4160749567]	auto[1]	62	1			T13	2		T15	1		T45	1
auto[4160749568:4294967295]	auto[0]	43	1			T45	1		T5	1		T7	2
auto[4160749568:4294967295]	auto[1]	51	1			T103	1		T224	1		T61	2