Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7470

1

T1

10

T3

6

T4

19

auto[1]

228

1

T1

9

T13

1

T110

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3138	1			T1	5		T3	3		T4	9
auto[134217728:268435455]	187	1			T1	1		T4	3		T13	1
auto[268435456:402653183]	164	1			T1	1		T5	2		T80	1
auto[402653184:536870911]	151	1			T47	1		T5	3		T6	1
auto[536870912:671088639]	153	1			T3	1		T4	1		T46	1
auto[671088640:805306367]	160	1			T1	2		T13	1		T15	1
auto[805306368:939524095]	154	1			T83	1		T5	1		T6	1
auto[939524096:1073741823]	149	1			T5	3		T52	1		T110	1
auto[1073741824:1207959551]	156	1			T16	2		T80	2		T6	1
auto[1207959552:1342177279]	139	1			T32	1		T5	3		T52	1
auto[1342177280:1476395007]	151	1			T4	2		T13	2		T33	1
auto[1476395008:1610612735]	144	1			T1	1		T33	1		T46	1
auto[1610612736:1744830463]	120	1			T3	1		T15	2		T56	1
auto[1744830464:1879048191]	174	1			T84	1		T103	1		T104	1
auto[1879048192:2013265919]	143	1			T103	1		T5	3		T6	1
auto[2013265920:2147483647]	155	1			T3	1		T103	1		T104	1
auto[2147483648:2281701375]	128	1			T16	1		T5	2		T6	1
auto[2281701376:2415919103]	144	1			T1	1		T13	1		T16	2
auto[2415919104:2550136831]	132	1			T4	2		T13	1		T103	1
auto[2550136832:2684354559]	144	1			T1	1		T32	1		T84	2
auto[2684354560:2818572287]	156	1			T1	1		T33	1		T5	1
auto[2818572288:2952790015]	150	1			T1	1		T13	1		T16	1
auto[2952790016:3087007743]	136	1			T4	1		T83	1		T84	1
auto[3087007744:3221225471]	142	1			T1	1		T4	1		T103	1
auto[3221225472:3355443199]	155	1			T1	1		T13	1		T56	1
auto[3355443200:3489660927]	135	1			T5	3		T53	1		T140	2
auto[3489660928:3623878655]	131	1			T83	1		T6	1		T52	1
auto[3623878656:3758096383]	146	1			T103	1		T46	1		T5	2
auto[3758096384:3892314111]	135	1			T1	1		T13	1		T45	1
auto[3892314112:4026531839]	143	1			T1	1		T15	1		T83	3
auto[4026531840:4160749567]	141	1			T1	1		T15	1		T83	1
auto[4160749568:4294967295]	142	1			T32	1		T5	2		T6	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3128	1			T1	5		T3	3		T4	9
auto[0:134217727]	auto[1]	10	1			T240	1		T395	1		T399	1
auto[134217728:268435455]	auto[0]	177	1			T1	1		T4	3		T13	1
auto[134217728:268435455]	auto[1]	10	1			T122	1		T391	1		T275	1
auto[268435456:402653183]	auto[0]	157	1			T5	2		T80	1		T6	1
auto[268435456:402653183]	auto[1]	7	1			T1	1		T131	1		T240	1
auto[402653184:536870911]	auto[0]	150	1			T47	1		T5	3		T6	1
auto[402653184:536870911]	auto[1]	1	1			T308	1		-	-		-	-
auto[536870912:671088639]	auto[0]	144	1			T3	1		T4	1		T46	1
auto[536870912:671088639]	auto[1]	9	1			T131	1		T134	1		T394	1
auto[671088640:805306367]	auto[0]	153	1			T13	1		T15	1		T33	1
auto[671088640:805306367]	auto[1]	7	1			T1	2		T122	1		T131	1
auto[805306368:939524095]	auto[0]	149	1			T83	1		T5	1		T6	1
auto[805306368:939524095]	auto[1]	5	1			T240	1		T308	2		T399	1
auto[939524096:1073741823]	auto[0]	140	1			T5	3		T52	1		T110	1
auto[939524096:1073741823]	auto[1]	9	1			T240	1		T304	1		T235	1
auto[1073741824:1207959551]	auto[0]	148	1			T16	2		T80	2		T6	1
auto[1073741824:1207959551]	auto[1]	8	1			T140	1		T243	1		T308	1
auto[1207959552:1342177279]	auto[0]	130	1			T32	1		T5	3		T52	1
auto[1207959552:1342177279]	auto[1]	9	1			T140	1		T391	1		T329	1
auto[1342177280:1476395007]	auto[0]	147	1			T4	2		T13	2		T33	1
auto[1342177280:1476395007]	auto[1]	4	1			T102	1		T391	1		T237	1
auto[1476395008:1610612735]	auto[0]	133	1			T1	1		T33	1		T46	1
auto[1476395008:1610612735]	auto[1]	11	1			T140	1		T131	1		T240	1
auto[1610612736:1744830463]	auto[0]	115	1			T3	1		T15	2		T56	1
auto[1610612736:1744830463]	auto[1]	5	1			T391	1		T308	1		T400	1
auto[1744830464:1879048191]	auto[0]	165	1			T84	1		T103	1		T104	1
auto[1744830464:1879048191]	auto[1]	9	1			T243	1		T133	1		T358	1
auto[1879048192:2013265919]	auto[0]	136	1			T103	1		T5	3		T6	1
auto[1879048192:2013265919]	auto[1]	7	1			T102	1		T242	2		T400	1
auto[2013265920:2147483647]	auto[0]	149	1			T3	1		T103	1		T104	1
auto[2013265920:2147483647]	auto[1]	6	1			T133	1		T378	1		T396	1
auto[2147483648:2281701375]	auto[0]	125	1			T16	1		T5	2		T6	1
auto[2147483648:2281701375]	auto[1]	3	1			T302	1		T397	1		T401	1
auto[2281701376:2415919103]	auto[0]	132	1			T16	2		T45	1		T5	1
auto[2281701376:2415919103]	auto[1]	12	1			T1	1		T13	1		T122	1
auto[2415919104:2550136831]	auto[0]	129	1			T4	2		T13	1		T103	1
auto[2415919104:2550136831]	auto[1]	3	1			T140	1		T378	1		T329	1
auto[2550136832:2684354559]	auto[0]	141	1			T32	1		T84	2		T47	1
auto[2550136832:2684354559]	auto[1]	3	1			T1	1		T242	1		T402	1
auto[2684354560:2818572287]	auto[0]	144	1			T33	1		T5	1		T80	1
auto[2684354560:2818572287]	auto[1]	12	1			T1	1		T240	2		T394	1
auto[2818572288:2952790015]	auto[0]	139	1			T13	1		T16	1		T83	1
auto[2818572288:2952790015]	auto[1]	11	1			T1	1		T110	1		T102	1
auto[2952790016:3087007743]	auto[0]	133	1			T4	1		T83	1		T84	1
auto[2952790016:3087007743]	auto[1]	3	1			T122	1		T395	1		T403	1
auto[3087007744:3221225471]	auto[0]	135	1			T1	1		T4	1		T103	1
auto[3087007744:3221225471]	auto[1]	7	1			T292	1		T394	1		T403	1
auto[3221225472:3355443199]	auto[0]	145	1			T13	1		T56	1		T5	1
auto[3221225472:3355443199]	auto[1]	10	1			T1	1		T240	1		T328	2
auto[3355443200:3489660927]	auto[0]	129	1			T5	3		T53	1		T140	1
auto[3355443200:3489660927]	auto[1]	6	1			T140	1		T391	1		T242	1
auto[3489660928:3623878655]	auto[0]	127	1			T83	1		T6	1		T52	1
auto[3489660928:3623878655]	auto[1]	4	1			T102	1		T308	1		T392	1
auto[3623878656:3758096383]	auto[0]	139	1			T103	1		T46	1		T5	2
auto[3623878656:3758096383]	auto[1]	7	1			T134	1		T237	1		T292	1
auto[3758096384:3892314111]	auto[0]	126	1			T1	1		T13	1		T45	1
auto[3758096384:3892314111]	auto[1]	9	1			T243	2		T391	1		T308	1
auto[3892314112:4026531839]	auto[0]	134	1			T15	1		T83	3		T45	1
auto[3892314112:4026531839]	auto[1]	9	1			T1	1		T134	1		T240	1
auto[4026531840:4160749567]	auto[0]	136	1			T1	1		T15	1		T83	1
auto[4026531840:4160749567]	auto[1]	5	1			T122	1		T140	1		T243	1
auto[4160749568:4294967295]	auto[0]	135	1			T32	1		T5	2		T6	2
auto[4160749568:4294967295]	auto[1]	7	1			T110	1		T102	1		T237	1