Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4858

1

T1

10

T3

4

T4

2

auto[1]

2290

1

T3

2

T4

6

T13

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	196	1			T47	2		T5	2		T52	2
auto[134217728:268435455]	250	1			T83	2		T84	2		T5	4
auto[268435456:402653183]	218	1			T16	2		T33	2		T5	4
auto[402653184:536870911]	228	1			T13	2		T104	2		T5	4
auto[536870912:671088639]	264	1			T83	2		T46	2		T5	2
auto[671088640:805306367]	216	1			T103	2		T5	10		T52	2
auto[805306368:939524095]	220	1			T46	2		T47	2		T5	4
auto[939524096:1073741823]	230	1			T13	2		T15	2		T33	2
auto[1073741824:1207959551]	250	1			T1	6		T4	2		T13	4
auto[1207959552:1342177279]	210	1			T5	8		T52	4		T224	2
auto[1342177280:1476395007]	206	1			T45	2		T5	4		T53	2
auto[1476395008:1610612735]	232	1			T3	2		T15	2		T104	2
auto[1610612736:1744830463]	238	1			T103	2		T53	2		T6	4
auto[1744830464:1879048191]	194	1			T3	2		T46	2		T47	2
auto[1879048192:2013265919]	228	1			T1	2		T5	8		T80	2
auto[2013265920:2147483647]	252	1			T13	2		T15	2		T83	2
auto[2147483648:2281701375]	218	1			T46	2		T5	6		T52	2
auto[2281701376:2415919103]	240	1			T32	2		T5	6		T52	6
auto[2415919104:2550136831]	220	1			T1	2		T32	2		T47	2
auto[2550136832:2684354559]	252	1			T4	2		T33	2		T5	2
auto[2684354560:2818572287]	218	1			T46	2		T47	2		T45	2
auto[2818572288:2952790015]	266	1			T3	2		T13	2		T83	2
auto[2952790016:3087007743]	216	1			T16	2		T84	2		T5	4
auto[3087007744:3221225471]	208	1			T104	2		T47	2		T5	6
auto[3221225472:3355443199]	186	1			T84	2		T46	2		T5	4
auto[3355443200:3489660927]	196	1			T16	2		T84	2		T5	4
auto[3489660928:3623878655]	200	1			T13	2		T104	2		T47	2
auto[3623878656:3758096383]	252	1			T16	2		T104	2		T47	2
auto[3758096384:3892314111]	234	1			T15	2		T5	8		T52	2
auto[3892314112:4026531839]	218	1			T16	2		T83	2		T80	2
auto[4026531840:4160749567]	206	1			T5	2		T6	2		T52	4
auto[4160749568:4294967295]	186	1			T4	4		T83	2		T46	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	122	1			T47	2		T5	2		T7	2
auto[0:134217727]	auto[1]	74	1			T52	2		T71	4		T131	2
auto[134217728:268435455]	auto[0]	160	1			T84	2		T5	2		T6	4
auto[134217728:268435455]	auto[1]	90	1			T83	2		T5	2		T122	2
auto[268435456:402653183]	auto[0]	138	1			T16	2		T33	2		T5	2
auto[268435456:402653183]	auto[1]	80	1			T5	2		T7	4		T72	2
auto[402653184:536870911]	auto[0]	176	1			T13	2		T104	2		T5	4
auto[402653184:536870911]	auto[1]	52	1			T124	2		T7	2		T100	2
auto[536870912:671088639]	auto[0]	186	1			T83	2		T46	2		T53	2
auto[536870912:671088639]	auto[1]	78	1			T5	2		T48	2		T258	4
auto[671088640:805306367]	auto[0]	142	1			T5	8		T7	2		T44	2
auto[671088640:805306367]	auto[1]	74	1			T103	2		T5	2		T52	2
auto[805306368:939524095]	auto[0]	158	1			T46	2		T47	2		T5	4
auto[805306368:939524095]	auto[1]	62	1			T80	2		T52	2		T189	2
auto[939524096:1073741823]	auto[0]	174	1			T15	2		T33	2		T56	2
auto[939524096:1073741823]	auto[1]	56	1			T13	2		T61	4		T57	2
auto[1073741824:1207959551]	auto[0]	172	1			T1	6		T13	4		T47	2
auto[1073741824:1207959551]	auto[1]	78	1			T4	2		T5	4		T7	2
auto[1207959552:1342177279]	auto[0]	146	1			T5	4		T52	4		T224	2
auto[1207959552:1342177279]	auto[1]	64	1			T5	4		T61	2		T73	2
auto[1342177280:1476395007]	auto[0]	130	1			T45	2		T5	2		T52	2
auto[1342177280:1476395007]	auto[1]	76	1			T5	2		T53	2		T192	2
auto[1476395008:1610612735]	auto[0]	146	1			T15	2		T104	2		T5	4
auto[1476395008:1610612735]	auto[1]	86	1			T3	2		T57	2		T71	2
auto[1610612736:1744830463]	auto[0]	166	1			T103	2		T6	4		T52	2
auto[1610612736:1744830463]	auto[1]	72	1			T53	2		T43	2		T227	2
auto[1744830464:1879048191]	auto[0]	138	1			T3	2		T46	2		T47	2
auto[1744830464:1879048191]	auto[1]	56	1			T5	2		T53	2		T110	2
auto[1879048192:2013265919]	auto[0]	168	1			T1	2		T5	6		T80	2
auto[1879048192:2013265919]	auto[1]	60	1			T5	2		T7	2		T28	2
auto[2013265920:2147483647]	auto[0]	172	1			T13	2		T15	2		T83	2
auto[2013265920:2147483647]	auto[1]	80	1			T7	2		T22	2		T57	2
auto[2147483648:2281701375]	auto[0]	142	1			T46	2		T5	4		T52	2
auto[2147483648:2281701375]	auto[1]	76	1			T5	2		T124	2		T7	4
auto[2281701376:2415919103]	auto[0]	168	1			T32	2		T5	6		T52	6
auto[2281701376:2415919103]	auto[1]	72	1			T61	6		T23	2		T167	2
auto[2415919104:2550136831]	auto[0]	150	1			T1	2		T32	2		T47	2
auto[2415919104:2550136831]	auto[1]	70	1			T52	2		T124	2		T188	2
auto[2550136832:2684354559]	auto[0]	154	1			T5	2		T52	4		T36	2
auto[2550136832:2684354559]	auto[1]	98	1			T4	2		T33	2		T7	2
auto[2684354560:2818572287]	auto[0]	142	1			T46	2		T47	2		T45	2
auto[2684354560:2818572287]	auto[1]	76	1			T7	2		T300	4		T74	2
auto[2818572288:2952790015]	auto[0]	176	1			T3	2		T83	2		T46	2
auto[2818572288:2952790015]	auto[1]	90	1			T13	2		T6	2		T110	2
auto[2952790016:3087007743]	auto[0]	156	1			T16	2		T84	2		T5	2
auto[2952790016:3087007743]	auto[1]	60	1			T5	2		T52	2		T7	2
auto[3087007744:3221225471]	auto[0]	140	1			T47	2		T5	4		T52	2
auto[3087007744:3221225471]	auto[1]	68	1			T104	2		T5	2		T80	2
auto[3221225472:3355443199]	auto[0]	124	1			T84	2		T46	2		T5	4
auto[3221225472:3355443199]	auto[1]	62	1			T124	2		T23	2		T115	2
auto[3355443200:3489660927]	auto[0]	136	1			T16	2		T84	2		T5	4
auto[3355443200:3489660927]	auto[1]	60	1			T44	2		T61	4		T221	2
auto[3489660928:3623878655]	auto[0]	124	1			T13	2		T104	2		T5	4
auto[3489660928:3623878655]	auto[1]	76	1			T47	2		T52	2		T48	2
auto[3623878656:3758096383]	auto[0]	188	1			T16	2		T104	2		T47	2
auto[3623878656:3758096383]	auto[1]	64	1			T53	2		T48	2		T58	2
auto[3758096384:3892314111]	auto[0]	148	1			T15	2		T5	6		T52	2
auto[3758096384:3892314111]	auto[1]	86	1			T5	2		T120	2		T7	2
auto[3892314112:4026531839]	auto[0]	148	1			T16	2		T43	2		T140	2
auto[3892314112:4026531839]	auto[1]	70	1			T83	2		T80	2		T48	2
auto[4026531840:4160749567]	auto[0]	146	1			T5	2		T6	2		T52	4
auto[4026531840:4160749567]	auto[1]	60	1			T192	2		T44	2		T57	2
auto[4160749568:4294967295]	auto[0]	122	1			T4	2		T83	2		T46	2
auto[4160749568:4294967295]	auto[1]	64	1			T4	2		T56	2		T36	2