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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.44 99.00 98.11 98.79 97.67 98.93 98.41 91.19


Total test records in report: 1085
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T1010 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2101521783 Aug 13 05:37:27 PM PDT 24 Aug 13 05:37:29 PM PDT 24 126691988 ps
T1011 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2836705545 Aug 13 05:37:34 PM PDT 24 Aug 13 05:37:37 PM PDT 24 174128855 ps
T146 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3259051966 Aug 13 05:37:18 PM PDT 24 Aug 13 05:37:29 PM PDT 24 977381916 ps
T1012 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3784213124 Aug 13 05:37:47 PM PDT 24 Aug 13 05:37:48 PM PDT 24 25993967 ps
T1013 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3622730704 Aug 13 05:37:45 PM PDT 24 Aug 13 05:37:46 PM PDT 24 12403738 ps
T1014 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1548436840 Aug 13 05:37:48 PM PDT 24 Aug 13 05:37:50 PM PDT 24 13261674 ps
T1015 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2364720277 Aug 13 05:37:54 PM PDT 24 Aug 13 05:37:57 PM PDT 24 424820082 ps
T1016 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1981339369 Aug 13 05:37:33 PM PDT 24 Aug 13 05:37:34 PM PDT 24 41688997 ps
T1017 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1685791942 Aug 13 05:37:48 PM PDT 24 Aug 13 05:37:49 PM PDT 24 13249195 ps
T1018 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.330244986 Aug 13 05:37:26 PM PDT 24 Aug 13 05:37:33 PM PDT 24 432178373 ps
T1019 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3524064051 Aug 13 05:37:18 PM PDT 24 Aug 13 05:37:19 PM PDT 24 23897447 ps
T1020 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2595654371 Aug 13 05:37:27 PM PDT 24 Aug 13 05:37:42 PM PDT 24 254445318 ps
T1021 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3891315601 Aug 13 05:37:48 PM PDT 24 Aug 13 05:38:04 PM PDT 24 418691901 ps
T1022 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1745006482 Aug 13 05:37:33 PM PDT 24 Aug 13 05:37:34 PM PDT 24 16881416 ps
T1023 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.483878172 Aug 13 05:37:20 PM PDT 24 Aug 13 05:37:22 PM PDT 24 196695036 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3749361666 Aug 13 05:37:24 PM PDT 24 Aug 13 05:37:26 PM PDT 24 492589148 ps
T1025 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2023620992 Aug 13 05:37:07 PM PDT 24 Aug 13 05:37:20 PM PDT 24 450735047 ps
T1026 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1004306343 Aug 13 05:37:33 PM PDT 24 Aug 13 05:37:36 PM PDT 24 69087314 ps
T1027 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2610915241 Aug 13 05:37:33 PM PDT 24 Aug 13 05:37:36 PM PDT 24 54433385 ps
T1028 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2960054721 Aug 13 05:38:00 PM PDT 24 Aug 13 05:38:01 PM PDT 24 29541956 ps
T1029 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3964880556 Aug 13 05:37:23 PM PDT 24 Aug 13 05:37:27 PM PDT 24 116146372 ps
T1030 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.558035234 Aug 13 05:37:30 PM PDT 24 Aug 13 05:37:32 PM PDT 24 65288392 ps
T1031 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2081690073 Aug 13 05:37:51 PM PDT 24 Aug 13 05:37:52 PM PDT 24 10979766 ps
T1032 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4156604169 Aug 13 05:37:21 PM PDT 24 Aug 13 05:37:23 PM PDT 24 83318149 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2473964093 Aug 13 05:37:57 PM PDT 24 Aug 13 05:37:59 PM PDT 24 54558909 ps
T1034 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1196681940 Aug 13 05:37:46 PM PDT 24 Aug 13 05:37:48 PM PDT 24 461259086 ps
T1035 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.339862636 Aug 13 05:37:39 PM PDT 24 Aug 13 05:37:40 PM PDT 24 34826383 ps
T151 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3925032270 Aug 13 05:37:49 PM PDT 24 Aug 13 05:37:57 PM PDT 24 896664343 ps
T1036 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.983904379 Aug 13 05:37:44 PM PDT 24 Aug 13 05:37:46 PM PDT 24 152509878 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1423600718 Aug 13 05:37:11 PM PDT 24 Aug 13 05:37:12 PM PDT 24 74942849 ps
T149 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3028348701 Aug 13 05:37:13 PM PDT 24 Aug 13 05:37:17 PM PDT 24 233763234 ps
T1038 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3214821477 Aug 13 05:37:42 PM PDT 24 Aug 13 05:37:43 PM PDT 24 9271761 ps
T1039 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.144273803 Aug 13 05:37:31 PM PDT 24 Aug 13 05:37:33 PM PDT 24 158304970 ps
T1040 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3966659971 Aug 13 05:37:31 PM PDT 24 Aug 13 05:37:33 PM PDT 24 614584329 ps
T1041 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2275424589 Aug 13 05:37:49 PM PDT 24 Aug 13 05:37:50 PM PDT 24 62539299 ps
T1042 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1456508146 Aug 13 05:37:59 PM PDT 24 Aug 13 05:38:04 PM PDT 24 117775414 ps
T1043 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3631642357 Aug 13 05:37:34 PM PDT 24 Aug 13 05:37:37 PM PDT 24 291164627 ps
T1044 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4126379514 Aug 13 05:37:10 PM PDT 24 Aug 13 05:37:11 PM PDT 24 23948561 ps
T1045 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3408439487 Aug 13 05:37:52 PM PDT 24 Aug 13 05:37:56 PM PDT 24 213079429 ps
T1046 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2626849571 Aug 13 05:37:29 PM PDT 24 Aug 13 05:37:33 PM PDT 24 214279496 ps
T1047 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1042934010 Aug 13 05:37:31 PM PDT 24 Aug 13 05:37:33 PM PDT 24 137642549 ps
T1048 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3467538388 Aug 13 05:38:01 PM PDT 24 Aug 13 05:38:02 PM PDT 24 74039881 ps
T1049 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.619800007 Aug 13 05:37:40 PM PDT 24 Aug 13 05:37:46 PM PDT 24 577134804 ps
T147 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2577313479 Aug 13 05:37:57 PM PDT 24 Aug 13 05:38:05 PM PDT 24 809294154 ps
T1050 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.771268812 Aug 13 05:37:27 PM PDT 24 Aug 13 05:37:30 PM PDT 24 92655737 ps
T142 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.473387609 Aug 13 05:37:37 PM PDT 24 Aug 13 05:37:46 PM PDT 24 412405341 ps
T1051 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.583920026 Aug 13 05:37:28 PM PDT 24 Aug 13 05:37:31 PM PDT 24 2264717060 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1961951519 Aug 13 05:37:29 PM PDT 24 Aug 13 05:37:33 PM PDT 24 138834755 ps
T1053 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.25797157 Aug 13 05:37:54 PM PDT 24 Aug 13 05:38:01 PM PDT 24 128816794 ps
T157 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3826584867 Aug 13 05:37:36 PM PDT 24 Aug 13 05:37:41 PM PDT 24 474934241 ps
T1054 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1850700719 Aug 13 05:37:33 PM PDT 24 Aug 13 05:37:35 PM PDT 24 38099970 ps
T1055 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1136917092 Aug 13 05:37:32 PM PDT 24 Aug 13 05:37:33 PM PDT 24 17286243 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2567280796 Aug 13 05:37:22 PM PDT 24 Aug 13 05:37:27 PM PDT 24 217034690 ps
T1057 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.215751138 Aug 13 05:37:45 PM PDT 24 Aug 13 05:37:48 PM PDT 24 504203445 ps
T1058 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2419777884 Aug 13 05:37:31 PM PDT 24 Aug 13 05:37:33 PM PDT 24 59465373 ps
T1059 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2476684006 Aug 13 05:37:31 PM PDT 24 Aug 13 05:37:33 PM PDT 24 92436403 ps
T1060 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2884829777 Aug 13 05:37:28 PM PDT 24 Aug 13 05:37:29 PM PDT 24 28999837 ps
T1061 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3949964666 Aug 13 05:37:35 PM PDT 24 Aug 13 05:37:36 PM PDT 24 39913571 ps
T1062 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3438999183 Aug 13 05:37:49 PM PDT 24 Aug 13 05:37:50 PM PDT 24 30625657 ps
T1063 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1364288623 Aug 13 05:37:58 PM PDT 24 Aug 13 05:38:12 PM PDT 24 725247270 ps
T1064 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.531096894 Aug 13 05:37:52 PM PDT 24 Aug 13 05:37:54 PM PDT 24 24822279 ps
T1065 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1103764772 Aug 13 05:37:45 PM PDT 24 Aug 13 05:37:47 PM PDT 24 18544905 ps
T1066 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3854565200 Aug 13 05:37:50 PM PDT 24 Aug 13 05:37:51 PM PDT 24 22424133 ps
T1067 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1840500385 Aug 13 05:37:42 PM PDT 24 Aug 13 05:37:43 PM PDT 24 20969023 ps
T1068 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4156063273 Aug 13 05:37:43 PM PDT 24 Aug 13 05:37:44 PM PDT 24 40836391 ps
T1069 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2609663757 Aug 13 05:37:35 PM PDT 24 Aug 13 05:37:38 PM PDT 24 80949526 ps
T1070 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2276543155 Aug 13 05:37:38 PM PDT 24 Aug 13 05:37:52 PM PDT 24 1001198007 ps
T1071 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1412761675 Aug 13 05:37:47 PM PDT 24 Aug 13 05:37:49 PM PDT 24 902297272 ps
T1072 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3306157489 Aug 13 05:37:35 PM PDT 24 Aug 13 05:37:36 PM PDT 24 41035341 ps
T141 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1742294877 Aug 13 05:37:33 PM PDT 24 Aug 13 05:37:37 PM PDT 24 60892586 ps
T1073 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3593859225 Aug 13 05:37:21 PM PDT 24 Aug 13 05:37:22 PM PDT 24 59368140 ps
T1074 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2664204008 Aug 13 05:37:48 PM PDT 24 Aug 13 05:37:49 PM PDT 24 56421435 ps
T1075 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2661914775 Aug 13 05:37:54 PM PDT 24 Aug 13 05:37:55 PM PDT 24 45611942 ps
T1076 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1884792080 Aug 13 05:37:42 PM PDT 24 Aug 13 05:38:00 PM PDT 24 595722819 ps
T1077 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1625929456 Aug 13 05:37:21 PM PDT 24 Aug 13 05:37:25 PM PDT 24 1805158089 ps
T158 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1418305900 Aug 13 05:37:42 PM PDT 24 Aug 13 05:37:48 PM PDT 24 98343622 ps
T145 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.258113155 Aug 13 05:37:30 PM PDT 24 Aug 13 05:37:34 PM PDT 24 117756499 ps
T1078 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.715166251 Aug 13 05:37:43 PM PDT 24 Aug 13 05:37:45 PM PDT 24 23966018 ps
T1079 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2050717488 Aug 13 05:37:38 PM PDT 24 Aug 13 05:37:39 PM PDT 24 19592624 ps
T1080 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3124949131 Aug 13 05:37:15 PM PDT 24 Aug 13 05:37:18 PM PDT 24 53068478 ps
T1081 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3504215142 Aug 13 05:37:46 PM PDT 24 Aug 13 05:37:50 PM PDT 24 288742384 ps
T1082 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3487445263 Aug 13 05:37:53 PM PDT 24 Aug 13 05:37:57 PM PDT 24 461448030 ps
T1083 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1448654368 Aug 13 05:37:32 PM PDT 24 Aug 13 05:37:37 PM PDT 24 251042413 ps
T1084 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2450765478 Aug 13 05:37:30 PM PDT 24 Aug 13 05:37:33 PM PDT 24 54272798 ps
T1085 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1884240218 Aug 13 05:37:36 PM PDT 24 Aug 13 05:37:37 PM PDT 24 19735849 ps

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.600953764
Short name T13
Test name
Test status
Simulation time 255120110 ps
CPU time 3.98 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:21 PM PDT 24
Peak memory 215792 kb
Host smart-55060b99-57b9-4517-8125-6c4838b78011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600953764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.600953764
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2000874800
Short name T5
Test name
Test status
Simulation time 3200752412 ps
CPU time 76.8 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:44:46 PM PDT 24
Peak memory 222948 kb
Host smart-7212c495-18ad-403c-9016-26a895685192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000874800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2000874800
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3572020802
Short name T72
Test name
Test status
Simulation time 2430088133 ps
CPU time 25.21 seconds
Started Aug 13 05:43:37 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 222636 kb
Host smart-83001e60-46c7-4db2-a238-05c34edd2f92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572020802 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3572020802
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.582323673
Short name T7
Test name
Test status
Simulation time 822659660 ps
CPU time 38.47 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 216816 kb
Host smart-8f641feb-63c2-4161-9ab4-1effdfe27a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582323673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.582323673
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3653584285
Short name T8
Test name
Test status
Simulation time 940667917 ps
CPU time 13.6 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:23 PM PDT 24
Peak memory 238116 kb
Host smart-f2a5506e-71e9-4ee4-9adb-85e70c549fd5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653584285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3653584285
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.914859987
Short name T1
Test name
Test status
Simulation time 154654049 ps
CPU time 8.1 seconds
Started Aug 13 05:44:22 PM PDT 24
Finished Aug 13 05:44:30 PM PDT 24
Peak memory 214776 kb
Host smart-47e00a33-7642-4d00-bc85-4a2e9f992a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914859987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.914859987
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.46658082
Short name T105
Test name
Test status
Simulation time 670066862 ps
CPU time 12.07 seconds
Started Aug 13 05:37:51 PM PDT 24
Finished Aug 13 05:38:03 PM PDT 24
Peak memory 214948 kb
Host smart-70156a10-c6e1-4b57-8783-92704f6b297f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46658082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_shadow_reg_errors_with_csr_rw.46658082
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3356498643
Short name T48
Test name
Test status
Simulation time 41884636 ps
CPU time 2.98 seconds
Started Aug 13 05:44:22 PM PDT 24
Finished Aug 13 05:44:25 PM PDT 24
Peak memory 214728 kb
Host smart-01a87051-9302-4de4-9a6f-080d1e876e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356498643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3356498643
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2927325738
Short name T42
Test name
Test status
Simulation time 202617297 ps
CPU time 2.53 seconds
Started Aug 13 05:43:55 PM PDT 24
Finished Aug 13 05:43:57 PM PDT 24
Peak memory 220016 kb
Host smart-7ac50b83-db12-4a4e-8cef-a9cfea35589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927325738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2927325738
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2309267038
Short name T61
Test name
Test status
Simulation time 1223074781 ps
CPU time 21.15 seconds
Started Aug 13 05:43:25 PM PDT 24
Finished Aug 13 05:43:47 PM PDT 24
Peak memory 223000 kb
Host smart-9aef2845-9d08-48e9-b098-c9975bb3ff35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309267038 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2309267038
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.208360031
Short name T23
Test name
Test status
Simulation time 626467735 ps
CPU time 9.17 seconds
Started Aug 13 05:42:27 PM PDT 24
Finished Aug 13 05:42:36 PM PDT 24
Peak memory 222920 kb
Host smart-4c7b6517-446f-4cf6-9017-58b75d87acc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208360031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.208360031
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2505246864
Short name T319
Test name
Test status
Simulation time 1508759905 ps
CPU time 39.3 seconds
Started Aug 13 05:43:12 PM PDT 24
Finished Aug 13 05:43:52 PM PDT 24
Peak memory 222872 kb
Host smart-0ccae429-2e70-448e-9d7d-4ce673e35c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505246864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2505246864
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.563990659
Short name T52
Test name
Test status
Simulation time 18016237574 ps
CPU time 168.02 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:46:37 PM PDT 24
Peak memory 223024 kb
Host smart-2dc7faf5-8bb6-4b95-a299-4a69549e3e41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563990659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.563990659
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1814056700
Short name T19
Test name
Test status
Simulation time 140581462 ps
CPU time 2.26 seconds
Started Aug 13 05:44:51 PM PDT 24
Finished Aug 13 05:44:54 PM PDT 24
Peak memory 209208 kb
Host smart-62decefe-efd3-4d21-9cda-760fec10c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814056700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1814056700
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3743532438
Short name T403
Test name
Test status
Simulation time 704484463 ps
CPU time 7.84 seconds
Started Aug 13 05:42:16 PM PDT 24
Finished Aug 13 05:42:24 PM PDT 24
Peak memory 214784 kb
Host smart-d8f2e02f-5a64-458a-b3a6-371f13032f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743532438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3743532438
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1213694292
Short name T4
Test name
Test status
Simulation time 65396516 ps
CPU time 2.93 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:43:34 PM PDT 24
Peak memory 222868 kb
Host smart-6002c3f0-9134-49a5-8d7c-0551076e573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213694292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1213694292
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2897712568
Short name T168
Test name
Test status
Simulation time 93183658 ps
CPU time 4.73 seconds
Started Aug 13 05:43:35 PM PDT 24
Finished Aug 13 05:43:40 PM PDT 24
Peak memory 218968 kb
Host smart-9d6dd566-2862-40af-96e2-ffb51f1d4a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897712568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2897712568
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2721362297
Short name T393
Test name
Test status
Simulation time 528791052 ps
CPU time 14.9 seconds
Started Aug 13 05:42:57 PM PDT 24
Finished Aug 13 05:43:12 PM PDT 24
Peak memory 216396 kb
Host smart-6d13edc1-f307-4bd5-8e6c-0360250ff047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721362297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2721362297
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2245975178
Short name T134
Test name
Test status
Simulation time 259736799 ps
CPU time 4.02 seconds
Started Aug 13 05:42:25 PM PDT 24
Finished Aug 13 05:42:29 PM PDT 24
Peak memory 214696 kb
Host smart-9480ed9e-9e65-445b-bd35-0d33e53364b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245975178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2245975178
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2190667274
Short name T69
Test name
Test status
Simulation time 13401166534 ps
CPU time 211.16 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:48:18 PM PDT 24
Peak memory 218396 kb
Host smart-aca22e7f-9c12-4a6d-bbca-7b84184168a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190667274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2190667274
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2356077057
Short name T113
Test name
Test status
Simulation time 811745344 ps
CPU time 3.01 seconds
Started Aug 13 05:37:45 PM PDT 24
Finished Aug 13 05:37:48 PM PDT 24
Peak memory 214796 kb
Host smart-1ae0dd5f-4e10-4552-b527-f839304b5303
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356077057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2356077057
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3946446029
Short name T140
Test name
Test status
Simulation time 289414996 ps
CPU time 6.9 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:13 PM PDT 24
Peak memory 214812 kb
Host smart-620ed49c-cd21-4342-b771-4f5f3191e15e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946446029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3946446029
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3634271387
Short name T64
Test name
Test status
Simulation time 493957514 ps
CPU time 5.85 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:11 PM PDT 24
Peak memory 210156 kb
Host smart-1d3072a4-3c89-4e66-968a-1228b7829889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634271387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3634271387
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3963804071
Short name T220
Test name
Test status
Simulation time 1153586830 ps
CPU time 8.19 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:54 PM PDT 24
Peak memory 214804 kb
Host smart-96d89e2d-ba9c-4eef-91fc-abb97adcfc85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963804071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3963804071
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1516036807
Short name T125
Test name
Test status
Simulation time 1718256561 ps
CPU time 23.12 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:29 PM PDT 24
Peak memory 223084 kb
Host smart-fa39b76c-5d43-4503-952f-bf43edb05be7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516036807 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1516036807
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3126171431
Short name T30
Test name
Test status
Simulation time 282139952 ps
CPU time 3.07 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:27 PM PDT 24
Peak memory 206620 kb
Host smart-6c93304e-ebd0-465f-8da0-536e91a83c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126171431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3126171431
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.600994494
Short name T392
Test name
Test status
Simulation time 122262124 ps
CPU time 6.7 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:05 PM PDT 24
Peak memory 216068 kb
Host smart-7d81d2e2-0b16-4218-b640-4b587a926542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600994494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.600994494
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1724201079
Short name T182
Test name
Test status
Simulation time 2996413335 ps
CPU time 64.47 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:44:27 PM PDT 24
Peak memory 221344 kb
Host smart-8cc862bf-8a8e-4d3a-bcc7-d45faca76359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724201079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1724201079
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3227917425
Short name T71
Test name
Test status
Simulation time 7974083796 ps
CPU time 21.94 seconds
Started Aug 13 05:44:36 PM PDT 24
Finished Aug 13 05:44:58 PM PDT 24
Peak memory 221636 kb
Host smart-5ce3a63c-7776-493d-8e67-12d9ffde31a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227917425 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3227917425
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1141956580
Short name T12
Test name
Test status
Simulation time 10656793 ps
CPU time 0.83 seconds
Started Aug 13 05:43:36 PM PDT 24
Finished Aug 13 05:43:37 PM PDT 24
Peak memory 206424 kb
Host smart-318c4bf9-a5b7-4a96-a8bb-0281a40d8cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141956580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1141956580
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2736250117
Short name T308
Test name
Test status
Simulation time 265067168 ps
CPU time 6.76 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 215824 kb
Host smart-cbb18b70-2adf-44cf-86f5-bc561c4a78c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736250117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2736250117
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1242616385
Short name T227
Test name
Test status
Simulation time 104162996 ps
CPU time 2.1 seconds
Started Aug 13 05:42:48 PM PDT 24
Finished Aug 13 05:42:51 PM PDT 24
Peak memory 214708 kb
Host smart-8beb4d45-b690-48e2-af70-36de7f0136b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242616385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1242616385
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.291087378
Short name T196
Test name
Test status
Simulation time 2920491905 ps
CPU time 42.01 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:45:29 PM PDT 24
Peak memory 216236 kb
Host smart-3239a71f-6fb1-456a-a775-81e942d0a4f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291087378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.291087378
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3028348701
Short name T149
Test name
Test status
Simulation time 233763234 ps
CPU time 3.54 seconds
Started Aug 13 05:37:13 PM PDT 24
Finished Aug 13 05:37:17 PM PDT 24
Peak memory 214544 kb
Host smart-1d91615f-4b54-4558-93ab-5d31effa7249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028348701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3028348701
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2934497362
Short name T199
Test name
Test status
Simulation time 2996602703 ps
CPU time 71.6 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:45:09 PM PDT 24
Peak memory 222924 kb
Host smart-2bc2cbdf-864b-4bf3-8903-fd64c456eb00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934497362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2934497362
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3875467258
Short name T243
Test name
Test status
Simulation time 3333091746 ps
CPU time 49.35 seconds
Started Aug 13 05:44:15 PM PDT 24
Finished Aug 13 05:45:04 PM PDT 24
Peak memory 215688 kb
Host smart-6ea65dd1-e839-4c67-8b1c-805cb9ccaf3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875467258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3875467258
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2907465676
Short name T70
Test name
Test status
Simulation time 440438480 ps
CPU time 2.93 seconds
Started Aug 13 05:42:43 PM PDT 24
Finished Aug 13 05:42:46 PM PDT 24
Peak memory 223256 kb
Host smart-7206aa09-3d02-4649-b55d-8f60faa779f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907465676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2907465676
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2577313479
Short name T147
Test name
Test status
Simulation time 809294154 ps
CPU time 7.95 seconds
Started Aug 13 05:37:57 PM PDT 24
Finished Aug 13 05:38:05 PM PDT 24
Peak memory 214436 kb
Host smart-9ea90f98-e460-472a-8ece-51f0936b02e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577313479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2577313479
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1811988007
Short name T321
Test name
Test status
Simulation time 188241517 ps
CPU time 2.79 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 209712 kb
Host smart-04bcbc10-6257-4184-8938-74ffd1a4dba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811988007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1811988007
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3060962507
Short name T197
Test name
Test status
Simulation time 690293780 ps
CPU time 17.41 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:27 PM PDT 24
Peak memory 216316 kb
Host smart-70964cda-432b-40f5-8b62-d104dd062f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060962507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3060962507
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2788502798
Short name T240
Test name
Test status
Simulation time 2956248000 ps
CPU time 36.71 seconds
Started Aug 13 05:42:47 PM PDT 24
Finished Aug 13 05:43:23 PM PDT 24
Peak memory 215032 kb
Host smart-f6be927e-4333-4df2-ad71-ff7302fdf48d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788502798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2788502798
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2386366534
Short name T54
Test name
Test status
Simulation time 36451092 ps
CPU time 2.18 seconds
Started Aug 13 05:42:41 PM PDT 24
Finished Aug 13 05:42:43 PM PDT 24
Peak memory 210420 kb
Host smart-5d3f993e-ccbe-4829-90f0-44b6fc6ca3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386366534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2386366534
Directory /workspace/9.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2298622921
Short name T282
Test name
Test status
Simulation time 45014435 ps
CPU time 2.6 seconds
Started Aug 13 05:43:01 PM PDT 24
Finished Aug 13 05:43:03 PM PDT 24
Peak memory 220564 kb
Host smart-da8be28d-7d3b-437a-81d0-3c114d6a20f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298622921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2298622921
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1969400061
Short name T208
Test name
Test status
Simulation time 9930173371 ps
CPU time 58.84 seconds
Started Aug 13 05:44:56 PM PDT 24
Finished Aug 13 05:45:55 PM PDT 24
Peak memory 222920 kb
Host smart-bfc20ce2-0788-4c7b-9edb-afd9f2eaab88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969400061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1969400061
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3222016186
Short name T155
Test name
Test status
Simulation time 192347689 ps
CPU time 5.21 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 214476 kb
Host smart-f296dd30-f4fc-4483-b1f1-65210dc32eca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222016186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3222016186
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2340968777
Short name T89
Test name
Test status
Simulation time 577094703 ps
CPU time 4.93 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 222832 kb
Host smart-6517f335-012c-431d-acf2-1a384b19ca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340968777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2340968777
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3778077945
Short name T330
Test name
Test status
Simulation time 843366700 ps
CPU time 6.03 seconds
Started Aug 13 05:42:41 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 214780 kb
Host smart-e3830f02-9e55-4a16-9da9-292062fd47ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778077945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3778077945
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.994318244
Short name T20
Test name
Test status
Simulation time 341502828 ps
CPU time 2.65 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:03 PM PDT 24
Peak memory 222184 kb
Host smart-99e3552c-8363-4a61-a1cd-296c356213b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994318244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.994318244
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3391057678
Short name T50
Test name
Test status
Simulation time 251375609 ps
CPU time 4.6 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 220396 kb
Host smart-ecb0865e-4748-4fcf-9bcf-12dd6cdb359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391057678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3391057678
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1462380882
Short name T236
Test name
Test status
Simulation time 249897014 ps
CPU time 2.59 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 209012 kb
Host smart-fb8b44f0-9e5a-449c-8d75-978c0d622dc6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462380882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1462380882
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3259051966
Short name T146
Test name
Test status
Simulation time 977381916 ps
CPU time 10.82 seconds
Started Aug 13 05:37:18 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 214492 kb
Host smart-c728ae6a-5597-4077-9353-ff01be34f5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259051966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3259051966
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.258113155
Short name T145
Test name
Test status
Simulation time 117756499 ps
CPU time 4.51 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 215636 kb
Host smart-890d88e2-69f2-48d2-9827-019b9a9b7938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258113155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.258113155
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1418305900
Short name T158
Test name
Test status
Simulation time 98343622 ps
CPU time 5.15 seconds
Started Aug 13 05:37:42 PM PDT 24
Finished Aug 13 05:37:48 PM PDT 24
Peak memory 214572 kb
Host smart-956c2cc3-d61e-469e-b645-7cf32c80d2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418305900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1418305900
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2272291861
Short name T368
Test name
Test status
Simulation time 887588721 ps
CPU time 6.62 seconds
Started Aug 13 05:41:56 PM PDT 24
Finished Aug 13 05:42:02 PM PDT 24
Peak memory 214680 kb
Host smart-f158df11-f2e2-4763-be38-01e97cd35e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272291861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2272291861
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2384075553
Short name T317
Test name
Test status
Simulation time 62435658 ps
CPU time 4.32 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:48 PM PDT 24
Peak memory 215084 kb
Host smart-856d6a15-573e-4211-9007-c041bb979f8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384075553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2384075553
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1133907380
Short name T278
Test name
Test status
Simulation time 62666395 ps
CPU time 2.65 seconds
Started Aug 13 05:42:50 PM PDT 24
Finished Aug 13 05:42:52 PM PDT 24
Peak memory 219812 kb
Host smart-abebf667-7635-4817-9efb-a214e0dcaa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133907380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1133907380
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1769682576
Short name T128
Test name
Test status
Simulation time 129600852 ps
CPU time 3.84 seconds
Started Aug 13 05:42:52 PM PDT 24
Finished Aug 13 05:42:56 PM PDT 24
Peak memory 211508 kb
Host smart-b7ef4c5c-99b7-4495-ab0d-fccab038fef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769682576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1769682576
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.640742167
Short name T262
Test name
Test status
Simulation time 357250020 ps
CPU time 2.81 seconds
Started Aug 13 05:42:19 PM PDT 24
Finished Aug 13 05:42:22 PM PDT 24
Peak memory 214772 kb
Host smart-86fbc971-1f71-458d-b718-e74c86d67dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640742167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.640742167
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3274520410
Short name T257
Test name
Test status
Simulation time 203561048 ps
CPU time 11.18 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:42 PM PDT 24
Peak memory 216172 kb
Host smart-39f25db8-a3a6-4ccb-95d5-e88489c64f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274520410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3274520410
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1013952906
Short name T167
Test name
Test status
Simulation time 184329341 ps
CPU time 4.33 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:27 PM PDT 24
Peak memory 223140 kb
Host smart-ea5ad3f9-c203-4305-8a28-6afe9a175500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013952906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1013952906
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3237799053
Short name T169
Test name
Test status
Simulation time 97674374 ps
CPU time 5.34 seconds
Started Aug 13 05:44:10 PM PDT 24
Finished Aug 13 05:44:15 PM PDT 24
Peak memory 223116 kb
Host smart-2ea0dd39-9572-44c3-a603-ab78670f6ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237799053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3237799053
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.873755108
Short name T170
Test name
Test status
Simulation time 84523572 ps
CPU time 3.64 seconds
Started Aug 13 05:42:56 PM PDT 24
Finished Aug 13 05:43:00 PM PDT 24
Peak memory 218376 kb
Host smart-0191992b-24e7-4f41-9a9d-6b0047225cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873755108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.873755108
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1985641972
Short name T166
Test name
Test status
Simulation time 33275709 ps
CPU time 2.54 seconds
Started Aug 13 05:42:16 PM PDT 24
Finished Aug 13 05:42:19 PM PDT 24
Peak memory 217556 kb
Host smart-ef6c6efe-0135-4b5a-9da8-609c1e4da7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985641972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1985641972
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2151873658
Short name T178
Test name
Test status
Simulation time 85316569 ps
CPU time 1.96 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:11 PM PDT 24
Peak memory 209168 kb
Host smart-01801291-2cbe-4afc-b018-58fd57929ce9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151873658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2151873658
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2007096778
Short name T183
Test name
Test status
Simulation time 5650652778 ps
CPU time 66.41 seconds
Started Aug 13 05:42:43 PM PDT 24
Finished Aug 13 05:43:50 PM PDT 24
Peak memory 222988 kb
Host smart-bf09c8e7-aadf-4dff-b874-660f8a92f733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007096778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2007096778
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.168178309
Short name T574
Test name
Test status
Simulation time 138553252 ps
CPU time 3.24 seconds
Started Aug 13 05:42:58 PM PDT 24
Finished Aug 13 05:43:01 PM PDT 24
Peak memory 222856 kb
Host smart-621a63bf-cd6e-4599-8e69-734ef111c81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168178309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.168178309
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1757667832
Short name T200
Test name
Test status
Simulation time 70925954688 ps
CPU time 353.07 seconds
Started Aug 13 05:42:59 PM PDT 24
Finished Aug 13 05:48:53 PM PDT 24
Peak memory 220532 kb
Host smart-3faf75c8-509c-47e8-9bed-f2abed5319e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757667832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1757667832
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1249212652
Short name T209
Test name
Test status
Simulation time 2147288018 ps
CPU time 66.4 seconds
Started Aug 13 05:42:59 PM PDT 24
Finished Aug 13 05:44:06 PM PDT 24
Peak memory 216268 kb
Host smart-136c7231-f572-43bd-8975-e1bbd0f3201d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249212652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1249212652
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3839101451
Short name T397
Test name
Test status
Simulation time 667267980 ps
CPU time 9.71 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 216316 kb
Host smart-179bb77f-b1c3-4eaf-8645-9b2eb79d8cca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3839101451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3839101451
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2259161934
Short name T364
Test name
Test status
Simulation time 3404844275 ps
CPU time 102.13 seconds
Started Aug 13 05:43:05 PM PDT 24
Finished Aug 13 05:44:47 PM PDT 24
Peak memory 217720 kb
Host smart-d03bf685-3119-4986-8b89-c5b17ed4990e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259161934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2259161934
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.622256802
Short name T339
Test name
Test status
Simulation time 188399190 ps
CPU time 1.57 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:19 PM PDT 24
Peak memory 214708 kb
Host smart-277ff433-dab6-4f9a-bab7-7e0c09392fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622256802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.622256802
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.332025697
Short name T214
Test name
Test status
Simulation time 16705567012 ps
CPU time 170.63 seconds
Started Aug 13 05:44:08 PM PDT 24
Finished Aug 13 05:46:59 PM PDT 24
Peak memory 216868 kb
Host smart-316b2018-2dd3-4acf-aa77-54d4d7496bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332025697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.332025697
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4265398955
Short name T22
Test name
Test status
Simulation time 83598088 ps
CPU time 3.49 seconds
Started Aug 13 05:44:12 PM PDT 24
Finished Aug 13 05:44:16 PM PDT 24
Peak memory 208276 kb
Host smart-e5af3235-0186-4bde-be6b-02c1f44dd2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265398955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4265398955
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1789739236
Short name T407
Test name
Test status
Simulation time 97009965 ps
CPU time 5.93 seconds
Started Aug 13 05:44:51 PM PDT 24
Finished Aug 13 05:44:57 PM PDT 24
Peak memory 214776 kb
Host smart-dc230662-eff7-4ab9-8744-e4b999be1c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1789739236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1789739236
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2958633891
Short name T161
Test name
Test status
Simulation time 372481861 ps
CPU time 5.04 seconds
Started Aug 13 05:37:51 PM PDT 24
Finished Aug 13 05:37:56 PM PDT 24
Peak memory 214416 kb
Host smart-d0db2345-91bf-43e3-a06e-f3fdf90366eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958633891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2958633891
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3925032270
Short name T151
Test name
Test status
Simulation time 896664343 ps
CPU time 8.15 seconds
Started Aug 13 05:37:49 PM PDT 24
Finished Aug 13 05:37:57 PM PDT 24
Peak memory 214424 kb
Host smart-f96620d0-ac1f-49e3-acc3-ca4203b60b47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925032270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3925032270
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1742294877
Short name T141
Test name
Test status
Simulation time 60892586 ps
CPU time 3.18 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 214424 kb
Host smart-5e993c89-1778-45d2-aaf3-1471a724144f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742294877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1742294877
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.473387609
Short name T142
Test name
Test status
Simulation time 412405341 ps
CPU time 8.62 seconds
Started Aug 13 05:37:37 PM PDT 24
Finished Aug 13 05:37:46 PM PDT 24
Peak memory 215768 kb
Host smart-94ce6ace-2354-4a7f-913d-0108488e8e52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473387609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
473387609
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3063688934
Short name T153
Test name
Test status
Simulation time 57069690 ps
CPU time 3.16 seconds
Started Aug 13 05:37:29 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 214592 kb
Host smart-71697fb3-2b71-4d8b-be6d-6d4e58ae73fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063688934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3063688934
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.4027936797
Short name T171
Test name
Test status
Simulation time 567113161 ps
CPU time 1.82 seconds
Started Aug 13 05:44:10 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 217028 kb
Host smart-6dafc9ec-029c-437c-be45-1c39f8ee791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027936797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.4027936797
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3105526096
Short name T163
Test name
Test status
Simulation time 151921176 ps
CPU time 3.08 seconds
Started Aug 13 05:44:53 PM PDT 24
Finished Aug 13 05:44:56 PM PDT 24
Peak memory 211356 kb
Host smart-94013191-3470-4ca0-9abe-7de69ace0b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105526096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3105526096
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1026592274
Short name T58
Test name
Test status
Simulation time 205625880 ps
CPU time 3.22 seconds
Started Aug 13 05:44:20 PM PDT 24
Finished Aug 13 05:44:24 PM PDT 24
Peak memory 223220 kb
Host smart-bd5060a6-57ec-4212-a0ef-c5645acddad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026592274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1026592274
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.648369256
Short name T195
Test name
Test status
Simulation time 43257802 ps
CPU time 1.7 seconds
Started Aug 13 05:42:00 PM PDT 24
Finished Aug 13 05:42:02 PM PDT 24
Peak memory 214716 kb
Host smart-c2851f43-b98f-4d0f-ba34-d6cdb6bdb9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648369256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.648369256
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3400323014
Short name T60
Test name
Test status
Simulation time 51141234 ps
CPU time 2.81 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:12 PM PDT 24
Peak memory 219536 kb
Host smart-109deb25-5d01-460a-a333-f84c97859298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400323014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3400323014
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2763506516
Short name T905
Test name
Test status
Simulation time 900060580 ps
CPU time 12.86 seconds
Started Aug 13 05:42:12 PM PDT 24
Finished Aug 13 05:42:25 PM PDT 24
Peak memory 223060 kb
Host smart-dcbb630b-1422-451e-a48d-590f10c6ca03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763506516 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2763506516
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.180784202
Short name T313
Test name
Test status
Simulation time 150170518 ps
CPU time 4.67 seconds
Started Aug 13 05:42:52 PM PDT 24
Finished Aug 13 05:42:56 PM PDT 24
Peak memory 209056 kb
Host smart-7decfebd-adda-4b00-a9c7-8e6d555f0533
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180784202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.180784202
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3148841082
Short name T323
Test name
Test status
Simulation time 33878755 ps
CPU time 2.36 seconds
Started Aug 13 05:43:01 PM PDT 24
Finished Aug 13 05:43:03 PM PDT 24
Peak memory 214904 kb
Host smart-f3db229a-3d88-4cb1-96c5-e79a725b8d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148841082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3148841082
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1107311065
Short name T640
Test name
Test status
Simulation time 4229092328 ps
CPU time 45.66 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 216204 kb
Host smart-df1f8628-42a6-4db5-893f-11ae517878e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107311065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1107311065
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3748461867
Short name T235
Test name
Test status
Simulation time 76856565 ps
CPU time 3.38 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:12 PM PDT 24
Peak memory 215512 kb
Host smart-e599297d-3702-487e-8f98-9e0e493a53a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748461867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3748461867
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.868710980
Short name T833
Test name
Test status
Simulation time 60116564 ps
CPU time 3.59 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:36 PM PDT 24
Peak memory 214864 kb
Host smart-8cbdff72-bfd8-440e-a206-52db0b38aca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868710980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.868710980
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sideload.901806491
Short name T360
Test name
Test status
Simulation time 72885420 ps
CPU time 3.39 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:36 PM PDT 24
Peak memory 209504 kb
Host smart-59ff0c07-bd00-4830-86ea-d4552e2c3311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901806491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.901806491
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2763129250
Short name T400
Test name
Test status
Simulation time 1098169574 ps
CPU time 4.17 seconds
Started Aug 13 05:43:38 PM PDT 24
Finished Aug 13 05:43:42 PM PDT 24
Peak memory 215876 kb
Host smart-570f7a9e-1a7f-4f9e-89e7-2570bd8d1523
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763129250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2763129250
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.219340091
Short name T300
Test name
Test status
Simulation time 171921149 ps
CPU time 3.01 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:52 PM PDT 24
Peak memory 220748 kb
Host smart-07e478b2-3012-455f-89e0-8d78e4d3b66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219340091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.219340091
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1754663803
Short name T233
Test name
Test status
Simulation time 118029439 ps
CPU time 2.24 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 219580 kb
Host smart-2ecbcb83-e6d4-4611-9cdd-45ef4ce06f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754663803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1754663803
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1728245702
Short name T329
Test name
Test status
Simulation time 104091557 ps
CPU time 4.01 seconds
Started Aug 13 05:44:16 PM PDT 24
Finished Aug 13 05:44:20 PM PDT 24
Peak memory 215232 kb
Host smart-1e4d9889-e07f-44ce-bf8b-e6fb78de070f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728245702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1728245702
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.332118547
Short name T359
Test name
Test status
Simulation time 852935028 ps
CPU time 6.09 seconds
Started Aug 13 05:44:26 PM PDT 24
Finished Aug 13 05:44:33 PM PDT 24
Peak memory 210300 kb
Host smart-39acca09-04df-4893-a9ec-9ee525f73ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332118547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.332118547
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.257254128
Short name T36
Test name
Test status
Simulation time 559033941 ps
CPU time 6.71 seconds
Started Aug 13 05:44:20 PM PDT 24
Finished Aug 13 05:44:27 PM PDT 24
Peak memory 222896 kb
Host smart-a03de59a-4530-4e48-ad60-96e5f5e197e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257254128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.257254128
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.403845366
Short name T929
Test name
Test status
Simulation time 274841786 ps
CPU time 4.66 seconds
Started Aug 13 05:37:46 PM PDT 24
Finished Aug 13 05:37:51 PM PDT 24
Peak memory 206372 kb
Host smart-061dbe8a-cdaf-4792-836b-3bdc3b3b690b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403845366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.403845366
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.330244986
Short name T1018
Test name
Test status
Simulation time 432178373 ps
CPU time 7.41 seconds
Started Aug 13 05:37:26 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206328 kb
Host smart-f50dc386-5050-4c80-b293-f3908416bfce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330244986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.330244986
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2275424589
Short name T1041
Test name
Test status
Simulation time 62539299 ps
CPU time 0.89 seconds
Started Aug 13 05:37:49 PM PDT 24
Finished Aug 13 05:37:50 PM PDT 24
Peak memory 206156 kb
Host smart-2b2d92b4-c162-4e0a-a37b-19190b9427b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275424589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
275424589
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1103764772
Short name T1065
Test name
Test status
Simulation time 18544905 ps
CPU time 1.55 seconds
Started Aug 13 05:37:45 PM PDT 24
Finished Aug 13 05:37:47 PM PDT 24
Peak memory 214644 kb
Host smart-9f75aa51-f4b0-475d-8ee1-18f53e080008
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103764772 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1103764772
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3593859225
Short name T1073
Test name
Test status
Simulation time 59368140 ps
CPU time 1.2 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 206224 kb
Host smart-1a108c42-3ebe-492b-aaf5-4ccd171a54ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593859225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3593859225
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1236437451
Short name T984
Test name
Test status
Simulation time 35539534 ps
CPU time 0.8 seconds
Started Aug 13 05:37:41 PM PDT 24
Finished Aug 13 05:37:42 PM PDT 24
Peak memory 206124 kb
Host smart-d4382427-bd5d-4601-be9a-802916405678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236437451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1236437451
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.739249391
Short name T972
Test name
Test status
Simulation time 167772672 ps
CPU time 2.49 seconds
Started Aug 13 05:37:28 PM PDT 24
Finished Aug 13 05:37:30 PM PDT 24
Peak memory 206296 kb
Host smart-2eaa7790-6bdd-4c3f-9751-0564021ae92b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739249391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.739249391
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.215751138
Short name T1057
Test name
Test status
Simulation time 504203445 ps
CPU time 3.14 seconds
Started Aug 13 05:37:45 PM PDT 24
Finished Aug 13 05:37:48 PM PDT 24
Peak memory 214888 kb
Host smart-83a09bd2-4001-49d5-8984-ff5137fc8d89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215751138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.215751138
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.619800007
Short name T1049
Test name
Test status
Simulation time 577134804 ps
CPU time 6.46 seconds
Started Aug 13 05:37:40 PM PDT 24
Finished Aug 13 05:37:46 PM PDT 24
Peak memory 222980 kb
Host smart-92b45d8a-c2eb-43a5-83a6-40046c256731
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619800007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.619800007
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1188491182
Short name T988
Test name
Test status
Simulation time 117788950 ps
CPU time 2.3 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 214672 kb
Host smart-1bdeb8d2-8ea9-42c5-9e63-9277ae84aa72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188491182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1188491182
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.4262486215
Short name T965
Test name
Test status
Simulation time 759345124 ps
CPU time 4.22 seconds
Started Aug 13 05:37:29 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206352 kb
Host smart-d7cfac33-b944-479a-b4dd-b1368313a417
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262486215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.4
262486215
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2595654371
Short name T1020
Test name
Test status
Simulation time 254445318 ps
CPU time 14.57 seconds
Started Aug 13 05:37:27 PM PDT 24
Finished Aug 13 05:37:42 PM PDT 24
Peak memory 205340 kb
Host smart-08055ab9-afa1-48dd-881c-b4e48aa1cc28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595654371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
595654371
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1415452342
Short name T950
Test name
Test status
Simulation time 69983795 ps
CPU time 1.27 seconds
Started Aug 13 05:37:20 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 206356 kb
Host smart-4345fcad-a98b-4a2c-9c8f-e8fa14222c68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415452342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
415452342
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.880466898
Short name T949
Test name
Test status
Simulation time 27219599 ps
CPU time 1.66 seconds
Started Aug 13 05:37:26 PM PDT 24
Finished Aug 13 05:37:28 PM PDT 24
Peak memory 214620 kb
Host smart-b61eff71-113f-4fc1-8ba4-e97b8729f362
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880466898 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.880466898
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4126379514
Short name T1044
Test name
Test status
Simulation time 23948561 ps
CPU time 1.51 seconds
Started Aug 13 05:37:10 PM PDT 24
Finished Aug 13 05:37:11 PM PDT 24
Peak memory 206364 kb
Host smart-0e9e3f66-8387-418b-987d-675edff6fe6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126379514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4126379514
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3524064051
Short name T1019
Test name
Test status
Simulation time 23897447 ps
CPU time 0.77 seconds
Started Aug 13 05:37:18 PM PDT 24
Finished Aug 13 05:37:19 PM PDT 24
Peak memory 206116 kb
Host smart-6bce423d-5fc3-4db0-9430-57a451fb66c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524064051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3524064051
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3124949131
Short name T1080
Test name
Test status
Simulation time 53068478 ps
CPU time 2.34 seconds
Started Aug 13 05:37:15 PM PDT 24
Finished Aug 13 05:37:18 PM PDT 24
Peak memory 206416 kb
Host smart-90cc835b-a88b-4c2d-9c8e-f2368a8a67bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124949131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3124949131
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1590448669
Short name T111
Test name
Test status
Simulation time 1361641858 ps
CPU time 2.84 seconds
Started Aug 13 05:37:08 PM PDT 24
Finished Aug 13 05:37:11 PM PDT 24
Peak memory 214844 kb
Host smart-7984e1bb-5ddf-4299-b7e5-1e4579636367
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590448669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1590448669
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1519619119
Short name T997
Test name
Test status
Simulation time 667618885 ps
CPU time 8.28 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:39 PM PDT 24
Peak memory 221080 kb
Host smart-339a0ddb-c4a2-4483-ac45-5cd102b77939
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519619119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1519619119
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1961951519
Short name T1052
Test name
Test status
Simulation time 138834755 ps
CPU time 3.07 seconds
Started Aug 13 05:37:29 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 214624 kb
Host smart-fa7f12eb-c7bc-4570-ab71-2c499b43a417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961951519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1961951519
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.69517970
Short name T940
Test name
Test status
Simulation time 92827534 ps
CPU time 1.68 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 214596 kb
Host smart-6ad77252-06e9-4205-a808-7ba354decb36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69517970 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.69517970
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1840500385
Short name T1067
Test name
Test status
Simulation time 20969023 ps
CPU time 0.97 seconds
Started Aug 13 05:37:42 PM PDT 24
Finished Aug 13 05:37:43 PM PDT 24
Peak memory 206080 kb
Host smart-29e06eb0-43fd-453b-aff4-42bfe5ee3194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840500385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1840500385
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.339862636
Short name T1035
Test name
Test status
Simulation time 34826383 ps
CPU time 0.71 seconds
Started Aug 13 05:37:39 PM PDT 24
Finished Aug 13 05:37:40 PM PDT 24
Peak memory 206056 kb
Host smart-4fd994c6-5986-4f6f-9338-6be5890b8b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339862636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.339862636
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.360292491
Short name T999
Test name
Test status
Simulation time 72384367 ps
CPU time 2.4 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 206284 kb
Host smart-496112b6-2387-461c-9868-c9894e2666a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360292491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.360292491
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1884792080
Short name T1076
Test name
Test status
Simulation time 595722819 ps
CPU time 17.32 seconds
Started Aug 13 05:37:42 PM PDT 24
Finished Aug 13 05:38:00 PM PDT 24
Peak memory 221076 kb
Host smart-75df4e45-0580-4f35-94b4-cabc6bdda536
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884792080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1884792080
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3487445263
Short name T1082
Test name
Test status
Simulation time 461448030 ps
CPU time 4.16 seconds
Started Aug 13 05:37:53 PM PDT 24
Finished Aug 13 05:37:57 PM PDT 24
Peak memory 214636 kb
Host smart-accc91cc-afe9-4d82-8937-f4b54d73d115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487445263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3487445263
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1287601406
Short name T143
Test name
Test status
Simulation time 16760221 ps
CPU time 1.36 seconds
Started Aug 13 05:37:37 PM PDT 24
Finished Aug 13 05:37:39 PM PDT 24
Peak memory 214540 kb
Host smart-15d9ea11-c2cd-41ba-ad38-9fb98f92145a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287601406 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1287601406
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3467538388
Short name T1048
Test name
Test status
Simulation time 74039881 ps
CPU time 0.99 seconds
Started Aug 13 05:38:01 PM PDT 24
Finished Aug 13 05:38:02 PM PDT 24
Peak memory 206108 kb
Host smart-230bdac0-23e0-432a-8c23-ae75e898281c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467538388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3467538388
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3306157489
Short name T1072
Test name
Test status
Simulation time 41035341 ps
CPU time 0.72 seconds
Started Aug 13 05:37:35 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 205976 kb
Host smart-49ed0fcb-80dd-4fd9-b239-e8fd2067d1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306157489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3306157489
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1710990049
Short name T931
Test name
Test status
Simulation time 201926862 ps
CPU time 1.8 seconds
Started Aug 13 05:37:51 PM PDT 24
Finished Aug 13 05:37:53 PM PDT 24
Peak memory 206424 kb
Host smart-ae4ebf3b-d1f3-4163-b27a-75d9b5f09032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710990049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1710990049
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.985351115
Short name T974
Test name
Test status
Simulation time 270612031 ps
CPU time 2.57 seconds
Started Aug 13 05:37:28 PM PDT 24
Finished Aug 13 05:37:31 PM PDT 24
Peak memory 214816 kb
Host smart-901e9763-044e-4727-9f1c-1e137474c15c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985351115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.985351115
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1178203307
Short name T1005
Test name
Test status
Simulation time 763874145 ps
CPU time 8.76 seconds
Started Aug 13 05:37:46 PM PDT 24
Finished Aug 13 05:37:55 PM PDT 24
Peak memory 220880 kb
Host smart-19cb1026-b42b-4bf0-bb28-6e2521047ea6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178203307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1178203307
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.626146995
Short name T926
Test name
Test status
Simulation time 152910756 ps
CPU time 3.6 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 214556 kb
Host smart-0954ed3a-ff1a-4922-814b-ebdf09dbb045
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626146995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.626146995
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.715166251
Short name T1078
Test name
Test status
Simulation time 23966018 ps
CPU time 1.61 seconds
Started Aug 13 05:37:43 PM PDT 24
Finished Aug 13 05:37:45 PM PDT 24
Peak memory 214572 kb
Host smart-57efa5eb-2564-4524-8bc0-f23970080a29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715166251 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.715166251
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2394406849
Short name T969
Test name
Test status
Simulation time 19363566 ps
CPU time 1.1 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206228 kb
Host smart-e898daba-f5f9-4b25-9397-0c6c2f7034b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394406849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2394406849
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1981339369
Short name T1016
Test name
Test status
Simulation time 41688997 ps
CPU time 0.81 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 206008 kb
Host smart-0733cb88-4c63-48c1-ae7b-4ea29c188bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981339369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1981339369
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.144273803
Short name T1039
Test name
Test status
Simulation time 158304970 ps
CPU time 1.85 seconds
Started Aug 13 05:37:31 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206356 kb
Host smart-335fc4ed-415f-40eb-b464-9c2cec2cd110
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144273803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.144273803
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1980747895
Short name T109
Test name
Test status
Simulation time 487771827 ps
CPU time 2.32 seconds
Started Aug 13 05:37:44 PM PDT 24
Finished Aug 13 05:37:46 PM PDT 24
Peak memory 214920 kb
Host smart-35ea3c3f-bdec-41ec-a17c-d74bfd4a6a87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980747895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1980747895
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3687203291
Short name T114
Test name
Test status
Simulation time 464722140 ps
CPU time 14.63 seconds
Started Aug 13 05:37:23 PM PDT 24
Finished Aug 13 05:37:38 PM PDT 24
Peak memory 214816 kb
Host smart-6d1fdb12-da77-4e69-9dcb-45fd138632b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687203291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3687203291
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3631642357
Short name T1043
Test name
Test status
Simulation time 291164627 ps
CPU time 2.97 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 216812 kb
Host smart-180c8be1-b8ee-4cab-8f6e-a9b33708de66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631642357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3631642357
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1850700719
Short name T1054
Test name
Test status
Simulation time 38099970 ps
CPU time 1.5 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 214540 kb
Host smart-8865d3e0-e5aa-4799-9cfe-aef1f42e5e6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850700719 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1850700719
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3434310710
Short name T136
Test name
Test status
Simulation time 31977794 ps
CPU time 1.2 seconds
Started Aug 13 05:37:23 PM PDT 24
Finished Aug 13 05:37:25 PM PDT 24
Peak memory 206344 kb
Host smart-b1e065dc-8a98-4aa2-a3d6-f2ade4fe9812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434310710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3434310710
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2664204008
Short name T1074
Test name
Test status
Simulation time 56421435 ps
CPU time 0.75 seconds
Started Aug 13 05:37:48 PM PDT 24
Finished Aug 13 05:37:49 PM PDT 24
Peak memory 206020 kb
Host smart-d52f8ae6-a587-4f10-ba70-6216d6543b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664204008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2664204008
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1196681940
Short name T1034
Test name
Test status
Simulation time 461259086 ps
CPU time 2.16 seconds
Started Aug 13 05:37:46 PM PDT 24
Finished Aug 13 05:37:48 PM PDT 24
Peak memory 206312 kb
Host smart-f9e64d13-305d-44e2-90bc-b50c7cfb6765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196681940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1196681940
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2450765478
Short name T1084
Test name
Test status
Simulation time 54272798 ps
CPU time 2.24 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 219308 kb
Host smart-bcfaa7ea-fc49-4201-b87c-bf86954d0724
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450765478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2450765478
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3568984373
Short name T986
Test name
Test status
Simulation time 284513513 ps
CPU time 3.53 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 214812 kb
Host smart-6b0854e8-bc54-4099-93c8-a8d78c50245b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568984373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3568984373
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2473964093
Short name T1033
Test name
Test status
Simulation time 54558909 ps
CPU time 2 seconds
Started Aug 13 05:37:57 PM PDT 24
Finished Aug 13 05:37:59 PM PDT 24
Peak memory 216856 kb
Host smart-f7016080-3878-4e75-ad1a-bf1aa3bbc3a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473964093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2473964093
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2331288759
Short name T154
Test name
Test status
Simulation time 523151678 ps
CPU time 4.75 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:39 PM PDT 24
Peak memory 214456 kb
Host smart-b509af19-6a50-4a66-b9fe-1bcb51f1c7dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331288759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2331288759
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1515380041
Short name T917
Test name
Test status
Simulation time 247785875 ps
CPU time 1.34 seconds
Started Aug 13 05:37:53 PM PDT 24
Finished Aug 13 05:37:54 PM PDT 24
Peak memory 214568 kb
Host smart-3ccc17fe-d50b-487b-acca-2bc5ce0bc228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515380041 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1515380041
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.158669327
Short name T137
Test name
Test status
Simulation time 14422945 ps
CPU time 1.01 seconds
Started Aug 13 05:37:52 PM PDT 24
Finished Aug 13 05:37:53 PM PDT 24
Peak memory 206220 kb
Host smart-ee719d5b-9131-487a-8f4e-34b4cfb23901
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158669327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.158669327
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3438999183
Short name T1062
Test name
Test status
Simulation time 30625657 ps
CPU time 0.7 seconds
Started Aug 13 05:37:49 PM PDT 24
Finished Aug 13 05:37:50 PM PDT 24
Peak memory 206124 kb
Host smart-2ba2b172-fbfe-4b2e-83c4-ac49a30e8b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438999183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3438999183
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3127963263
Short name T1004
Test name
Test status
Simulation time 49578117 ps
CPU time 2.28 seconds
Started Aug 13 05:37:27 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 206348 kb
Host smart-217f6a9b-73d0-45c9-b623-30bad8b375a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127963263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3127963263
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2297523029
Short name T930
Test name
Test status
Simulation time 535048214 ps
CPU time 2.69 seconds
Started Aug 13 05:37:29 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 214848 kb
Host smart-4a6192b1-daa6-4e90-a44e-2e8cbaba4212
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297523029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2297523029
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1220326731
Short name T995
Test name
Test status
Simulation time 78382864 ps
CPU time 1.49 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 216780 kb
Host smart-c3cab5e7-c8cc-416a-8aa1-b7850711caa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220326731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1220326731
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2818297194
Short name T144
Test name
Test status
Simulation time 929467606 ps
CPU time 5.01 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:38 PM PDT 24
Peak memory 215668 kb
Host smart-ca8af893-47c9-490a-9f98-237d1b9cae33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818297194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2818297194
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2824312445
Short name T1008
Test name
Test status
Simulation time 24184675 ps
CPU time 1.45 seconds
Started Aug 13 05:38:00 PM PDT 24
Finished Aug 13 05:38:01 PM PDT 24
Peak memory 214616 kb
Host smart-32c81103-db2e-47a3-93a2-d172fa293b59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824312445 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2824312445
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1455540335
Short name T982
Test name
Test status
Simulation time 456536923 ps
CPU time 1.66 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 206256 kb
Host smart-d38e5329-1db2-45ed-a9c3-b89bd8ae324c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455540335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1455540335
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3622730704
Short name T1013
Test name
Test status
Simulation time 12403738 ps
CPU time 0.69 seconds
Started Aug 13 05:37:45 PM PDT 24
Finished Aug 13 05:37:46 PM PDT 24
Peak memory 206128 kb
Host smart-58464820-7eae-4417-a8f6-19e690c47c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622730704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3622730704
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1644651331
Short name T1007
Test name
Test status
Simulation time 338025267 ps
CPU time 2.63 seconds
Started Aug 13 05:37:50 PM PDT 24
Finished Aug 13 05:37:53 PM PDT 24
Peak memory 206300 kb
Host smart-c79b6fcb-b4bf-4a0c-9f95-53f55be2db5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644651331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1644651331
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.558069111
Short name T938
Test name
Test status
Simulation time 644730594 ps
CPU time 5.36 seconds
Started Aug 13 05:37:45 PM PDT 24
Finished Aug 13 05:37:51 PM PDT 24
Peak memory 219700 kb
Host smart-1a6614aa-7c0d-4f33-8b22-c5f7a38d0c70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558069111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.558069111
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4069932401
Short name T107
Test name
Test status
Simulation time 843275369 ps
CPU time 8.11 seconds
Started Aug 13 05:37:46 PM PDT 24
Finished Aug 13 05:37:54 PM PDT 24
Peak memory 214920 kb
Host smart-f5ece2e5-b2ac-49ab-b39e-3320ce009f4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069932401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4069932401
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4090538027
Short name T915
Test name
Test status
Simulation time 121336872 ps
CPU time 2.58 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 214628 kb
Host smart-344c085f-2208-4757-8a02-9f44863951d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090538027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4090538027
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3067771806
Short name T160
Test name
Test status
Simulation time 129949829 ps
CPU time 2.66 seconds
Started Aug 13 05:37:46 PM PDT 24
Finished Aug 13 05:37:49 PM PDT 24
Peak memory 214472 kb
Host smart-7623647c-b4f4-46b7-ab7e-8dc80278bcba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067771806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3067771806
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.465086279
Short name T944
Test name
Test status
Simulation time 62008645 ps
CPU time 1.57 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 214492 kb
Host smart-cabf3fb1-e77a-4d05-bc25-1184eeae658a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465086279 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.465086279
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1944667771
Short name T1001
Test name
Test status
Simulation time 61748097 ps
CPU time 1.57 seconds
Started Aug 13 05:38:00 PM PDT 24
Finished Aug 13 05:38:02 PM PDT 24
Peak memory 206368 kb
Host smart-d3b3deed-c88b-4330-a11a-7f399b43d4b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944667771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1944667771
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1128622261
Short name T967
Test name
Test status
Simulation time 41822280 ps
CPU time 0.71 seconds
Started Aug 13 05:37:49 PM PDT 24
Finished Aug 13 05:37:49 PM PDT 24
Peak memory 206000 kb
Host smart-3b86703a-f78e-46fd-be5e-49c0132bb0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128622261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1128622261
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1042934010
Short name T1047
Test name
Test status
Simulation time 137642549 ps
CPU time 1.83 seconds
Started Aug 13 05:37:31 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206180 kb
Host smart-39b24bf0-9f68-4b94-af0f-757cc1bbcfe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042934010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1042934010
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.583920026
Short name T1051
Test name
Test status
Simulation time 2264717060 ps
CPU time 3.63 seconds
Started Aug 13 05:37:28 PM PDT 24
Finished Aug 13 05:37:31 PM PDT 24
Peak memory 214944 kb
Host smart-d5a53155-a53c-4307-9a2c-9cc3c45eadd3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583920026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.583920026
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1046110332
Short name T112
Test name
Test status
Simulation time 148191384 ps
CPU time 3.7 seconds
Started Aug 13 05:37:44 PM PDT 24
Finished Aug 13 05:37:48 PM PDT 24
Peak memory 214960 kb
Host smart-3f0a0093-49b0-41c2-8f21-8716680736d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046110332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1046110332
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3163900565
Short name T921
Test name
Test status
Simulation time 181090201 ps
CPU time 3.52 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 214608 kb
Host smart-bcac7fba-0c72-41d7-ae33-117aa734f74a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163900565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3163900565
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2823928754
Short name T156
Test name
Test status
Simulation time 96711326 ps
CPU time 2.43 seconds
Started Aug 13 05:37:31 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 214540 kb
Host smart-5afe4f4a-3f26-4de5-95c5-f378412818cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823928754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2823928754
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3172218556
Short name T935
Test name
Test status
Simulation time 99150562 ps
CPU time 2.22 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 214636 kb
Host smart-3e0531f2-1cd4-4c12-93e9-ab4e7a717afa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172218556 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3172218556
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4281021251
Short name T998
Test name
Test status
Simulation time 18923858 ps
CPU time 0.98 seconds
Started Aug 13 05:37:28 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 206308 kb
Host smart-3ef6162c-46ff-4b3e-951d-7d74e1a17d33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281021251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4281021251
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1521322054
Short name T964
Test name
Test status
Simulation time 123500837 ps
CPU time 0.79 seconds
Started Aug 13 05:37:38 PM PDT 24
Finished Aug 13 05:37:39 PM PDT 24
Peak memory 205924 kb
Host smart-455281ed-d878-40a9-9eec-e84de459db15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521322054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1521322054
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.876097925
Short name T139
Test name
Test status
Simulation time 35795560 ps
CPU time 2.23 seconds
Started Aug 13 05:37:29 PM PDT 24
Finished Aug 13 05:37:32 PM PDT 24
Peak memory 206376 kb
Host smart-1db4f5ea-a5eb-4809-8064-3fa6ae3099cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876097925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.876097925
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.771268812
Short name T1050
Test name
Test status
Simulation time 92655737 ps
CPU time 2.65 seconds
Started Aug 13 05:37:27 PM PDT 24
Finished Aug 13 05:37:30 PM PDT 24
Peak memory 214896 kb
Host smart-9808137e-aef0-4502-a724-63d4a2e6343f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771268812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.771268812
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2804742241
Short name T106
Test name
Test status
Simulation time 693364943 ps
CPU time 3.84 seconds
Started Aug 13 05:37:26 PM PDT 24
Finished Aug 13 05:37:30 PM PDT 24
Peak memory 214944 kb
Host smart-d1de86a1-f10f-4f34-9a2c-13916ee41fcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804742241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2804742241
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2374703090
Short name T936
Test name
Test status
Simulation time 120524588 ps
CPU time 2.93 seconds
Started Aug 13 05:37:45 PM PDT 24
Finished Aug 13 05:37:48 PM PDT 24
Peak memory 214456 kb
Host smart-5f3a72e5-f1eb-4aaf-af82-f05720ba0566
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374703090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2374703090
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2269612362
Short name T934
Test name
Test status
Simulation time 178617675 ps
CPU time 1.56 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 222668 kb
Host smart-bb50fe0f-d423-4600-b8d8-98fa30e7f78d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269612362 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2269612362
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2661914775
Short name T1075
Test name
Test status
Simulation time 45611942 ps
CPU time 1.06 seconds
Started Aug 13 05:37:54 PM PDT 24
Finished Aug 13 05:37:55 PM PDT 24
Peak memory 206236 kb
Host smart-c3de5246-9a67-4b63-9f92-b338d4591df9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661914775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2661914775
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2795334879
Short name T927
Test name
Test status
Simulation time 11501517 ps
CPU time 0.86 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206120 kb
Host smart-d99c1e23-4a8f-4643-a9ad-12e6051b58af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795334879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2795334879
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2610915241
Short name T1027
Test name
Test status
Simulation time 54433385 ps
CPU time 2.08 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 206344 kb
Host smart-6a83b63e-834f-4c3c-bcd3-06cd99bdbef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610915241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2610915241
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3504215142
Short name T1081
Test name
Test status
Simulation time 288742384 ps
CPU time 3.38 seconds
Started Aug 13 05:37:46 PM PDT 24
Finished Aug 13 05:37:50 PM PDT 24
Peak memory 219492 kb
Host smart-77a07ca0-1e61-42e7-8f94-50c7eed62c87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504215142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3504215142
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3231397782
Short name T993
Test name
Test status
Simulation time 400986000 ps
CPU time 9.14 seconds
Started Aug 13 05:37:51 PM PDT 24
Finished Aug 13 05:38:00 PM PDT 24
Peak memory 214968 kb
Host smart-24093e99-eb9b-4070-9b2a-2de5bc5f49c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231397782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3231397782
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3102499230
Short name T962
Test name
Test status
Simulation time 166197804 ps
CPU time 3.42 seconds
Started Aug 13 05:37:38 PM PDT 24
Finished Aug 13 05:37:42 PM PDT 24
Peak memory 214520 kb
Host smart-a96a00d5-74ba-46f7-9f2a-531f33ee1f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102499230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3102499230
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2785834797
Short name T148
Test name
Test status
Simulation time 116075436 ps
CPU time 2.97 seconds
Started Aug 13 05:37:37 PM PDT 24
Finished Aug 13 05:37:40 PM PDT 24
Peak memory 206184 kb
Host smart-ed1741b9-6095-4b67-b5b5-95b99293d188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785834797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2785834797
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3590107064
Short name T989
Test name
Test status
Simulation time 26916580 ps
CPU time 1.36 seconds
Started Aug 13 05:37:53 PM PDT 24
Finished Aug 13 05:37:54 PM PDT 24
Peak memory 214592 kb
Host smart-442ab68d-5840-44ba-8c34-7bdf55e47721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590107064 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3590107064
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1016130851
Short name T135
Test name
Test status
Simulation time 325744207 ps
CPU time 1.21 seconds
Started Aug 13 05:37:40 PM PDT 24
Finished Aug 13 05:37:42 PM PDT 24
Peak memory 206324 kb
Host smart-7f90326f-7b49-4764-96c0-c100d638b244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016130851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1016130851
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3214821477
Short name T1038
Test name
Test status
Simulation time 9271761 ps
CPU time 0.83 seconds
Started Aug 13 05:37:42 PM PDT 24
Finished Aug 13 05:37:43 PM PDT 24
Peak memory 206068 kb
Host smart-8861a880-77e7-4e87-9418-b0cc4e309432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214821477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3214821477
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2670109688
Short name T932
Test name
Test status
Simulation time 78118339 ps
CPU time 2.48 seconds
Started Aug 13 05:37:40 PM PDT 24
Finished Aug 13 05:37:42 PM PDT 24
Peak memory 206268 kb
Host smart-661d74ca-ea00-49e4-93fa-497f20b35690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670109688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2670109688
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3936275826
Short name T939
Test name
Test status
Simulation time 177963580 ps
CPU time 4.39 seconds
Started Aug 13 05:37:31 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 214864 kb
Host smart-d07c2ac4-84c6-4783-9303-e1010f8f247d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936275826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3936275826
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1364288623
Short name T1063
Test name
Test status
Simulation time 725247270 ps
CPU time 13.26 seconds
Started Aug 13 05:37:58 PM PDT 24
Finished Aug 13 05:38:12 PM PDT 24
Peak memory 222076 kb
Host smart-2f165dc7-ff80-4779-89b9-4979a1b8cc70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364288623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1364288623
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3854565200
Short name T1066
Test name
Test status
Simulation time 22424133 ps
CPU time 1.3 seconds
Started Aug 13 05:37:50 PM PDT 24
Finished Aug 13 05:37:51 PM PDT 24
Peak memory 214640 kb
Host smart-b2eb5853-799c-4a4e-b6fa-8c01799df17b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854565200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3854565200
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2567280796
Short name T1056
Test name
Test status
Simulation time 217034690 ps
CPU time 5.02 seconds
Started Aug 13 05:37:22 PM PDT 24
Finished Aug 13 05:37:27 PM PDT 24
Peak memory 206340 kb
Host smart-39705b51-ec64-4e29-bef7-1f9ad189886e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567280796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
567280796
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2276543155
Short name T1070
Test name
Test status
Simulation time 1001198007 ps
CPU time 14.33 seconds
Started Aug 13 05:37:38 PM PDT 24
Finished Aug 13 05:37:52 PM PDT 24
Peak memory 206348 kb
Host smart-e3a8256b-93c3-42a6-986d-e462a4b79b99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276543155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
276543155
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1423600718
Short name T1037
Test name
Test status
Simulation time 74942849 ps
CPU time 0.97 seconds
Started Aug 13 05:37:11 PM PDT 24
Finished Aug 13 05:37:12 PM PDT 24
Peak memory 206120 kb
Host smart-8d154064-93a3-4e10-bf0d-4bd50eb1318c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423600718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
423600718
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3636985888
Short name T992
Test name
Test status
Simulation time 80509955 ps
CPU time 1.91 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 214620 kb
Host smart-c6f41656-6cef-4616-ad90-73b72aa7d535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636985888 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3636985888
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2319766242
Short name T941
Test name
Test status
Simulation time 56554986 ps
CPU time 1.06 seconds
Started Aug 13 05:37:42 PM PDT 24
Finished Aug 13 05:37:43 PM PDT 24
Peak memory 206180 kb
Host smart-3ae8c7f2-00ce-42a4-bf92-c828fa1939d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319766242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2319766242
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4156063273
Short name T1068
Test name
Test status
Simulation time 40836391 ps
CPU time 0.7 seconds
Started Aug 13 05:37:43 PM PDT 24
Finished Aug 13 05:37:44 PM PDT 24
Peak memory 206088 kb
Host smart-1a81654f-3435-44ef-8d44-90ad7e7bb4e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156063273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4156063273
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.483878172
Short name T1023
Test name
Test status
Simulation time 196695036 ps
CPU time 2.13 seconds
Started Aug 13 05:37:20 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 206344 kb
Host smart-ddbf8501-fcdd-44e9-ae34-19a91836883d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483878172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.483878172
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4156604169
Short name T1032
Test name
Test status
Simulation time 83318149 ps
CPU time 1.67 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:23 PM PDT 24
Peak memory 214796 kb
Host smart-a6b78ade-5079-458b-bdfd-2a53959863d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156604169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4156604169
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1966836703
Short name T960
Test name
Test status
Simulation time 1639337642 ps
CPU time 9.92 seconds
Started Aug 13 05:37:40 PM PDT 24
Finished Aug 13 05:37:50 PM PDT 24
Peak memory 221568 kb
Host smart-43c849f4-1205-4a1d-93b0-7878b9ffd3b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966836703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1966836703
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.983904379
Short name T1036
Test name
Test status
Simulation time 152509878 ps
CPU time 1.78 seconds
Started Aug 13 05:37:44 PM PDT 24
Finished Aug 13 05:37:46 PM PDT 24
Peak memory 214708 kb
Host smart-a3144833-cd2c-47de-906a-840041ca4401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983904379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.983904379
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2081690073
Short name T1031
Test name
Test status
Simulation time 10979766 ps
CPU time 0.75 seconds
Started Aug 13 05:37:51 PM PDT 24
Finished Aug 13 05:37:52 PM PDT 24
Peak memory 206064 kb
Host smart-cf511d7b-4268-4028-81ad-ff0d5f81d82b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081690073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2081690073
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2839196583
Short name T961
Test name
Test status
Simulation time 53281328 ps
CPU time 0.73 seconds
Started Aug 13 05:38:05 PM PDT 24
Finished Aug 13 05:38:06 PM PDT 24
Peak memory 206096 kb
Host smart-1c1de2ad-4f96-4c42-a699-bf65fb66decf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839196583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2839196583
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2619713997
Short name T994
Test name
Test status
Simulation time 20496615 ps
CPU time 0.81 seconds
Started Aug 13 05:37:49 PM PDT 24
Finished Aug 13 05:37:50 PM PDT 24
Peak memory 206124 kb
Host smart-c3019367-6eab-4569-ae5a-1e5e46cb1829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619713997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2619713997
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2960054721
Short name T1028
Test name
Test status
Simulation time 29541956 ps
CPU time 0.71 seconds
Started Aug 13 05:38:00 PM PDT 24
Finished Aug 13 05:38:01 PM PDT 24
Peak memory 206104 kb
Host smart-c15c73de-c568-4f57-a837-9558a8c98eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960054721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2960054721
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2050717488
Short name T1079
Test name
Test status
Simulation time 19592624 ps
CPU time 0.7 seconds
Started Aug 13 05:37:38 PM PDT 24
Finished Aug 13 05:37:39 PM PDT 24
Peak memory 206036 kb
Host smart-24e9c3fb-8b15-467c-aa22-21c9b7d7ef2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050717488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2050717488
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3784848377
Short name T920
Test name
Test status
Simulation time 22791968 ps
CPU time 0.82 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 206008 kb
Host smart-c58daf4e-f460-4386-b73c-afb29bedf902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784848377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3784848377
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4243785475
Short name T996
Test name
Test status
Simulation time 65078877 ps
CPU time 0.7 seconds
Started Aug 13 05:38:03 PM PDT 24
Finished Aug 13 05:38:04 PM PDT 24
Peak memory 206048 kb
Host smart-65e17f61-5c4e-4322-9d91-8ee9588d8cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243785475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.4243785475
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1386463048
Short name T978
Test name
Test status
Simulation time 10095458 ps
CPU time 0.72 seconds
Started Aug 13 05:37:52 PM PDT 24
Finished Aug 13 05:37:53 PM PDT 24
Peak memory 206092 kb
Host smart-a74997cd-d230-48ef-ba04-351f605f2031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386463048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1386463048
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4087161746
Short name T945
Test name
Test status
Simulation time 30025168 ps
CPU time 0.71 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 206052 kb
Host smart-2c27fc2c-5353-4ce7-a36c-7d8c0ccda526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087161746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.4087161746
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.285320882
Short name T985
Test name
Test status
Simulation time 42044058 ps
CPU time 0.79 seconds
Started Aug 13 05:37:55 PM PDT 24
Finished Aug 13 05:38:01 PM PDT 24
Peak memory 206124 kb
Host smart-fec84358-6f6a-496f-963d-633d0ee288bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285320882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.285320882
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3809422778
Short name T966
Test name
Test status
Simulation time 921473552 ps
CPU time 9.4 seconds
Started Aug 13 05:37:20 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 206288 kb
Host smart-f0980426-ec4c-4961-8999-b9eab09fda48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809422778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
809422778
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2023620992
Short name T1025
Test name
Test status
Simulation time 450735047 ps
CPU time 13.04 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:20 PM PDT 24
Peak memory 206304 kb
Host smart-b5dbc7c3-0aec-4e4b-a1a9-c7391b4d8d2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023620992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
023620992
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2454397213
Short name T923
Test name
Test status
Simulation time 54912680 ps
CPU time 0.88 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 206196 kb
Host smart-542e4404-253e-4987-b949-bf2da198a71c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454397213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
454397213
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.558035234
Short name T1030
Test name
Test status
Simulation time 65288392 ps
CPU time 1.42 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:32 PM PDT 24
Peak memory 205288 kb
Host smart-a78cf061-64ff-435f-98bf-99b1c56accca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558035234 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.558035234
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.447491717
Short name T947
Test name
Test status
Simulation time 14578232 ps
CPU time 1 seconds
Started Aug 13 05:37:43 PM PDT 24
Finished Aug 13 05:37:44 PM PDT 24
Peak memory 205292 kb
Host smart-239bf241-b3f6-41ca-b083-336663be818d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447491717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.447491717
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2846092062
Short name T933
Test name
Test status
Simulation time 10325341 ps
CPU time 0.8 seconds
Started Aug 13 05:37:39 PM PDT 24
Finished Aug 13 05:37:40 PM PDT 24
Peak memory 206124 kb
Host smart-78609807-acd2-4dcd-8d83-1c890954e4de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846092062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2846092062
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2364720277
Short name T1015
Test name
Test status
Simulation time 424820082 ps
CPU time 2.61 seconds
Started Aug 13 05:37:54 PM PDT 24
Finished Aug 13 05:37:57 PM PDT 24
Peak memory 206344 kb
Host smart-7a82ce36-7173-48ec-b9ca-22149f6acfc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364720277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2364720277
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2459743226
Short name T991
Test name
Test status
Simulation time 436841664 ps
CPU time 2.77 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 214864 kb
Host smart-b87feea0-8151-4bc8-a3c7-603e25f5f5d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459743226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2459743226
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1456508146
Short name T1042
Test name
Test status
Simulation time 117775414 ps
CPU time 4.89 seconds
Started Aug 13 05:37:59 PM PDT 24
Finished Aug 13 05:38:04 PM PDT 24
Peak memory 214956 kb
Host smart-62fe13db-4815-4ec4-a406-7310f12d11f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456508146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1456508146
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3106183255
Short name T956
Test name
Test status
Simulation time 168995683 ps
CPU time 2.33 seconds
Started Aug 13 05:37:54 PM PDT 24
Finished Aug 13 05:37:56 PM PDT 24
Peak memory 214600 kb
Host smart-a46209d2-6233-4222-87a0-cdd2ca5d5190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106183255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3106183255
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.732786701
Short name T976
Test name
Test status
Simulation time 555305640 ps
CPU time 5.4 seconds
Started Aug 13 05:37:40 PM PDT 24
Finished Aug 13 05:37:45 PM PDT 24
Peak memory 213416 kb
Host smart-e563dfe0-8aa9-4a0d-abb1-e436d507c141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732786701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
732786701
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1685791942
Short name T1017
Test name
Test status
Simulation time 13249195 ps
CPU time 0.79 seconds
Started Aug 13 05:37:48 PM PDT 24
Finished Aug 13 05:37:49 PM PDT 24
Peak memory 205992 kb
Host smart-122c154b-5b32-4109-b402-e7dacfde0a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685791942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1685791942
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1581377747
Short name T968
Test name
Test status
Simulation time 21169688 ps
CPU time 0.77 seconds
Started Aug 13 05:37:52 PM PDT 24
Finished Aug 13 05:37:53 PM PDT 24
Peak memory 205960 kb
Host smart-9f8ccf60-1ad3-4b30-82d0-a3f49854a129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581377747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1581377747
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2037091042
Short name T970
Test name
Test status
Simulation time 20505469 ps
CPU time 0.85 seconds
Started Aug 13 05:37:59 PM PDT 24
Finished Aug 13 05:38:00 PM PDT 24
Peak memory 206124 kb
Host smart-cbd55bea-e574-44ff-8d66-3ebc0db1ee4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037091042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2037091042
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3512544062
Short name T959
Test name
Test status
Simulation time 10691587 ps
CPU time 0.72 seconds
Started Aug 13 05:37:56 PM PDT 24
Finished Aug 13 05:37:57 PM PDT 24
Peak memory 206048 kb
Host smart-cf70cdf3-1da5-4fe9-9acf-7cf1d3a67f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512544062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3512544062
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1745006482
Short name T1022
Test name
Test status
Simulation time 16881416 ps
CPU time 0.84 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 206004 kb
Host smart-864bf0cd-3023-45b7-9bef-5ed318f1ee78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745006482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1745006482
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2826542817
Short name T990
Test name
Test status
Simulation time 33202877 ps
CPU time 0.69 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 206060 kb
Host smart-e8412b04-f7a0-462d-84e6-1ec18ac53f98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826542817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2826542817
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1136917092
Short name T1055
Test name
Test status
Simulation time 17286243 ps
CPU time 0.72 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206060 kb
Host smart-24d33497-2670-41cb-b8de-df3df050834f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136917092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1136917092
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1003809419
Short name T951
Test name
Test status
Simulation time 11282720 ps
CPU time 0.69 seconds
Started Aug 13 05:37:50 PM PDT 24
Finished Aug 13 05:37:51 PM PDT 24
Peak memory 206048 kb
Host smart-8b605ff3-1de6-4cf8-b2c6-d7c46ce5d3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003809419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1003809419
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2377466493
Short name T980
Test name
Test status
Simulation time 35535575 ps
CPU time 0.83 seconds
Started Aug 13 05:37:36 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 206084 kb
Host smart-103b857b-49ae-428e-b66f-b4bff998e1a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377466493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2377466493
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1078354160
Short name T977
Test name
Test status
Simulation time 102926884 ps
CPU time 0.88 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 206092 kb
Host smart-439c3852-62cc-4b80-a6c1-302f413fd56e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078354160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1078354160
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.25797157
Short name T1053
Test name
Test status
Simulation time 128816794 ps
CPU time 7.62 seconds
Started Aug 13 05:37:54 PM PDT 24
Finished Aug 13 05:38:01 PM PDT 24
Peak memory 206400 kb
Host smart-f2c97b3a-f786-4c2e-b26e-6b43abc8fa27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25797157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.25797157
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.510960536
Short name T377
Test name
Test status
Simulation time 3268093445 ps
CPU time 24.96 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:57 PM PDT 24
Peak memory 206476 kb
Host smart-e51d7e80-b5a6-445b-a631-78ecaa679498
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510960536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.510960536
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1548436840
Short name T1014
Test name
Test status
Simulation time 13261674 ps
CPU time 0.99 seconds
Started Aug 13 05:37:48 PM PDT 24
Finished Aug 13 05:37:50 PM PDT 24
Peak memory 206196 kb
Host smart-5ced320b-c7f9-481b-9ffd-027408a27351
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548436840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
548436840
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1180623465
Short name T955
Test name
Test status
Simulation time 93509255 ps
CPU time 1.27 seconds
Started Aug 13 05:37:43 PM PDT 24
Finished Aug 13 05:37:45 PM PDT 24
Peak memory 214568 kb
Host smart-585c7589-df1f-46eb-a7a0-6d33d4682741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180623465 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1180623465
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.350820168
Short name T983
Test name
Test status
Simulation time 10107684 ps
CPU time 0.91 seconds
Started Aug 13 05:37:36 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 206112 kb
Host smart-fb34036b-ca20-4859-945a-24fb7cec4c53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350820168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.350820168
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.120852609
Short name T919
Test name
Test status
Simulation time 43465845 ps
CPU time 0.71 seconds
Started Aug 13 05:37:41 PM PDT 24
Finished Aug 13 05:37:47 PM PDT 24
Peak memory 206124 kb
Host smart-1e18fab7-b133-4934-9923-e0ec6f85c1a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120852609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.120852609
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2419777884
Short name T1058
Test name
Test status
Simulation time 59465373 ps
CPU time 1.94 seconds
Started Aug 13 05:37:31 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206360 kb
Host smart-dfc333e3-2f3b-40f7-bddb-81e566eb27dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419777884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2419777884
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2041635648
Short name T1003
Test name
Test status
Simulation time 113725494 ps
CPU time 4.03 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:25 PM PDT 24
Peak memory 214864 kb
Host smart-0f279d4c-9eac-40cb-a451-c45375e8486c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041635648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2041635648
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2366419489
Short name T981
Test name
Test status
Simulation time 159140655 ps
CPU time 6.91 seconds
Started Aug 13 05:37:15 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 214888 kb
Host smart-95683512-f373-43c5-88c7-91a09ba85475
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366419489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2366419489
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3193425169
Short name T952
Test name
Test status
Simulation time 140107836 ps
CPU time 3.65 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 216624 kb
Host smart-3b17ec79-429e-4835-b26f-7000a199ca85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193425169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3193425169
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3826584867
Short name T157
Test name
Test status
Simulation time 474934241 ps
CPU time 4.57 seconds
Started Aug 13 05:37:36 PM PDT 24
Finished Aug 13 05:37:41 PM PDT 24
Peak memory 214516 kb
Host smart-7ba5e063-ae53-481a-b436-443c23dbcd1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826584867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3826584867
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2866744183
Short name T925
Test name
Test status
Simulation time 56830975 ps
CPU time 0.85 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 206104 kb
Host smart-4b6ac3ea-d0f7-4a22-b82a-55d833fc2560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866744183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2866744183
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.965103817
Short name T957
Test name
Test status
Simulation time 10001421 ps
CPU time 0.82 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 206008 kb
Host smart-903fc0aa-a1ae-4455-8751-4f876f868b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965103817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.965103817
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3949964666
Short name T1061
Test name
Test status
Simulation time 39913571 ps
CPU time 0.85 seconds
Started Aug 13 05:37:35 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 206048 kb
Host smart-ca65e612-3818-46fe-9b30-a934a691c529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949964666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3949964666
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2402404617
Short name T1002
Test name
Test status
Simulation time 15889321 ps
CPU time 0.72 seconds
Started Aug 13 05:38:01 PM PDT 24
Finished Aug 13 05:38:07 PM PDT 24
Peak memory 206024 kb
Host smart-32519678-b9f5-4281-bf76-7fd632c84b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402404617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2402404617
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1749823779
Short name T922
Test name
Test status
Simulation time 10729197 ps
CPU time 0.71 seconds
Started Aug 13 05:37:50 PM PDT 24
Finished Aug 13 05:37:51 PM PDT 24
Peak memory 206020 kb
Host smart-d29d276a-3e60-4e64-9471-8b8efae09cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749823779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1749823779
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2489151295
Short name T937
Test name
Test status
Simulation time 15402536 ps
CPU time 0.8 seconds
Started Aug 13 05:37:58 PM PDT 24
Finished Aug 13 05:37:59 PM PDT 24
Peak memory 206092 kb
Host smart-4d3e5137-f18e-4cea-8832-51f794182626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489151295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2489151295
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3784213124
Short name T1012
Test name
Test status
Simulation time 25993967 ps
CPU time 0.79 seconds
Started Aug 13 05:37:47 PM PDT 24
Finished Aug 13 05:37:48 PM PDT 24
Peak memory 206132 kb
Host smart-0b5a8420-bfee-44e0-b418-955ce445bb70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784213124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3784213124
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2989724962
Short name T958
Test name
Test status
Simulation time 26026461 ps
CPU time 0.69 seconds
Started Aug 13 05:37:40 PM PDT 24
Finished Aug 13 05:37:41 PM PDT 24
Peak memory 206060 kb
Host smart-b84da7d1-89f8-4cd0-a163-e49972960b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989724962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2989724962
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3367525030
Short name T975
Test name
Test status
Simulation time 12835225 ps
CPU time 0.85 seconds
Started Aug 13 05:37:42 PM PDT 24
Finished Aug 13 05:37:43 PM PDT 24
Peak memory 206132 kb
Host smart-b38358b1-42f9-4e24-b372-3a0f83e3a71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367525030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3367525030
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.309795941
Short name T943
Test name
Test status
Simulation time 18272830 ps
CPU time 0.81 seconds
Started Aug 13 05:38:13 PM PDT 24
Finished Aug 13 05:38:14 PM PDT 24
Peak memory 206124 kb
Host smart-26ad4e97-674f-4bef-90a2-62f309871161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309795941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.309795941
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1367904962
Short name T963
Test name
Test status
Simulation time 181002437 ps
CPU time 1.57 seconds
Started Aug 13 05:37:35 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 206444 kb
Host smart-5ee73472-4427-4b9c-bac2-36bfa2ab7b65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367904962 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1367904962
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2884829777
Short name T1060
Test name
Test status
Simulation time 28999837 ps
CPU time 1.19 seconds
Started Aug 13 05:37:28 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 206396 kb
Host smart-8d31c6f0-2a75-477f-9787-632c2d915edb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884829777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2884829777
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1005610055
Short name T924
Test name
Test status
Simulation time 26134015 ps
CPU time 0.72 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:31 PM PDT 24
Peak memory 206100 kb
Host smart-c91f6b74-d794-49d0-a7cd-6a4528599f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005610055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1005610055
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2626849571
Short name T1046
Test name
Test status
Simulation time 214279496 ps
CPU time 3.94 seconds
Started Aug 13 05:37:29 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206244 kb
Host smart-c247227a-1517-4225-841c-5dd14f4c45e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626849571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2626849571
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1625929456
Short name T1077
Test name
Test status
Simulation time 1805158089 ps
CPU time 4.15 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:25 PM PDT 24
Peak memory 214740 kb
Host smart-1ff0ecbc-d624-414d-8593-6a5d97a9c4b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625929456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1625929456
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.503567716
Short name T1006
Test name
Test status
Simulation time 295360361 ps
CPU time 6.87 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:40 PM PDT 24
Peak memory 220996 kb
Host smart-ac90649c-3770-41b5-ad2b-dda11ef0a82e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503567716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.503567716
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.666492312
Short name T916
Test name
Test status
Simulation time 1089245862 ps
CPU time 2.8 seconds
Started Aug 13 05:37:37 PM PDT 24
Finished Aug 13 05:37:40 PM PDT 24
Peak memory 217624 kb
Host smart-34e7332e-8bff-4ee9-b553-1121e94e07cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666492312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.666492312
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2830918757
Short name T165
Test name
Test status
Simulation time 212254378 ps
CPU time 4.95 seconds
Started Aug 13 05:37:44 PM PDT 24
Finished Aug 13 05:37:49 PM PDT 24
Peak memory 215540 kb
Host smart-41104bb3-a7a2-4fb4-b1e7-5962a471a323
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830918757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2830918757
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3932518841
Short name T928
Test name
Test status
Simulation time 33086610 ps
CPU time 1.57 seconds
Started Aug 13 05:37:38 PM PDT 24
Finished Aug 13 05:37:45 PM PDT 24
Peak memory 206296 kb
Host smart-c6258c85-faae-4158-8b82-1c4ca6928f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932518841 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3932518841
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3349134756
Short name T971
Test name
Test status
Simulation time 56108891 ps
CPU time 1.6 seconds
Started Aug 13 05:37:47 PM PDT 24
Finished Aug 13 05:37:49 PM PDT 24
Peak memory 206344 kb
Host smart-34885ede-a7ed-4dbe-ac19-40f1fe346f24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349134756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3349134756
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3407987804
Short name T987
Test name
Test status
Simulation time 12119936 ps
CPU time 0.7 seconds
Started Aug 13 05:37:46 PM PDT 24
Finished Aug 13 05:37:47 PM PDT 24
Peak memory 206124 kb
Host smart-9ec15564-2fe8-423e-853a-699d25865075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407987804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3407987804
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3749361666
Short name T1024
Test name
Test status
Simulation time 492589148 ps
CPU time 1.67 seconds
Started Aug 13 05:37:24 PM PDT 24
Finished Aug 13 05:37:26 PM PDT 24
Peak memory 206392 kb
Host smart-70718f30-b85f-4e9e-926c-68ac77087b60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749361666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3749361666
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.979892032
Short name T953
Test name
Test status
Simulation time 1677753889 ps
CPU time 3.03 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 214920 kb
Host smart-46b4dd90-0e8f-4a9e-8ba5-c9331c6210dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979892032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.979892032
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3891315601
Short name T1021
Test name
Test status
Simulation time 418691901 ps
CPU time 15.02 seconds
Started Aug 13 05:37:48 PM PDT 24
Finished Aug 13 05:38:04 PM PDT 24
Peak memory 223084 kb
Host smart-de98e920-3d14-4b20-bf28-ea0d1ce70588
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891315601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3891315601
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2029515545
Short name T918
Test name
Test status
Simulation time 498763436 ps
CPU time 3.22 seconds
Started Aug 13 05:37:36 PM PDT 24
Finished Aug 13 05:37:39 PM PDT 24
Peak memory 214500 kb
Host smart-f08bc6d0-5022-4450-bda2-47fd4b9671e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029515545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2029515545
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2609663757
Short name T1069
Test name
Test status
Simulation time 80949526 ps
CPU time 2.33 seconds
Started Aug 13 05:37:35 PM PDT 24
Finished Aug 13 05:37:38 PM PDT 24
Peak memory 214648 kb
Host smart-3aecc459-8184-44dc-987e-8ba7ab2ee7ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609663757 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2609663757
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.531096894
Short name T1064
Test name
Test status
Simulation time 24822279 ps
CPU time 1.15 seconds
Started Aug 13 05:37:52 PM PDT 24
Finished Aug 13 05:37:54 PM PDT 24
Peak memory 206396 kb
Host smart-54e92255-32f3-4d4c-98f9-2bddc73ffe42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531096894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.531096894
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2721042319
Short name T954
Test name
Test status
Simulation time 62271001 ps
CPU time 0.76 seconds
Started Aug 13 05:37:28 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 206000 kb
Host smart-85f313c2-5f2e-41d7-95ae-1a02d2b6d709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721042319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2721042319
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3964880556
Short name T1029
Test name
Test status
Simulation time 116146372 ps
CPU time 3.98 seconds
Started Aug 13 05:37:23 PM PDT 24
Finished Aug 13 05:37:27 PM PDT 24
Peak memory 206392 kb
Host smart-5f11044c-02e8-4c4e-8d9c-8ff604b8461a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964880556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3964880556
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1412761675
Short name T1071
Test name
Test status
Simulation time 902297272 ps
CPU time 1.86 seconds
Started Aug 13 05:37:47 PM PDT 24
Finished Aug 13 05:37:49 PM PDT 24
Peak memory 214888 kb
Host smart-65ed6d5d-a7de-4546-902e-35fe2148f0c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412761675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1412761675
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1448654368
Short name T1083
Test name
Test status
Simulation time 251042413 ps
CPU time 4.51 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 214732 kb
Host smart-0f5368d3-0cb5-4cf0-9754-358cebcee4c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448654368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1448654368
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3966659971
Short name T1040
Test name
Test status
Simulation time 614584329 ps
CPU time 2.4 seconds
Started Aug 13 05:37:31 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 214580 kb
Host smart-109f6208-a270-481b-9417-9f61d9ec1471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966659971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3966659971
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2869651768
Short name T1009
Test name
Test status
Simulation time 47709349 ps
CPU time 2.14 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:23 PM PDT 24
Peak memory 214632 kb
Host smart-dfa1ef3b-7c25-4c35-bffa-81cee5446f47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869651768 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2869651768
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2555815563
Short name T1000
Test name
Test status
Simulation time 59917968 ps
CPU time 1.19 seconds
Started Aug 13 05:37:31 PM PDT 24
Finished Aug 13 05:37:32 PM PDT 24
Peak memory 206248 kb
Host smart-12f8dbdf-40e7-47e0-b807-72709add7b24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555815563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2555815563
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1884240218
Short name T1085
Test name
Test status
Simulation time 19735849 ps
CPU time 0.75 seconds
Started Aug 13 05:37:36 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 206060 kb
Host smart-202ba9ef-1ae4-47c5-b6e4-0d75798fed6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884240218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1884240218
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1004306343
Short name T1026
Test name
Test status
Simulation time 69087314 ps
CPU time 2.36 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 206428 kb
Host smart-4c4abd6a-39f7-4c4a-bf01-6da69da8e11c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004306343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1004306343
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3408439487
Short name T1045
Test name
Test status
Simulation time 213079429 ps
CPU time 3.68 seconds
Started Aug 13 05:37:52 PM PDT 24
Finished Aug 13 05:37:56 PM PDT 24
Peak memory 214916 kb
Host smart-641bce17-ee7a-4feb-bfee-140ec109bdac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408439487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3408439487
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2649700277
Short name T946
Test name
Test status
Simulation time 495019317 ps
CPU time 13.24 seconds
Started Aug 13 05:37:27 PM PDT 24
Finished Aug 13 05:37:40 PM PDT 24
Peak memory 214924 kb
Host smart-f5764173-e1aa-40d6-84d9-7a418579cab1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649700277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2649700277
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2453796683
Short name T948
Test name
Test status
Simulation time 176974670 ps
CPU time 3 seconds
Started Aug 13 05:37:25 PM PDT 24
Finished Aug 13 05:37:28 PM PDT 24
Peak memory 214564 kb
Host smart-bc27f121-6907-403d-b635-922ae2bc08e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453796683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2453796683
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.45967937
Short name T374
Test name
Test status
Simulation time 703199344 ps
CPU time 6.35 seconds
Started Aug 13 05:37:45 PM PDT 24
Finished Aug 13 05:37:52 PM PDT 24
Peak memory 214556 kb
Host smart-2a137318-c078-449b-8fa3-66204a75a9dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45967937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.45967937
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2476684006
Short name T1059
Test name
Test status
Simulation time 92436403 ps
CPU time 1.67 seconds
Started Aug 13 05:37:31 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 214648 kb
Host smart-fc969143-7ca5-4fc5-bd11-d31eaf92f430
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476684006 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2476684006
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.482342112
Short name T138
Test name
Test status
Simulation time 13725075 ps
CPU time 1.04 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 206224 kb
Host smart-76da0e65-4f2c-4101-9017-bbdaf3e941ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482342112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.482342112
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3069998708
Short name T973
Test name
Test status
Simulation time 8827938 ps
CPU time 0.77 seconds
Started Aug 13 05:37:49 PM PDT 24
Finished Aug 13 05:37:49 PM PDT 24
Peak memory 206000 kb
Host smart-a4cf8527-8b22-4907-9e63-fdf74d93653e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069998708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3069998708
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3521181689
Short name T942
Test name
Test status
Simulation time 300256992 ps
CPU time 1.52 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:32 PM PDT 24
Peak memory 206320 kb
Host smart-974adc0d-1922-4435-b8ea-5df9d3dec141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521181689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3521181689
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2101521783
Short name T1010
Test name
Test status
Simulation time 126691988 ps
CPU time 1.33 seconds
Started Aug 13 05:37:27 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 215008 kb
Host smart-a3b6c648-09c7-4627-937f-44eea58c69f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101521783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2101521783
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1125949935
Short name T979
Test name
Test status
Simulation time 1164706057 ps
CPU time 4.32 seconds
Started Aug 13 05:37:29 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 214760 kb
Host smart-760b5582-579e-4981-abb3-e8737734330a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125949935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1125949935
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2836705545
Short name T1011
Test name
Test status
Simulation time 174128855 ps
CPU time 3.58 seconds
Started Aug 13 05:37:34 PM PDT 24
Finished Aug 13 05:37:37 PM PDT 24
Peak memory 214628 kb
Host smart-e3e58c2d-9d7b-4104-96d1-8ff0d306c2a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836705545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2836705545
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3891159845
Short name T665
Test name
Test status
Simulation time 39092061 ps
CPU time 0.82 seconds
Started Aug 13 05:42:10 PM PDT 24
Finished Aug 13 05:42:11 PM PDT 24
Peak memory 206424 kb
Host smart-33e197d4-963b-47e5-8457-ae48a7d9a21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891159845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3891159845
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.244889362
Short name T133
Test name
Test status
Simulation time 132313292 ps
CPU time 2.55 seconds
Started Aug 13 05:42:01 PM PDT 24
Finished Aug 13 05:42:04 PM PDT 24
Peak memory 214796 kb
Host smart-76a6ab59-1ef6-4747-a4d1-b797c118d56b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=244889362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.244889362
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1769397748
Short name T796
Test name
Test status
Simulation time 1191823347 ps
CPU time 3.65 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:13 PM PDT 24
Peak memory 222228 kb
Host smart-f275d986-71b0-42a5-8ec6-f9eded1a84de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769397748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1769397748
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.59677654
Short name T298
Test name
Test status
Simulation time 3235740980 ps
CPU time 9.37 seconds
Started Aug 13 05:41:59 PM PDT 24
Finished Aug 13 05:42:08 PM PDT 24
Peak memory 210276 kb
Host smart-7f53f089-a3b9-48c5-9647-3714b6d2c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59677654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.59677654
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1199985480
Short name T514
Test name
Test status
Simulation time 90882644 ps
CPU time 4.67 seconds
Started Aug 13 05:41:57 PM PDT 24
Finished Aug 13 05:42:02 PM PDT 24
Peak memory 218304 kb
Host smart-2f4303d4-6c7c-44a2-a58c-5372523958f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199985480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1199985480
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1743196080
Short name T189
Test name
Test status
Simulation time 1716202162 ps
CPU time 38.4 seconds
Started Aug 13 05:41:58 PM PDT 24
Finished Aug 13 05:42:36 PM PDT 24
Peak memory 218912 kb
Host smart-9f56cbb7-d283-466a-abf6-7afd422fc3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743196080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1743196080
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3014661691
Short name T503
Test name
Test status
Simulation time 119204940 ps
CPU time 3.63 seconds
Started Aug 13 05:41:58 PM PDT 24
Finished Aug 13 05:42:02 PM PDT 24
Peak memory 208672 kb
Host smart-1106142f-789f-4e57-86f6-086d3c08aa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014661691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3014661691
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3278190470
Short name T604
Test name
Test status
Simulation time 60632260 ps
CPU time 2.54 seconds
Started Aug 13 05:41:57 PM PDT 24
Finished Aug 13 05:41:59 PM PDT 24
Peak memory 207916 kb
Host smart-50c00672-6b7d-4f1f-b9d1-16a7694c3543
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278190470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3278190470
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1912643239
Short name T772
Test name
Test status
Simulation time 133151910 ps
CPU time 2.93 seconds
Started Aug 13 05:42:00 PM PDT 24
Finished Aug 13 05:42:03 PM PDT 24
Peak memory 207468 kb
Host smart-46b6b1f4-4a1a-40d7-9737-ff708dbbc69a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912643239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1912643239
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1939919901
Short name T535
Test name
Test status
Simulation time 180015097 ps
CPU time 5.64 seconds
Started Aug 13 05:41:59 PM PDT 24
Finished Aug 13 05:42:04 PM PDT 24
Peak memory 209248 kb
Host smart-5e39cc0e-6d51-4e38-a7d3-8a6de7b58df4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939919901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1939919901
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3697959112
Short name T349
Test name
Test status
Simulation time 5818984567 ps
CPU time 14.91 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:23 PM PDT 24
Peak memory 218860 kb
Host smart-b9abb0d1-e52e-4b8a-ae87-6f013cbe5461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697959112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3697959112
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1049301669
Short name T699
Test name
Test status
Simulation time 236689865 ps
CPU time 2.89 seconds
Started Aug 13 05:42:01 PM PDT 24
Finished Aug 13 05:42:04 PM PDT 24
Peak memory 207260 kb
Host smart-d0c8cea2-baca-471d-aa8e-a8f91893e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049301669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1049301669
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1944249290
Short name T305
Test name
Test status
Simulation time 3952228303 ps
CPU time 85.23 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:43:34 PM PDT 24
Peak memory 222888 kb
Host smart-9f9d8fe6-6f45-47d3-86f8-47af50943aee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944249290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1944249290
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.75543975
Short name T381
Test name
Test status
Simulation time 105338996 ps
CPU time 3.95 seconds
Started Aug 13 05:41:59 PM PDT 24
Finished Aug 13 05:42:03 PM PDT 24
Peak memory 208952 kb
Host smart-6912ce0a-f3ab-4865-8840-bf21099dec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75543975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.75543975
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.932248233
Short name T184
Test name
Test status
Simulation time 591563627 ps
CPU time 3.33 seconds
Started Aug 13 05:42:13 PM PDT 24
Finished Aug 13 05:42:17 PM PDT 24
Peak memory 210268 kb
Host smart-3ed36d34-226e-4ac4-b712-a176101486ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932248233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.932248233
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1734791942
Short name T573
Test name
Test status
Simulation time 26724427 ps
CPU time 0.92 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:09 PM PDT 24
Peak memory 206560 kb
Host smart-334445b3-ac6d-4dfa-b1fa-797a6963b53b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734791942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1734791942
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.352897734
Short name T328
Test name
Test status
Simulation time 198479717 ps
CPU time 3.43 seconds
Started Aug 13 05:42:10 PM PDT 24
Finished Aug 13 05:42:14 PM PDT 24
Peak memory 214784 kb
Host smart-84a96163-d32a-4779-a52c-2e19d6a38c4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352897734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.352897734
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1623734018
Short name T473
Test name
Test status
Simulation time 230062163 ps
CPU time 6.15 seconds
Started Aug 13 05:42:10 PM PDT 24
Finished Aug 13 05:42:16 PM PDT 24
Peak memory 217380 kb
Host smart-8db6e5ef-3b23-468b-9d0d-b9b15ba507d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623734018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1623734018
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1016902232
Short name T765
Test name
Test status
Simulation time 294746262 ps
CPU time 2.09 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:11 PM PDT 24
Peak memory 209928 kb
Host smart-5d02e8dd-8d1b-4478-af8f-3bf99ff24dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016902232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1016902232
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3557857939
Short name T316
Test name
Test status
Simulation time 104589615 ps
CPU time 4.43 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:13 PM PDT 24
Peak memory 214748 kb
Host smart-ad071076-0f67-4119-853d-0957e3936b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557857939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3557857939
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3326941056
Short name T452
Test name
Test status
Simulation time 84660868 ps
CPU time 2.79 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:11 PM PDT 24
Peak memory 211724 kb
Host smart-e5224780-6e3d-4d18-bcbd-2fcad0f1b2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326941056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3326941056
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_random.1949779364
Short name T825
Test name
Test status
Simulation time 777214706 ps
CPU time 7.01 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:17 PM PDT 24
Peak memory 210452 kb
Host smart-480201e4-f382-4a1b-a4c6-7df33e412ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949779364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1949779364
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1352807398
Short name T10
Test name
Test status
Simulation time 890002766 ps
CPU time 5.28 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:15 PM PDT 24
Peak memory 237984 kb
Host smart-46cbc726-34a3-4041-a885-e5bb01e8b2ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352807398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1352807398
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3156940603
Short name T98
Test name
Test status
Simulation time 344442026 ps
CPU time 9.21 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:18 PM PDT 24
Peak memory 208420 kb
Host smart-ba185916-2d37-4bf8-b3e0-7d8e07ad2930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156940603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3156940603
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.314711076
Short name T544
Test name
Test status
Simulation time 456029416 ps
CPU time 3.64 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:12 PM PDT 24
Peak memory 209012 kb
Host smart-749d7852-6049-4fcd-8d67-ee736ba20577
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314711076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.314711076
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3136974967
Short name T180
Test name
Test status
Simulation time 183531624 ps
CPU time 2.78 seconds
Started Aug 13 05:42:07 PM PDT 24
Finished Aug 13 05:42:10 PM PDT 24
Peak memory 209352 kb
Host smart-3b983101-b361-4e51-8713-ff8a5258fac3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136974967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3136974967
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.932004011
Short name T737
Test name
Test status
Simulation time 96964565 ps
CPU time 3.93 seconds
Started Aug 13 05:42:10 PM PDT 24
Finished Aug 13 05:42:14 PM PDT 24
Peak memory 210220 kb
Host smart-7d3c4b06-b1e9-40d3-8acf-10c3e6d41496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932004011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.932004011
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1509885291
Short name T846
Test name
Test status
Simulation time 84714813 ps
CPU time 3.14 seconds
Started Aug 13 05:42:11 PM PDT 24
Finished Aug 13 05:42:15 PM PDT 24
Peak memory 207916 kb
Host smart-b2f7fc14-73b6-421d-a0bf-937026f5da5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509885291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1509885291
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1999317094
Short name T713
Test name
Test status
Simulation time 66661707 ps
CPU time 3.79 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:12 PM PDT 24
Peak memory 210144 kb
Host smart-c2eb424f-00ae-4c2a-a0f0-6c5bbde50b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999317094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1999317094
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1874679684
Short name T807
Test name
Test status
Simulation time 57831927 ps
CPU time 1.7 seconds
Started Aug 13 05:42:11 PM PDT 24
Finished Aug 13 05:42:13 PM PDT 24
Peak memory 210552 kb
Host smart-495ab442-1fde-4543-b0ad-e1c806c0a690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874679684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1874679684
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1633901423
Short name T887
Test name
Test status
Simulation time 19258357 ps
CPU time 0.72 seconds
Started Aug 13 05:42:40 PM PDT 24
Finished Aug 13 05:42:41 PM PDT 24
Peak memory 206424 kb
Host smart-19b765d0-00fc-4682-a91d-84599ff7c79f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633901423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1633901423
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.338214821
Short name T275
Test name
Test status
Simulation time 62076073 ps
CPU time 4.1 seconds
Started Aug 13 05:42:41 PM PDT 24
Finished Aug 13 05:42:45 PM PDT 24
Peak memory 215896 kb
Host smart-4011e716-e5c9-4d33-8ac6-2fa7753c20c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338214821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.338214821
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1119599191
Short name T769
Test name
Test status
Simulation time 51918500 ps
CPU time 1.61 seconds
Started Aug 13 05:42:43 PM PDT 24
Finished Aug 13 05:42:45 PM PDT 24
Peak memory 209756 kb
Host smart-de3d3549-d543-494a-8e4b-baaac92209d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119599191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1119599191
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2700891969
Short name T369
Test name
Test status
Simulation time 532749226 ps
CPU time 8.72 seconds
Started Aug 13 05:42:42 PM PDT 24
Finished Aug 13 05:42:51 PM PDT 24
Peak memory 222172 kb
Host smart-a6ae73fb-3265-4549-9d2a-09866236ac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700891969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2700891969
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.263286921
Short name T741
Test name
Test status
Simulation time 237592858 ps
CPU time 3.39 seconds
Started Aug 13 05:42:43 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 214600 kb
Host smart-e126c3bf-edd2-4cce-bdd7-5cada76dd274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263286921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.263286921
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2592292920
Short name T217
Test name
Test status
Simulation time 145072358 ps
CPU time 3.66 seconds
Started Aug 13 05:42:46 PM PDT 24
Finished Aug 13 05:42:50 PM PDT 24
Peak memory 214764 kb
Host smart-2be88bee-b41c-48e0-ab4b-17624a4d6ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592292920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2592292920
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3331018426
Short name T862
Test name
Test status
Simulation time 82560600 ps
CPU time 4.02 seconds
Started Aug 13 05:42:43 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 207296 kb
Host smart-96536a35-9c53-45ca-9aad-ab73bd06fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331018426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3331018426
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3656456142
Short name T532
Test name
Test status
Simulation time 325658259 ps
CPU time 5.41 seconds
Started Aug 13 05:42:39 PM PDT 24
Finished Aug 13 05:42:45 PM PDT 24
Peak memory 208396 kb
Host smart-ac66a451-b888-44a3-8c7e-3763c5dc3f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656456142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3656456142
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3186188669
Short name T2
Test name
Test status
Simulation time 376634245 ps
CPU time 4.18 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:48 PM PDT 24
Peak memory 209332 kb
Host smart-039074cd-5e99-407f-abec-ff15a4e2f77f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186188669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3186188669
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.201071875
Short name T310
Test name
Test status
Simulation time 104808247 ps
CPU time 1.85 seconds
Started Aug 13 05:42:41 PM PDT 24
Finished Aug 13 05:42:43 PM PDT 24
Peak memory 207372 kb
Host smart-48501105-0e33-4745-9bde-4ec8ecdc64da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201071875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.201071875
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.414313661
Short name T577
Test name
Test status
Simulation time 33709480 ps
CPU time 2.35 seconds
Started Aug 13 05:42:43 PM PDT 24
Finished Aug 13 05:42:46 PM PDT 24
Peak memory 207912 kb
Host smart-54b88eca-747d-4661-9e36-fb6ebc55d82b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414313661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.414313661
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2444972923
Short name T357
Test name
Test status
Simulation time 155701920 ps
CPU time 3.69 seconds
Started Aug 13 05:42:47 PM PDT 24
Finished Aug 13 05:42:50 PM PDT 24
Peak memory 222844 kb
Host smart-9302e660-31d7-48df-b628-01f9b21fa20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444972923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2444972923
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3661921340
Short name T446
Test name
Test status
Simulation time 131394910 ps
CPU time 2.79 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 208600 kb
Host smart-0fd59efe-a13c-40d6-afdc-3b14229acbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661921340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3661921340
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2652543799
Short name T440
Test name
Test status
Simulation time 803365886 ps
CPU time 9.18 seconds
Started Aug 13 05:42:43 PM PDT 24
Finished Aug 13 05:42:53 PM PDT 24
Peak memory 214872 kb
Host smart-6bb4cde2-ea7d-4801-87d9-dd45384337e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652543799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2652543799
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1890047388
Short name T37
Test name
Test status
Simulation time 80100191 ps
CPU time 2.2 seconds
Started Aug 13 05:42:46 PM PDT 24
Finished Aug 13 05:42:49 PM PDT 24
Peak memory 210500 kb
Host smart-441fd052-3578-4733-9a61-63764e02775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890047388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1890047388
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1688616847
Short name T496
Test name
Test status
Simulation time 72102753 ps
CPU time 0.8 seconds
Started Aug 13 05:42:51 PM PDT 24
Finished Aug 13 05:42:52 PM PDT 24
Peak memory 206388 kb
Host smart-37ff41f0-d85e-4b93-a8d0-db9924bfdda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688616847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1688616847
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3503903811
Short name T277
Test name
Test status
Simulation time 35920175 ps
CPU time 2.55 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:46 PM PDT 24
Peak memory 218620 kb
Host smart-41d2c7a3-b832-4d74-bedd-e7c8fe0b084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503903811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3503903811
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3302812678
Short name T92
Test name
Test status
Simulation time 90744000 ps
CPU time 3.93 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:48 PM PDT 24
Peak memory 214772 kb
Host smart-a3322e48-d5bc-4d47-8914-1b38450792a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302812678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3302812678
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3016601561
Short name T219
Test name
Test status
Simulation time 54511012 ps
CPU time 3.34 seconds
Started Aug 13 05:42:48 PM PDT 24
Finished Aug 13 05:42:52 PM PDT 24
Peak memory 209316 kb
Host smart-ddeb3bdb-a87a-4c90-9cea-645ff8199032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016601561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3016601561
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.798687312
Short name T348
Test name
Test status
Simulation time 280993009 ps
CPU time 9.68 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:54 PM PDT 24
Peak memory 214768 kb
Host smart-75cce502-ebd1-4237-91b9-04c2f9cb982c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798687312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.798687312
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.918987215
Short name T288
Test name
Test status
Simulation time 172237071 ps
CPU time 5.36 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:50 PM PDT 24
Peak memory 208920 kb
Host smart-fa79eae1-bed5-4a96-b8ba-70aa744607bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918987215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.918987215
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1186255251
Short name T891
Test name
Test status
Simulation time 197107924 ps
CPU time 2.73 seconds
Started Aug 13 05:42:49 PM PDT 24
Finished Aug 13 05:42:52 PM PDT 24
Peak memory 209340 kb
Host smart-a8bb0127-32cf-408d-a94e-3e5939b30289
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186255251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1186255251
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.681501565
Short name T193
Test name
Test status
Simulation time 119956951 ps
CPU time 2.18 seconds
Started Aug 13 05:42:43 PM PDT 24
Finished Aug 13 05:42:45 PM PDT 24
Peak memory 209324 kb
Host smart-dd358ce7-3c5c-4cf8-bc59-9e65ec69e90d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681501565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.681501565
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3492356454
Short name T295
Test name
Test status
Simulation time 41565393 ps
CPU time 2.4 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 207456 kb
Host smart-466c109d-68b3-4f3d-93ca-eb349d945959
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492356454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3492356454
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1849010448
Short name T609
Test name
Test status
Simulation time 18223496 ps
CPU time 1.42 seconds
Started Aug 13 05:42:48 PM PDT 24
Finished Aug 13 05:42:49 PM PDT 24
Peak memory 207920 kb
Host smart-a4fe9622-2b30-4500-bcc2-3ac4eacc3b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849010448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1849010448
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1648853387
Short name T759
Test name
Test status
Simulation time 190717241 ps
CPU time 2.4 seconds
Started Aug 13 05:42:39 PM PDT 24
Finished Aug 13 05:42:42 PM PDT 24
Peak memory 207272 kb
Host smart-ab5cc3b9-d15c-4974-8c39-1ac59902a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648853387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1648853387
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1100797086
Short name T207
Test name
Test status
Simulation time 2464799320 ps
CPU time 61.06 seconds
Started Aug 13 05:42:52 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 217516 kb
Host smart-95aaf300-8d7f-4580-88db-e8ed9c3c7927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100797086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1100797086
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2529512465
Short name T876
Test name
Test status
Simulation time 203553138 ps
CPU time 8.16 seconds
Started Aug 13 05:42:50 PM PDT 24
Finished Aug 13 05:42:59 PM PDT 24
Peak memory 223100 kb
Host smart-3ee1f286-cb87-4cae-b5bf-38c44df35a03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529512465 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2529512465
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.4079797919
Short name T457
Test name
Test status
Simulation time 190593601 ps
CPU time 6.02 seconds
Started Aug 13 05:42:46 PM PDT 24
Finished Aug 13 05:42:52 PM PDT 24
Peak memory 210300 kb
Host smart-99c3618b-9c3a-44e7-bb16-e8fcc9139bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079797919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.4079797919
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.987054974
Short name T701
Test name
Test status
Simulation time 64586049 ps
CPU time 0.95 seconds
Started Aug 13 05:43:01 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 206612 kb
Host smart-c97b6b77-aeef-498f-bb7a-86ef05a559d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987054974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.987054974
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3895653426
Short name T406
Test name
Test status
Simulation time 136504321 ps
CPU time 3.14 seconds
Started Aug 13 05:42:52 PM PDT 24
Finished Aug 13 05:42:55 PM PDT 24
Peak memory 214888 kb
Host smart-b87d396f-3270-45a9-8dc8-a6af352746db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895653426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3895653426
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.309420610
Short name T599
Test name
Test status
Simulation time 112739899 ps
CPU time 2.54 seconds
Started Aug 13 05:42:49 PM PDT 24
Finished Aug 13 05:42:51 PM PDT 24
Peak memory 209332 kb
Host smart-fc8adc1b-129f-47e6-bab1-e156109744a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309420610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.309420610
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.105883483
Short name T404
Test name
Test status
Simulation time 462781985 ps
CPU time 3.09 seconds
Started Aug 13 05:42:57 PM PDT 24
Finished Aug 13 05:43:01 PM PDT 24
Peak memory 220184 kb
Host smart-a63b475b-5ee3-4598-8239-cb4247097e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105883483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.105883483
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1723582258
Short name T643
Test name
Test status
Simulation time 529594799 ps
CPU time 2.65 seconds
Started Aug 13 05:42:52 PM PDT 24
Finished Aug 13 05:42:55 PM PDT 24
Peak memory 220172 kb
Host smart-fd685325-eee4-414b-8f42-38735963fdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723582258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1723582258
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.4033394400
Short name T903
Test name
Test status
Simulation time 161776191 ps
CPU time 2.62 seconds
Started Aug 13 05:42:47 PM PDT 24
Finished Aug 13 05:42:50 PM PDT 24
Peak memory 207740 kb
Host smart-2087c3e5-d933-4b5d-8fe7-c03d78fcd8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033394400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4033394400
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3999733989
Short name T814
Test name
Test status
Simulation time 1567652484 ps
CPU time 19.7 seconds
Started Aug 13 05:42:48 PM PDT 24
Finished Aug 13 05:43:08 PM PDT 24
Peak memory 209388 kb
Host smart-afa7396f-7cb2-4d2a-a200-7bce0e7c6ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999733989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3999733989
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2276082350
Short name T623
Test name
Test status
Simulation time 396866638 ps
CPU time 4.74 seconds
Started Aug 13 05:42:47 PM PDT 24
Finished Aug 13 05:42:52 PM PDT 24
Peak memory 209452 kb
Host smart-88f39b4c-f579-449a-9300-67e29d197622
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276082350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2276082350
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1233947932
Short name T551
Test name
Test status
Simulation time 811150911 ps
CPU time 4.94 seconds
Started Aug 13 05:42:56 PM PDT 24
Finished Aug 13 05:43:01 PM PDT 24
Peak memory 207424 kb
Host smart-1671d157-76a4-40ba-8673-11fb5ff39653
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233947932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1233947932
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2398083707
Short name T526
Test name
Test status
Simulation time 521664611 ps
CPU time 3.13 seconds
Started Aug 13 05:42:52 PM PDT 24
Finished Aug 13 05:42:55 PM PDT 24
Peak memory 214840 kb
Host smart-d82c62a5-c604-43be-b729-47f1a17a962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398083707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2398083707
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3222539056
Short name T538
Test name
Test status
Simulation time 657313397 ps
CPU time 4.08 seconds
Started Aug 13 05:42:57 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 207284 kb
Host smart-13970568-ad4f-421b-bdf7-756fd772c7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222539056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3222539056
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.744245710
Short name T296
Test name
Test status
Simulation time 75884355 ps
CPU time 3.98 seconds
Started Aug 13 05:42:51 PM PDT 24
Finished Aug 13 05:42:55 PM PDT 24
Peak memory 208904 kb
Host smart-815e12b5-5f4d-48ca-be9a-1654cff42e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744245710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.744245710
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1363016021
Short name T907
Test name
Test status
Simulation time 113318940 ps
CPU time 1.83 seconds
Started Aug 13 05:42:49 PM PDT 24
Finished Aug 13 05:42:51 PM PDT 24
Peak memory 210280 kb
Host smart-a9f1beb0-0502-47c6-9307-de450fa8646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363016021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1363016021
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1538898482
Short name T778
Test name
Test status
Simulation time 20368938 ps
CPU time 0.76 seconds
Started Aug 13 05:42:59 PM PDT 24
Finished Aug 13 05:43:00 PM PDT 24
Peak memory 206396 kb
Host smart-ae60a2f6-bd80-4616-908e-8435f73eefd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538898482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1538898482
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.820410614
Short name T121
Test name
Test status
Simulation time 56339725 ps
CPU time 2.8 seconds
Started Aug 13 05:42:59 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 208100 kb
Host smart-d5939087-2fd9-4439-8c8c-f266d7d45b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820410614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.820410614
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2530962455
Short name T231
Test name
Test status
Simulation time 101464985 ps
CPU time 5.3 seconds
Started Aug 13 05:42:58 PM PDT 24
Finished Aug 13 05:43:03 PM PDT 24
Peak memory 222832 kb
Host smart-056f952b-5a5d-480b-8308-3940ee83c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530962455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2530962455
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2575479808
Short name T600
Test name
Test status
Simulation time 256832639 ps
CPU time 3.64 seconds
Started Aug 13 05:42:58 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 209872 kb
Host smart-07e137a7-ea74-4aa7-9010-28ed45ed5bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575479808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2575479808
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.991611940
Short name T734
Test name
Test status
Simulation time 1735655251 ps
CPU time 62.56 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 210204 kb
Host smart-cbc5786c-7fab-4ae6-abdb-37acb6a65f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991611940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.991611940
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1925787797
Short name T859
Test name
Test status
Simulation time 141859564 ps
CPU time 4.35 seconds
Started Aug 13 05:42:57 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 207844 kb
Host smart-9ac0a26a-63e5-48a1-ab7e-fef975690c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925787797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1925787797
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3758505274
Short name T775
Test name
Test status
Simulation time 55414118 ps
CPU time 2.18 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 209368 kb
Host smart-dfffd95e-a485-4f58-9ba8-18a41c28c967
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758505274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3758505274
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1424379754
Short name T747
Test name
Test status
Simulation time 876534488 ps
CPU time 6.42 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:06 PM PDT 24
Peak memory 208664 kb
Host smart-337ab13f-991c-441f-bd6d-7eaefc98834b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424379754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1424379754
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4261676996
Short name T81
Test name
Test status
Simulation time 242444414 ps
CPU time 2.29 seconds
Started Aug 13 05:42:59 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 207232 kb
Host smart-bb005fed-1372-4e3c-b63a-20db31fdffa6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261676996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4261676996
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1017528027
Short name T485
Test name
Test status
Simulation time 2242115469 ps
CPU time 11.74 seconds
Started Aug 13 05:42:57 PM PDT 24
Finished Aug 13 05:43:09 PM PDT 24
Peak memory 209500 kb
Host smart-4c24f603-e5db-430a-acfd-1d3eac57274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017528027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1017528027
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.225554610
Short name T419
Test name
Test status
Simulation time 237700246 ps
CPU time 2.59 seconds
Started Aug 13 05:42:56 PM PDT 24
Finished Aug 13 05:42:59 PM PDT 24
Peak memory 209120 kb
Host smart-21036da5-a68d-4c41-92d3-3f24933d46cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225554610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.225554610
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3966267578
Short name T853
Test name
Test status
Simulation time 316030327 ps
CPU time 12.94 seconds
Started Aug 13 05:42:58 PM PDT 24
Finished Aug 13 05:43:11 PM PDT 24
Peak memory 220240 kb
Host smart-f568cd03-192f-41b7-9d2a-009ffa941dd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966267578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3966267578
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.770871099
Short name T118
Test name
Test status
Simulation time 336710001 ps
CPU time 12.8 seconds
Started Aug 13 05:43:01 PM PDT 24
Finished Aug 13 05:43:14 PM PDT 24
Peak memory 223060 kb
Host smart-1da313e2-32bf-4386-bf8c-daada0ab8ead
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770871099 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.770871099
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2963826401
Short name T831
Test name
Test status
Simulation time 404401291 ps
CPU time 4.88 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:05 PM PDT 24
Peak memory 210324 kb
Host smart-d8e89ff9-f3fd-4cda-9dc2-c610e390d0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963826401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2963826401
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3947034788
Short name T516
Test name
Test status
Simulation time 46610534 ps
CPU time 2.41 seconds
Started Aug 13 05:42:59 PM PDT 24
Finished Aug 13 05:43:01 PM PDT 24
Peak memory 210256 kb
Host smart-c49d6581-b395-4bf1-9c46-fdec8020d901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947034788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3947034788
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3977168688
Short name T536
Test name
Test status
Simulation time 42422836 ps
CPU time 0.76 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:01 PM PDT 24
Peak memory 206412 kb
Host smart-aa608661-122b-4302-b363-44f60fc99cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977168688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3977168688
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1550470598
Short name T293
Test name
Test status
Simulation time 34804992 ps
CPU time 2.56 seconds
Started Aug 13 05:42:58 PM PDT 24
Finished Aug 13 05:43:00 PM PDT 24
Peak memory 214700 kb
Host smart-15ca5719-a0be-481a-8731-3b64524d3bb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550470598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1550470598
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.208421635
Short name T194
Test name
Test status
Simulation time 684623023 ps
CPU time 10.13 seconds
Started Aug 13 05:42:58 PM PDT 24
Finished Aug 13 05:43:09 PM PDT 24
Peak memory 223172 kb
Host smart-67713994-2753-4912-90b5-377b33f4d449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208421635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.208421635
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.896811229
Short name T620
Test name
Test status
Simulation time 403824994 ps
CPU time 5.81 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:06 PM PDT 24
Peak memory 208908 kb
Host smart-bb96480a-344c-4a7a-ab38-efdbba7ead8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896811229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.896811229
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2696861641
Short name T672
Test name
Test status
Simulation time 40023342 ps
CPU time 1.75 seconds
Started Aug 13 05:42:58 PM PDT 24
Finished Aug 13 05:43:00 PM PDT 24
Peak memory 214780 kb
Host smart-4d77a9e4-3a25-4d8f-a7d3-a88cbab6e89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696861641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2696861641
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1941020952
Short name T593
Test name
Test status
Simulation time 76896243 ps
CPU time 3.87 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:04 PM PDT 24
Peak memory 220708 kb
Host smart-959528dd-5540-40e0-b244-db040f2d989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941020952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1941020952
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.296299965
Short name T583
Test name
Test status
Simulation time 191722596 ps
CPU time 3.61 seconds
Started Aug 13 05:43:02 PM PDT 24
Finished Aug 13 05:43:05 PM PDT 24
Peak memory 208668 kb
Host smart-a2cce841-e7e2-42f2-b38a-29982343f5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296299965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.296299965
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3544257564
Short name T552
Test name
Test status
Simulation time 163003011 ps
CPU time 2.44 seconds
Started Aug 13 05:42:57 PM PDT 24
Finished Aug 13 05:43:00 PM PDT 24
Peak memory 206704 kb
Host smart-2a9d9881-20f6-4ccc-9bd0-6db1b3400466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544257564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3544257564
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.121252273
Short name T890
Test name
Test status
Simulation time 93195974 ps
CPU time 2.61 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 209188 kb
Host smart-b388e7be-8378-4907-8baa-1203e9493041
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121252273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.121252273
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1087830678
Short name T459
Test name
Test status
Simulation time 258670456 ps
CPU time 4.66 seconds
Started Aug 13 05:43:02 PM PDT 24
Finished Aug 13 05:43:06 PM PDT 24
Peak memory 207492 kb
Host smart-e18622b1-69a8-4d30-9b3c-f21984693844
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087830678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1087830678
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1097590603
Short name T332
Test name
Test status
Simulation time 532286302 ps
CPU time 5.91 seconds
Started Aug 13 05:42:59 PM PDT 24
Finished Aug 13 05:43:05 PM PDT 24
Peak memory 209056 kb
Host smart-0923cea1-0382-4a1e-a449-30ab29b6d670
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097590603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1097590603
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2519477311
Short name T910
Test name
Test status
Simulation time 21793564 ps
CPU time 1.8 seconds
Started Aug 13 05:42:56 PM PDT 24
Finished Aug 13 05:42:58 PM PDT 24
Peak memory 209208 kb
Host smart-685663e6-5cc4-4f20-9fe2-a29e1ec3e834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519477311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2519477311
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3524678785
Short name T463
Test name
Test status
Simulation time 288321430 ps
CPU time 3.49 seconds
Started Aug 13 05:42:56 PM PDT 24
Finished Aug 13 05:43:00 PM PDT 24
Peak memory 207092 kb
Host smart-1bc41bee-63a6-4391-a7f3-a2d488b262ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524678785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3524678785
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.951576093
Short name T347
Test name
Test status
Simulation time 1418855676 ps
CPU time 14.58 seconds
Started Aug 13 05:43:01 PM PDT 24
Finished Aug 13 05:43:15 PM PDT 24
Peak memory 223024 kb
Host smart-a42d85aa-cca2-4b3a-ab99-e4d225b7600c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951576093 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.951576093
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2068632192
Short name T467
Test name
Test status
Simulation time 58700897 ps
CPU time 3.79 seconds
Started Aug 13 05:43:01 PM PDT 24
Finished Aug 13 05:43:05 PM PDT 24
Peak memory 218708 kb
Host smart-d4fb031a-9954-4749-9e28-ced2c615c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068632192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2068632192
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3630131631
Short name T108
Test name
Test status
Simulation time 78252056 ps
CPU time 2 seconds
Started Aug 13 05:42:59 PM PDT 24
Finished Aug 13 05:43:01 PM PDT 24
Peak memory 210744 kb
Host smart-1c60199e-5d81-4113-926e-978a106ad8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630131631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3630131631
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3150015780
Short name T413
Test name
Test status
Simulation time 42221427 ps
CPU time 0.88 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:08 PM PDT 24
Peak memory 206380 kb
Host smart-915ac268-a656-41d7-8e18-5e6001ca8b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150015780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3150015780
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2661649308
Short name T692
Test name
Test status
Simulation time 680577948 ps
CPU time 4.89 seconds
Started Aug 13 05:43:04 PM PDT 24
Finished Aug 13 05:43:09 PM PDT 24
Peak memory 209208 kb
Host smart-765e9602-fd11-432e-a3e4-04b29e63c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661649308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2661649308
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2466925385
Short name T854
Test name
Test status
Simulation time 63012217 ps
CPU time 2.26 seconds
Started Aug 13 05:43:10 PM PDT 24
Finished Aug 13 05:43:12 PM PDT 24
Peak memory 208284 kb
Host smart-a18b5a3d-1051-4c8f-8ebb-22fab3f27966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466925385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2466925385
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2922776894
Short name T646
Test name
Test status
Simulation time 954316321 ps
CPU time 6.41 seconds
Started Aug 13 05:43:08 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 214876 kb
Host smart-f337874d-0bdf-4d4d-807f-8f566f52b3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922776894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2922776894
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3610741677
Short name T265
Test name
Test status
Simulation time 799902520 ps
CPU time 2.5 seconds
Started Aug 13 05:43:05 PM PDT 24
Finished Aug 13 05:43:08 PM PDT 24
Peak memory 214704 kb
Host smart-251d3bdf-9afc-4b3f-b110-b2cec5c21eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610741677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3610741677
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.342951048
Short name T464
Test name
Test status
Simulation time 284023020 ps
CPU time 2.44 seconds
Started Aug 13 05:43:08 PM PDT 24
Finished Aug 13 05:43:11 PM PDT 24
Peak memory 219228 kb
Host smart-950939d2-fe30-493a-a543-21b6b8f3851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342951048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.342951048
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.674228117
Short name T33
Test name
Test status
Simulation time 124062696 ps
CPU time 5.59 seconds
Started Aug 13 05:43:10 PM PDT 24
Finished Aug 13 05:43:15 PM PDT 24
Peak memory 208212 kb
Host smart-e82ec6b4-e98d-4896-ac26-56cf5db90ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674228117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.674228117
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3229040904
Short name T820
Test name
Test status
Simulation time 583532462 ps
CPU time 2.65 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:03 PM PDT 24
Peak memory 207212 kb
Host smart-98c028f9-de57-47fc-ab00-7d0004cd0225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229040904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3229040904
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3297125913
Short name T719
Test name
Test status
Simulation time 87031334 ps
CPU time 3.83 seconds
Started Aug 13 05:42:58 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 209352 kb
Host smart-e7974f42-fbaa-4e9b-b02e-70f0ee005dc1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297125913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3297125913
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2811061233
Short name T460
Test name
Test status
Simulation time 164617784 ps
CPU time 2.58 seconds
Started Aug 13 05:43:00 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 209420 kb
Host smart-6693296a-9aad-4974-9257-f0aa6dabd6e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811061233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2811061233
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.4072920452
Short name T580
Test name
Test status
Simulation time 1389823037 ps
CPU time 3.98 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:10 PM PDT 24
Peak memory 209272 kb
Host smart-f635a0c9-aab4-4581-be5f-42f08a64c075
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072920452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4072920452
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.296376872
Short name T693
Test name
Test status
Simulation time 43860798 ps
CPU time 2.19 seconds
Started Aug 13 05:43:03 PM PDT 24
Finished Aug 13 05:43:05 PM PDT 24
Peak memory 210416 kb
Host smart-2ff228e0-1710-444a-87a0-130814bd0c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296376872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.296376872
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.4256259884
Short name T720
Test name
Test status
Simulation time 5472315588 ps
CPU time 18.31 seconds
Started Aug 13 05:42:58 PM PDT 24
Finished Aug 13 05:43:17 PM PDT 24
Peak memory 209028 kb
Host smart-86980942-40eb-4d58-bd9c-103b622682a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256259884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4256259884
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1280243263
Short name T863
Test name
Test status
Simulation time 276062584 ps
CPU time 11.75 seconds
Started Aug 13 05:43:11 PM PDT 24
Finished Aug 13 05:43:23 PM PDT 24
Peak memory 223072 kb
Host smart-1f1b95ac-2c48-4aba-8ce9-9283936d7bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280243263 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1280243263
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.211812140
Short name T683
Test name
Test status
Simulation time 105774425 ps
CPU time 4.79 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:12 PM PDT 24
Peak memory 218660 kb
Host smart-c91f9c0e-5982-40e5-8773-4875546a1319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211812140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.211812140
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.742152752
Short name T41
Test name
Test status
Simulation time 163149563 ps
CPU time 1.5 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:07 PM PDT 24
Peak memory 210376 kb
Host smart-650e18ba-e871-4244-b461-2e073aff68a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742152752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.742152752
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.478596683
Short name T668
Test name
Test status
Simulation time 23130188 ps
CPU time 0.74 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:07 PM PDT 24
Peak memory 206412 kb
Host smart-cdd2c364-27d6-4459-a1a2-a2977f00758f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478596683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.478596683
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2578273310
Short name T379
Test name
Test status
Simulation time 997631795 ps
CPU time 2.76 seconds
Started Aug 13 05:43:05 PM PDT 24
Finished Aug 13 05:43:08 PM PDT 24
Peak memory 209552 kb
Host smart-e3fe93b5-4666-4b5e-a395-346ead9a7aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578273310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2578273310
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.4002773337
Short name T354
Test name
Test status
Simulation time 301324045 ps
CPU time 2.69 seconds
Started Aug 13 05:43:08 PM PDT 24
Finished Aug 13 05:43:11 PM PDT 24
Peak memory 209576 kb
Host smart-5e6e005e-3654-4d82-bddd-43c897b8b5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002773337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.4002773337
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.350306926
Short name T85
Test name
Test status
Simulation time 1028954238 ps
CPU time 3.44 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:10 PM PDT 24
Peak memory 214732 kb
Host smart-38fe2806-167b-46f4-849f-4ba1d0d8ac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350306926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.350306926
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2714736234
Short name T815
Test name
Test status
Simulation time 357488754 ps
CPU time 5.11 seconds
Started Aug 13 05:43:08 PM PDT 24
Finished Aug 13 05:43:14 PM PDT 24
Peak memory 222856 kb
Host smart-3265c4c6-3880-422c-b284-e9cb18b0f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714736234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2714736234
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.468978013
Short name T218
Test name
Test status
Simulation time 110175193 ps
CPU time 4.79 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:11 PM PDT 24
Peak memory 211088 kb
Host smart-85146c37-9ac1-4a20-8533-56882aaf458e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468978013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.468978013
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3629994140
Short name T673
Test name
Test status
Simulation time 110528724 ps
CPU time 4.84 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:12 PM PDT 24
Peak memory 209784 kb
Host smart-7a7ef631-e3a3-49ce-b93b-8fa9a3b90874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629994140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3629994140
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.451498475
Short name T606
Test name
Test status
Simulation time 638960111 ps
CPU time 5.41 seconds
Started Aug 13 05:43:11 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 209232 kb
Host smart-35882c4a-f035-48ba-9f84-3c671603c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451498475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.451498475
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.462314745
Short name T594
Test name
Test status
Simulation time 576807572 ps
CPU time 4.7 seconds
Started Aug 13 05:43:11 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 207544 kb
Host smart-a54e12bf-4a63-4db8-96db-c8598d3cf655
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462314745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.462314745
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3641872853
Short name T355
Test name
Test status
Simulation time 28890335 ps
CPU time 2.2 seconds
Started Aug 13 05:43:05 PM PDT 24
Finished Aug 13 05:43:07 PM PDT 24
Peak memory 207444 kb
Host smart-50cb8378-1b4a-4268-95c7-4877d22562dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641872853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3641872853
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1246494827
Short name T835
Test name
Test status
Simulation time 249541988 ps
CPU time 2.88 seconds
Started Aug 13 05:43:05 PM PDT 24
Finished Aug 13 05:43:08 PM PDT 24
Peak memory 207396 kb
Host smart-0b0a6952-aefe-4eb8-b0c4-d5c0f5a4cb3a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246494827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1246494827
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3191046119
Short name T415
Test name
Test status
Simulation time 209622225 ps
CPU time 2.01 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:08 PM PDT 24
Peak memory 209316 kb
Host smart-ca223b05-4826-447d-909d-1c37415efa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191046119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3191046119
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1827464119
Short name T824
Test name
Test status
Simulation time 306925156 ps
CPU time 7.53 seconds
Started Aug 13 05:43:05 PM PDT 24
Finished Aug 13 05:43:13 PM PDT 24
Peak memory 208368 kb
Host smart-0dd717bb-2812-4908-8b99-f1e629400818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827464119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1827464119
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3309931129
Short name T506
Test name
Test status
Simulation time 136245205 ps
CPU time 5.35 seconds
Started Aug 13 05:43:08 PM PDT 24
Finished Aug 13 05:43:14 PM PDT 24
Peak memory 223072 kb
Host smart-e2ce0680-26c6-4d9b-9947-11c0bdc4982b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309931129 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3309931129
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3678236889
Short name T697
Test name
Test status
Simulation time 116519391 ps
CPU time 3.08 seconds
Started Aug 13 05:43:05 PM PDT 24
Finished Aug 13 05:43:09 PM PDT 24
Peak memory 208812 kb
Host smart-b4d07662-2a0c-4215-8cc7-e7e632844d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678236889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3678236889
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.590160426
Short name T373
Test name
Test status
Simulation time 60584349 ps
CPU time 1.78 seconds
Started Aug 13 05:43:11 PM PDT 24
Finished Aug 13 05:43:13 PM PDT 24
Peak memory 210484 kb
Host smart-2f301e0b-584e-45f6-98d9-1c5e69ad2cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590160426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.590160426
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1854406399
Short name T11
Test name
Test status
Simulation time 19679130 ps
CPU time 0.73 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:07 PM PDT 24
Peak memory 206308 kb
Host smart-4a586b79-6a60-4fd5-bb5f-dae260c44d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854406399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1854406399
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3372465405
Short name T396
Test name
Test status
Simulation time 626615878 ps
CPU time 10.73 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:18 PM PDT 24
Peak memory 223040 kb
Host smart-8976a1bc-fcac-41f8-8a81-a481f2ce5311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372465405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3372465405
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4003490587
Short name T850
Test name
Test status
Simulation time 157435283 ps
CPU time 6.66 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:12 PM PDT 24
Peak memory 210760 kb
Host smart-43a63f54-01d0-498a-ba3e-8436c1a7349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003490587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4003490587
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.655084016
Short name T312
Test name
Test status
Simulation time 81342953 ps
CPU time 3.79 seconds
Started Aug 13 05:43:10 PM PDT 24
Finished Aug 13 05:43:14 PM PDT 24
Peak memory 210596 kb
Host smart-f4ca9262-f1e2-4c5c-b897-c6e902918989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655084016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.655084016
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1093723424
Short name T860
Test name
Test status
Simulation time 203884920 ps
CPU time 5.75 seconds
Started Aug 13 05:43:08 PM PDT 24
Finished Aug 13 05:43:15 PM PDT 24
Peak memory 220936 kb
Host smart-b520ce3f-798e-4127-a9ca-f46f48e3a85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093723424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1093723424
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3877932521
Short name T682
Test name
Test status
Simulation time 534905828 ps
CPU time 5.82 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:13 PM PDT 24
Peak memory 215324 kb
Host smart-7c30f0bd-d7d9-470b-83a4-7b8012edbe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877932521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3877932521
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.384563986
Short name T291
Test name
Test status
Simulation time 328230445 ps
CPU time 4.01 seconds
Started Aug 13 05:43:11 PM PDT 24
Finished Aug 13 05:43:15 PM PDT 24
Peak memory 208600 kb
Host smart-bf382a5a-d911-4d26-921b-5e3dc09ba147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384563986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.384563986
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2251892354
Short name T491
Test name
Test status
Simulation time 3894021344 ps
CPU time 19.01 seconds
Started Aug 13 05:43:11 PM PDT 24
Finished Aug 13 05:43:31 PM PDT 24
Peak memory 209052 kb
Host smart-055c9a01-2363-4eb9-9f5e-f8a64899d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251892354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2251892354
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.793528027
Short name T880
Test name
Test status
Simulation time 304781869 ps
CPU time 5.14 seconds
Started Aug 13 05:43:08 PM PDT 24
Finished Aug 13 05:43:14 PM PDT 24
Peak memory 208388 kb
Host smart-59428f34-1192-4849-8e56-394550288cd5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793528027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.793528027
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.873559963
Short name T350
Test name
Test status
Simulation time 177756194 ps
CPU time 5.16 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:12 PM PDT 24
Peak memory 209060 kb
Host smart-4658362d-d94e-4982-99c2-f6c1e1d5064b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873559963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.873559963
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1395107739
Short name T589
Test name
Test status
Simulation time 700792357 ps
CPU time 22.63 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:30 PM PDT 24
Peak memory 208988 kb
Host smart-0287e611-0197-4192-9401-1e9e5b7cb678
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395107739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1395107739
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.766618983
Short name T3
Test name
Test status
Simulation time 34766954 ps
CPU time 2.5 seconds
Started Aug 13 05:43:05 PM PDT 24
Finished Aug 13 05:43:08 PM PDT 24
Peak memory 218612 kb
Host smart-abe7c713-8930-4d87-be84-dd14587aa463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766618983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.766618983
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.258424700
Short name T505
Test name
Test status
Simulation time 121124330 ps
CPU time 4.37 seconds
Started Aug 13 05:43:11 PM PDT 24
Finished Aug 13 05:43:15 PM PDT 24
Peak memory 209024 kb
Host smart-09d44590-c271-4728-b969-3853a879f95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258424700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.258424700
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.583787307
Short name T272
Test name
Test status
Simulation time 839136124 ps
CPU time 12.08 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:18 PM PDT 24
Peak memory 216668 kb
Host smart-0e89f309-c589-4bba-ae8e-2dfb5006b7ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583787307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.583787307
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2137312488
Short name T175
Test name
Test status
Simulation time 342493408 ps
CPU time 6.86 seconds
Started Aug 13 05:43:10 PM PDT 24
Finished Aug 13 05:43:17 PM PDT 24
Peak memory 219288 kb
Host smart-155cacc7-d6a5-4dca-b8e6-5eec3d455ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137312488 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2137312488
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2023757304
Short name T826
Test name
Test status
Simulation time 178397832 ps
CPU time 5.94 seconds
Started Aug 13 05:43:07 PM PDT 24
Finished Aug 13 05:43:13 PM PDT 24
Peak memory 214700 kb
Host smart-e96875d5-9f60-4027-933d-ad9167d50d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023757304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2023757304
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2749027883
Short name T649
Test name
Test status
Simulation time 55596755 ps
CPU time 3.08 seconds
Started Aug 13 05:43:08 PM PDT 24
Finished Aug 13 05:43:12 PM PDT 24
Peak memory 210460 kb
Host smart-53e2e850-9c57-42ff-83bb-d964845305ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749027883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2749027883
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1465370262
Short name T410
Test name
Test status
Simulation time 161500337 ps
CPU time 0.91 seconds
Started Aug 13 05:43:13 PM PDT 24
Finished Aug 13 05:43:14 PM PDT 24
Peak memory 206444 kb
Host smart-f34cf66e-a2df-4815-8060-c05701d168bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465370262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1465370262
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1825904237
Short name T122
Test name
Test status
Simulation time 60938250 ps
CPU time 4.11 seconds
Started Aug 13 05:43:14 PM PDT 24
Finished Aug 13 05:43:18 PM PDT 24
Peak memory 214700 kb
Host smart-95108c7c-a5f1-45d1-9776-168abecaf7cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825904237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1825904237
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2494974079
Short name T641
Test name
Test status
Simulation time 298659861 ps
CPU time 3.87 seconds
Started Aug 13 05:43:14 PM PDT 24
Finished Aug 13 05:43:18 PM PDT 24
Peak memory 214756 kb
Host smart-34009c64-c550-4f4d-81e3-977a00e23498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494974079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2494974079
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2022574895
Short name T67
Test name
Test status
Simulation time 104886982 ps
CPU time 2.58 seconds
Started Aug 13 05:43:13 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 209084 kb
Host smart-e99afea5-2bd8-4038-9500-2caa904253e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022574895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2022574895
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.485834753
Short name T286
Test name
Test status
Simulation time 395076361 ps
CPU time 2.75 seconds
Started Aug 13 05:43:15 PM PDT 24
Finished Aug 13 05:43:18 PM PDT 24
Peak memory 222552 kb
Host smart-447f6207-e7b2-44f4-aed5-6d5b8e261c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485834753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.485834753
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.68266207
Short name T299
Test name
Test status
Simulation time 230606648 ps
CPU time 2.6 seconds
Started Aug 13 05:43:15 PM PDT 24
Finished Aug 13 05:43:18 PM PDT 24
Peak memory 221404 kb
Host smart-9fdacec1-1c40-4150-9270-addd85f21c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68266207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.68266207
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.911146681
Short name T912
Test name
Test status
Simulation time 232711019 ps
CPU time 3.39 seconds
Started Aug 13 05:43:15 PM PDT 24
Finished Aug 13 05:43:19 PM PDT 24
Peak memory 210200 kb
Host smart-2ee15dc2-c976-40b5-81d5-3f349173bd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911146681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.911146681
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2646603421
Short name T434
Test name
Test status
Simulation time 185475178 ps
CPU time 5.47 seconds
Started Aug 13 05:43:13 PM PDT 24
Finished Aug 13 05:43:19 PM PDT 24
Peak memory 208036 kb
Host smart-8cfa9b91-1074-4794-9556-81ad5e704f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646603421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2646603421
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3721052868
Short name T311
Test name
Test status
Simulation time 630552834 ps
CPU time 7.31 seconds
Started Aug 13 05:43:08 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 208496 kb
Host smart-bed93dc1-0347-4173-808a-f8781b8253d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721052868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3721052868
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.462559722
Short name T830
Test name
Test status
Simulation time 4253602377 ps
CPU time 26.84 seconds
Started Aug 13 05:43:09 PM PDT 24
Finished Aug 13 05:43:36 PM PDT 24
Peak memory 208528 kb
Host smart-28cc8e68-f7cc-444c-96c3-19b0189440fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462559722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.462559722
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2105593667
Short name T881
Test name
Test status
Simulation time 658676536 ps
CPU time 3.18 seconds
Started Aug 13 05:43:06 PM PDT 24
Finished Aug 13 05:43:09 PM PDT 24
Peak memory 207456 kb
Host smart-df871543-3d05-40f8-b60b-20ad78c002b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105593667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2105593667
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2275717967
Short name T787
Test name
Test status
Simulation time 70056527 ps
CPU time 3.35 seconds
Started Aug 13 05:43:12 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 208860 kb
Host smart-ce24149d-ce43-4d81-a761-05b841e0f9d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275717967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2275717967
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3742513028
Short name T466
Test name
Test status
Simulation time 117360963 ps
CPU time 3.56 seconds
Started Aug 13 05:43:17 PM PDT 24
Finished Aug 13 05:43:21 PM PDT 24
Peak memory 216216 kb
Host smart-638ba530-9d8a-4e32-a19f-52608c40a64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742513028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3742513028
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3296490919
Short name T380
Test name
Test status
Simulation time 95125485 ps
CPU time 2.6 seconds
Started Aug 13 05:43:09 PM PDT 24
Finished Aug 13 05:43:12 PM PDT 24
Peak memory 207800 kb
Host smart-bef4844a-76cd-4f3e-966b-78fa970b61cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296490919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3296490919
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2762285542
Short name T768
Test name
Test status
Simulation time 3458824950 ps
CPU time 35.64 seconds
Started Aug 13 05:43:13 PM PDT 24
Finished Aug 13 05:43:48 PM PDT 24
Peak memory 221940 kb
Host smart-dcba8a70-4582-499c-a834-b149773a9da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762285542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2762285542
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.342907770
Short name T882
Test name
Test status
Simulation time 1107779366 ps
CPU time 15.82 seconds
Started Aug 13 05:43:14 PM PDT 24
Finished Aug 13 05:43:30 PM PDT 24
Peak memory 223020 kb
Host smart-69a02c9c-88bc-453c-ab89-814712cb9396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342907770 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.342907770
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1709778463
Short name T269
Test name
Test status
Simulation time 2060288490 ps
CPU time 67.99 seconds
Started Aug 13 05:43:12 PM PDT 24
Finished Aug 13 05:44:20 PM PDT 24
Peak memory 222880 kb
Host smart-5bc9bf1b-ea03-4148-bc7f-38605852fca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709778463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1709778463
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2622454524
Short name T818
Test name
Test status
Simulation time 71947682 ps
CPU time 1.92 seconds
Started Aug 13 05:43:15 PM PDT 24
Finished Aug 13 05:43:17 PM PDT 24
Peak memory 210548 kb
Host smart-aecf91a3-e664-4c9f-bc9c-d6b4771cf28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622454524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2622454524
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2708299913
Short name T509
Test name
Test status
Simulation time 11798640 ps
CPU time 0.77 seconds
Started Aug 13 05:43:20 PM PDT 24
Finished Aug 13 05:43:21 PM PDT 24
Peak memory 206300 kb
Host smart-9c3118dd-f1de-4ff5-ba48-a7132e439614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708299913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2708299913
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2700467625
Short name T799
Test name
Test status
Simulation time 182167455 ps
CPU time 3.07 seconds
Started Aug 13 05:43:13 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 214760 kb
Host smart-e617385a-8b0b-410b-9009-9f4e505c7f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700467625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2700467625
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.4167216440
Short name T49
Test name
Test status
Simulation time 31887973 ps
CPU time 1.76 seconds
Started Aug 13 05:43:14 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 214892 kb
Host smart-fd886822-1094-460f-84d9-0bc52ea4fb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167216440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4167216440
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3846364451
Short name T648
Test name
Test status
Simulation time 84559121 ps
CPU time 2.61 seconds
Started Aug 13 05:43:13 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 214604 kb
Host smart-153e8a02-936a-40d7-a58f-d7be1d3ac32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846364451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3846364451
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.177713137
Short name T745
Test name
Test status
Simulation time 333223546 ps
CPU time 2.21 seconds
Started Aug 13 05:43:20 PM PDT 24
Finished Aug 13 05:43:22 PM PDT 24
Peak memory 214784 kb
Host smart-47903e69-6b95-4caa-a5f9-23a51365fab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177713137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.177713137
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.600049638
Short name T249
Test name
Test status
Simulation time 120780431 ps
CPU time 5.23 seconds
Started Aug 13 05:43:10 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 209652 kb
Host smart-61252fcb-ddf8-4b06-8735-69f5620fd67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600049638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.600049638
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3668226806
Short name T556
Test name
Test status
Simulation time 806912333 ps
CPU time 3.46 seconds
Started Aug 13 05:43:14 PM PDT 24
Finished Aug 13 05:43:18 PM PDT 24
Peak memory 207308 kb
Host smart-776fef64-7a5f-40de-ae13-a03525066945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668226806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3668226806
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1896777990
Short name T550
Test name
Test status
Simulation time 115085453 ps
CPU time 4.02 seconds
Started Aug 13 05:43:12 PM PDT 24
Finished Aug 13 05:43:16 PM PDT 24
Peak memory 209308 kb
Host smart-c756384a-2006-4d77-9bb6-a4503ebec9ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896777990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1896777990
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2218748541
Short name T675
Test name
Test status
Simulation time 312293526 ps
CPU time 2.65 seconds
Started Aug 13 05:43:14 PM PDT 24
Finished Aug 13 05:43:17 PM PDT 24
Peak memory 207408 kb
Host smart-a67cf4e5-8d5d-4c51-9861-bb6321b90b22
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218748541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2218748541
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3904194884
Short name T97
Test name
Test status
Simulation time 422654644 ps
CPU time 4.1 seconds
Started Aug 13 05:43:15 PM PDT 24
Finished Aug 13 05:43:19 PM PDT 24
Peak memory 209188 kb
Host smart-465ab39c-280f-4966-954d-c530723a8b74
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904194884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3904194884
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.618074400
Short name T715
Test name
Test status
Simulation time 106169182 ps
CPU time 3.02 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:26 PM PDT 24
Peak memory 214844 kb
Host smart-dc43b118-2a51-4b10-8027-c1ec7510f495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618074400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.618074400
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.4206963613
Short name T489
Test name
Test status
Simulation time 192937402 ps
CPU time 2.48 seconds
Started Aug 13 05:43:16 PM PDT 24
Finished Aug 13 05:43:19 PM PDT 24
Peak memory 207356 kb
Host smart-70bccb71-dd5d-4581-a54f-7175cf224da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206963613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.4206963613
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1763013451
Short name T270
Test name
Test status
Simulation time 1514426674 ps
CPU time 26.7 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:49 PM PDT 24
Peak memory 222924 kb
Host smart-56c522a0-e407-4b24-a92c-2b4631170807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763013451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1763013451
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3153272609
Short name T637
Test name
Test status
Simulation time 352103614 ps
CPU time 8.85 seconds
Started Aug 13 05:43:15 PM PDT 24
Finished Aug 13 05:43:24 PM PDT 24
Peak memory 218788 kb
Host smart-3f3b6f4d-af07-4cb1-ab60-5bd54e0f6bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153272609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3153272609
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2598669642
Short name T513
Test name
Test status
Simulation time 69350142 ps
CPU time 1.42 seconds
Started Aug 13 05:43:19 PM PDT 24
Finished Aug 13 05:43:20 PM PDT 24
Peak memory 210552 kb
Host smart-c980965d-b613-46f5-95f1-eacebbb16ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598669642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2598669642
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3369065433
Short name T575
Test name
Test status
Simulation time 12370657 ps
CPU time 0.73 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:18 PM PDT 24
Peak memory 206392 kb
Host smart-4523acb2-56ac-4fca-9ded-d0eeeebf1923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369065433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3369065433
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.771416379
Short name T896
Test name
Test status
Simulation time 180901948 ps
CPU time 2.5 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:20 PM PDT 24
Peak memory 209636 kb
Host smart-e0243440-be33-43ac-8049-728eb0c78ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771416379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.771416379
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3519697070
Short name T266
Test name
Test status
Simulation time 112352702 ps
CPU time 2.67 seconds
Started Aug 13 05:42:15 PM PDT 24
Finished Aug 13 05:42:18 PM PDT 24
Peak memory 214760 kb
Host smart-c6fd6960-a728-4aea-81d1-5f49b8f0565f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519697070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3519697070
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.66060507
Short name T59
Test name
Test status
Simulation time 87596892 ps
CPU time 3.19 seconds
Started Aug 13 05:42:15 PM PDT 24
Finished Aug 13 05:42:18 PM PDT 24
Peak memory 220612 kb
Host smart-363e2441-f087-48a2-acae-fba70d75c96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66060507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.66060507
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2558724694
Short name T738
Test name
Test status
Simulation time 106934592 ps
CPU time 2.29 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:11 PM PDT 24
Peak memory 208692 kb
Host smart-b392d93b-ddb1-4d7e-bc1c-4a9eb3138a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558724694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2558724694
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.378238212
Short name T95
Test name
Test status
Simulation time 554178465 ps
CPU time 6.37 seconds
Started Aug 13 05:42:18 PM PDT 24
Finished Aug 13 05:42:24 PM PDT 24
Peak memory 237764 kb
Host smart-67a31db3-8b84-43ee-b802-9275bf860904
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378238212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.378238212
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.225742282
Short name T346
Test name
Test status
Simulation time 74734303 ps
CPU time 3.37 seconds
Started Aug 13 05:42:08 PM PDT 24
Finished Aug 13 05:42:12 PM PDT 24
Peak memory 209004 kb
Host smart-35a6db84-ada3-4142-bb71-b904e37a9947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225742282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.225742282
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2244752274
Short name T494
Test name
Test status
Simulation time 656728172 ps
CPU time 15.32 seconds
Started Aug 13 05:42:13 PM PDT 24
Finished Aug 13 05:42:29 PM PDT 24
Peak memory 209160 kb
Host smart-667f8e7e-0c80-49d0-8555-e6c0b7a3b49c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244752274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2244752274
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1383751485
Short name T760
Test name
Test status
Simulation time 37291579 ps
CPU time 2.22 seconds
Started Aug 13 05:42:11 PM PDT 24
Finished Aug 13 05:42:13 PM PDT 24
Peak memory 207412 kb
Host smart-c8ba76af-0879-4027-a79b-5b6c5917f605
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383751485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1383751485
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1384550489
Short name T758
Test name
Test status
Simulation time 1197709153 ps
CPU time 30.37 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:39 PM PDT 24
Peak memory 208808 kb
Host smart-6320590f-157f-42e3-997a-9d15df20ffdd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384550489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1384550489
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3527585296
Short name T752
Test name
Test status
Simulation time 593195849 ps
CPU time 2.77 seconds
Started Aug 13 05:42:16 PM PDT 24
Finished Aug 13 05:42:19 PM PDT 24
Peak memory 216384 kb
Host smart-059a14f1-bb2e-47dc-b462-f0f6a5b22354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527585296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3527585296
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2645400299
Short name T545
Test name
Test status
Simulation time 115357107 ps
CPU time 2.04 seconds
Started Aug 13 05:42:09 PM PDT 24
Finished Aug 13 05:42:11 PM PDT 24
Peak memory 207476 kb
Host smart-9d52fdf0-b6db-4de2-b64c-1b1267385ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645400299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2645400299
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.722573565
Short name T352
Test name
Test status
Simulation time 21757833909 ps
CPU time 365.35 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:48:29 PM PDT 24
Peak memory 223044 kb
Host smart-420226fb-61c2-4df9-a64b-65135bd69680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722573565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.722573565
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3750412121
Short name T115
Test name
Test status
Simulation time 554232256 ps
CPU time 15.94 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:33 PM PDT 24
Peak memory 222896 kb
Host smart-06627fa5-7b14-42cc-acb2-38d88d98d556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750412121 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3750412121
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1972968044
Short name T508
Test name
Test status
Simulation time 49299100 ps
CPU time 3.7 seconds
Started Aug 13 05:42:16 PM PDT 24
Finished Aug 13 05:42:20 PM PDT 24
Peak memory 210880 kb
Host smart-00e93f88-30c0-4fbe-88a7-173672e4bfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972968044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1972968044
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2221596047
Short name T150
Test name
Test status
Simulation time 82235763 ps
CPU time 2.35 seconds
Started Aug 13 05:42:19 PM PDT 24
Finished Aug 13 05:42:22 PM PDT 24
Peak memory 210372 kb
Host smart-1e5900a9-5fec-4e95-80ea-a1654d4a230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221596047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2221596047
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3134146324
Short name T476
Test name
Test status
Simulation time 20698469 ps
CPU time 0.8 seconds
Started Aug 13 05:43:21 PM PDT 24
Finished Aug 13 05:43:22 PM PDT 24
Peak memory 206380 kb
Host smart-9fb12c93-2088-472b-a5d3-50278f645da6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134146324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3134146324
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3276702716
Short name T795
Test name
Test status
Simulation time 43553543 ps
CPU time 2.98 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:26 PM PDT 24
Peak memory 214856 kb
Host smart-e9dc610f-6207-4e38-8039-011c21730f2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276702716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3276702716
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.951942057
Short name T605
Test name
Test status
Simulation time 17955317 ps
CPU time 1.39 seconds
Started Aug 13 05:43:24 PM PDT 24
Finished Aug 13 05:43:26 PM PDT 24
Peak memory 208040 kb
Host smart-c73ca852-5500-4692-9a3e-dfa7ec01e80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951942057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.951942057
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1024345364
Short name T902
Test name
Test status
Simulation time 273600623 ps
CPU time 6.8 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:29 PM PDT 24
Peak memory 214812 kb
Host smart-71813d6e-9214-4ee5-a5d8-0ce3c0675316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024345364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1024345364
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2793090809
Short name T801
Test name
Test status
Simulation time 301225376 ps
CPU time 3.77 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:26 PM PDT 24
Peak memory 214728 kb
Host smart-4c3f0ef5-62e6-48e7-b2dd-676e9476823b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793090809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2793090809
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1226467702
Short name T645
Test name
Test status
Simulation time 247672449 ps
CPU time 3.69 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:26 PM PDT 24
Peak memory 214776 kb
Host smart-f92ada6b-5ec4-4365-91cb-5972f3469576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226467702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1226467702
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3458076070
Short name T579
Test name
Test status
Simulation time 4892419633 ps
CPU time 31.04 seconds
Started Aug 13 05:43:20 PM PDT 24
Finished Aug 13 05:43:51 PM PDT 24
Peak memory 210308 kb
Host smart-0acf37b1-5d69-4cec-9ca7-ca44d7cf2e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458076070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3458076070
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1550452242
Short name T435
Test name
Test status
Simulation time 63731691 ps
CPU time 2.9 seconds
Started Aug 13 05:43:19 PM PDT 24
Finished Aug 13 05:43:22 PM PDT 24
Peak memory 208560 kb
Host smart-8e53e7d7-acb7-4a6b-915b-fc0ca32bea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550452242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1550452242
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1330127591
Short name T455
Test name
Test status
Simulation time 164445421 ps
CPU time 6.26 seconds
Started Aug 13 05:43:21 PM PDT 24
Finished Aug 13 05:43:28 PM PDT 24
Peak memory 209108 kb
Host smart-12aaccdb-a5eb-4f05-a783-eeac384f65ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330127591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1330127591
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2535509155
Short name T565
Test name
Test status
Simulation time 71167567 ps
CPU time 3.09 seconds
Started Aug 13 05:43:21 PM PDT 24
Finished Aug 13 05:43:24 PM PDT 24
Peak memory 207436 kb
Host smart-f5de35bc-f051-432f-bb60-570a26ced60d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535509155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2535509155
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3159636313
Short name T560
Test name
Test status
Simulation time 48936861 ps
CPU time 2.79 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:25 PM PDT 24
Peak memory 207528 kb
Host smart-4c28326a-ceb0-4ed7-921b-5a469d03077e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159636313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3159636313
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3482598667
Short name T422
Test name
Test status
Simulation time 243108233 ps
CPU time 3.27 seconds
Started Aug 13 05:43:20 PM PDT 24
Finished Aug 13 05:43:23 PM PDT 24
Peak memory 214744 kb
Host smart-f4f4f1d4-165e-4fdd-8ce5-554cf22b0aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482598667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3482598667
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2936945425
Short name T886
Test name
Test status
Simulation time 80107314 ps
CPU time 3.45 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:25 PM PDT 24
Peak memory 209016 kb
Host smart-3de814c9-c560-459f-bf04-472a0043ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936945425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2936945425
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1081633814
Short name T174
Test name
Test status
Simulation time 334676754 ps
CPU time 11.1 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 222984 kb
Host smart-8f95fa23-c2c1-4d5d-8774-e62e995ef30a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081633814 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1081633814
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3660985927
Short name T83
Test name
Test status
Simulation time 63177481 ps
CPU time 2.99 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:25 PM PDT 24
Peak memory 209340 kb
Host smart-8dc91b96-9220-430c-9692-e944354e23b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660985927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3660985927
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3382294360
Short name T664
Test name
Test status
Simulation time 37090762 ps
CPU time 1.88 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:24 PM PDT 24
Peak memory 210136 kb
Host smart-22880165-34bd-4d2a-baaa-ffa19a211dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382294360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3382294360
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.733214568
Short name T493
Test name
Test status
Simulation time 13171850 ps
CPU time 0.85 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:23 PM PDT 24
Peak memory 206404 kb
Host smart-fc75c3b9-ba62-4829-b58c-32ada152d894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733214568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.733214568
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3647909510
Short name T292
Test name
Test status
Simulation time 71038938 ps
CPU time 4.3 seconds
Started Aug 13 05:43:21 PM PDT 24
Finished Aug 13 05:43:25 PM PDT 24
Peak memory 216140 kb
Host smart-b0c9d963-0b46-4ee8-b49f-4b930b62686b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647909510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3647909510
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.303008634
Short name T517
Test name
Test status
Simulation time 327093327 ps
CPU time 3.09 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:25 PM PDT 24
Peak memory 210136 kb
Host smart-770822a9-dcc5-4ebf-9f60-70ce3f6ba840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303008634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.303008634
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1838148466
Short name T841
Test name
Test status
Simulation time 75408932 ps
CPU time 1.58 seconds
Started Aug 13 05:43:20 PM PDT 24
Finished Aug 13 05:43:22 PM PDT 24
Peak memory 207460 kb
Host smart-2c805b72-8aad-4c3d-9f79-3d110106efb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838148466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1838148466
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2100086953
Short name T657
Test name
Test status
Simulation time 378708035 ps
CPU time 9.24 seconds
Started Aug 13 05:43:24 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 214832 kb
Host smart-feaeedee-1e7b-4927-9629-aa48d38e57fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100086953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2100086953
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3142000603
Short name T365
Test name
Test status
Simulation time 59868736 ps
CPU time 2.94 seconds
Started Aug 13 05:43:24 PM PDT 24
Finished Aug 13 05:43:27 PM PDT 24
Peak memory 214692 kb
Host smart-199ade63-3e40-40bc-a315-5c49db22d024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142000603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3142000603
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1107696558
Short name T205
Test name
Test status
Simulation time 87737836 ps
CPU time 3.51 seconds
Started Aug 13 05:43:26 PM PDT 24
Finished Aug 13 05:43:30 PM PDT 24
Peak memory 222928 kb
Host smart-a7c74922-9cf3-4e7f-86ca-efe9e360e9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107696558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1107696558
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3769207402
Short name T810
Test name
Test status
Simulation time 217416022 ps
CPU time 3.47 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:25 PM PDT 24
Peak memory 207752 kb
Host smart-abf89d86-c037-47d6-b093-7b4a8e201ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769207402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3769207402
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.417507555
Short name T245
Test name
Test status
Simulation time 5184389804 ps
CPU time 38.84 seconds
Started Aug 13 05:43:21 PM PDT 24
Finished Aug 13 05:44:00 PM PDT 24
Peak memory 208912 kb
Host smart-1aeb596a-34f3-4169-8ec7-255667428973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417507555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.417507555
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2382123230
Short name T479
Test name
Test status
Simulation time 671358683 ps
CPU time 7.63 seconds
Started Aug 13 05:43:24 PM PDT 24
Finished Aug 13 05:43:31 PM PDT 24
Peak memory 209032 kb
Host smart-16e8d47d-bf5c-409d-9f81-facc31087445
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382123230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2382123230
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3064448004
Short name T527
Test name
Test status
Simulation time 783046824 ps
CPU time 4.57 seconds
Started Aug 13 05:43:24 PM PDT 24
Finished Aug 13 05:43:29 PM PDT 24
Peak memory 208900 kb
Host smart-bca3e173-1c73-4424-b34b-7d866fb9e472
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064448004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3064448004
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1297781515
Short name T487
Test name
Test status
Simulation time 41700416 ps
CPU time 2.25 seconds
Started Aug 13 05:43:25 PM PDT 24
Finished Aug 13 05:43:27 PM PDT 24
Peak memory 207504 kb
Host smart-3ff45957-cf35-4fd1-a083-9c8dcbc38430
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297781515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1297781515
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1042196037
Short name T626
Test name
Test status
Simulation time 67884590 ps
CPU time 2.21 seconds
Started Aug 13 05:43:25 PM PDT 24
Finished Aug 13 05:43:27 PM PDT 24
Peak memory 214816 kb
Host smart-f432551c-b7a0-4dee-b1c5-a88b195935c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042196037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1042196037
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3276174079
Short name T684
Test name
Test status
Simulation time 199932018 ps
CPU time 4.57 seconds
Started Aug 13 05:43:21 PM PDT 24
Finished Aug 13 05:43:26 PM PDT 24
Peak memory 207428 kb
Host smart-8226afc3-71e0-426b-90e0-42cd5ec9cbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276174079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3276174079
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1287280267
Short name T716
Test name
Test status
Simulation time 4407813816 ps
CPU time 42.33 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 223040 kb
Host smart-b815e43f-aa7c-4f99-a528-efa8666fdbbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287280267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1287280267
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3310043191
Short name T343
Test name
Test status
Simulation time 9538620593 ps
CPU time 96.13 seconds
Started Aug 13 05:43:21 PM PDT 24
Finished Aug 13 05:44:58 PM PDT 24
Peak memory 214848 kb
Host smart-c23bae60-7095-488d-9d0f-16657bccb921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310043191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3310043191
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.585698284
Short name T561
Test name
Test status
Simulation time 65300126 ps
CPU time 2.05 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:25 PM PDT 24
Peak memory 210488 kb
Host smart-f0e29d50-5777-42fe-a68b-ba84c7c9847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585698284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.585698284
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1362363448
Short name T655
Test name
Test status
Simulation time 26261129 ps
CPU time 0.79 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 206412 kb
Host smart-8490dfb0-4765-48e2-a2b5-9371e592051e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362363448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1362363448
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.864820394
Short name T390
Test name
Test status
Simulation time 490973192 ps
CPU time 6.85 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:43:36 PM PDT 24
Peak memory 214812 kb
Host smart-1bd7aa47-3a1f-40b6-8e69-19aeb28e1b51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864820394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.864820394
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2316263518
Short name T28
Test name
Test status
Simulation time 296007534 ps
CPU time 3.22 seconds
Started Aug 13 05:43:27 PM PDT 24
Finished Aug 13 05:43:31 PM PDT 24
Peak memory 214860 kb
Host smart-92f181ad-9942-4e94-be0f-e40f220503e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316263518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2316263518
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2016447984
Short name T338
Test name
Test status
Simulation time 717546430 ps
CPU time 13.08 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:44 PM PDT 24
Peak memory 209336 kb
Host smart-572cf4a9-d26d-48a0-a959-b2b0f1526a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016447984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2016447984
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1498385823
Short name T588
Test name
Test status
Simulation time 44741485 ps
CPU time 2.62 seconds
Started Aug 13 05:43:27 PM PDT 24
Finished Aug 13 05:43:30 PM PDT 24
Peak memory 214764 kb
Host smart-c684746b-d5e2-4d85-b28f-a6b7f0b7e958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498385823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1498385823
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.545717792
Short name T229
Test name
Test status
Simulation time 77482310 ps
CPU time 3.65 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:34 PM PDT 24
Peak memory 214712 kb
Host smart-bef66e8a-0a46-45af-8c67-045888efd775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545717792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.545717792
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2395347052
Short name T202
Test name
Test status
Simulation time 35917531 ps
CPU time 2.3 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:43:32 PM PDT 24
Peak memory 208516 kb
Host smart-7b79a7b8-f47f-45e8-a535-a57ae466130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395347052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2395347052
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2244811092
Short name T794
Test name
Test status
Simulation time 34504484 ps
CPU time 2.36 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:24 PM PDT 24
Peak memory 207900 kb
Host smart-f621de24-3152-456d-863c-4d417cd3e054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244811092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2244811092
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1169280336
Short name T443
Test name
Test status
Simulation time 53269868 ps
CPU time 2.94 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:26 PM PDT 24
Peak memory 209168 kb
Host smart-0513ec8b-d910-4eb0-8355-2df5592956f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169280336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1169280336
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1093837902
Short name T177
Test name
Test status
Simulation time 195149870 ps
CPU time 2.82 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:26 PM PDT 24
Peak memory 207808 kb
Host smart-90f3d58a-a3e5-44b8-ab2a-61652cdb7760
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093837902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1093837902
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.4111669164
Short name T630
Test name
Test status
Simulation time 242738797 ps
CPU time 3.36 seconds
Started Aug 13 05:43:22 PM PDT 24
Finished Aug 13 05:43:26 PM PDT 24
Peak memory 207748 kb
Host smart-ee073621-77fb-4de7-bdad-4ac1eec86c59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111669164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.4111669164
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1519618494
Short name T642
Test name
Test status
Simulation time 88343415 ps
CPU time 3.84 seconds
Started Aug 13 05:43:21 PM PDT 24
Finished Aug 13 05:43:25 PM PDT 24
Peak memory 209476 kb
Host smart-0f21a275-ec41-4550-b8aa-110fd7f7740e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519618494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1519618494
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.782551346
Short name T99
Test name
Test status
Simulation time 62333717 ps
CPU time 2.27 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:34 PM PDT 24
Peak memory 209748 kb
Host smart-f4de6d1c-f3f2-4088-bede-842e03528daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782551346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.782551346
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1605267511
Short name T530
Test name
Test status
Simulation time 180076821 ps
CPU time 5.42 seconds
Started Aug 13 05:43:23 PM PDT 24
Finished Aug 13 05:43:29 PM PDT 24
Peak memory 207316 kb
Host smart-e0184623-5ea7-4446-97a8-9c49ab6cf841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605267511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1605267511
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3801376230
Short name T173
Test name
Test status
Simulation time 2613501858 ps
CPU time 25.95 seconds
Started Aug 13 05:43:28 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 223248 kb
Host smart-3a683e80-9c30-45a0-8331-3f989b8ca1b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801376230 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3801376230
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1819922496
Short name T234
Test name
Test status
Simulation time 2354338058 ps
CPU time 5.65 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:38 PM PDT 24
Peak memory 218772 kb
Host smart-6aa11ffb-9c53-493c-9a3b-9a4ab4e4f407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819922496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1819922496
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3791866891
Short name T34
Test name
Test status
Simulation time 341168717 ps
CPU time 5.27 seconds
Started Aug 13 05:43:28 PM PDT 24
Finished Aug 13 05:43:34 PM PDT 24
Peak memory 210812 kb
Host smart-2e696bcc-e8d2-4bb5-a777-096dddf4455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791866891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3791866891
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1706292772
Short name T822
Test name
Test status
Simulation time 43489747 ps
CPU time 0.85 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:43:30 PM PDT 24
Peak memory 206416 kb
Host smart-dae60270-648b-4e30-a4a3-8dd23d834638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706292772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1706292772
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.499850293
Short name T273
Test name
Test status
Simulation time 56263751 ps
CPU time 3.91 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 215944 kb
Host smart-3a08c165-8b39-4046-8efa-47fb1d2bc059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499850293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.499850293
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.113065320
Short name T21
Test name
Test status
Simulation time 154160526 ps
CPU time 2.71 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:34 PM PDT 24
Peak memory 219676 kb
Host smart-4280423f-3e5f-478d-8c51-a3ffe8e14cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113065320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.113065320
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.28451385
Short name T629
Test name
Test status
Simulation time 93415892 ps
CPU time 2.45 seconds
Started Aug 13 05:43:28 PM PDT 24
Finished Aug 13 05:43:30 PM PDT 24
Peak memory 218796 kb
Host smart-2ac89163-69cf-4d14-af52-16c9201793e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28451385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.28451385
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1213542930
Short name T341
Test name
Test status
Simulation time 252018351 ps
CPU time 3.28 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:43:32 PM PDT 24
Peak memory 214776 kb
Host smart-0b976825-e107-494c-9e8e-5a88072eca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213542930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1213542930
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1759460254
Short name T389
Test name
Test status
Simulation time 109216257 ps
CPU time 4.25 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:43:35 PM PDT 24
Peak memory 210144 kb
Host smart-d9b6f242-cdb7-4814-8011-8c17eefcec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759460254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1759460254
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3898881652
Short name T239
Test name
Test status
Simulation time 1766208649 ps
CPU time 5.3 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:36 PM PDT 24
Peak memory 214684 kb
Host smart-1f8ba821-347e-4aeb-8111-e834f390a431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898881652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3898881652
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.541708251
Short name T318
Test name
Test status
Simulation time 331393118 ps
CPU time 2.91 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:35 PM PDT 24
Peak memory 207344 kb
Host smart-da611239-95d1-48a5-a023-2e15014edd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541708251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.541708251
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3931599961
Short name T438
Test name
Test status
Simulation time 6424220434 ps
CPU time 45.59 seconds
Started Aug 13 05:43:28 PM PDT 24
Finished Aug 13 05:44:14 PM PDT 24
Peak memory 208892 kb
Host smart-1d848cb0-869c-4d58-b8bd-b1ebea6c3406
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931599961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3931599961
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3927400287
Short name T130
Test name
Test status
Simulation time 31103077 ps
CPU time 2.08 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:43:32 PM PDT 24
Peak memory 209064 kb
Host smart-587dee41-ee66-480b-b4b8-69708f5e9459
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927400287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3927400287
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1955433456
Short name T448
Test name
Test status
Simulation time 968045489 ps
CPU time 6.4 seconds
Started Aug 13 05:43:27 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 209132 kb
Host smart-d9b5e376-0fce-49e7-b98b-ccbb4b57bdc1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955433456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1955433456
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4095381156
Short name T327
Test name
Test status
Simulation time 938293025 ps
CPU time 12.72 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:45 PM PDT 24
Peak memory 214828 kb
Host smart-fee5f2ff-8fdc-4479-a88e-2187c02c6ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095381156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4095381156
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3243343787
Short name T834
Test name
Test status
Simulation time 213575902 ps
CPU time 2.69 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:43:31 PM PDT 24
Peak memory 207384 kb
Host smart-2000a2cf-7693-47fc-86fe-9a0e063fb4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243343787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3243343787
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2598869965
Short name T559
Test name
Test status
Simulation time 227641501 ps
CPU time 3.09 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:34 PM PDT 24
Peak memory 209480 kb
Host smart-24383cd0-a6fa-4345-83f8-58171646d086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598869965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2598869965
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3483941227
Short name T771
Test name
Test status
Simulation time 57277546 ps
CPU time 3.18 seconds
Started Aug 13 05:43:28 PM PDT 24
Finished Aug 13 05:43:31 PM PDT 24
Peak memory 210396 kb
Host smart-7831b579-8751-4eff-a641-263e32cc62cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483941227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3483941227
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1436326970
Short name T127
Test name
Test status
Simulation time 7169264 ps
CPU time 0.78 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:43:30 PM PDT 24
Peak memory 206368 kb
Host smart-c6715196-7141-48eb-9762-7131e5e076da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436326970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1436326970
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.120706039
Short name T726
Test name
Test status
Simulation time 195657141 ps
CPU time 2.84 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 223184 kb
Host smart-73006bbc-52f9-4c2f-b57f-8e5aa4bf77b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120706039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.120706039
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1708322179
Short name T322
Test name
Test status
Simulation time 1012024022 ps
CPU time 30.66 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:44:01 PM PDT 24
Peak memory 209676 kb
Host smart-37207994-b10d-4982-a21b-bdff533dad72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708322179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1708322179
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2483752809
Short name T221
Test name
Test status
Simulation time 163896309 ps
CPU time 6.15 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:43:36 PM PDT 24
Peak memory 222776 kb
Host smart-1600bdd5-00c0-49fb-9390-19542109e434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483752809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2483752809
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2299397335
Short name T472
Test name
Test status
Simulation time 64712959 ps
CPU time 2.16 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 215988 kb
Host smart-07a73c2a-1d81-4a2e-9792-0accf8d9c05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299397335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2299397335
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.82317977
Short name T238
Test name
Test status
Simulation time 8585209836 ps
CPU time 78.19 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 218708 kb
Host smart-421af6e1-7869-4cc7-9cf3-f1ae1fe0f31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82317977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.82317977
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2338412043
Short name T784
Test name
Test status
Simulation time 854402163 ps
CPU time 3.19 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:43:32 PM PDT 24
Peak memory 207320 kb
Host smart-068c27c2-4781-4fd8-9221-876a1965926b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338412043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2338412043
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1376024301
Short name T430
Test name
Test status
Simulation time 70582688 ps
CPU time 2.99 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:35 PM PDT 24
Peak memory 209168 kb
Host smart-45afc6d9-6773-40ba-8f3e-f4c56cf8a17b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376024301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1376024301
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.170310074
Short name T523
Test name
Test status
Simulation time 107498232 ps
CPU time 4.72 seconds
Started Aug 13 05:43:29 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 207440 kb
Host smart-3561d85a-9c1c-4592-97ba-46dd8fe57380
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170310074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.170310074
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3771922246
Short name T428
Test name
Test status
Simulation time 316403403 ps
CPU time 3.04 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 209304 kb
Host smart-b5030486-6d30-4a08-9a57-b21f00d92759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771922246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3771922246
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1852836970
Short name T382
Test name
Test status
Simulation time 87582979 ps
CPU time 3.03 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 207432 kb
Host smart-7c956776-2253-47d5-b883-a35b25e1e917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852836970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1852836970
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2202367427
Short name T498
Test name
Test status
Simulation time 10131726939 ps
CPU time 110.09 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:45:21 PM PDT 24
Peak memory 219788 kb
Host smart-8fc9bded-d594-4954-86ee-7c1fad5e566d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202367427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2202367427
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2429417691
Short name T710
Test name
Test status
Simulation time 1253372037 ps
CPU time 21.74 seconds
Started Aug 13 05:43:26 PM PDT 24
Finished Aug 13 05:43:48 PM PDT 24
Peak memory 223088 kb
Host smart-58a65676-89d2-4dcf-937a-8da464d0197e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429417691 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2429417691
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3684880355
Short name T190
Test name
Test status
Simulation time 219648038 ps
CPU time 3.99 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:36 PM PDT 24
Peak memory 208732 kb
Host smart-a7fbc50b-ff1a-46c2-978a-0268272128b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684880355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3684880355
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2440051378
Short name T740
Test name
Test status
Simulation time 180132099 ps
CPU time 2.18 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:34 PM PDT 24
Peak memory 210520 kb
Host smart-da0aee5c-70bb-4805-97d8-f2e33a9db21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440051378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2440051378
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2568892289
Short name T378
Test name
Test status
Simulation time 130619758 ps
CPU time 4.02 seconds
Started Aug 13 05:43:32 PM PDT 24
Finished Aug 13 05:43:36 PM PDT 24
Peak memory 215092 kb
Host smart-683b654d-2ff5-4e6b-a672-e0bf216f11ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568892289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2568892289
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.107771432
Short name T25
Test name
Test status
Simulation time 380172501 ps
CPU time 4.03 seconds
Started Aug 13 05:43:39 PM PDT 24
Finished Aug 13 05:43:43 PM PDT 24
Peak memory 222112 kb
Host smart-f665e571-5575-468d-b43d-90ac1672863a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107771432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.107771432
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.85794109
Short name T120
Test name
Test status
Simulation time 592001210 ps
CPU time 3.81 seconds
Started Aug 13 05:43:40 PM PDT 24
Finished Aug 13 05:43:44 PM PDT 24
Peak memory 218816 kb
Host smart-ad4bdbeb-066f-4d97-8031-0bfaa8081697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85794109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.85794109
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.415121013
Short name T15
Test name
Test status
Simulation time 496665391 ps
CPU time 5.65 seconds
Started Aug 13 05:43:39 PM PDT 24
Finished Aug 13 05:43:44 PM PDT 24
Peak memory 222932 kb
Host smart-f3619309-90ac-488e-98b0-7bed0aa8c5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415121013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.415121013
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3394126806
Short name T279
Test name
Test status
Simulation time 72546019 ps
CPU time 3.04 seconds
Started Aug 13 05:43:39 PM PDT 24
Finished Aug 13 05:43:42 PM PDT 24
Peak memory 214716 kb
Host smart-534587c2-0a02-407e-9a1e-90f49ece9ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394126806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3394126806
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3080498616
Short name T216
Test name
Test status
Simulation time 246045899 ps
CPU time 3.17 seconds
Started Aug 13 05:43:39 PM PDT 24
Finished Aug 13 05:43:42 PM PDT 24
Peak memory 210736 kb
Host smart-298d1cba-61dd-4a87-b8b0-b8d2c89f2fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080498616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3080498616
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2738104947
Short name T727
Test name
Test status
Simulation time 956764147 ps
CPU time 29.28 seconds
Started Aug 13 05:43:27 PM PDT 24
Finished Aug 13 05:43:57 PM PDT 24
Peak memory 214704 kb
Host smart-e6261448-bc48-4081-bde2-c6945b47283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738104947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2738104947
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4215503666
Short name T702
Test name
Test status
Simulation time 74104928 ps
CPU time 2.83 seconds
Started Aug 13 05:43:27 PM PDT 24
Finished Aug 13 05:43:31 PM PDT 24
Peak memory 207316 kb
Host smart-1793839f-1d38-4728-9847-3925d7da0d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215503666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4215503666
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.4015184344
Short name T847
Test name
Test status
Simulation time 1708820033 ps
CPU time 8.63 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:40 PM PDT 24
Peak memory 209152 kb
Host smart-ff0a1dd5-5561-444d-876c-42df69443b8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015184344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4015184344
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3974339696
Short name T484
Test name
Test status
Simulation time 42098819 ps
CPU time 2.83 seconds
Started Aug 13 05:43:30 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 209352 kb
Host smart-c12ad831-0c7c-4aaf-965a-0369e5ffa891
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974339696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3974339696
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.307881050
Short name T678
Test name
Test status
Simulation time 231226909 ps
CPU time 2.8 seconds
Started Aug 13 05:43:31 PM PDT 24
Finished Aug 13 05:43:34 PM PDT 24
Peak memory 207440 kb
Host smart-faa7ee5f-773c-4d33-9134-4b501c6e00c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307881050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.307881050
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2665654827
Short name T124
Test name
Test status
Simulation time 177696677 ps
CPU time 4.25 seconds
Started Aug 13 05:43:40 PM PDT 24
Finished Aug 13 05:43:45 PM PDT 24
Peak memory 210364 kb
Host smart-48519370-0646-42e5-be52-f576ea8ec79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665654827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2665654827
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2719634692
Short name T412
Test name
Test status
Simulation time 65539297 ps
CPU time 2.93 seconds
Started Aug 13 05:43:28 PM PDT 24
Finished Aug 13 05:43:31 PM PDT 24
Peak memory 208840 kb
Host smart-df3109bb-95fc-438d-aa11-73d422338c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719634692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2719634692
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.4262444905
Short name T894
Test name
Test status
Simulation time 920322035 ps
CPU time 16.34 seconds
Started Aug 13 05:43:38 PM PDT 24
Finished Aug 13 05:43:55 PM PDT 24
Peak memory 219944 kb
Host smart-2a96e860-114a-4667-a9ce-a2bb1066f6c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262444905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4262444905
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3788521912
Short name T669
Test name
Test status
Simulation time 1348878911 ps
CPU time 4.42 seconds
Started Aug 13 05:43:42 PM PDT 24
Finished Aug 13 05:43:46 PM PDT 24
Peak memory 208080 kb
Host smart-a2b81ec3-3329-400c-b465-4a39c6ff6ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788521912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3788521912
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2501940776
Short name T690
Test name
Test status
Simulation time 50867554 ps
CPU time 1.92 seconds
Started Aug 13 05:43:37 PM PDT 24
Finished Aug 13 05:43:39 PM PDT 24
Peak memory 210680 kb
Host smart-097fd725-7fef-4744-b741-2935ccb408f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501940776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2501940776
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1430134507
Short name T500
Test name
Test status
Simulation time 15520785 ps
CPU time 0.74 seconds
Started Aug 13 05:43:41 PM PDT 24
Finished Aug 13 05:43:41 PM PDT 24
Peak memory 206408 kb
Host smart-ca0d62b5-4ad5-4240-b7a2-efb3c4d2ae20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430134507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1430134507
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3947325732
Short name T502
Test name
Test status
Simulation time 2279651249 ps
CPU time 4.96 seconds
Started Aug 13 05:43:36 PM PDT 24
Finished Aug 13 05:43:42 PM PDT 24
Peak memory 207956 kb
Host smart-37e9225f-ce51-42cf-8ab7-4fe1d0b22224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947325732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3947325732
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1862274101
Short name T24
Test name
Test status
Simulation time 246426265 ps
CPU time 4.17 seconds
Started Aug 13 05:43:39 PM PDT 24
Finished Aug 13 05:43:43 PM PDT 24
Peak memory 214836 kb
Host smart-c8d8f76b-a91b-43e7-b6ed-72cd34fc807f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862274101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1862274101
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1989070169
Short name T280
Test name
Test status
Simulation time 37418754 ps
CPU time 2.06 seconds
Started Aug 13 05:43:36 PM PDT 24
Finished Aug 13 05:43:38 PM PDT 24
Peak memory 214752 kb
Host smart-86ae140a-a931-4d6a-89c5-697e98c73b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989070169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1989070169
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3879212912
Short name T211
Test name
Test status
Simulation time 185874162 ps
CPU time 3.56 seconds
Started Aug 13 05:43:40 PM PDT 24
Finished Aug 13 05:43:44 PM PDT 24
Peak memory 210620 kb
Host smart-531c3df4-6c83-4e26-9459-189c89c67a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879212912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3879212912
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3093037814
Short name T252
Test name
Test status
Simulation time 911971561 ps
CPU time 19.11 seconds
Started Aug 13 05:43:38 PM PDT 24
Finished Aug 13 05:43:58 PM PDT 24
Peak memory 220728 kb
Host smart-7a1c6555-a730-48f4-8851-8e757a5dead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093037814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3093037814
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3316267915
Short name T706
Test name
Test status
Simulation time 209401259 ps
CPU time 6.2 seconds
Started Aug 13 05:43:37 PM PDT 24
Finished Aug 13 05:43:43 PM PDT 24
Peak memory 207484 kb
Host smart-330a798d-7f1d-4442-8a00-46689382252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316267915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3316267915
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2614878160
Short name T671
Test name
Test status
Simulation time 134333643 ps
CPU time 4.16 seconds
Started Aug 13 05:43:34 PM PDT 24
Finished Aug 13 05:43:38 PM PDT 24
Peak memory 209156 kb
Host smart-229a7186-e654-4ecd-bdb6-9941fb7161d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614878160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2614878160
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.311877866
Short name T495
Test name
Test status
Simulation time 160685501 ps
CPU time 3.93 seconds
Started Aug 13 05:43:41 PM PDT 24
Finished Aug 13 05:43:45 PM PDT 24
Peak memory 209244 kb
Host smart-f677f75a-5a0d-448d-be08-bbf85330cba0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311877866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.311877866
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3454234895
Short name T627
Test name
Test status
Simulation time 147359839 ps
CPU time 4.08 seconds
Started Aug 13 05:43:36 PM PDT 24
Finished Aug 13 05:43:41 PM PDT 24
Peak memory 208572 kb
Host smart-d5e34206-02ca-4e1b-b24a-af1bda0f3703
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454234895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3454234895
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.48417745
Short name T185
Test name
Test status
Simulation time 67277800 ps
CPU time 1.59 seconds
Started Aug 13 05:43:37 PM PDT 24
Finished Aug 13 05:43:39 PM PDT 24
Peak memory 208336 kb
Host smart-10736167-eb9d-4333-b52f-fa57c04b969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48417745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.48417745
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1361642665
Short name T806
Test name
Test status
Simulation time 202803274 ps
CPU time 2.62 seconds
Started Aug 13 05:43:41 PM PDT 24
Finished Aug 13 05:43:44 PM PDT 24
Peak memory 207416 kb
Host smart-77ad8865-1124-4ee5-bed3-88e10f193a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361642665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1361642665
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.795750054
Short name T254
Test name
Test status
Simulation time 303369747 ps
CPU time 15.99 seconds
Started Aug 13 05:43:37 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 217916 kb
Host smart-6b815aec-6c11-4b84-8b7f-4aa0970fa3c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795750054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.795750054
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2181744471
Short name T870
Test name
Test status
Simulation time 1252481426 ps
CPU time 18.79 seconds
Started Aug 13 05:43:37 PM PDT 24
Finished Aug 13 05:43:56 PM PDT 24
Peak memory 223068 kb
Host smart-f9c13f30-8ebd-4a31-ac7a-3c7d675eeed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181744471 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2181744471
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2459460726
Short name T650
Test name
Test status
Simulation time 228726384 ps
CPU time 4.34 seconds
Started Aug 13 05:43:40 PM PDT 24
Finished Aug 13 05:43:45 PM PDT 24
Peak memory 209552 kb
Host smart-d806dd5d-259c-43b9-8001-f02e8ecf3e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459460726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2459460726
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1948726674
Short name T510
Test name
Test status
Simulation time 73429263 ps
CPU time 1.63 seconds
Started Aug 13 05:43:34 PM PDT 24
Finished Aug 13 05:43:36 PM PDT 24
Peak memory 210944 kb
Host smart-682bcb0a-e0ac-4c95-9f8c-db1d9f54d837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948726674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1948726674
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2314516095
Short name T828
Test name
Test status
Simulation time 14706804 ps
CPU time 0.87 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:43:52 PM PDT 24
Peak memory 206552 kb
Host smart-1a47ff41-90a6-4b47-b3b3-779fc200ffea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314516095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2314516095
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3969248124
Short name T237
Test name
Test status
Simulation time 2535104146 ps
CPU time 17.02 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:44:09 PM PDT 24
Peak memory 215060 kb
Host smart-18e3495c-fa41-4adb-bf80-108059ba2b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969248124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3969248124
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1936764447
Short name T40
Test name
Test status
Simulation time 70081424 ps
CPU time 2.69 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 209680 kb
Host smart-577250a9-6bdc-495e-9884-20c7594c20da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936764447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1936764447
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1510279800
Short name T809
Test name
Test status
Simulation time 492243508 ps
CPU time 3.57 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:52 PM PDT 24
Peak memory 218864 kb
Host smart-9b438257-f5e8-44cb-9b7a-1f9c5990ccdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510279800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1510279800
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1248831984
Short name T812
Test name
Test status
Simulation time 238696214 ps
CPU time 2.49 seconds
Started Aug 13 05:43:47 PM PDT 24
Finished Aug 13 05:43:50 PM PDT 24
Peak memory 214776 kb
Host smart-971e8849-4e11-4ddd-9e8a-39820de89a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248831984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1248831984
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2033599718
Short name T206
Test name
Test status
Simulation time 785174761 ps
CPU time 9.61 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:43:59 PM PDT 24
Peak memory 214864 kb
Host smart-b2018eb8-820c-4ef4-9f9f-78b0a3b27617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033599718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2033599718
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1407450702
Short name T877
Test name
Test status
Simulation time 1688355887 ps
CPU time 5.02 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:43:55 PM PDT 24
Peak memory 207816 kb
Host smart-453b6cb8-4910-4292-a6f4-9010830c24d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407450702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1407450702
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2415431886
Short name T303
Test name
Test status
Simulation time 59077365 ps
CPU time 2.24 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 209160 kb
Host smart-7f330c66-4f08-4a8c-bb7c-62407c629834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415431886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2415431886
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3557306020
Short name T633
Test name
Test status
Simulation time 10617940418 ps
CPU time 49.17 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:48 PM PDT 24
Peak memory 209616 kb
Host smart-52db4f26-9300-418e-ab5b-221e4384d2f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557306020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3557306020
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2981956182
Short name T429
Test name
Test status
Simulation time 42873451 ps
CPU time 2.29 seconds
Started Aug 13 05:43:52 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 207408 kb
Host smart-cefb6df7-cd06-40c5-bab2-c4b463a76545
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981956182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2981956182
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.113779315
Short name T592
Test name
Test status
Simulation time 109037469 ps
CPU time 4.14 seconds
Started Aug 13 05:43:46 PM PDT 24
Finished Aug 13 05:43:50 PM PDT 24
Peak memory 208744 kb
Host smart-2b5aa658-03b1-4050-bb85-98b649181195
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113779315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.113779315
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3565182241
Short name T283
Test name
Test status
Simulation time 299842385 ps
CPU time 7.3 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:43:59 PM PDT 24
Peak memory 220860 kb
Host smart-ea4ac801-3ce0-4b9a-8a10-25ddef9b2efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565182241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3565182241
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1265354803
Short name T613
Test name
Test status
Simulation time 185427117 ps
CPU time 5.56 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 208872 kb
Host smart-13c54c66-0535-4c58-b20e-4a941e424fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265354803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1265354803
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3922497136
Short name T57
Test name
Test status
Simulation time 237610372 ps
CPU time 11.04 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 221548 kb
Host smart-91798c35-9d52-4235-bf67-2e848605c8dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922497136 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3922497136
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3067587221
Short name T520
Test name
Test status
Simulation time 1058031299 ps
CPU time 11.75 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 210072 kb
Host smart-61d73583-4bf0-49df-b4be-72aa7d8f8d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067587221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3067587221
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2151713002
Short name T584
Test name
Test status
Simulation time 189365392 ps
CPU time 2.06 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:51 PM PDT 24
Peak memory 210648 kb
Host smart-97953be8-5c98-49ab-bbd8-0c4c7265c66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151713002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2151713002
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3619889771
Short name T483
Test name
Test status
Simulation time 10956702 ps
CPU time 0.73 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:49 PM PDT 24
Peak memory 206392 kb
Host smart-abb8ffab-77d8-42e6-bbcb-65195cc7e966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619889771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3619889771
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.4253619955
Short name T132
Test name
Test status
Simulation time 210099625 ps
CPU time 2.6 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:50 PM PDT 24
Peak memory 222736 kb
Host smart-27f665a7-2c8d-42bb-9f42-db7b6c8aceff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253619955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.4253619955
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.6325333
Short name T705
Test name
Test status
Simulation time 244157503 ps
CPU time 4.09 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:52 PM PDT 24
Peak memory 210288 kb
Host smart-1c05edd3-aa10-4fff-a79a-9de751aaccef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6325333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.6325333
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2989414115
Short name T735
Test name
Test status
Simulation time 265144779 ps
CPU time 3.12 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:52 PM PDT 24
Peak memory 214744 kb
Host smart-2a3f45a8-df2e-40b9-ae30-8f6a9d8d6e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989414115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2989414115
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3824060493
Short name T268
Test name
Test status
Simulation time 245821687 ps
CPU time 2.14 seconds
Started Aug 13 05:43:52 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 214772 kb
Host smart-7f868525-926a-4c49-9a34-7029bc5fe2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824060493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3824060493
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3489360648
Short name T754
Test name
Test status
Simulation time 59732799 ps
CPU time 2.98 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:52 PM PDT 24
Peak memory 222880 kb
Host smart-9b0a7c23-a8fa-4865-aa6d-5339e37786e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489360648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3489360648
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3591505091
Short name T714
Test name
Test status
Simulation time 314965119 ps
CPU time 3.57 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:52 PM PDT 24
Peak memory 209932 kb
Host smart-98d24ad1-cd08-4625-8023-409e1f47c355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591505091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3591505091
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1696521461
Short name T222
Test name
Test status
Simulation time 106125371 ps
CPU time 4.9 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:43:56 PM PDT 24
Peak memory 208704 kb
Host smart-aab84e12-23a3-479e-ad6a-1727e0399f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696521461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1696521461
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1239043732
Short name T901
Test name
Test status
Simulation time 121231925 ps
CPU time 3.88 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 207324 kb
Host smart-c64e320a-5736-47f0-bf55-c7454caa84fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239043732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1239043732
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1692530611
Short name T543
Test name
Test status
Simulation time 67684098 ps
CPU time 2.36 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:51 PM PDT 24
Peak memory 207436 kb
Host smart-f2832cf6-a5ff-48fd-a897-3feafdca7266
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692530611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1692530611
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.320268372
Short name T614
Test name
Test status
Simulation time 114065893 ps
CPU time 2.24 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 207328 kb
Host smart-b36b375b-ddc9-4e25-8e76-b042fe532b16
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320268372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.320268372
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3610204730
Short name T798
Test name
Test status
Simulation time 1115049517 ps
CPU time 12.07 seconds
Started Aug 13 05:43:52 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 209324 kb
Host smart-18a11009-9f18-4600-ae54-5bc103256a55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610204730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3610204730
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.856696544
Short name T585
Test name
Test status
Simulation time 590381685 ps
CPU time 14.88 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:44:06 PM PDT 24
Peak memory 214780 kb
Host smart-c7e96210-b010-4759-8652-616421570bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856696544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.856696544
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.937749104
Short name T864
Test name
Test status
Simulation time 276125107 ps
CPU time 7.72 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:55 PM PDT 24
Peak memory 207360 kb
Host smart-fdd5c078-1791-4d14-8eba-a98ce43e7b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937749104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.937749104
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1432895742
Short name T6
Test name
Test status
Simulation time 2307109859 ps
CPU time 21.61 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:44:13 PM PDT 24
Peak memory 222876 kb
Host smart-cf69cb0a-2dc6-410c-8c69-a4bc8ae0e6d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432895742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1432895742
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2526415
Short name T176
Test name
Test status
Simulation time 323741647 ps
CPU time 4.04 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:52 PM PDT 24
Peak memory 214856 kb
Host smart-e27c4a33-f336-45a9-9520-a222aa205e83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526415 -assert nopostpr
oc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2526415
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2093495049
Short name T285
Test name
Test status
Simulation time 682394433 ps
CPU time 19.11 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:44:10 PM PDT 24
Peak memory 214732 kb
Host smart-a8f1a5b0-4c7f-4335-99ac-2c5a68063e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093495049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2093495049
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.4008549226
Short name T497
Test name
Test status
Simulation time 38439474 ps
CPU time 2.18 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:51 PM PDT 24
Peak memory 210700 kb
Host smart-ed9c8dbf-b458-4603-9065-3c8bf33f49fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008549226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4008549226
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1319506904
Short name T709
Test name
Test status
Simulation time 35637247 ps
CPU time 0.83 seconds
Started Aug 13 05:43:56 PM PDT 24
Finished Aug 13 05:43:57 PM PDT 24
Peak memory 206412 kb
Host smart-9d7922b3-74d0-4698-b522-cfb037c9aec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319506904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1319506904
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3589232195
Short name T131
Test name
Test status
Simulation time 55968854 ps
CPU time 3.94 seconds
Started Aug 13 05:43:49 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 215764 kb
Host smart-57015d72-5158-4e06-a7bf-d28d50040326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589232195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3589232195
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1404632781
Short name T874
Test name
Test status
Simulation time 173984664 ps
CPU time 4.65 seconds
Started Aug 13 05:43:51 PM PDT 24
Finished Aug 13 05:43:56 PM PDT 24
Peak memory 219272 kb
Host smart-eb108995-948e-418a-bc1a-fb0b2b584ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404632781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1404632781
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3811679440
Short name T261
Test name
Test status
Simulation time 106069992 ps
CPU time 2.23 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 208512 kb
Host smart-d35fcda5-c3d9-4bbb-9fc7-0cf8a39bb1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811679440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3811679440
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2858281167
Short name T888
Test name
Test status
Simulation time 456860983 ps
CPU time 6.74 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:43:56 PM PDT 24
Peak memory 220952 kb
Host smart-515698e5-2bc1-4365-bb74-8afa1bc949a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858281167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2858281167
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.522537789
Short name T301
Test name
Test status
Simulation time 383879782 ps
CPU time 4.21 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 214704 kb
Host smart-83881404-4b39-41b2-90c8-e56dad88b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522537789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.522537789
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2862435485
Short name T685
Test name
Test status
Simulation time 171716981 ps
CPU time 3.4 seconds
Started Aug 13 05:43:47 PM PDT 24
Finished Aug 13 05:43:51 PM PDT 24
Peak memory 214928 kb
Host smart-167b4745-bac8-4453-877a-ef1f9d362126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862435485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2862435485
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.118784480
Short name T764
Test name
Test status
Simulation time 1478029225 ps
CPU time 6.27 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 209628 kb
Host smart-062eb27c-e57a-427e-88c5-8cfe4aafbd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118784480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.118784480
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.384228633
Short name T789
Test name
Test status
Simulation time 381128491 ps
CPU time 5.47 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 208392 kb
Host smart-c7ff8923-cbbf-4bbf-a3d7-4f296e8a2cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384228633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.384228633
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2671127094
Short name T307
Test name
Test status
Simulation time 197113060 ps
CPU time 2.76 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:43:53 PM PDT 24
Peak memory 209412 kb
Host smart-fa7bc28d-279b-4e1e-8c77-dbdec078bd9e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671127094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2671127094
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3251378992
Short name T712
Test name
Test status
Simulation time 135503937 ps
CPU time 3.19 seconds
Started Aug 13 05:43:50 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 207276 kb
Host smart-4b1ba124-577d-4233-bdb0-a660e01f883f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251378992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3251378992
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1805706952
Short name T353
Test name
Test status
Simulation time 65833249 ps
CPU time 2.77 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:51 PM PDT 24
Peak memory 210504 kb
Host smart-ef19f773-97bf-4748-b40f-c23245cb3cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805706952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1805706952
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2063044773
Short name T659
Test name
Test status
Simulation time 2104917157 ps
CPU time 12.6 seconds
Started Aug 13 05:43:47 PM PDT 24
Finished Aug 13 05:44:00 PM PDT 24
Peak memory 208844 kb
Host smart-b1ba3bfb-879f-473b-872b-31aec2af8684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063044773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2063044773
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.4289349114
Short name T576
Test name
Test status
Simulation time 205760018 ps
CPU time 5.6 seconds
Started Aug 13 05:43:48 PM PDT 24
Finished Aug 13 05:43:54 PM PDT 24
Peak memory 210696 kb
Host smart-6c24ed5e-a2bd-4b97-a03e-485ef36f576f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289349114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.4289349114
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3146723003
Short name T790
Test name
Test status
Simulation time 288169336 ps
CPU time 1.82 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:01 PM PDT 24
Peak memory 210296 kb
Host smart-82b7eed1-5623-4e03-b8a8-49c3ea26fd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146723003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3146723003
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2579920205
Short name T647
Test name
Test status
Simulation time 41011220 ps
CPU time 0.77 seconds
Started Aug 13 05:42:18 PM PDT 24
Finished Aug 13 05:42:18 PM PDT 24
Peak memory 206396 kb
Host smart-bf59e550-81b2-425e-b92e-d09a36bb06f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579920205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2579920205
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.868761042
Short name T861
Test name
Test status
Simulation time 197205149 ps
CPU time 2.84 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:20 PM PDT 24
Peak memory 209096 kb
Host smart-701d6a87-1a56-4ebb-a61b-1dba4015b2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868761042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.868761042
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.156806313
Short name T884
Test name
Test status
Simulation time 359487436 ps
CPU time 5.96 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:30 PM PDT 24
Peak memory 209720 kb
Host smart-5dd2ebc9-d245-4042-992b-3c9d6f0c42da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156806313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.156806313
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.21590937
Short name T679
Test name
Test status
Simulation time 243845066 ps
CPU time 3.37 seconds
Started Aug 13 05:42:13 PM PDT 24
Finished Aug 13 05:42:17 PM PDT 24
Peak memory 214700 kb
Host smart-c490196d-70cf-43f0-b912-acd32599a338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21590937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.21590937
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1018397218
Short name T334
Test name
Test status
Simulation time 74944908 ps
CPU time 3.54 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:21 PM PDT 24
Peak memory 210356 kb
Host smart-1a0d21e2-fcab-48fb-9aca-bd8282ff52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018397218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1018397218
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1755895766
Short name T32
Test name
Test status
Simulation time 49218032 ps
CPU time 3.34 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:20 PM PDT 24
Peak memory 207404 kb
Host smart-38a0bd32-0468-4cc3-8e8f-a06594e9ccac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755895766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1755895766
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3789559444
Short name T9
Test name
Test status
Simulation time 891992372 ps
CPU time 9.81 seconds
Started Aug 13 05:42:18 PM PDT 24
Finished Aug 13 05:42:27 PM PDT 24
Peak memory 235912 kb
Host smart-8620cef7-9a16-4685-8154-9e662149fed0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789559444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3789559444
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3029956984
Short name T783
Test name
Test status
Simulation time 154403707 ps
CPU time 5.06 seconds
Started Aug 13 05:42:18 PM PDT 24
Finished Aug 13 05:42:23 PM PDT 24
Peak memory 208308 kb
Host smart-f16a9a01-51c2-4165-a738-fb189a1da40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029956984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3029956984
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1199312293
Short name T546
Test name
Test status
Simulation time 638350399 ps
CPU time 16.31 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:34 PM PDT 24
Peak memory 208768 kb
Host smart-1b8eb7bd-05aa-40e7-a4bc-1f38d5c050bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199312293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1199312293
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2432370905
Short name T883
Test name
Test status
Simulation time 412744744 ps
CPU time 6.03 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:30 PM PDT 24
Peak memory 208544 kb
Host smart-02b9fefb-e07d-46d8-87d6-118aa96aab4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432370905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2432370905
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1340007077
Short name T442
Test name
Test status
Simulation time 22602303 ps
CPU time 1.87 seconds
Started Aug 13 05:42:16 PM PDT 24
Finished Aug 13 05:42:18 PM PDT 24
Peak memory 207500 kb
Host smart-5639a720-d937-4769-9bca-2b3fb07b8144
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340007077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1340007077
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3910297189
Short name T761
Test name
Test status
Simulation time 300400001 ps
CPU time 2.62 seconds
Started Aug 13 05:42:15 PM PDT 24
Finished Aug 13 05:42:18 PM PDT 24
Peak memory 216216 kb
Host smart-0e3fd345-9644-4217-b9ea-4fdbb1550a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910297189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3910297189
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2097743469
Short name T906
Test name
Test status
Simulation time 2729431660 ps
CPU time 22.38 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:40 PM PDT 24
Peak memory 208600 kb
Host smart-126d157d-3140-4626-a275-744a6ac9c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097743469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2097743469
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1541544884
Short name T449
Test name
Test status
Simulation time 232411645 ps
CPU time 5.12 seconds
Started Aug 13 05:42:19 PM PDT 24
Finished Aug 13 05:42:24 PM PDT 24
Peak memory 218784 kb
Host smart-f1040aed-d52e-42f6-8a50-c4d42bcad9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541544884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1541544884
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2497666433
Short name T35
Test name
Test status
Simulation time 204891648 ps
CPU time 2.66 seconds
Started Aug 13 05:42:16 PM PDT 24
Finished Aug 13 05:42:19 PM PDT 24
Peak memory 210676 kb
Host smart-136f7b4f-d3a4-4f63-b01c-5e87335d693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497666433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2497666433
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3246283569
Short name T541
Test name
Test status
Simulation time 15052756 ps
CPU time 0.77 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:43:58 PM PDT 24
Peak memory 206440 kb
Host smart-09a3e580-db2c-4306-be52-f3a7ab52c2c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246283569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3246283569
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.763548316
Short name T102
Test name
Test status
Simulation time 58056729 ps
CPU time 4.07 seconds
Started Aug 13 05:44:00 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 214816 kb
Host smart-b2a88d14-82fa-44bc-9740-4e8776ac17af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763548316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.763548316
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3056075265
Short name T631
Test name
Test status
Simulation time 37617101 ps
CPU time 2.48 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 222884 kb
Host smart-dbcb6732-d75a-4a14-93b8-a6602ac0aae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056075265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3056075265
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3237810053
Short name T511
Test name
Test status
Simulation time 182114810 ps
CPU time 1.94 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:01 PM PDT 24
Peak memory 208220 kb
Host smart-53011c55-60d9-4d1c-afad-71a07db07256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237810053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3237810053
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3140538848
Short name T281
Test name
Test status
Simulation time 92083274 ps
CPU time 3.13 seconds
Started Aug 13 05:44:00 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 214784 kb
Host smart-3558398e-b66a-4afe-83c9-f9324aa57afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140538848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3140538848
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1259985206
Short name T539
Test name
Test status
Simulation time 154928148 ps
CPU time 7.18 seconds
Started Aug 13 05:44:00 PM PDT 24
Finished Aug 13 05:44:07 PM PDT 24
Peak memory 222784 kb
Host smart-19b6e15b-0127-43d1-8335-36ec2b55ae2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259985206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1259985206
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3735449114
Short name T383
Test name
Test status
Simulation time 94350940 ps
CPU time 3.5 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:01 PM PDT 24
Peak memory 214664 kb
Host smart-6793a1b5-0e3b-42f4-8345-4a567e518b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735449114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3735449114
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2543006267
Short name T465
Test name
Test status
Simulation time 178102096 ps
CPU time 5.56 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 209116 kb
Host smart-a4dc7d0b-b3b7-4a9f-bf6e-9dc3fa05c247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543006267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2543006267
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.616995655
Short name T849
Test name
Test status
Simulation time 199971965 ps
CPU time 3.09 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:00 PM PDT 24
Peak memory 209056 kb
Host smart-6914dd6a-359b-49d3-aace-adf1f97c2cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616995655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.616995655
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.844967895
Short name T256
Test name
Test status
Simulation time 5209851679 ps
CPU time 12.81 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 209412 kb
Host smart-11c9ff42-bcaf-4488-a28f-75795130d096
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844967895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.844967895
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.586392326
Short name T425
Test name
Test status
Simulation time 54481088 ps
CPU time 2.9 seconds
Started Aug 13 05:43:55 PM PDT 24
Finished Aug 13 05:43:58 PM PDT 24
Peak memory 207400 kb
Host smart-d7cef9f4-e1c9-44ba-8cae-4a57f7e7e5e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586392326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.586392326
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.958986102
Short name T624
Test name
Test status
Simulation time 191776618 ps
CPU time 5.52 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 208644 kb
Host smart-63e734e2-7d73-469f-834b-51131ab4be64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958986102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.958986102
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2328333087
Short name T755
Test name
Test status
Simulation time 94915774 ps
CPU time 2.58 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:00 PM PDT 24
Peak memory 209840 kb
Host smart-ccf8f0ce-4f16-4233-9ff3-c2dbd996aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328333087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2328333087
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3384541045
Short name T557
Test name
Test status
Simulation time 163322813 ps
CPU time 2.27 seconds
Started Aug 13 05:44:02 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 207724 kb
Host smart-11d4f573-c1f9-4287-a783-e78c374ebffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384541045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3384541045
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2611200970
Short name T622
Test name
Test status
Simulation time 84154502 ps
CPU time 4.22 seconds
Started Aug 13 05:43:54 PM PDT 24
Finished Aug 13 05:43:59 PM PDT 24
Peak memory 223092 kb
Host smart-97252acb-94d5-47ce-a28d-0eaabcf10c67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611200970 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2611200970
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.239431416
Short name T733
Test name
Test status
Simulation time 68859041 ps
CPU time 2.96 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:00 PM PDT 24
Peak memory 207884 kb
Host smart-e959595b-62e2-472d-a7c5-95ba8dfe8fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239431416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.239431416
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3570529008
Short name T386
Test name
Test status
Simulation time 503095114 ps
CPU time 3.35 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 210192 kb
Host smart-9216b6ce-b1fc-4794-9ead-cf190f3309e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570529008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3570529008
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1079953275
Short name T504
Test name
Test status
Simulation time 59475403 ps
CPU time 0.8 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 205972 kb
Host smart-5f48cb5e-e547-4346-b36a-a1030dc7033d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079953275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1079953275
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1821070773
Short name T401
Test name
Test status
Simulation time 53950724 ps
CPU time 3.9 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:44:05 PM PDT 24
Peak memory 214792 kb
Host smart-7137b2ff-5504-4887-8ed1-ac7aa296fb4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821070773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1821070773
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3138601788
Short name T686
Test name
Test status
Simulation time 276486178 ps
CPU time 3.43 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 215108 kb
Host smart-2a5f8dfc-b376-4380-8910-334adc74ec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138601788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3138601788
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.4017005906
Short name T725
Test name
Test status
Simulation time 672741015 ps
CPU time 14.17 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:11 PM PDT 24
Peak memory 209132 kb
Host smart-3717fd84-160e-4a80-85db-bb9f274769e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017005906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.4017005906
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.468993515
Short name T228
Test name
Test status
Simulation time 40723196 ps
CPU time 2.1 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 214740 kb
Host smart-2eb26e82-fbce-4904-9fe9-d7110e979418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468993515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.468993515
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2445802900
Short name T340
Test name
Test status
Simulation time 55419354 ps
CPU time 2.11 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:00 PM PDT 24
Peak memory 214700 kb
Host smart-ab8ecf1e-5c6c-4c73-a243-f66e05243f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445802900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2445802900
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.35106747
Short name T634
Test name
Test status
Simulation time 601792607 ps
CPU time 4.29 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 214876 kb
Host smart-9045488a-7c90-421c-b3d7-64f6eba7fa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35106747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.35106747
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3591671103
Short name T792
Test name
Test status
Simulation time 1020455994 ps
CPU time 11.58 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:09 PM PDT 24
Peak memory 208660 kb
Host smart-e1114a24-9acb-4b28-b30c-6fe6698ed2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591671103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3591671103
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1809650843
Short name T548
Test name
Test status
Simulation time 112911552 ps
CPU time 3.02 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 209028 kb
Host smart-007a97bd-5e78-4f78-b56c-a710e4a3988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809650843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1809650843
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2620577955
Short name T515
Test name
Test status
Simulation time 131430906 ps
CPU time 4.18 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 209044 kb
Host smart-271e696e-dbeb-46a6-945b-465468443e40
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620577955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2620577955
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.465961081
Short name T14
Test name
Test status
Simulation time 343132545 ps
CPU time 5.47 seconds
Started Aug 13 05:43:56 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 209144 kb
Host smart-e5aeec9b-e417-46ad-8adc-af51ed97646c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465961081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.465961081
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3731204554
Short name T525
Test name
Test status
Simulation time 76303868 ps
CPU time 3.49 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:01 PM PDT 24
Peak memory 209236 kb
Host smart-4d7ce693-1c23-486f-a46a-b24693d73e12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731204554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3731204554
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3299186674
Short name T639
Test name
Test status
Simulation time 568252553 ps
CPU time 15.74 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:15 PM PDT 24
Peak memory 214596 kb
Host smart-ccab40fb-b37c-4e5a-8260-e71f4218c8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299186674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3299186674
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3874917940
Short name T785
Test name
Test status
Simulation time 152722340 ps
CPU time 4.67 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 208388 kb
Host smart-e103f48c-bd38-44be-9359-7b9b8e9ec1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874917940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3874917940
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3556398384
Short name T126
Test name
Test status
Simulation time 258845224 ps
CPU time 5.6 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 209148 kb
Host smart-f960bc3c-0ef1-483e-b9e5-de0d6b44fd45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556398384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3556398384
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3229222313
Short name T77
Test name
Test status
Simulation time 6640520340 ps
CPU time 34.62 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:33 PM PDT 24
Peak memory 222772 kb
Host smart-7019cda1-ab32-40ad-ae71-db7c43458550
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229222313 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3229222313
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1996554731
Short name T482
Test name
Test status
Simulation time 322899071 ps
CPU time 4.95 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 210316 kb
Host smart-55dfe183-8707-48d2-9233-99d3ad6abda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996554731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1996554731
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3577739635
Short name T889
Test name
Test status
Simulation time 11850008 ps
CPU time 0.86 seconds
Started Aug 13 05:44:00 PM PDT 24
Finished Aug 13 05:44:01 PM PDT 24
Peak memory 206380 kb
Host smart-f342d215-f315-40eb-aed3-6e29ee682c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577739635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3577739635
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.148133092
Short name T17
Test name
Test status
Simulation time 186784621 ps
CPU time 2.75 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 221180 kb
Host smart-bfa6b786-5df1-4d9a-9304-37bf2e8045b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148133092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.148133092
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2455777988
Short name T45
Test name
Test status
Simulation time 2104563642 ps
CPU time 24.24 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:23 PM PDT 24
Peak memory 214800 kb
Host smart-57d2ca67-971d-4d3a-a875-716604159ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455777988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2455777988
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1455196489
Short name T408
Test name
Test status
Simulation time 206814653 ps
CPU time 5.21 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 214736 kb
Host smart-78d67d4e-88d0-4f3e-9aa5-9b8c9bcfcdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455196489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1455196489
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1961057076
Short name T181
Test name
Test status
Simulation time 485786437 ps
CPU time 9.61 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:09 PM PDT 24
Peak memory 214772 kb
Host smart-a819290c-7ed5-4a37-a076-32d244c9c13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961057076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1961057076
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3005831050
Short name T453
Test name
Test status
Simulation time 154865991 ps
CPU time 5.19 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 207376 kb
Host smart-cb6d05f9-6b47-4002-bb03-3a3b22adea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005831050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3005831050
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2997083043
Short name T450
Test name
Test status
Simulation time 1366368984 ps
CPU time 24.81 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:22 PM PDT 24
Peak memory 207520 kb
Host smart-cd876e06-57f9-40c1-875a-f3e6aac7b522
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997083043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2997083043
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2861538716
Short name T871
Test name
Test status
Simulation time 167084941 ps
CPU time 3.4 seconds
Started Aug 13 05:43:56 PM PDT 24
Finished Aug 13 05:44:00 PM PDT 24
Peak memory 208968 kb
Host smart-d9c68532-bd2a-4da6-81a5-495041642550
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861538716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2861538716
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1782161532
Short name T821
Test name
Test status
Simulation time 612431218 ps
CPU time 3.26 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:44:00 PM PDT 24
Peak memory 207400 kb
Host smart-7a00b1d6-4e8a-4c3f-85ad-4c0e8fb6c8ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782161532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1782161532
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3142927230
Short name T447
Test name
Test status
Simulation time 88719562 ps
CPU time 2.41 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:43:59 PM PDT 24
Peak memory 209796 kb
Host smart-84d07467-8ad2-439a-97ce-60f927dc8901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142927230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3142927230
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1720214024
Short name T753
Test name
Test status
Simulation time 59369265 ps
CPU time 2.22 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:01 PM PDT 24
Peak memory 207440 kb
Host smart-0f164e2a-1ce5-4f27-8de1-41fee718688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720214024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1720214024
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2782380079
Short name T201
Test name
Test status
Simulation time 8913980188 ps
CPU time 231.74 seconds
Started Aug 13 05:43:56 PM PDT 24
Finished Aug 13 05:47:48 PM PDT 24
Peak memory 222920 kb
Host smart-8b1da813-a97a-47f1-ad65-c43b9458b863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782380079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2782380079
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1056485164
Short name T306
Test name
Test status
Simulation time 482780503 ps
CPU time 15.07 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:14 PM PDT 24
Peak memory 220980 kb
Host smart-9cff78f4-f642-4696-9d07-d6e9433fa090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056485164 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1056485164
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.964103594
Short name T258
Test name
Test status
Simulation time 506165761 ps
CPU time 4.53 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:02 PM PDT 24
Peak memory 214740 kb
Host smart-dbee21d6-49b4-4141-86a3-125eb441ec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964103594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.964103594
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1489922554
Short name T619
Test name
Test status
Simulation time 100082174 ps
CPU time 1.97 seconds
Started Aug 13 05:43:57 PM PDT 24
Finished Aug 13 05:43:59 PM PDT 24
Peak memory 210632 kb
Host smart-21e06e4d-e954-4c89-8615-7f31d92364c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489922554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1489922554
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.651202015
Short name T776
Test name
Test status
Simulation time 20030544 ps
CPU time 0.74 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:00 PM PDT 24
Peak memory 206404 kb
Host smart-98b8b94e-67a8-47b3-90a9-f0277bcef965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651202015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.651202015
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2128591773
Short name T405
Test name
Test status
Simulation time 955959937 ps
CPU time 4.31 seconds
Started Aug 13 05:44:00 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 214792 kb
Host smart-ac8c4336-bb69-4b63-b329-4b8123b65c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128591773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2128591773
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2496546028
Short name T689
Test name
Test status
Simulation time 125292012 ps
CPU time 1.7 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:44:03 PM PDT 24
Peak memory 208216 kb
Host smart-6895a678-0a58-4aff-9a65-ee3482aa1fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496546028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2496546028
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3613580039
Short name T93
Test name
Test status
Simulation time 37883392 ps
CPU time 2.38 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:07 PM PDT 24
Peak memory 210376 kb
Host smart-75c3c1e6-3b4c-477c-90b8-b4ab6f1b951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613580039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3613580039
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1916633498
Short name T852
Test name
Test status
Simulation time 526948857 ps
CPU time 5.44 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:05 PM PDT 24
Peak memory 222872 kb
Host smart-a19a9411-3c6d-4a3a-ad6b-bcc58a1c7859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916633498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1916633498
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_random.3866879848
Short name T632
Test name
Test status
Simulation time 1260881958 ps
CPU time 8.11 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:07 PM PDT 24
Peak memory 214796 kb
Host smart-ffcfb48f-f146-4ca2-8113-4d325f37afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866879848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3866879848
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.740778052
Short name T800
Test name
Test status
Simulation time 156717268 ps
CPU time 4.21 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 207316 kb
Host smart-96da4cf0-122e-416a-a936-bd59f37dfaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740778052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.740778052
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.59131966
Short name T595
Test name
Test status
Simulation time 5000000259 ps
CPU time 26.66 seconds
Started Aug 13 05:43:59 PM PDT 24
Finished Aug 13 05:44:26 PM PDT 24
Peak memory 208740 kb
Host smart-055077f9-e24d-4e3b-8fa1-3be3c5d8c527
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59131966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.59131966
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.648799285
Short name T529
Test name
Test status
Simulation time 171450169 ps
CPU time 6.2 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:44:07 PM PDT 24
Peak memory 209324 kb
Host smart-1c5264cd-5f87-4a99-a4ca-0c18fe9baba1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648799285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.648799285
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1276979816
Short name T567
Test name
Test status
Simulation time 65725730 ps
CPU time 2.41 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 207136 kb
Host smart-0cdc4eed-0ab7-4bfc-b9f8-7e5926a2c871
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276979816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1276979816
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3184892308
Short name T897
Test name
Test status
Simulation time 243652853 ps
CPU time 5.25 seconds
Started Aug 13 05:44:04 PM PDT 24
Finished Aug 13 05:44:09 PM PDT 24
Peak memory 209332 kb
Host smart-ef49aa9d-f855-4f63-a359-5cecedd10eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184892308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3184892308
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.362212146
Short name T468
Test name
Test status
Simulation time 815558651 ps
CPU time 13.07 seconds
Started Aug 13 05:43:58 PM PDT 24
Finished Aug 13 05:44:11 PM PDT 24
Peak memory 209112 kb
Host smart-c584ef79-776e-461e-b2fb-2524741bc6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362212146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.362212146
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1451757541
Short name T786
Test name
Test status
Simulation time 13435177534 ps
CPU time 234.4 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:47:59 PM PDT 24
Peak memory 222912 kb
Host smart-a52ff1b4-df74-468b-a5d5-d6fafdfea7c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451757541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1451757541
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3800461281
Short name T788
Test name
Test status
Simulation time 3890370458 ps
CPU time 38.11 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:44:40 PM PDT 24
Peak memory 218724 kb
Host smart-22789f15-4f5f-47a2-8147-90508c05e0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800461281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3800461281
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.465711767
Short name T164
Test name
Test status
Simulation time 1274358670 ps
CPU time 3 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:08 PM PDT 24
Peak memory 210928 kb
Host smart-1e3423b4-f2d9-4c0f-b7c5-3fa800be97b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465711767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.465711767
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1654803373
Short name T762
Test name
Test status
Simulation time 22223699 ps
CPU time 0.9 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:04 PM PDT 24
Peak memory 206336 kb
Host smart-167255d2-c313-482b-b6e7-6cdf2bad6dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654803373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1654803373
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2851249245
Short name T66
Test name
Test status
Simulation time 154900522 ps
CPU time 6.13 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:11 PM PDT 24
Peak memory 211388 kb
Host smart-cba4db81-1b9f-40c1-a646-332449a5b3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851249245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2851249245
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3724134800
Short name T742
Test name
Test status
Simulation time 1227927154 ps
CPU time 8.41 seconds
Started Aug 13 05:44:06 PM PDT 24
Finished Aug 13 05:44:14 PM PDT 24
Peak memory 209756 kb
Host smart-213775c1-11fe-4088-ac7f-e72eff81138e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724134800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3724134800
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.283938038
Short name T225
Test name
Test status
Simulation time 239922052 ps
CPU time 2.97 seconds
Started Aug 13 05:44:10 PM PDT 24
Finished Aug 13 05:44:13 PM PDT 24
Peak memory 214804 kb
Host smart-3a2b1e2e-024c-4656-a652-76e9490d658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283938038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.283938038
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3632042247
Short name T698
Test name
Test status
Simulation time 1162031913 ps
CPU time 3.72 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:07 PM PDT 24
Peak memory 214736 kb
Host smart-b6aa96fc-8608-4050-819b-785c069549af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632042247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3632042247
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3320627443
Short name T385
Test name
Test status
Simulation time 240906283 ps
CPU time 3.62 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:06 PM PDT 24
Peak memory 221136 kb
Host smart-f164d1e3-9cd0-48ad-9566-d26792e79f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320627443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3320627443
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.826826429
Short name T361
Test name
Test status
Simulation time 71738172 ps
CPU time 3.71 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:18 PM PDT 24
Peak memory 210060 kb
Host smart-ca63b7cd-111d-4d32-ab97-ab2e72b8f896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826826429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.826826429
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.543340402
Short name T519
Test name
Test status
Simulation time 177985332 ps
CPU time 4.98 seconds
Started Aug 13 05:44:11 PM PDT 24
Finished Aug 13 05:44:16 PM PDT 24
Peak memory 208920 kb
Host smart-3649ba73-19e7-43ab-bb57-4bdfefaa7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543340402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.543340402
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3559501993
Short name T315
Test name
Test status
Simulation time 33757353 ps
CPU time 2.24 seconds
Started Aug 13 05:44:10 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 206588 kb
Host smart-3f93ac31-a937-4181-8c09-b2ce3d234579
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559501993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3559501993
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.292899205
Short name T808
Test name
Test status
Simulation time 381285688 ps
CPU time 6.05 seconds
Started Aug 13 05:44:04 PM PDT 24
Finished Aug 13 05:44:10 PM PDT 24
Peak memory 208456 kb
Host smart-f8367001-897f-4af2-b0b9-c1378b5dcb91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292899205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.292899205
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2069861274
Short name T676
Test name
Test status
Simulation time 3343072239 ps
CPU time 20.24 seconds
Started Aug 13 05:44:04 PM PDT 24
Finished Aug 13 05:44:24 PM PDT 24
Peak memory 208876 kb
Host smart-f3149f45-00e2-4a8e-97e0-6ba3cfa9808f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069861274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2069861274
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.949706486
Short name T596
Test name
Test status
Simulation time 194781224 ps
CPU time 2.04 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:07 PM PDT 24
Peak memory 215984 kb
Host smart-78068cb6-0e65-4200-b108-4abf0eba9a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949706486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.949706486
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3841814329
Short name T537
Test name
Test status
Simulation time 2370756663 ps
CPU time 4.75 seconds
Started Aug 13 05:44:04 PM PDT 24
Finished Aug 13 05:44:09 PM PDT 24
Peak memory 207360 kb
Host smart-307197c5-7001-4554-91bc-560714b00322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841814329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3841814329
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2232158329
Short name T44
Test name
Test status
Simulation time 12612152155 ps
CPU time 150.9 seconds
Started Aug 13 05:44:01 PM PDT 24
Finished Aug 13 05:46:32 PM PDT 24
Peak memory 217576 kb
Host smart-0dd07973-1620-42d6-a7ff-580b41f00dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232158329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2232158329
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.460924585
Short name T351
Test name
Test status
Simulation time 1320621913 ps
CPU time 10.4 seconds
Started Aug 13 05:44:04 PM PDT 24
Finished Aug 13 05:44:15 PM PDT 24
Peak memory 223008 kb
Host smart-2fcd0bae-8dbb-45f5-9dc5-f95bb51eea79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460924585 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.460924585
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1685271477
Short name T16
Test name
Test status
Simulation time 199563906 ps
CPU time 3.45 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:06 PM PDT 24
Peak memory 208116 kb
Host smart-3bab9074-dfb1-4c12-8615-18330c3ad1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685271477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1685271477
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3737865399
Short name T732
Test name
Test status
Simulation time 127171300 ps
CPU time 4.35 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:08 PM PDT 24
Peak memory 211100 kb
Host smart-c1edc426-dd88-45df-b81a-56dfdcbe0ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737865399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3737865399
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4036726694
Short name T424
Test name
Test status
Simulation time 104811366 ps
CPU time 0.76 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:05 PM PDT 24
Peak memory 206368 kb
Host smart-503b9ac7-26ba-41e0-a44e-59322df5348a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036726694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4036726694
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2997277473
Short name T110
Test name
Test status
Simulation time 106505656 ps
CPU time 2.23 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:05 PM PDT 24
Peak memory 214788 kb
Host smart-d40a2db1-3721-4377-9974-36034e774db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2997277473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2997277473
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.397773394
Short name T813
Test name
Test status
Simulation time 69673307 ps
CPU time 3.06 seconds
Started Aug 13 05:44:09 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 211060 kb
Host smart-3c7cd421-c78c-4ae5-93b9-85a443c86141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397773394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.397773394
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3429735260
Short name T426
Test name
Test status
Simulation time 98093135 ps
CPU time 1.95 seconds
Started Aug 13 05:44:06 PM PDT 24
Finished Aug 13 05:44:08 PM PDT 24
Peak memory 208852 kb
Host smart-2fccce36-0ef3-4232-8a22-c3ff034dd986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429735260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3429735260
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1737805061
Short name T708
Test name
Test status
Simulation time 33354740 ps
CPU time 2.41 seconds
Started Aug 13 05:44:06 PM PDT 24
Finished Aug 13 05:44:08 PM PDT 24
Peak memory 214904 kb
Host smart-26effd62-a7bf-463d-867c-66d84669c6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737805061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1737805061
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.4149228166
Short name T615
Test name
Test status
Simulation time 286292848 ps
CPU time 3.82 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:07 PM PDT 24
Peak memory 214696 kb
Host smart-ec2412ab-0918-4632-91d1-7be06decd7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149228166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.4149228166
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3432897225
Short name T840
Test name
Test status
Simulation time 125430431 ps
CPU time 3.19 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:06 PM PDT 24
Peak memory 223016 kb
Host smart-68a0e05b-24f1-45b4-b5f5-76fb2402a6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432897225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3432897225
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1470926957
Short name T803
Test name
Test status
Simulation time 384629287 ps
CPU time 5.01 seconds
Started Aug 13 05:44:11 PM PDT 24
Finished Aug 13 05:44:16 PM PDT 24
Peak memory 214728 kb
Host smart-6bdde43e-de17-4f63-a703-c0ba5be4481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470926957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1470926957
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3231065699
Short name T621
Test name
Test status
Simulation time 739427312 ps
CPU time 8.6 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:14 PM PDT 24
Peak memory 209176 kb
Host smart-0bdd70ce-8607-472d-8b82-2a05499d3b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231065699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3231065699
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3433361621
Short name T908
Test name
Test status
Simulation time 123932646 ps
CPU time 2.49 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 208120 kb
Host smart-79098cc0-046b-4ce6-87a0-860ec35256a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433361621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3433361621
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.4139699219
Short name T420
Test name
Test status
Simulation time 63946558 ps
CPU time 2.49 seconds
Started Aug 13 05:44:04 PM PDT 24
Finished Aug 13 05:44:07 PM PDT 24
Peak memory 207316 kb
Host smart-bec1c3ca-80f8-4bf3-a049-92c8f89d3f34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139699219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.4139699219
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2463292058
Short name T248
Test name
Test status
Simulation time 119802567 ps
CPU time 4.06 seconds
Started Aug 13 05:44:09 PM PDT 24
Finished Aug 13 05:44:13 PM PDT 24
Peak memory 207220 kb
Host smart-87bbd727-acbe-4aa8-bc1a-c06fcba5cd67
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463292058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2463292058
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.417363744
Short name T418
Test name
Test status
Simulation time 145502896 ps
CPU time 3.37 seconds
Started Aug 13 05:44:15 PM PDT 24
Finished Aug 13 05:44:19 PM PDT 24
Peak memory 208700 kb
Host smart-29921996-e75b-4411-a8da-8eeef6a0e01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417363744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.417363744
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1376984759
Short name T838
Test name
Test status
Simulation time 377128405 ps
CPU time 2.69 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 208856 kb
Host smart-fa5c7401-e956-40f8-98c7-1f44a0319d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376984759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1376984759
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2546180475
Short name T100
Test name
Test status
Simulation time 138021977 ps
CPU time 5.06 seconds
Started Aug 13 05:44:10 PM PDT 24
Finished Aug 13 05:44:15 PM PDT 24
Peak memory 208448 kb
Host smart-494b0b01-652e-420b-ac8c-c4b27a9c192b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546180475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2546180475
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2375317812
Short name T751
Test name
Test status
Simulation time 921693424 ps
CPU time 12.81 seconds
Started Aug 13 05:44:04 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 222936 kb
Host smart-a72050f1-022f-4e44-98fb-417a717eb730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375317812 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2375317812
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1897725242
Short name T356
Test name
Test status
Simulation time 418617934 ps
CPU time 3.37 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:18 PM PDT 24
Peak memory 209760 kb
Host smart-1adcc814-c52c-433f-bad9-25eae55f2b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897725242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1897725242
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2958302276
Short name T371
Test name
Test status
Simulation time 48832546 ps
CPU time 2.38 seconds
Started Aug 13 05:44:10 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 210424 kb
Host smart-573344ed-5895-401b-a7e6-a59661b58fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958302276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2958302276
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1653071257
Short name T454
Test name
Test status
Simulation time 12905677 ps
CPU time 0.86 seconds
Started Aug 13 05:44:11 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 206396 kb
Host smart-c24bb840-d26f-43af-b8ba-72fbf031c71f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653071257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1653071257
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2286215280
Short name T68
Test name
Test status
Simulation time 132788260 ps
CPU time 2.4 seconds
Started Aug 13 05:44:02 PM PDT 24
Finished Aug 13 05:44:05 PM PDT 24
Peak memory 209656 kb
Host smart-25b8b9c6-3efa-4ad5-9795-5358d4b589f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286215280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2286215280
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2767592429
Short name T367
Test name
Test status
Simulation time 60009642 ps
CPU time 2.21 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:05 PM PDT 24
Peak memory 214740 kb
Host smart-85a7ebf6-cb25-4e01-920e-ac56b6e67c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767592429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2767592429
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1617671122
Short name T644
Test name
Test status
Simulation time 89350434 ps
CPU time 2.97 seconds
Started Aug 13 05:44:06 PM PDT 24
Finished Aug 13 05:44:09 PM PDT 24
Peak memory 214704 kb
Host smart-ee8fc9a8-177b-4025-83d5-f9a74e99dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617671122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1617671122
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1028116598
Short name T499
Test name
Test status
Simulation time 450358588 ps
CPU time 3.77 seconds
Started Aug 13 05:44:03 PM PDT 24
Finished Aug 13 05:44:07 PM PDT 24
Peak memory 222832 kb
Host smart-d1c5ecf4-f166-4e93-945b-86fc8b86ad9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028116598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1028116598
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3024894996
Short name T188
Test name
Test status
Simulation time 75865073 ps
CPU time 2.55 seconds
Started Aug 13 05:44:07 PM PDT 24
Finished Aug 13 05:44:09 PM PDT 24
Peak memory 218664 kb
Host smart-1da6b27a-093c-47ad-a7ea-be7c3c2b2ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024894996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3024894996
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1821015938
Short name T187
Test name
Test status
Simulation time 1481458716 ps
CPU time 43.13 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:48 PM PDT 24
Peak memory 208864 kb
Host smart-6b5868e4-efa5-4922-8f5e-44eac7e1f6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821015938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1821015938
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3766910516
Short name T119
Test name
Test status
Simulation time 633985436 ps
CPU time 2.68 seconds
Started Aug 13 05:44:02 PM PDT 24
Finished Aug 13 05:44:05 PM PDT 24
Peak memory 207496 kb
Host smart-4bfb300b-8159-4b59-9bbd-c4667d0dc9a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766910516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3766910516
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2972746498
Short name T309
Test name
Test status
Simulation time 640005485 ps
CPU time 15.79 seconds
Started Aug 13 05:44:10 PM PDT 24
Finished Aug 13 05:44:26 PM PDT 24
Peak memory 209272 kb
Host smart-678c2585-d715-4f36-bf1a-d899fee7a9fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972746498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2972746498
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3042419673
Short name T528
Test name
Test status
Simulation time 166090832 ps
CPU time 2.32 seconds
Started Aug 13 05:44:06 PM PDT 24
Finished Aug 13 05:44:08 PM PDT 24
Peak memory 207336 kb
Host smart-2166b3e4-5bfa-4a2f-8aef-a194234ab59a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042419673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3042419673
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2281230256
Short name T695
Test name
Test status
Simulation time 166597950 ps
CPU time 3.22 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:09 PM PDT 24
Peak memory 221080 kb
Host smart-3ea9012f-294b-49dc-a78d-fd857f8244da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281230256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2281230256
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2094544880
Short name T427
Test name
Test status
Simulation time 66951725 ps
CPU time 2.51 seconds
Started Aug 13 05:44:09 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 208680 kb
Host smart-acbfa765-1e03-4d5a-8e73-f94da283894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094544880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2094544880
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1382725994
Short name T914
Test name
Test status
Simulation time 602032993 ps
CPU time 21.33 seconds
Started Aug 13 05:44:12 PM PDT 24
Finished Aug 13 05:44:33 PM PDT 24
Peak memory 223068 kb
Host smart-a96c43ef-6cf8-4c73-a145-733ff335ae29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382725994 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1382725994
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3755024045
Short name T554
Test name
Test status
Simulation time 2897260031 ps
CPU time 9.21 seconds
Started Aug 13 05:44:05 PM PDT 24
Finished Aug 13 05:44:14 PM PDT 24
Peak memory 214792 kb
Host smart-4eb2ba68-1c2a-421b-b7ac-9acbd8538d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755024045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3755024045
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1607514445
Short name T370
Test name
Test status
Simulation time 33754498 ps
CPU time 1.94 seconds
Started Aug 13 05:44:07 PM PDT 24
Finished Aug 13 05:44:09 PM PDT 24
Peak memory 210512 kb
Host smart-fdf1b037-d816-4243-b85b-44b0c5ca49cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607514445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1607514445
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3632932675
Short name T94
Test name
Test status
Simulation time 14980802 ps
CPU time 0.95 seconds
Started Aug 13 05:44:12 PM PDT 24
Finished Aug 13 05:44:13 PM PDT 24
Peak memory 206532 kb
Host smart-220ebf7d-32fc-4a43-bd51-b617dc799e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632932675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3632932675
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2660010854
Short name T395
Test name
Test status
Simulation time 237226204 ps
CPU time 4.37 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:18 PM PDT 24
Peak memory 216040 kb
Host smart-dcdbaa45-6fbf-40a2-91db-bc2b944ae8a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660010854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2660010854
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2320006910
Short name T898
Test name
Test status
Simulation time 98498042 ps
CPU time 4.34 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:18 PM PDT 24
Peak memory 210316 kb
Host smart-049a83e1-c061-4ec4-81b2-7f8359b9debd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320006910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2320006910
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.581493238
Short name T842
Test name
Test status
Simulation time 40345988 ps
CPU time 1.69 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:14 PM PDT 24
Peak memory 208796 kb
Host smart-c979f89d-cba0-4af1-ae70-891c9fd27d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581493238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.581493238
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2043496160
Short name T366
Test name
Test status
Simulation time 191831879 ps
CPU time 3.32 seconds
Started Aug 13 05:44:16 PM PDT 24
Finished Aug 13 05:44:20 PM PDT 24
Peak memory 214768 kb
Host smart-c4e048cc-c477-40d6-80ca-da2434ced3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043496160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2043496160
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3674967488
Short name T43
Test name
Test status
Simulation time 119797771 ps
CPU time 4.62 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:19 PM PDT 24
Peak memory 216356 kb
Host smart-0424f1bb-763f-4be4-860c-cd30616f29c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674967488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3674967488
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1879373280
Short name T791
Test name
Test status
Simulation time 366741997 ps
CPU time 7.44 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:21 PM PDT 24
Peak memory 214704 kb
Host smart-f7a80ddb-bb7d-4d2e-a3ee-f982e34ba806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879373280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1879373280
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.720759032
Short name T804
Test name
Test status
Simulation time 129697804 ps
CPU time 2.17 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:15 PM PDT 24
Peak memory 207476 kb
Host smart-f4e8a55b-0765-4595-a29e-6aa3b113c11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720759032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.720759032
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2998134531
Short name T521
Test name
Test status
Simulation time 1730684129 ps
CPU time 32.11 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:46 PM PDT 24
Peak memory 209368 kb
Host smart-f45908ec-fb35-4d7d-a802-2f379ff50e21
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998134531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2998134531
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3900035126
Short name T250
Test name
Test status
Simulation time 1419093031 ps
CPU time 4.44 seconds
Started Aug 13 05:44:11 PM PDT 24
Finished Aug 13 05:44:16 PM PDT 24
Peak memory 209208 kb
Host smart-67457295-be75-4b3f-a18d-616daec4f0ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900035126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3900035126
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1545658636
Short name T564
Test name
Test status
Simulation time 252361137 ps
CPU time 5.03 seconds
Started Aug 13 05:44:17 PM PDT 24
Finished Aug 13 05:44:22 PM PDT 24
Peak memory 208508 kb
Host smart-37eefbba-2771-4ada-b260-77358fcdf3b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545658636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1545658636
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2300599468
Short name T441
Test name
Test status
Simulation time 197176080 ps
CPU time 4.28 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 210152 kb
Host smart-35af1cdd-b4b4-40e3-993d-057575d8051e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300599468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2300599468
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.696811305
Short name T625
Test name
Test status
Simulation time 1117773952 ps
CPU time 10.63 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:25 PM PDT 24
Peak memory 208492 kb
Host smart-f4089423-5602-4078-bafc-e4850329bd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696811305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.696811305
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2814073069
Short name T210
Test name
Test status
Simulation time 5165463026 ps
CPU time 48.1 seconds
Started Aug 13 05:44:11 PM PDT 24
Finished Aug 13 05:44:59 PM PDT 24
Peak memory 222908 kb
Host smart-8a80ecd0-9b16-4138-ae3e-f089c1fec541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814073069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2814073069
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3208250017
Short name T616
Test name
Test status
Simulation time 66629297 ps
CPU time 3.14 seconds
Started Aug 13 05:44:11 PM PDT 24
Finished Aug 13 05:44:15 PM PDT 24
Peak memory 209924 kb
Host smart-9d0ffbc9-ec51-4136-bb14-e7ae99722203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208250017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3208250017
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3300947969
Short name T186
Test name
Test status
Simulation time 84135781 ps
CPU time 3.12 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:16 PM PDT 24
Peak memory 210440 kb
Host smart-f3eec958-b4e0-43fc-adab-e51cf1b3b1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300947969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3300947969
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1732164416
Short name T653
Test name
Test status
Simulation time 18486597 ps
CPU time 0.94 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:14 PM PDT 24
Peak memory 206556 kb
Host smart-cc401c7c-98f1-4e95-b8c7-7b0f3b37309c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732164416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1732164416
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3053381190
Short name T763
Test name
Test status
Simulation time 37385149 ps
CPU time 1.53 seconds
Started Aug 13 05:44:10 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 207408 kb
Host smart-60c8e78e-3cae-46dc-8385-78d2707c96fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053381190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3053381190
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3716157098
Short name T86
Test name
Test status
Simulation time 377066604 ps
CPU time 3.57 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:16 PM PDT 24
Peak memory 209240 kb
Host smart-e3f0619f-c2d8-44a4-bbf9-7e4e0ae245e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716157098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3716157098
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1549206837
Short name T677
Test name
Test status
Simulation time 139341475 ps
CPU time 2.41 seconds
Started Aug 13 05:44:22 PM PDT 24
Finished Aug 13 05:44:24 PM PDT 24
Peak memory 214724 kb
Host smart-ca78e2f9-986f-4e2d-ada9-bb0d80849d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549206837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1549206837
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2812930039
Short name T51
Test name
Test status
Simulation time 90982198 ps
CPU time 1.71 seconds
Started Aug 13 05:44:16 PM PDT 24
Finished Aug 13 05:44:18 PM PDT 24
Peak memory 214788 kb
Host smart-98fd2c68-79d8-4ffe-a1ca-9b3120549ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812930039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2812930039
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3364694666
Short name T586
Test name
Test status
Simulation time 1021970785 ps
CPU time 11.18 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:24 PM PDT 24
Peak memory 209784 kb
Host smart-3373a329-cde4-4ea0-8c84-8746b67c526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364694666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3364694666
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.4030060536
Short name T780
Test name
Test status
Simulation time 97407922 ps
CPU time 2.76 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:16 PM PDT 24
Peak memory 207344 kb
Host smart-c170e4b4-b21e-4202-9d6a-42c5c9c3cdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030060536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.4030060536
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3214711177
Short name T608
Test name
Test status
Simulation time 1288510048 ps
CPU time 6.42 seconds
Started Aug 13 05:44:10 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 208428 kb
Host smart-da196429-0d87-4c86-90e2-10908a4c0273
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214711177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3214711177
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3032282538
Short name T590
Test name
Test status
Simulation time 1010447933 ps
CPU time 33.67 seconds
Started Aug 13 05:44:11 PM PDT 24
Finished Aug 13 05:44:45 PM PDT 24
Peak memory 209024 kb
Host smart-ea65ea6a-e670-42bc-b9bb-7518cdcda313
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032282538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3032282538
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.179972204
Short name T451
Test name
Test status
Simulation time 46384993 ps
CPU time 2.68 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 208980 kb
Host smart-0bfb0592-5d26-4cc9-a441-78dbaca7b124
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179972204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.179972204
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2514011875
Short name T247
Test name
Test status
Simulation time 88510627 ps
CPU time 3.59 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 209936 kb
Host smart-524c9ea7-7242-445c-8e71-c3526d371ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514011875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2514011875
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2258700113
Short name T610
Test name
Test status
Simulation time 74369559 ps
CPU time 3.21 seconds
Started Aug 13 05:44:08 PM PDT 24
Finished Aug 13 05:44:12 PM PDT 24
Peak memory 208876 kb
Host smart-5e8dd1d8-8479-4812-b309-3c7f0ad01a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258700113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2258700113
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2918148868
Short name T333
Test name
Test status
Simulation time 648710379 ps
CPU time 13.79 seconds
Started Aug 13 05:44:12 PM PDT 24
Finished Aug 13 05:44:26 PM PDT 24
Peak memory 215716 kb
Host smart-862cb727-c610-4b30-a90d-4005222b34b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918148868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2918148868
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3580717654
Short name T80
Test name
Test status
Simulation time 178729874 ps
CPU time 4.67 seconds
Started Aug 13 05:44:15 PM PDT 24
Finished Aug 13 05:44:20 PM PDT 24
Peak memory 214768 kb
Host smart-45ea61e0-c791-4bfa-8c16-f00d94a73256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580717654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3580717654
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2701883522
Short name T162
Test name
Test status
Simulation time 873992922 ps
CPU time 8.51 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:22 PM PDT 24
Peak memory 211556 kb
Host smart-afdb706b-058f-409d-8ff5-432078b7701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701883522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2701883522
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2671043713
Short name T777
Test name
Test status
Simulation time 12089145 ps
CPU time 0.78 seconds
Started Aug 13 05:44:21 PM PDT 24
Finished Aug 13 05:44:22 PM PDT 24
Peak memory 206440 kb
Host smart-9fecaca5-f97d-411d-92e4-efb8102f43d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671043713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2671043713
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2926282960
Short name T394
Test name
Test status
Simulation time 91526770 ps
CPU time 5.02 seconds
Started Aug 13 05:44:12 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 215948 kb
Host smart-b67399e7-b581-41f5-93fd-bfa257943240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926282960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2926282960
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1305033679
Short name T688
Test name
Test status
Simulation time 91011177 ps
CPU time 2.42 seconds
Started Aug 13 05:44:11 PM PDT 24
Finished Aug 13 05:44:13 PM PDT 24
Peak memory 207448 kb
Host smart-2feb68c6-50cf-4757-802a-608ad6076abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305033679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1305033679
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4163872161
Short name T816
Test name
Test status
Simulation time 219674571 ps
CPU time 3.79 seconds
Started Aug 13 05:44:18 PM PDT 24
Finished Aug 13 05:44:22 PM PDT 24
Peak memory 214720 kb
Host smart-e2b1b39e-3cb3-41c2-b0f1-952c1d6db4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163872161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4163872161
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1223007179
Short name T718
Test name
Test status
Simulation time 577477349 ps
CPU time 4.3 seconds
Started Aug 13 05:44:25 PM PDT 24
Finished Aug 13 05:44:29 PM PDT 24
Peak memory 222844 kb
Host smart-07961979-c70c-44fc-8ebc-e576f5ee8ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223007179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1223007179
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1538077679
Short name T866
Test name
Test status
Simulation time 259128978 ps
CPU time 3.91 seconds
Started Aug 13 05:44:16 PM PDT 24
Finished Aug 13 05:44:20 PM PDT 24
Peak memory 208608 kb
Host smart-8512bad5-5339-499d-86f8-effb7e016d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538077679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1538077679
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.97971689
Short name T865
Test name
Test status
Simulation time 694494315 ps
CPU time 3.85 seconds
Started Aug 13 05:44:09 PM PDT 24
Finished Aug 13 05:44:14 PM PDT 24
Peak memory 207484 kb
Host smart-ca03c839-92b8-41fc-8a5f-04120a58a140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97971689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.97971689
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.845820391
Short name T666
Test name
Test status
Simulation time 309369787 ps
CPU time 6.32 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:20 PM PDT 24
Peak memory 208432 kb
Host smart-7ec14aef-54a3-43ac-b8e1-c1bcb03e876a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845820391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.845820391
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.849423819
Short name T661
Test name
Test status
Simulation time 625295369 ps
CPU time 3.8 seconds
Started Aug 13 05:44:13 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 209092 kb
Host smart-74183850-7a0b-432d-95b4-ec16d6cee28c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849423819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.849423819
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2729907712
Short name T363
Test name
Test status
Simulation time 20978654 ps
CPU time 1.71 seconds
Started Aug 13 05:44:21 PM PDT 24
Finished Aug 13 05:44:23 PM PDT 24
Peak memory 207508 kb
Host smart-5658f7be-d95c-4acf-8ba5-461ea8e60bc4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729907712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2729907712
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1581495228
Short name T540
Test name
Test status
Simulation time 163046581 ps
CPU time 2.84 seconds
Started Aug 13 05:44:20 PM PDT 24
Finished Aug 13 05:44:23 PM PDT 24
Peak memory 218672 kb
Host smart-9473c5e7-c5ef-4140-a748-ce8ea6f5dd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581495228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1581495228
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1777884517
Short name T856
Test name
Test status
Simulation time 166598151 ps
CPU time 3.63 seconds
Started Aug 13 05:44:14 PM PDT 24
Finished Aug 13 05:44:17 PM PDT 24
Peak memory 207176 kb
Host smart-326fb8ce-f855-41b0-9006-ba0ba2a285e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777884517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1777884517
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.800492205
Short name T203
Test name
Test status
Simulation time 14205718642 ps
CPU time 186.54 seconds
Started Aug 13 05:44:23 PM PDT 24
Finished Aug 13 05:47:30 PM PDT 24
Peak memory 221812 kb
Host smart-7bc12b10-07c4-4a49-ac11-4accc93e3f37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800492205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.800492205
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.663372362
Short name T591
Test name
Test status
Simulation time 182742992 ps
CPU time 3.14 seconds
Started Aug 13 05:44:22 PM PDT 24
Finished Aug 13 05:44:25 PM PDT 24
Peak memory 214872 kb
Host smart-c8bf512b-c3d2-4fb5-a80e-9c9353bb04b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663372362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.663372362
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2924098005
Short name T478
Test name
Test status
Simulation time 249131580 ps
CPU time 1.53 seconds
Started Aug 13 05:44:18 PM PDT 24
Finished Aug 13 05:44:19 PM PDT 24
Peak memory 210240 kb
Host smart-23d03b33-7bec-4879-b3d6-18449356c3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924098005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2924098005
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.646937037
Short name T481
Test name
Test status
Simulation time 109516671 ps
CPU time 1 seconds
Started Aug 13 05:42:24 PM PDT 24
Finished Aug 13 05:42:25 PM PDT 24
Peak memory 206540 kb
Host smart-c33d275a-922b-478e-9a26-ab63c15c9cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646937037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.646937037
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3433010836
Short name T39
Test name
Test status
Simulation time 166674029 ps
CPU time 4.16 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 210312 kb
Host smart-c8503070-663a-4eb3-a920-fcf3a24d1c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433010836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3433010836
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.691210776
Short name T879
Test name
Test status
Simulation time 74511760 ps
CPU time 2.02 seconds
Started Aug 13 05:42:15 PM PDT 24
Finished Aug 13 05:42:17 PM PDT 24
Peak memory 207692 kb
Host smart-6bd02663-e8f2-4e35-bb35-1eb464eac1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691210776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.691210776
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.466499897
Short name T885
Test name
Test status
Simulation time 341848389 ps
CPU time 5.18 seconds
Started Aug 13 05:42:22 PM PDT 24
Finished Aug 13 05:42:27 PM PDT 24
Peak memory 214700 kb
Host smart-fcee7c5e-f90e-46d6-9c83-319095a9f78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466499897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.466499897
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.916303310
Short name T843
Test name
Test status
Simulation time 40733850 ps
CPU time 2.78 seconds
Started Aug 13 05:42:25 PM PDT 24
Finished Aug 13 05:42:28 PM PDT 24
Peak memory 220600 kb
Host smart-91d45aab-3779-4159-80c7-ed83f1cbbcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916303310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.916303310
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3345340078
Short name T779
Test name
Test status
Simulation time 403243380 ps
CPU time 3.79 seconds
Started Aug 13 05:42:18 PM PDT 24
Finished Aug 13 05:42:22 PM PDT 24
Peak memory 210636 kb
Host smart-5c69d5a2-b873-4d2d-96ab-ff5389bb1285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345340078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3345340078
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1265261412
Short name T96
Test name
Test status
Simulation time 1040035559 ps
CPU time 6.69 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:30 PM PDT 24
Peak memory 229676 kb
Host smart-6e47e221-ac2f-4808-b136-b3ce43df7f7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265261412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1265261412
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1616449996
Short name T423
Test name
Test status
Simulation time 123603259 ps
CPU time 4.38 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:28 PM PDT 24
Peak memory 208584 kb
Host smart-a8480adb-ec6b-4322-b50a-5f45cc0a4abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616449996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1616449996
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3501226567
Short name T611
Test name
Test status
Simulation time 86287945 ps
CPU time 2.52 seconds
Started Aug 13 05:42:18 PM PDT 24
Finished Aug 13 05:42:20 PM PDT 24
Peak memory 207460 kb
Host smart-bd6e23ab-0e57-4bf8-947e-22b76fdbd658
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501226567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3501226567
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1686565515
Short name T782
Test name
Test status
Simulation time 716862579 ps
CPU time 4.57 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:22 PM PDT 24
Peak memory 209024 kb
Host smart-b5759eaf-fa4b-42d4-bac2-3a31422b7e8a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686565515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1686565515
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3873605835
Short name T892
Test name
Test status
Simulation time 417871872 ps
CPU time 2.78 seconds
Started Aug 13 05:42:17 PM PDT 24
Finished Aug 13 05:42:19 PM PDT 24
Peak memory 207232 kb
Host smart-ca815152-f15e-4265-9035-3011dcf63c66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873605835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3873605835
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3262568752
Short name T246
Test name
Test status
Simulation time 55445481 ps
CPU time 2.44 seconds
Started Aug 13 05:42:26 PM PDT 24
Finished Aug 13 05:42:28 PM PDT 24
Peak memory 209888 kb
Host smart-f6713d4c-a5b5-406a-9600-24acdecda3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262568752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3262568752
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.881590623
Short name T524
Test name
Test status
Simulation time 939648660 ps
CPU time 3.95 seconds
Started Aug 13 05:42:19 PM PDT 24
Finished Aug 13 05:42:23 PM PDT 24
Peak memory 208832 kb
Host smart-486c6760-7a6b-4cba-946e-30d917d79dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881590623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.881590623
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1863045131
Short name T555
Test name
Test status
Simulation time 1476819735 ps
CPU time 53.12 seconds
Started Aug 13 05:42:24 PM PDT 24
Finished Aug 13 05:43:17 PM PDT 24
Peak memory 214748 kb
Host smart-55095ff3-a7d0-41e3-936e-b6857b705b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863045131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1863045131
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.198839672
Short name T636
Test name
Test status
Simulation time 2896535909 ps
CPU time 20 seconds
Started Aug 13 05:42:25 PM PDT 24
Finished Aug 13 05:42:45 PM PDT 24
Peak memory 221376 kb
Host smart-9e963f1d-b7db-4db7-898d-58eb536b0c34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198839672 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.198839672
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.4119341191
Short name T289
Test name
Test status
Simulation time 602592882 ps
CPU time 15.03 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:39 PM PDT 24
Peak memory 209628 kb
Host smart-b8000413-352f-4e71-af6d-338b9dc5db50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119341191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.4119341191
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1952719439
Short name T433
Test name
Test status
Simulation time 292078871 ps
CPU time 2.65 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:36 PM PDT 24
Peak memory 210784 kb
Host smart-3eb34b88-7f1f-443e-9a38-b5182ba18984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952719439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1952719439
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1374954795
Short name T436
Test name
Test status
Simulation time 13845317 ps
CPU time 0.94 seconds
Started Aug 13 05:44:23 PM PDT 24
Finished Aug 13 05:44:24 PM PDT 24
Peak memory 206448 kb
Host smart-8b595954-b028-4a99-a466-17e7ed791032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374954795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1374954795
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3254263567
Short name T198
Test name
Test status
Simulation time 423591424 ps
CPU time 4.85 seconds
Started Aug 13 05:44:20 PM PDT 24
Finished Aug 13 05:44:25 PM PDT 24
Peak memory 223196 kb
Host smart-10e3a846-753f-42de-810b-ee87519c3faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254263567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3254263567
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.698665631
Short name T179
Test name
Test status
Simulation time 409440910 ps
CPU time 8.84 seconds
Started Aug 13 05:44:19 PM PDT 24
Finished Aug 13 05:44:28 PM PDT 24
Peak memory 209452 kb
Host smart-c179eb04-c0af-4ab2-b493-dd89791bfebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698665631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.698665631
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3552550379
Short name T568
Test name
Test status
Simulation time 219456036 ps
CPU time 3.44 seconds
Started Aug 13 05:44:23 PM PDT 24
Finished Aug 13 05:44:26 PM PDT 24
Peak memory 214708 kb
Host smart-ea86a56b-e357-4c30-a535-bcc63fd6f41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552550379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3552550379
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.246797331
Short name T601
Test name
Test status
Simulation time 3168664500 ps
CPU time 21.27 seconds
Started Aug 13 05:44:20 PM PDT 24
Finished Aug 13 05:44:42 PM PDT 24
Peak memory 214864 kb
Host smart-f091d345-6e09-40d4-9c19-02dda5ac8183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246797331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.246797331
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3942201570
Short name T811
Test name
Test status
Simulation time 614842189 ps
CPU time 2.62 seconds
Started Aug 13 05:44:23 PM PDT 24
Finished Aug 13 05:44:26 PM PDT 24
Peak memory 207300 kb
Host smart-d97e68a1-7f69-47c1-9317-f85c8d6ede7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942201570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3942201570
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2588936655
Short name T723
Test name
Test status
Simulation time 30758844 ps
CPU time 2.31 seconds
Started Aug 13 05:44:23 PM PDT 24
Finished Aug 13 05:44:25 PM PDT 24
Peak memory 207404 kb
Host smart-f863113e-2406-44e2-81a4-2ef6915a9538
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588936655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2588936655
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1765524164
Short name T569
Test name
Test status
Simulation time 407387621 ps
CPU time 6.51 seconds
Started Aug 13 05:44:21 PM PDT 24
Finished Aug 13 05:44:27 PM PDT 24
Peak memory 207512 kb
Host smart-85326496-55fd-452f-8dc1-2551f34d2a29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765524164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1765524164
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1275365652
Short name T628
Test name
Test status
Simulation time 361179170 ps
CPU time 4.13 seconds
Started Aug 13 05:44:21 PM PDT 24
Finished Aug 13 05:44:26 PM PDT 24
Peak memory 209376 kb
Host smart-4faa9904-fef2-46bf-adee-a3551e06f659
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275365652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1275365652
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4012958968
Short name T223
Test name
Test status
Simulation time 156292886 ps
CPU time 4.33 seconds
Started Aug 13 05:44:19 PM PDT 24
Finished Aug 13 05:44:24 PM PDT 24
Peak memory 216428 kb
Host smart-a9d71a73-33a4-4dd6-af77-1de30af6af42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012958968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4012958968
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.171841424
Short name T832
Test name
Test status
Simulation time 688103291 ps
CPU time 3.94 seconds
Started Aug 13 05:44:21 PM PDT 24
Finished Aug 13 05:44:25 PM PDT 24
Peak memory 209016 kb
Host smart-08404d27-3e3c-40d6-bfe8-7f02419dad3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171841424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.171841424
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3225493843
Short name T212
Test name
Test status
Simulation time 2156645175 ps
CPU time 41.38 seconds
Started Aug 13 05:44:22 PM PDT 24
Finished Aug 13 05:45:03 PM PDT 24
Peak memory 221328 kb
Host smart-c5bce057-70ba-4333-89ef-86a3dc278ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225493843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3225493843
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3304257732
Short name T707
Test name
Test status
Simulation time 1091115377 ps
CPU time 9.54 seconds
Started Aug 13 05:44:22 PM PDT 24
Finished Aug 13 05:44:32 PM PDT 24
Peak memory 210520 kb
Host smart-ff5974ad-85c3-490b-b3aa-5017b7a4cde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304257732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3304257732
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4064407494
Short name T376
Test name
Test status
Simulation time 332778072 ps
CPU time 3.75 seconds
Started Aug 13 05:44:24 PM PDT 24
Finished Aug 13 05:44:28 PM PDT 24
Peak memory 210980 kb
Host smart-9618019c-692b-4a52-9072-a012a33727eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064407494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4064407494
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.210371395
Short name T869
Test name
Test status
Simulation time 44545517 ps
CPU time 0.87 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:35 PM PDT 24
Peak memory 206220 kb
Host smart-3d1af814-401f-496d-ae92-75c906e1a0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210371395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.210371395
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3396316364
Short name T749
Test name
Test status
Simulation time 125249428 ps
CPU time 2.86 seconds
Started Aug 13 05:44:22 PM PDT 24
Finished Aug 13 05:44:26 PM PDT 24
Peak memory 214652 kb
Host smart-aed19617-494e-49d8-88a3-fbdaeaa80020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396316364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3396316364
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2324657130
Short name T29
Test name
Test status
Simulation time 230218615 ps
CPU time 4.23 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:39 PM PDT 24
Peak memory 221084 kb
Host smart-3b9f2f46-5d4e-4413-8747-73f4256c6bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324657130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2324657130
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4025355494
Short name T711
Test name
Test status
Simulation time 123561856 ps
CPU time 1.74 seconds
Started Aug 13 05:44:23 PM PDT 24
Finished Aug 13 05:44:25 PM PDT 24
Peak memory 207284 kb
Host smart-0f586450-1ae0-4d50-9010-06887c188ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025355494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4025355494
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.4149850281
Short name T88
Test name
Test status
Simulation time 134574243 ps
CPU time 3.94 seconds
Started Aug 13 05:44:19 PM PDT 24
Finished Aug 13 05:44:23 PM PDT 24
Peak memory 222928 kb
Host smart-656c88df-977e-4ce3-a4c1-cd11e6c60a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149850281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.4149850281
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.625197488
Short name T823
Test name
Test status
Simulation time 1203729876 ps
CPU time 4.43 seconds
Started Aug 13 05:44:33 PM PDT 24
Finished Aug 13 05:44:38 PM PDT 24
Peak memory 214720 kb
Host smart-d1fef266-f54c-4aa4-aa22-692b21318917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625197488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.625197488
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.357001638
Short name T204
Test name
Test status
Simulation time 43627441 ps
CPU time 2.65 seconds
Started Aug 13 05:44:20 PM PDT 24
Finished Aug 13 05:44:23 PM PDT 24
Peak memory 221308 kb
Host smart-e21e5a3e-b7aa-400d-aa64-ec9922a06e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357001638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.357001638
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1023709620
Short name T660
Test name
Test status
Simulation time 1082663418 ps
CPU time 5.8 seconds
Started Aug 13 05:44:25 PM PDT 24
Finished Aug 13 05:44:31 PM PDT 24
Peak memory 208404 kb
Host smart-a3672c0a-d2bb-4e57-93be-b85751ddbdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023709620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1023709620
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1216174731
Short name T287
Test name
Test status
Simulation time 286340439 ps
CPU time 3.25 seconds
Started Aug 13 05:44:26 PM PDT 24
Finished Aug 13 05:44:30 PM PDT 24
Peak memory 207592 kb
Host smart-fa483b3b-1d09-45ed-830a-53e2b308479b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216174731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1216174731
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2334709032
Short name T602
Test name
Test status
Simulation time 174742391 ps
CPU time 3.45 seconds
Started Aug 13 05:44:22 PM PDT 24
Finished Aug 13 05:44:26 PM PDT 24
Peak memory 209356 kb
Host smart-43f0662a-d2e2-4598-9da6-c19f079db22c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334709032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2334709032
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.549416692
Short name T618
Test name
Test status
Simulation time 551136588 ps
CPU time 7.11 seconds
Started Aug 13 05:44:23 PM PDT 24
Finished Aug 13 05:44:30 PM PDT 24
Peak memory 208552 kb
Host smart-8555f2f1-5d53-4163-8b8f-a4bd049c0e47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549416692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.549416692
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3235367154
Short name T845
Test name
Test status
Simulation time 94518428 ps
CPU time 3.75 seconds
Started Aug 13 05:44:21 PM PDT 24
Finished Aug 13 05:44:25 PM PDT 24
Peak memory 209080 kb
Host smart-c27911e8-bb35-470e-bc08-ec16117e0784
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235367154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3235367154
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3402648268
Short name T241
Test name
Test status
Simulation time 116927866 ps
CPU time 3.02 seconds
Started Aug 13 05:44:33 PM PDT 24
Finished Aug 13 05:44:36 PM PDT 24
Peak memory 209152 kb
Host smart-7fd3acca-cd1f-452b-8c37-baea30d564ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402648268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3402648268
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3269196805
Short name T384
Test name
Test status
Simulation time 32462876 ps
CPU time 2.25 seconds
Started Aug 13 05:44:17 PM PDT 24
Finished Aug 13 05:44:20 PM PDT 24
Peak memory 207100 kb
Host smart-61c12244-1f25-4006-b95a-431be03312d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269196805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3269196805
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3134504745
Short name T802
Test name
Test status
Simulation time 3204861297 ps
CPU time 42.84 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:45:17 PM PDT 24
Peak memory 215744 kb
Host smart-058c3ccf-ddfe-4300-8e94-37ee4ca265ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134504745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3134504745
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2978227348
Short name T793
Test name
Test status
Simulation time 447531761 ps
CPU time 16.4 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 220912 kb
Host smart-ceac6838-bec4-43ce-9148-33cc2b065eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978227348 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2978227348
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2955717844
Short name T680
Test name
Test status
Simulation time 74427968 ps
CPU time 3.6 seconds
Started Aug 13 05:44:21 PM PDT 24
Finished Aug 13 05:44:25 PM PDT 24
Peak memory 207576 kb
Host smart-2f88dabb-a05f-44c4-94e2-7d4e7bd19117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955717844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2955717844
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1219177772
Short name T159
Test name
Test status
Simulation time 105418470 ps
CPU time 2.7 seconds
Started Aug 13 05:44:33 PM PDT 24
Finished Aug 13 05:44:36 PM PDT 24
Peak memory 210516 kb
Host smart-3f7ce708-79ea-4b07-838d-bcbd47e3b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219177772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1219177772
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3991661662
Short name T421
Test name
Test status
Simulation time 14234098 ps
CPU time 0.88 seconds
Started Aug 13 05:44:32 PM PDT 24
Finished Aug 13 05:44:33 PM PDT 24
Peak memory 206368 kb
Host smart-4a971fc2-deeb-46c8-a7f9-038a31e06604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991661662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3991661662
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3581457599
Short name T242
Test name
Test status
Simulation time 112668364 ps
CPU time 4.2 seconds
Started Aug 13 05:44:35 PM PDT 24
Finished Aug 13 05:44:40 PM PDT 24
Peak memory 214784 kb
Host smart-f5bfc28d-f3d0-43b6-b048-177a4a37ed36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581457599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3581457599
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2719138871
Short name T38
Test name
Test status
Simulation time 216350284 ps
CPU time 2.56 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:37 PM PDT 24
Peak memory 208828 kb
Host smart-5991c8e1-3360-4efc-a9ca-33cb28059b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719138871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2719138871
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1261510917
Short name T336
Test name
Test status
Simulation time 904861396 ps
CPU time 5.26 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:40 PM PDT 24
Peak memory 208160 kb
Host smart-0501f22c-2095-4ac4-abb1-3cecad804160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261510917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1261510917
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3311768059
Short name T878
Test name
Test status
Simulation time 56352649 ps
CPU time 3.34 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:37 PM PDT 24
Peak memory 209400 kb
Host smart-97e88345-4100-4f3b-833a-f815773e9deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311768059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3311768059
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1062974154
Short name T267
Test name
Test status
Simulation time 815150555 ps
CPU time 3.76 seconds
Started Aug 13 05:44:36 PM PDT 24
Finished Aug 13 05:44:40 PM PDT 24
Peak memory 214788 kb
Host smart-89b63a23-5f82-45a1-a6a3-5178dcae254c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062974154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1062974154
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1837480545
Short name T47
Test name
Test status
Simulation time 210371246 ps
CPU time 6.4 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:40 PM PDT 24
Peak memory 219908 kb
Host smart-e6ec5cfb-843e-4477-8f59-7fbb31785895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837480545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1837480545
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.650414697
Short name T490
Test name
Test status
Simulation time 754232677 ps
CPU time 5.68 seconds
Started Aug 13 05:44:37 PM PDT 24
Finished Aug 13 05:44:43 PM PDT 24
Peak memory 219008 kb
Host smart-cb5b3063-df96-4f23-8b4c-e602ecab4322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650414697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.650414697
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2267653087
Short name T607
Test name
Test status
Simulation time 1714528185 ps
CPU time 24.84 seconds
Started Aug 13 05:44:33 PM PDT 24
Finished Aug 13 05:44:58 PM PDT 24
Peak memory 209428 kb
Host smart-61ab1511-9fc5-4711-8b25-f92b96a0ff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267653087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2267653087
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.987898246
Short name T855
Test name
Test status
Simulation time 215980001 ps
CPU time 7.3 seconds
Started Aug 13 05:44:35 PM PDT 24
Finished Aug 13 05:44:43 PM PDT 24
Peak memory 208588 kb
Host smart-4573b317-8b5f-4d83-8b38-8a1468382996
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987898246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.987898246
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1816121346
Short name T913
Test name
Test status
Simulation time 57347184 ps
CPU time 3.26 seconds
Started Aug 13 05:44:36 PM PDT 24
Finished Aug 13 05:44:40 PM PDT 24
Peak memory 207504 kb
Host smart-0108fa4d-42db-4bcd-a67e-af5b1209d765
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816121346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1816121346
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.4244603960
Short name T507
Test name
Test status
Simulation time 260216941 ps
CPU time 3.12 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:37 PM PDT 24
Peak memory 207420 kb
Host smart-91a15d2e-7758-4d0a-9a9c-d8738b3b20b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244603960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.4244603960
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.605700669
Short name T255
Test name
Test status
Simulation time 77838107 ps
CPU time 3.09 seconds
Started Aug 13 05:44:35 PM PDT 24
Finished Aug 13 05:44:38 PM PDT 24
Peak memory 208672 kb
Host smart-fdf15669-a137-43f7-9262-3a7e0ff8d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605700669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.605700669
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3490349637
Short name T694
Test name
Test status
Simulation time 220618995 ps
CPU time 4.36 seconds
Started Aug 13 05:44:33 PM PDT 24
Finished Aug 13 05:44:38 PM PDT 24
Peak memory 208348 kb
Host smart-286fcec3-4e6f-4764-b71a-6e053680d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490349637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3490349637
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1432398422
Short name T213
Test name
Test status
Simulation time 19420331728 ps
CPU time 633.24 seconds
Started Aug 13 05:44:35 PM PDT 24
Finished Aug 13 05:55:09 PM PDT 24
Peak memory 223020 kb
Host smart-9997aa3d-18cb-4a23-8702-515db66b1b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432398422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1432398422
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2206894468
Short name T656
Test name
Test status
Simulation time 503901225 ps
CPU time 4.19 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:39 PM PDT 24
Peak memory 210736 kb
Host smart-e7031473-ad3a-4938-8e7e-f80314976bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206894468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2206894468
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.739282013
Short name T388
Test name
Test status
Simulation time 75134580 ps
CPU time 1.5 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:36 PM PDT 24
Peak memory 210156 kb
Host smart-f89a1d7f-77ff-4d07-9ea4-0d4dfe8d5d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739282013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.739282013
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1522217950
Short name T101
Test name
Test status
Simulation time 34797686 ps
CPU time 0.8 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:47 PM PDT 24
Peak memory 206412 kb
Host smart-1d555ada-ee41-4666-b1f9-9ec6bd4b051f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522217950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1522217950
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.140068251
Short name T304
Test name
Test status
Simulation time 35635049 ps
CPU time 2.91 seconds
Started Aug 13 05:44:33 PM PDT 24
Finished Aug 13 05:44:36 PM PDT 24
Peak memory 214800 kb
Host smart-989bdda3-4d25-44bf-8482-ce4138267d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140068251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.140068251
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3376373979
Short name T18
Test name
Test status
Simulation time 246289324 ps
CPU time 3.91 seconds
Started Aug 13 05:44:35 PM PDT 24
Finished Aug 13 05:44:39 PM PDT 24
Peak memory 215092 kb
Host smart-11245df3-eba1-4b07-828e-9b7dae8cca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376373979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3376373979
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2735561458
Short name T74
Test name
Test status
Simulation time 224675473 ps
CPU time 2.67 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:37 PM PDT 24
Peak memory 209928 kb
Host smart-384ef9d6-b07e-48f6-8d72-a1d95e4807e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735561458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2735561458
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4294446799
Short name T271
Test name
Test status
Simulation time 231029530 ps
CPU time 3.86 seconds
Started Aug 13 05:44:36 PM PDT 24
Finished Aug 13 05:44:40 PM PDT 24
Peak memory 217440 kb
Host smart-ade5b2f8-95e4-444e-bee7-7672a6388f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294446799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4294446799
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3366620957
Short name T263
Test name
Test status
Simulation time 485503865 ps
CPU time 4.16 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:44:38 PM PDT 24
Peak memory 214724 kb
Host smart-b2d79a19-daa3-432e-9b07-15243eaef4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366620957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3366620957
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2636147142
Short name T522
Test name
Test status
Simulation time 337237423 ps
CPU time 5.74 seconds
Started Aug 13 05:44:35 PM PDT 24
Finished Aug 13 05:44:41 PM PDT 24
Peak memory 211404 kb
Host smart-792633b5-8bd3-4850-9bb4-81249c5c9ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636147142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2636147142
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.410580644
Short name T104
Test name
Test status
Simulation time 713199343 ps
CPU time 4.65 seconds
Started Aug 13 05:44:37 PM PDT 24
Finished Aug 13 05:44:42 PM PDT 24
Peak memory 208128 kb
Host smart-4a57d171-8b6d-4413-8ef6-f7696746c5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410580644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.410580644
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.306486374
Short name T294
Test name
Test status
Simulation time 148033091 ps
CPU time 4.88 seconds
Started Aug 13 05:44:33 PM PDT 24
Finished Aug 13 05:44:38 PM PDT 24
Peak memory 207248 kb
Host smart-312b7da1-4419-45c8-b91d-39b6eac8aa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306486374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.306486374
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3466404296
Short name T314
Test name
Test status
Simulation time 1366138254 ps
CPU time 6.26 seconds
Started Aug 13 05:44:38 PM PDT 24
Finished Aug 13 05:44:44 PM PDT 24
Peak memory 209280 kb
Host smart-2edc9219-3736-481d-b02f-d7f95cfc9337
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466404296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3466404296
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1653155267
Short name T662
Test name
Test status
Simulation time 77933205 ps
CPU time 2.34 seconds
Started Aug 13 05:44:32 PM PDT 24
Finished Aug 13 05:44:35 PM PDT 24
Peak memory 207496 kb
Host smart-4b46d880-b331-46a5-95df-3deaa6ef6d9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653155267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1653155267
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1069736356
Short name T462
Test name
Test status
Simulation time 6728721697 ps
CPU time 36.77 seconds
Started Aug 13 05:44:34 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 209016 kb
Host smart-8af51575-de4b-4f86-9739-dee5cbd82f1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069736356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1069736356
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3180284024
Short name T687
Test name
Test status
Simulation time 391303460 ps
CPU time 4.81 seconds
Started Aug 13 05:44:36 PM PDT 24
Finished Aug 13 05:44:41 PM PDT 24
Peak memory 208880 kb
Host smart-c6efb8b4-80f9-420a-b403-b68b89cb4022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180284024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3180284024
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.901313952
Short name T670
Test name
Test status
Simulation time 307834438 ps
CPU time 9.29 seconds
Started Aug 13 05:44:36 PM PDT 24
Finished Aug 13 05:44:46 PM PDT 24
Peak memory 208512 kb
Host smart-336da8d8-e7be-4b45-9cf0-d5063235e637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901313952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.901313952
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.987070555
Short name T123
Test name
Test status
Simulation time 515913199 ps
CPU time 4.01 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 207384 kb
Host smart-192c9be7-fe59-4963-9f29-91fb18864df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987070555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.987070555
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.178871296
Short name T398
Test name
Test status
Simulation time 184404105 ps
CPU time 5.31 seconds
Started Aug 13 05:44:35 PM PDT 24
Finished Aug 13 05:44:40 PM PDT 24
Peak memory 209192 kb
Host smart-01504b7e-0c72-46a0-a26e-d33a89d6b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178871296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.178871296
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1849983169
Short name T129
Test name
Test status
Simulation time 2462890248 ps
CPU time 12.48 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:58 PM PDT 24
Peak memory 211036 kb
Host smart-1703176e-cbb5-4786-9ac7-cbd5f68643eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849983169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1849983169
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.993213206
Short name T617
Test name
Test status
Simulation time 28819998 ps
CPU time 0.72 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:44:46 PM PDT 24
Peak memory 206324 kb
Host smart-783b287a-5441-4dd5-82a9-7b315da12a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993213206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.993213206
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.48863779
Short name T274
Test name
Test status
Simulation time 55192529 ps
CPU time 3.75 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:44:48 PM PDT 24
Peak memory 222784 kb
Host smart-24b94f97-9dc9-4624-bb5b-d1faacc5e61b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48863779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.48863779
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2781619406
Short name T868
Test name
Test status
Simulation time 533213748 ps
CPU time 17.78 seconds
Started Aug 13 05:44:43 PM PDT 24
Finished Aug 13 05:45:01 PM PDT 24
Peak memory 223356 kb
Host smart-4ac0d9a0-5ac5-43b2-987a-91ffe91b9568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781619406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2781619406
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4031858139
Short name T774
Test name
Test status
Simulation time 194757011 ps
CPU time 2.17 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 208620 kb
Host smart-a000321a-bca7-4781-af9c-d4a8029f4ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031858139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4031858139
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2602440970
Short name T226
Test name
Test status
Simulation time 141269344 ps
CPU time 2.5 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:44:47 PM PDT 24
Peak memory 214664 kb
Host smart-d63a28d8-d8fb-43ee-9601-8286b330f195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602440970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2602440970
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3078940040
Short name T770
Test name
Test status
Simulation time 272011200 ps
CPU time 3.18 seconds
Started Aug 13 05:44:51 PM PDT 24
Finished Aug 13 05:44:55 PM PDT 24
Peak memory 217456 kb
Host smart-48ec8e27-3fba-455a-9327-9877980d3278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078940040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3078940040
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1729693167
Short name T65
Test name
Test status
Simulation time 244729775 ps
CPU time 8.98 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:44:55 PM PDT 24
Peak memory 221232 kb
Host smart-e34cee8a-3cec-4e1d-b799-4584784424dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729693167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1729693167
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3295355779
Short name T571
Test name
Test status
Simulation time 268694025 ps
CPU time 8.78 seconds
Started Aug 13 05:44:42 PM PDT 24
Finished Aug 13 05:44:51 PM PDT 24
Peak memory 208880 kb
Host smart-a86f2324-ed1f-4ac3-aa8e-0972f9a59a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295355779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3295355779
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1147201172
Short name T681
Test name
Test status
Simulation time 1838075499 ps
CPU time 19.35 seconds
Started Aug 13 05:44:41 PM PDT 24
Finished Aug 13 05:45:00 PM PDT 24
Peak memory 207252 kb
Host smart-6b3e6903-81d1-4a9e-834b-9878a71a0540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147201172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1147201172
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3866951387
Short name T518
Test name
Test status
Simulation time 336204884 ps
CPU time 2.75 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:44:46 PM PDT 24
Peak memory 207380 kb
Host smart-81578b70-ca9d-460d-8386-9dad43a8096d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866951387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3866951387
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3302649747
Short name T445
Test name
Test status
Simulation time 417297561 ps
CPU time 11.07 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:44:56 PM PDT 24
Peak memory 209248 kb
Host smart-33365560-5290-4dd0-9fb4-823899a4f9d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302649747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3302649747
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2595606067
Short name T652
Test name
Test status
Simulation time 714976395 ps
CPU time 8.88 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:56 PM PDT 24
Peak memory 209156 kb
Host smart-d63584c1-860b-4db0-b4a4-5c49b9d26b53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595606067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2595606067
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1712909619
Short name T904
Test name
Test status
Simulation time 89400492 ps
CPU time 3.56 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:49 PM PDT 24
Peak memory 218848 kb
Host smart-8b2df036-b3e2-45f4-afa9-c8863a8da05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712909619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1712909619
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1949003529
Short name T570
Test name
Test status
Simulation time 176495503 ps
CPU time 2.28 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:44:48 PM PDT 24
Peak memory 208936 kb
Host smart-8cfe7097-6381-4bba-860a-38d47ccd7854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949003529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1949003529
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.251534794
Short name T78
Test name
Test status
Simulation time 514616184 ps
CPU time 25.44 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:45:09 PM PDT 24
Peak memory 223056 kb
Host smart-bdb2df41-74cd-4b16-a1c3-053c8e0bb637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251534794 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.251534794
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3327423180
Short name T345
Test name
Test status
Simulation time 170408410 ps
CPU time 4.59 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:57 PM PDT 24
Peak memory 210424 kb
Host smart-0574e736-26e0-4a2b-ac27-07c46bca67d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327423180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3327423180
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2314964396
Short name T572
Test name
Test status
Simulation time 211964482 ps
CPU time 1.83 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:48 PM PDT 24
Peak memory 210740 kb
Host smart-1221efeb-0cb0-402d-946a-1113faedf1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314964396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2314964396
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3626938701
Short name T654
Test name
Test status
Simulation time 15254681 ps
CPU time 0.9 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:48 PM PDT 24
Peak memory 206592 kb
Host smart-f26c5c71-8ae0-409f-bdf3-c5c3df187763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626938701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3626938701
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3652599722
Short name T391
Test name
Test status
Simulation time 103274641 ps
CPU time 5.57 seconds
Started Aug 13 05:44:49 PM PDT 24
Finished Aug 13 05:44:55 PM PDT 24
Peak memory 214788 kb
Host smart-8a7d662a-0bf9-4b46-989a-f70786c42b28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652599722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3652599722
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2782599464
Short name T27
Test name
Test status
Simulation time 81485219 ps
CPU time 3.25 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 215108 kb
Host smart-a90a8f46-9208-4e98-a08f-b124bd5cdc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782599464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2782599464
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3200980235
Short name T62
Test name
Test status
Simulation time 892327227 ps
CPU time 6.06 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 209924 kb
Host smart-36db2576-0259-4166-b320-f4ea64b5414f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200980235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3200980235
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.889606991
Short name T331
Test name
Test status
Simulation time 5019845780 ps
CPU time 10.11 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:44:54 PM PDT 24
Peak memory 214892 kb
Host smart-f77393f7-9ccd-4001-b95a-0e1fad2b0e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889606991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.889606991
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2224395120
Short name T230
Test name
Test status
Simulation time 488101803 ps
CPU time 2.6 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:44:48 PM PDT 24
Peak memory 214832 kb
Host smart-86fb316c-836c-49d4-89f4-30c9b9cfb15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224395120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2224395120
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1876355386
Short name T756
Test name
Test status
Simulation time 80080809 ps
CPU time 3.14 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:49 PM PDT 24
Peak memory 210844 kb
Host smart-b163eb83-4e9d-45f0-a2c5-2d423c1ecd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876355386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1876355386
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1870462079
Short name T432
Test name
Test status
Simulation time 209477948 ps
CPU time 6.09 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:54 PM PDT 24
Peak memory 214656 kb
Host smart-c0fd671b-347b-4751-b34a-a3b175825b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870462079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1870462079
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1349735876
Short name T587
Test name
Test status
Simulation time 185493782 ps
CPU time 2.28 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:44:47 PM PDT 24
Peak memory 206548 kb
Host smart-57679028-e57c-4638-85db-08506ca01dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349735876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1349735876
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3637595875
Short name T899
Test name
Test status
Simulation time 180691904 ps
CPU time 2.65 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 207420 kb
Host smart-ab0c454b-3e04-426a-b426-9b0f7888a253
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637595875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3637595875
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.411610427
Short name T603
Test name
Test status
Simulation time 98268565 ps
CPU time 3.39 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:44:49 PM PDT 24
Peak memory 207352 kb
Host smart-d6e77ddd-fc0c-4818-ba60-8fdc969cccb4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411610427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.411610427
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.990374001
Short name T563
Test name
Test status
Simulation time 192454833 ps
CPU time 4.16 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:51 PM PDT 24
Peak memory 207424 kb
Host smart-80bc10fe-a911-4f52-a09b-99452ff41c0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990374001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.990374001
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.791332662
Short name T739
Test name
Test status
Simulation time 164435310 ps
CPU time 3.09 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:51 PM PDT 24
Peak memory 214728 kb
Host smart-cb0ea013-cb85-454d-9038-09cb9e254ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791332662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.791332662
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3286621349
Short name T82
Test name
Test status
Simulation time 658368566 ps
CPU time 3.79 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:44:48 PM PDT 24
Peak memory 209140 kb
Host smart-2b674c60-7ca9-4ae8-8a92-75fa72ade637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286621349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3286621349
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.176775162
Short name T638
Test name
Test status
Simulation time 79151708 ps
CPU time 0.78 seconds
Started Aug 13 05:44:49 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 206300 kb
Host smart-033340b5-5b10-4568-bc65-bb7ac2725a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176775162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.176775162
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1774608413
Short name T172
Test name
Test status
Simulation time 370436195 ps
CPU time 7.67 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:44:53 PM PDT 24
Peak memory 222972 kb
Host smart-8edf7b87-b521-42e4-8cbd-1072d4bce840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774608413 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1774608413
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3244488171
Short name T542
Test name
Test status
Simulation time 345954130 ps
CPU time 10.53 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:58 PM PDT 24
Peak memory 208544 kb
Host smart-662f3676-63cc-46f4-9296-f22efdcb55d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244488171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3244488171
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3187907231
Short name T152
Test name
Test status
Simulation time 81277896 ps
CPU time 1.51 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:48 PM PDT 24
Peak memory 210476 kb
Host smart-38641bf3-aa26-4258-9958-7fe7552baa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187907231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3187907231
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2221151777
Short name T480
Test name
Test status
Simulation time 28988774 ps
CPU time 0.7 seconds
Started Aug 13 05:44:42 PM PDT 24
Finished Aug 13 05:44:43 PM PDT 24
Peak memory 206520 kb
Host smart-3adda903-dc42-43c1-9522-3ca94a3329c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221151777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2221151777
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1716460205
Short name T362
Test name
Test status
Simulation time 90607772 ps
CPU time 5.69 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:54 PM PDT 24
Peak memory 214952 kb
Host smart-6dfa99f2-159e-4f09-bf07-dbbfbc09b7d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1716460205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1716460205
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1873016185
Short name T63
Test name
Test status
Simulation time 198025041 ps
CPU time 3.16 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:49 PM PDT 24
Peak memory 218020 kb
Host smart-6970f134-1ea3-4428-a38e-78a0fdd36b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873016185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1873016185
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3987338138
Short name T76
Test name
Test status
Simulation time 132835058 ps
CPU time 3.58 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:52 PM PDT 24
Peak memory 214712 kb
Host smart-1657be70-f113-4fed-8667-241376b65f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987338138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3987338138
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3992155110
Short name T91
Test name
Test status
Simulation time 111932079 ps
CPU time 3.39 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:51 PM PDT 24
Peak memory 209832 kb
Host smart-65df4f6a-0462-480d-9318-f483f1e4c433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992155110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3992155110
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1163869950
Short name T55
Test name
Test status
Simulation time 543569120 ps
CPU time 6.55 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:53 PM PDT 24
Peak memory 222884 kb
Host smart-e6bbfeab-1ce4-44ca-9b31-84fb64725c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163869950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1163869950
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3052587162
Short name T703
Test name
Test status
Simulation time 153221779 ps
CPU time 1.85 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:44:46 PM PDT 24
Peak memory 207252 kb
Host smart-e9eb3b91-6c37-40d9-ada2-a745633c2939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052587162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3052587162
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.885343587
Short name T731
Test name
Test status
Simulation time 15576629191 ps
CPU time 56.59 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:45:45 PM PDT 24
Peak memory 209172 kb
Host smart-3e2f6887-a785-4a53-94f5-b75a7752e58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885343587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.885343587
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1048942656
Short name T387
Test name
Test status
Simulation time 97602284 ps
CPU time 3.9 seconds
Started Aug 13 05:44:49 PM PDT 24
Finished Aug 13 05:44:53 PM PDT 24
Peak memory 208936 kb
Host smart-30a0af75-efee-4889-9b2c-21381d5f8f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048942656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1048942656
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.997604734
Short name T721
Test name
Test status
Simulation time 2851499987 ps
CPU time 24.65 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:45:17 PM PDT 24
Peak memory 209428 kb
Host smart-9fbbe0aa-0d56-4b39-b15a-a86972b60e2e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997604734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.997604734
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.885812779
Short name T547
Test name
Test status
Simulation time 121096645 ps
CPU time 3.32 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:51 PM PDT 24
Peak memory 208260 kb
Host smart-3d655d78-d9aa-4d9a-8eff-83fa0ea852f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885812779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.885812779
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1223255967
Short name T872
Test name
Test status
Simulation time 6932407166 ps
CPU time 37.53 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 209444 kb
Host smart-c38c2c6d-9280-4e69-b8ef-daed55687763
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223255967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1223255967
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3010524458
Short name T612
Test name
Test status
Simulation time 211881796 ps
CPU time 5.18 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:53 PM PDT 24
Peak memory 214684 kb
Host smart-b2a2b5b5-9d69-48e6-b9c4-78d524f1e393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010524458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3010524458
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.4238590022
Short name T444
Test name
Test status
Simulation time 64582600 ps
CPU time 2.97 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 208332 kb
Host smart-1582ce25-ed0f-4534-9e6d-d900cc896cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238590022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.4238590022
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2663011030
Short name T736
Test name
Test status
Simulation time 1014580052 ps
CPU time 9.68 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:56 PM PDT 24
Peak memory 209024 kb
Host smart-7e897c23-d65a-45ce-86de-eefa9024870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663011030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2663011030
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.4214247292
Short name T558
Test name
Test status
Simulation time 357769737 ps
CPU time 2.76 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:49 PM PDT 24
Peak memory 210604 kb
Host smart-8a68dbc1-c470-45a9-ac85-077c6c15639d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214247292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.4214247292
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.234287267
Short name T895
Test name
Test status
Simulation time 51446462 ps
CPU time 0.79 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:49 PM PDT 24
Peak memory 206372 kb
Host smart-2deb80c0-aeba-4ade-9f56-1a5ead5a5724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234287267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.234287267
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3715673915
Short name T302
Test name
Test status
Simulation time 502829599 ps
CPU time 4.83 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:52 PM PDT 24
Peak memory 215808 kb
Host smart-cd96bf6a-b4d9-41c2-8cb7-2a3a17893670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715673915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3715673915
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2514236085
Short name T817
Test name
Test status
Simulation time 200230301 ps
CPU time 2.1 seconds
Started Aug 13 05:44:49 PM PDT 24
Finished Aug 13 05:44:51 PM PDT 24
Peak memory 210468 kb
Host smart-c4fd24db-514a-487f-aea1-0bd0966bfb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514236085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2514236085
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.924515068
Short name T844
Test name
Test status
Simulation time 48886106 ps
CPU time 2.64 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:49 PM PDT 24
Peak memory 209924 kb
Host smart-a0e5e71d-6e38-40f5-8f1e-982197a0e4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924515068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.924515068
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.4251167327
Short name T90
Test name
Test status
Simulation time 143556345 ps
CPU time 3.3 seconds
Started Aug 13 05:44:53 PM PDT 24
Finished Aug 13 05:44:57 PM PDT 24
Peak memory 209652 kb
Host smart-d9c4901a-2350-4cef-ba82-70fbcdb83ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251167327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.4251167327
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2783950472
Short name T729
Test name
Test status
Simulation time 47338946 ps
CPU time 2.02 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 214716 kb
Host smart-51a3b1dc-b07e-464c-8e6b-b2cb40c026be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783950472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2783950472
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.958879423
Short name T797
Test name
Test status
Simulation time 94935248 ps
CPU time 4.01 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:52 PM PDT 24
Peak memory 214712 kb
Host smart-2b3f1aa3-bb00-472e-84ab-2d74639aeba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958879423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.958879423
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3986638306
Short name T829
Test name
Test status
Simulation time 54809125 ps
CPU time 3.6 seconds
Started Aug 13 05:44:44 PM PDT 24
Finished Aug 13 05:44:47 PM PDT 24
Peak memory 222992 kb
Host smart-a2ff2096-779a-408d-a6d6-1c9fe5a60d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986638306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3986638306
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3686805830
Short name T819
Test name
Test status
Simulation time 52611345 ps
CPU time 2.76 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:49 PM PDT 24
Peak memory 208872 kb
Host smart-e3963f68-7699-4ef5-b1de-1557e888a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686805830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3686805830
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.792573454
Short name T191
Test name
Test status
Simulation time 62739787 ps
CPU time 2.46 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:49 PM PDT 24
Peak memory 207384 kb
Host smart-e9490666-ab21-4b88-9d4a-86b27959d3be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792573454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.792573454
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.258360843
Short name T893
Test name
Test status
Simulation time 170811545 ps
CPU time 3.98 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 209116 kb
Host smart-d055f45d-14d7-448c-b242-c821864db8bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258360843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.258360843
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.786521585
Short name T744
Test name
Test status
Simulation time 634203011 ps
CPU time 5.35 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:53 PM PDT 24
Peak memory 209180 kb
Host smart-80464ddd-fb50-40bc-9012-2757bb7fa2c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786521585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.786521585
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3355820
Short name T290
Test name
Test status
Simulation time 67056608 ps
CPU time 3.12 seconds
Started Aug 13 05:44:49 PM PDT 24
Finished Aug 13 05:44:52 PM PDT 24
Peak memory 210028 kb
Host smart-6ad76d17-35d0-48b9-b156-6b68d71d5e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3355820
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1806180804
Short name T578
Test name
Test status
Simulation time 675554043 ps
CPU time 4.88 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:51 PM PDT 24
Peak memory 209016 kb
Host smart-6cd9deab-6b14-44e1-8b46-7eacc9f16bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806180804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1806180804
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1289492710
Short name T75
Test name
Test status
Simulation time 119587659 ps
CPU time 8 seconds
Started Aug 13 05:44:45 PM PDT 24
Finished Aug 13 05:44:53 PM PDT 24
Peak memory 223084 kb
Host smart-e91b6365-07de-4711-ad0c-c527f80200c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289492710 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1289492710
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1604279459
Short name T704
Test name
Test status
Simulation time 358397847 ps
CPU time 5.84 seconds
Started Aug 13 05:44:49 PM PDT 24
Finished Aug 13 05:44:55 PM PDT 24
Peak memory 210768 kb
Host smart-4c0f8530-80ed-4ede-958b-31f43ea6aaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604279459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1604279459
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2117320222
Short name T767
Test name
Test status
Simulation time 54190573 ps
CPU time 2.49 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 210656 kb
Host smart-3b6e7383-0ecf-475a-8686-24035ab006e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117320222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2117320222
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2041974239
Short name T471
Test name
Test status
Simulation time 18105646 ps
CPU time 0.83 seconds
Started Aug 13 05:44:49 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 206432 kb
Host smart-c02165a8-2dcb-4ad8-94cf-a8aefd82ec80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041974239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2041974239
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1869094573
Short name T581
Test name
Test status
Simulation time 7018288966 ps
CPU time 15.29 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:45:02 PM PDT 24
Peak memory 209456 kb
Host smart-a050da44-c1ac-4869-b364-d0b5cf52f495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869094573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1869094573
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3637265087
Short name T750
Test name
Test status
Simulation time 250835797 ps
CPU time 5.53 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:57 PM PDT 24
Peak memory 221812 kb
Host smart-1400365f-55c9-43b1-92be-1e00d67117a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637265087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3637265087
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.876054947
Short name T501
Test name
Test status
Simulation time 82924576 ps
CPU time 3.33 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:55 PM PDT 24
Peak memory 221784 kb
Host smart-2abe56e0-d968-41c1-805f-bf49b3f9e9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876054947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.876054947
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3601942038
Short name T837
Test name
Test status
Simulation time 548479262 ps
CPU time 5.45 seconds
Started Aug 13 05:44:50 PM PDT 24
Finished Aug 13 05:44:56 PM PDT 24
Peak memory 210156 kb
Host smart-69de5505-7b1b-48c4-bcdb-1c84c8c5c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601942038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3601942038
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.889226468
Short name T335
Test name
Test status
Simulation time 1458471944 ps
CPU time 9.6 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:57 PM PDT 24
Peak memory 222824 kb
Host smart-f5a07350-a462-4f2c-9f24-2b451cc8a926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889226468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.889226468
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.838990113
Short name T492
Test name
Test status
Simulation time 511855295 ps
CPU time 4.52 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:53 PM PDT 24
Peak memory 207340 kb
Host smart-13cdd480-eb4e-4550-9bfb-6efbbac23437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838990113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.838990113
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2631183631
Short name T836
Test name
Test status
Simulation time 64289172 ps
CPU time 3.05 seconds
Started Aug 13 05:44:48 PM PDT 24
Finished Aug 13 05:44:52 PM PDT 24
Peak memory 209492 kb
Host smart-545cf607-9888-49ab-976c-ba44bac048ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631183631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2631183631
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.373943834
Short name T857
Test name
Test status
Simulation time 25580389 ps
CPU time 1.92 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:54 PM PDT 24
Peak memory 207612 kb
Host smart-8de69380-3a8e-4dde-aa9a-8f2f935a7382
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373943834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.373943834
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3123315651
Short name T717
Test name
Test status
Simulation time 159749966 ps
CPU time 4.06 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:52 PM PDT 24
Peak memory 216248 kb
Host smart-ede4fdd4-0b33-429a-9fcd-ad0cccdd9fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123315651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3123315651
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3591493177
Short name T658
Test name
Test status
Simulation time 82619574 ps
CPU time 1.82 seconds
Started Aug 13 05:44:49 PM PDT 24
Finished Aug 13 05:44:51 PM PDT 24
Peak memory 209064 kb
Host smart-694b0812-c68a-4859-907a-b8a5b6ea6c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591493177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3591493177
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3677811682
Short name T549
Test name
Test status
Simulation time 166308508 ps
CPU time 3.38 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:55 PM PDT 24
Peak memory 220548 kb
Host smart-a6c0fae8-4fe2-4664-8b01-95fbe98d4452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677811682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3677811682
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3442230075
Short name T192
Test name
Test status
Simulation time 871596137 ps
CPU time 3.69 seconds
Started Aug 13 05:44:46 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 208196 kb
Host smart-5421d015-3a72-4e32-99a8-524de46ca5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442230075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3442230075
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2328832461
Short name T372
Test name
Test status
Simulation time 115820814 ps
CPU time 1.92 seconds
Started Aug 13 05:44:49 PM PDT 24
Finished Aug 13 05:44:51 PM PDT 24
Peak memory 211332 kb
Host smart-5428e3ee-1406-43be-8ad8-4f9caca7b9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328832461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2328832461
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1821723942
Short name T416
Test name
Test status
Simulation time 32243873 ps
CPU time 0.86 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:53 PM PDT 24
Peak memory 206440 kb
Host smart-31956dd6-494a-49e9-bbd3-dec01c1492ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821723942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1821723942
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1149236896
Short name T663
Test name
Test status
Simulation time 74576012 ps
CPU time 1.72 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:45:02 PM PDT 24
Peak memory 214764 kb
Host smart-75e625e9-ae88-4d81-8ab7-5dd0d303faba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149236896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1149236896
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2162006937
Short name T598
Test name
Test status
Simulation time 277363770 ps
CPU time 3.42 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:55 PM PDT 24
Peak memory 210552 kb
Host smart-3fde0be4-61af-4d92-87e8-c60056407e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162006937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2162006937
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1473420393
Short name T284
Test name
Test status
Simulation time 717147108 ps
CPU time 19.39 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:45:12 PM PDT 24
Peak memory 214712 kb
Host smart-1f3dac1b-0787-43b6-ba36-4710f9df0626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473420393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1473420393
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.205964631
Short name T324
Test name
Test status
Simulation time 110726581 ps
CPU time 4.93 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:57 PM PDT 24
Peak memory 214684 kb
Host smart-6736ad43-8999-424b-be65-93f3a688418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205964631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.205964631
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.790281656
Short name T84
Test name
Test status
Simulation time 205911885 ps
CPU time 4.48 seconds
Started Aug 13 05:45:02 PM PDT 24
Finished Aug 13 05:45:07 PM PDT 24
Peak memory 207908 kb
Host smart-9661ba23-42c7-4ad1-8223-3f18ad4ae91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790281656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.790281656
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1033495114
Short name T900
Test name
Test status
Simulation time 272536646 ps
CPU time 2.98 seconds
Started Aug 13 05:44:54 PM PDT 24
Finished Aug 13 05:44:57 PM PDT 24
Peak memory 208900 kb
Host smart-526f7045-826a-4ba9-9875-840e9533657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033495114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1033495114
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3285512079
Short name T700
Test name
Test status
Simulation time 38538663 ps
CPU time 2.41 seconds
Started Aug 13 05:44:53 PM PDT 24
Finished Aug 13 05:44:55 PM PDT 24
Peak memory 207440 kb
Host smart-46894bbc-0f48-4748-b254-a7820f17cc65
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285512079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3285512079
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.660828200
Short name T417
Test name
Test status
Simulation time 187306032 ps
CPU time 2.93 seconds
Started Aug 13 05:44:53 PM PDT 24
Finished Aug 13 05:44:56 PM PDT 24
Peak memory 207488 kb
Host smart-c2875d04-ac4c-4a82-af97-86e1f266c74f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660828200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.660828200
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3160707997
Short name T431
Test name
Test status
Simulation time 36717424 ps
CPU time 2.53 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:55 PM PDT 24
Peak memory 207440 kb
Host smart-2b93bc2f-91f6-4176-9c10-a99bfa047d9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160707997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3160707997
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3689676766
Short name T858
Test name
Test status
Simulation time 108725654 ps
CPU time 2.42 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:01 PM PDT 24
Peak memory 210352 kb
Host smart-ca161e3d-14a6-4613-94e3-350f5ff3fa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689676766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3689676766
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3699587004
Short name T488
Test name
Test status
Simulation time 104342829 ps
CPU time 2.43 seconds
Started Aug 13 05:44:47 PM PDT 24
Finished Aug 13 05:44:50 PM PDT 24
Peak memory 207276 kb
Host smart-f0eb0875-cdbe-4ecd-aa38-1ab428138718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699587004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3699587004
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.4227125247
Short name T781
Test name
Test status
Simulation time 267993670 ps
CPU time 16.25 seconds
Started Aug 13 05:44:56 PM PDT 24
Finished Aug 13 05:45:13 PM PDT 24
Peak memory 222988 kb
Host smart-76694fc7-1992-4c2c-b06f-12078a30a59a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227125247 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.4227125247
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.4222576978
Short name T224
Test name
Test status
Simulation time 432886153 ps
CPU time 4.23 seconds
Started Aug 13 05:44:54 PM PDT 24
Finished Aug 13 05:44:58 PM PDT 24
Peak memory 214796 kb
Host smart-aec807ce-92cf-4f32-a5df-cf2fe8b176d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222576978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4222576978
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2402379172
Short name T746
Test name
Test status
Simulation time 17975597 ps
CPU time 1.04 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:24 PM PDT 24
Peak memory 206536 kb
Host smart-69676635-35ed-4ba0-918c-8631bf6c64d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402379172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2402379172
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.444901318
Short name T399
Test name
Test status
Simulation time 56525860 ps
CPU time 4.27 seconds
Started Aug 13 05:42:22 PM PDT 24
Finished Aug 13 05:42:27 PM PDT 24
Peak memory 214808 kb
Host smart-df1e8778-e5ec-4511-88ee-826efc42e277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444901318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.444901318
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3280344242
Short name T839
Test name
Test status
Simulation time 274534980 ps
CPU time 3.2 seconds
Started Aug 13 05:42:25 PM PDT 24
Finished Aug 13 05:42:28 PM PDT 24
Peak memory 208572 kb
Host smart-92313855-8e0f-4983-9055-c02930485712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280344242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3280344242
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1482920255
Short name T553
Test name
Test status
Simulation time 152297961 ps
CPU time 3.72 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:27 PM PDT 24
Peak memory 209364 kb
Host smart-238eadf0-eb2d-4754-9d86-3260b95efc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482920255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1482920255
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2558082640
Short name T773
Test name
Test status
Simulation time 105684254 ps
CPU time 4.7 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:38 PM PDT 24
Peak memory 214752 kb
Host smart-7b5ebefb-1a9e-4b0d-9efd-b277072f5639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558082640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2558082640
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.75820513
Short name T325
Test name
Test status
Simulation time 74829754 ps
CPU time 2.4 seconds
Started Aug 13 05:42:25 PM PDT 24
Finished Aug 13 05:42:27 PM PDT 24
Peak memory 214708 kb
Host smart-a23a79eb-8a58-4789-a024-937dbfe9011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75820513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.75820513
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.697332861
Short name T56
Test name
Test status
Simulation time 53183717 ps
CPU time 3.15 seconds
Started Aug 13 05:42:28 PM PDT 24
Finished Aug 13 05:42:31 PM PDT 24
Peak memory 214820 kb
Host smart-beb045dc-3cb2-450e-9026-e433d42bffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697332861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.697332861
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1657090503
Short name T259
Test name
Test status
Simulation time 31886011 ps
CPU time 2.45 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:25 PM PDT 24
Peak memory 208004 kb
Host smart-6b31f3a5-4212-42bc-abf3-8d2064556ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657090503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1657090503
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4276163850
Short name T486
Test name
Test status
Simulation time 745390292 ps
CPU time 11.41 seconds
Started Aug 13 05:42:26 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 209120 kb
Host smart-2c8a63b5-39f2-45a0-903b-762f722075e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276163850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4276163850
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2185402964
Short name T344
Test name
Test status
Simulation time 442991764 ps
CPU time 5.01 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:39 PM PDT 24
Peak memory 209144 kb
Host smart-ef531036-cebc-4120-a0e0-e1279412f8f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185402964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2185402964
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2494227055
Short name T439
Test name
Test status
Simulation time 64286991 ps
CPU time 2.34 seconds
Started Aug 13 05:42:27 PM PDT 24
Finished Aug 13 05:42:29 PM PDT 24
Peak memory 207448 kb
Host smart-e0c83e4b-b767-4e3c-8aab-7c3e4b767960
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494227055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2494227055
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1627964752
Short name T667
Test name
Test status
Simulation time 1087632325 ps
CPU time 3.84 seconds
Started Aug 13 05:42:27 PM PDT 24
Finished Aug 13 05:42:31 PM PDT 24
Peak memory 209380 kb
Host smart-776de405-0dab-4eef-99d9-17e7b2105849
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627964752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1627964752
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3896414565
Short name T253
Test name
Test status
Simulation time 148076636 ps
CPU time 3.32 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:27 PM PDT 24
Peak memory 218488 kb
Host smart-815aced4-a259-485d-9019-c90e187a0148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896414565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3896414565
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2332734651
Short name T411
Test name
Test status
Simulation time 309806710 ps
CPU time 3.16 seconds
Started Aug 13 05:42:24 PM PDT 24
Finished Aug 13 05:42:28 PM PDT 24
Peak memory 209160 kb
Host smart-c261d502-06c0-48b8-80ef-02ca73d5a77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332734651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2332734651
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2797310921
Short name T320
Test name
Test status
Simulation time 35355047 ps
CPU time 2.84 seconds
Started Aug 13 05:42:24 PM PDT 24
Finished Aug 13 05:42:27 PM PDT 24
Peak memory 214788 kb
Host smart-ca9365eb-7aef-4fd1-87ab-f881f32066a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797310921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2797310921
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3749980593
Short name T375
Test name
Test status
Simulation time 46827026 ps
CPU time 2.09 seconds
Started Aug 13 05:42:25 PM PDT 24
Finished Aug 13 05:42:27 PM PDT 24
Peak memory 210572 kb
Host smart-1a3087d8-e48f-49f7-9353-2aebab0026e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749980593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3749980593
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1495849867
Short name T512
Test name
Test status
Simulation time 13679149 ps
CPU time 0.75 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:34 PM PDT 24
Peak memory 206364 kb
Host smart-bc4513b2-d591-40ea-a838-0b9da0c50c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495849867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1495849867
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3385503517
Short name T31
Test name
Test status
Simulation time 385717525 ps
CPU time 3.49 seconds
Started Aug 13 05:42:35 PM PDT 24
Finished Aug 13 05:42:38 PM PDT 24
Peak memory 209748 kb
Host smart-7a2c27c0-8a1b-49cc-aef6-5d21246af378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385503517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3385503517
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1203733976
Short name T728
Test name
Test status
Simulation time 25614035 ps
CPU time 1.68 seconds
Started Aug 13 05:42:32 PM PDT 24
Finished Aug 13 05:42:34 PM PDT 24
Peak memory 220328 kb
Host smart-268a9522-1444-4b8f-9d95-1df374e1b6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203733976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1203733976
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2084336362
Short name T724
Test name
Test status
Simulation time 659701631 ps
CPU time 15.6 seconds
Started Aug 13 05:42:36 PM PDT 24
Finished Aug 13 05:42:52 PM PDT 24
Peak memory 222412 kb
Host smart-c010ac77-291a-4bde-9fe0-e55e884972c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084336362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2084336362
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.4287658476
Short name T251
Test name
Test status
Simulation time 281406038 ps
CPU time 2.48 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:36 PM PDT 24
Peak memory 214712 kb
Host smart-b6a722bf-73dc-468d-9d3e-42085f6d2ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287658476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.4287658476
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3168539981
Short name T46
Test name
Test status
Simulation time 521162124 ps
CPU time 4.68 seconds
Started Aug 13 05:42:32 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 221056 kb
Host smart-d325255b-5fb5-4594-bc52-5bf427b86912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168539981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3168539981
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2999848306
Short name T851
Test name
Test status
Simulation time 229110472 ps
CPU time 5.79 seconds
Started Aug 13 05:42:27 PM PDT 24
Finished Aug 13 05:42:33 PM PDT 24
Peak memory 220172 kb
Host smart-5dc4ff1a-4d1e-4da9-9e60-c3833f8940d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999848306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2999848306
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3638056333
Short name T244
Test name
Test status
Simulation time 619494062 ps
CPU time 14.51 seconds
Started Aug 13 05:42:25 PM PDT 24
Finished Aug 13 05:42:39 PM PDT 24
Peak memory 208616 kb
Host smart-1be0fe93-3235-4fac-ae54-1f153258a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638056333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3638056333
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3499338078
Short name T743
Test name
Test status
Simulation time 69677954 ps
CPU time 2.61 seconds
Started Aug 13 05:42:22 PM PDT 24
Finished Aug 13 05:42:24 PM PDT 24
Peak memory 209468 kb
Host smart-4d998c92-e274-4f38-8fe8-30e2ab1dbbd1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499338078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3499338078
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3519147298
Short name T458
Test name
Test status
Simulation time 149478989 ps
CPU time 4.53 seconds
Started Aug 13 05:42:28 PM PDT 24
Finished Aug 13 05:42:32 PM PDT 24
Peak memory 208980 kb
Host smart-1ab5ab76-b769-48be-aee1-ba414c25b5a3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519147298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3519147298
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1687042201
Short name T414
Test name
Test status
Simulation time 109876554 ps
CPU time 2.92 seconds
Started Aug 13 05:42:25 PM PDT 24
Finished Aug 13 05:42:28 PM PDT 24
Peak memory 207256 kb
Host smart-5f85c157-407a-435f-baf0-d3d75dc001a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687042201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1687042201
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4218497401
Short name T562
Test name
Test status
Simulation time 25264438 ps
CPU time 1.88 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:36 PM PDT 24
Peak memory 215932 kb
Host smart-9163d77b-3d78-4ea4-b32c-359b5712e2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218497401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4218497401
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2238719057
Short name T456
Test name
Test status
Simulation time 94728518 ps
CPU time 2.44 seconds
Started Aug 13 05:42:23 PM PDT 24
Finished Aug 13 05:42:26 PM PDT 24
Peak memory 207200 kb
Host smart-12e92470-b388-42a9-ab3c-2dd1d48a8679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238719057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2238719057
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.530298376
Short name T297
Test name
Test status
Simulation time 2165651002 ps
CPU time 29.17 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:43:02 PM PDT 24
Peak memory 215748 kb
Host smart-9c7bd867-3ac5-4131-bdd4-ecfc8835bff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530298376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.530298376
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.4183491079
Short name T469
Test name
Test status
Simulation time 369474170 ps
CPU time 10.47 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:45 PM PDT 24
Peak memory 211068 kb
Host smart-dcd62a0b-0c1a-42ac-b4a6-d9b4c8a295df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183491079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.4183491079
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2517254920
Short name T597
Test name
Test status
Simulation time 60385661 ps
CPU time 2 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:36 PM PDT 24
Peak memory 210600 kb
Host smart-9a22f698-30c7-49c6-8f86-9ced4930706c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517254920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2517254920
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3057432544
Short name T696
Test name
Test status
Simulation time 65464136 ps
CPU time 1 seconds
Started Aug 13 05:42:36 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 206112 kb
Host smart-3a4d99c3-e200-4831-a1e8-2033295740f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057432544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3057432544
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.192355015
Short name T402
Test name
Test status
Simulation time 1797261315 ps
CPU time 22.56 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:56 PM PDT 24
Peak memory 215512 kb
Host smart-b3520d20-66b0-43d2-9e66-7894f9c04d94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192355015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.192355015
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2381715101
Short name T26
Test name
Test status
Simulation time 58109612 ps
CPU time 1.46 seconds
Started Aug 13 05:42:36 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 209564 kb
Host smart-93e5b0ed-5f05-4072-8b6b-f8d489b9d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381715101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2381715101
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1334334209
Short name T582
Test name
Test status
Simulation time 330789480 ps
CPU time 6.5 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:40 PM PDT 24
Peak memory 209044 kb
Host smart-f3b73a01-3bdf-4323-910e-7a7b5b7986f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334334209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1334334209
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1524592059
Short name T748
Test name
Test status
Simulation time 89817970 ps
CPU time 4.32 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:38 PM PDT 24
Peak memory 214816 kb
Host smart-1d53dac5-f65f-4ded-8a4e-095c33a7b797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524592059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1524592059
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3485979228
Short name T264
Test name
Test status
Simulation time 187532889 ps
CPU time 3.5 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 214716 kb
Host smart-88343ebb-a7ba-44af-826d-c77d335838eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485979228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3485979228
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1747524617
Short name T215
Test name
Test status
Simulation time 96062946 ps
CPU time 4.63 seconds
Started Aug 13 05:42:37 PM PDT 24
Finished Aug 13 05:42:41 PM PDT 24
Peak memory 220996 kb
Host smart-9cffd3f0-e1a9-4ed8-925e-8ad25e5e789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747524617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1747524617
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.360904209
Short name T533
Test name
Test status
Simulation time 122132701 ps
CPU time 5.91 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:40 PM PDT 24
Peak memory 214808 kb
Host smart-48b4bb66-5993-4471-8f5d-0b8f901ce8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360904209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.360904209
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3837472614
Short name T909
Test name
Test status
Simulation time 364526023 ps
CPU time 9.59 seconds
Started Aug 13 05:42:30 PM PDT 24
Finished Aug 13 05:42:40 PM PDT 24
Peak memory 207460 kb
Host smart-ec94450d-8e84-4cfa-bdb2-0411a9bc11c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837472614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3837472614
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1383898
Short name T911
Test name
Test status
Simulation time 32040037 ps
CPU time 2.35 seconds
Started Aug 13 05:42:31 PM PDT 24
Finished Aug 13 05:42:33 PM PDT 24
Peak memory 207844 kb
Host smart-7521c7b2-c11b-4d5d-9db7-c45cc2ebb7b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1383898
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2520880297
Short name T474
Test name
Test status
Simulation time 1727043721 ps
CPU time 6.73 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:41 PM PDT 24
Peak memory 209360 kb
Host smart-55fddaa0-dd84-4124-bfc4-ce016c7e86ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520880297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2520880297
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1990026783
Short name T531
Test name
Test status
Simulation time 80896787 ps
CPU time 3.78 seconds
Started Aug 13 05:42:36 PM PDT 24
Finished Aug 13 05:42:40 PM PDT 24
Peak memory 209484 kb
Host smart-24c86d8e-ea69-4038-a13a-62f78f205767
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990026783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1990026783
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3854550051
Short name T79
Test name
Test status
Simulation time 372619198 ps
CPU time 3.42 seconds
Started Aug 13 05:42:36 PM PDT 24
Finished Aug 13 05:42:39 PM PDT 24
Peak memory 209396 kb
Host smart-734460d0-698f-4f48-bd54-57a90eb108ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854550051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3854550051
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.801660787
Short name T805
Test name
Test status
Simulation time 256523330 ps
CPU time 2.85 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 209096 kb
Host smart-2307bc1e-9657-4ef4-a61d-d09b476ee480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801660787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.801660787
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.673200475
Short name T848
Test name
Test status
Simulation time 445430665 ps
CPU time 17.89 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:52 PM PDT 24
Peak memory 222852 kb
Host smart-b38fae39-7efd-4bce-ad3e-90f5b66bd411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673200475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.673200475
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1089888893
Short name T116
Test name
Test status
Simulation time 1575403574 ps
CPU time 17.76 seconds
Started Aug 13 05:42:29 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 223124 kb
Host smart-ae697d1d-5f00-4051-a298-d894e18cc2c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089888893 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1089888893
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3712481731
Short name T260
Test name
Test status
Simulation time 170231395 ps
CPU time 4.19 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 211028 kb
Host smart-4b2fa8dd-acc1-4635-bbe1-2ac5342dc31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712481731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3712481731
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2873315044
Short name T475
Test name
Test status
Simulation time 71934633 ps
CPU time 1.34 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:35 PM PDT 24
Peak memory 210336 kb
Host smart-a653723c-6089-434c-8a5a-0d0787b12666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873315044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2873315044
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1334808614
Short name T461
Test name
Test status
Simulation time 11132841 ps
CPU time 0.71 seconds
Started Aug 13 05:42:49 PM PDT 24
Finished Aug 13 05:42:49 PM PDT 24
Peak memory 206396 kb
Host smart-c712648c-9d8e-433a-a5b9-c59401db2395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334808614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1334808614
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1037543778
Short name T358
Test name
Test status
Simulation time 107321502 ps
CPU time 2.29 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:36 PM PDT 24
Peak memory 214812 kb
Host smart-9084b9c5-5a6d-4794-a6c9-fa119602f5f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037543778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1037543778
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3367975337
Short name T566
Test name
Test status
Simulation time 101056021 ps
CPU time 1.63 seconds
Started Aug 13 05:42:41 PM PDT 24
Finished Aug 13 05:42:43 PM PDT 24
Peak memory 209456 kb
Host smart-665989b4-3d8f-41c6-b145-37fd3d4a62f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367975337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3367975337
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3499569544
Short name T691
Test name
Test status
Simulation time 45878289 ps
CPU time 2.47 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:36 PM PDT 24
Peak memory 210140 kb
Host smart-191d2f90-5046-4bcb-906a-7bb283547869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499569544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3499569544
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.265160061
Short name T87
Test name
Test status
Simulation time 358602970 ps
CPU time 5.22 seconds
Started Aug 13 05:42:38 PM PDT 24
Finished Aug 13 05:42:43 PM PDT 24
Peak memory 211832 kb
Host smart-83fd6241-4101-4bcd-a477-5517e9fdb22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265160061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.265160061
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.307645625
Short name T342
Test name
Test status
Simulation time 172907606 ps
CPU time 4.71 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 210708 kb
Host smart-37ff3dfb-6795-4ed9-bb08-fb10a2dec5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307645625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.307645625
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1423321971
Short name T477
Test name
Test status
Simulation time 4361905754 ps
CPU time 42.45 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:43:17 PM PDT 24
Peak memory 209924 kb
Host smart-63b93e94-02be-44d3-8082-d63c88510638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423321971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1423321971
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3145168655
Short name T437
Test name
Test status
Simulation time 410213391 ps
CPU time 4.53 seconds
Started Aug 13 05:42:32 PM PDT 24
Finished Aug 13 05:42:36 PM PDT 24
Peak memory 207244 kb
Host smart-b82ebf45-5ec7-41c5-a028-c12c5b708f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145168655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3145168655
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3204433011
Short name T766
Test name
Test status
Simulation time 832374427 ps
CPU time 6.62 seconds
Started Aug 13 05:42:35 PM PDT 24
Finished Aug 13 05:42:42 PM PDT 24
Peak memory 209248 kb
Host smart-f09a54e0-179e-470c-8438-7b128ad4f37d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204433011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3204433011
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2193951274
Short name T867
Test name
Test status
Simulation time 39572378 ps
CPU time 2.39 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:35 PM PDT 24
Peak memory 207420 kb
Host smart-152b32a9-d071-49bf-83ce-960801170d2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193951274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2193951274
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2789285214
Short name T534
Test name
Test status
Simulation time 48913171 ps
CPU time 2.66 seconds
Started Aug 13 05:42:32 PM PDT 24
Finished Aug 13 05:42:35 PM PDT 24
Peak memory 209092 kb
Host smart-378285cd-8ade-43c8-9de2-1bd8b37f81de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789285214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2789285214
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.688594390
Short name T635
Test name
Test status
Simulation time 273598223 ps
CPU time 2.66 seconds
Started Aug 13 05:42:41 PM PDT 24
Finished Aug 13 05:42:44 PM PDT 24
Peak memory 208744 kb
Host smart-d14cf77e-85ff-4978-9bef-e41cada92e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688594390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.688594390
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2565144256
Short name T875
Test name
Test status
Simulation time 126607664 ps
CPU time 3.61 seconds
Started Aug 13 05:42:33 PM PDT 24
Finished Aug 13 05:42:37 PM PDT 24
Peak memory 207284 kb
Host smart-00ec539f-f6bd-4828-b96d-87739f8bd191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565144256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2565144256
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3446992947
Short name T757
Test name
Test status
Simulation time 281143721 ps
CPU time 12.57 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:57 PM PDT 24
Peak memory 215620 kb
Host smart-08a098d2-cd52-4f4a-9e36-d97869bed680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446992947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3446992947
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.720063761
Short name T470
Test name
Test status
Simulation time 65100791 ps
CPU time 4.01 seconds
Started Aug 13 05:42:34 PM PDT 24
Finished Aug 13 05:42:38 PM PDT 24
Peak memory 218980 kb
Host smart-1a63dee0-3db0-4900-b88f-f6bca2d20504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720063761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.720063761
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3602598759
Short name T409
Test name
Test status
Simulation time 55025252 ps
CPU time 0.84 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:45 PM PDT 24
Peak memory 206388 kb
Host smart-43ea43f0-1a54-4282-835b-c11f21ff2594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602598759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3602598759
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1093609368
Short name T873
Test name
Test status
Simulation time 61998234 ps
CPU time 2.22 seconds
Started Aug 13 05:42:39 PM PDT 24
Finished Aug 13 05:42:41 PM PDT 24
Peak memory 222152 kb
Host smart-89c13c27-e044-4f25-81da-ee4b3bbedd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093609368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1093609368
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3457155047
Short name T232
Test name
Test status
Simulation time 172665897 ps
CPU time 3.67 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:48 PM PDT 24
Peak memory 214780 kb
Host smart-e8efa125-fa07-405f-a0f2-e1f9366d8134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457155047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3457155047
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2417677669
Short name T326
Test name
Test status
Simulation time 69052507 ps
CPU time 3.38 seconds
Started Aug 13 05:42:43 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 214716 kb
Host smart-51a27225-f2d2-4266-93a3-19c1dc7bd3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417677669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2417677669
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4148572072
Short name T53
Test name
Test status
Simulation time 141051226 ps
CPU time 2.65 seconds
Started Aug 13 05:42:39 PM PDT 24
Finished Aug 13 05:42:42 PM PDT 24
Peak memory 222884 kb
Host smart-8df2e527-2b1e-49fa-b44a-7b6f4dad88d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148572072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4148572072
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.41750368
Short name T730
Test name
Test status
Simulation time 2996487517 ps
CPU time 14.65 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:58 PM PDT 24
Peak memory 209528 kb
Host smart-4f93c5b0-7779-4ec4-bf6e-5cf6187a602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41750368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.41750368
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.689023181
Short name T276
Test name
Test status
Simulation time 23687731 ps
CPU time 1.74 seconds
Started Aug 13 05:42:41 PM PDT 24
Finished Aug 13 05:42:42 PM PDT 24
Peak memory 207656 kb
Host smart-077e4e57-120c-4cc0-a5b3-effd18974d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689023181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.689023181
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3579017067
Short name T337
Test name
Test status
Simulation time 406529424 ps
CPU time 4.35 seconds
Started Aug 13 05:42:40 PM PDT 24
Finished Aug 13 05:42:45 PM PDT 24
Peak memory 208964 kb
Host smart-006dd09e-c718-48ea-b732-1d66f8192c02
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579017067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3579017067
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1275084795
Short name T651
Test name
Test status
Simulation time 310248566 ps
CPU time 3.55 seconds
Started Aug 13 05:42:42 PM PDT 24
Finished Aug 13 05:42:46 PM PDT 24
Peak memory 209484 kb
Host smart-80940808-4b28-4020-9d25-99e2ed80b65c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275084795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1275084795
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3357808471
Short name T674
Test name
Test status
Simulation time 294262550 ps
CPU time 4.45 seconds
Started Aug 13 05:42:49 PM PDT 24
Finished Aug 13 05:42:54 PM PDT 24
Peak memory 207284 kb
Host smart-11b3256a-501a-4dfb-a861-7c4a605ce275
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357808471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3357808471
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.974942782
Short name T827
Test name
Test status
Simulation time 47200738 ps
CPU time 2.8 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 210276 kb
Host smart-cf88d33c-4869-4caa-b12e-d904f5530ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974942782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.974942782
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3234581445
Short name T722
Test name
Test status
Simulation time 186886962 ps
CPU time 2.49 seconds
Started Aug 13 05:42:41 PM PDT 24
Finished Aug 13 05:42:44 PM PDT 24
Peak memory 207448 kb
Host smart-bfb0493d-1a22-40dc-9e25-9c07dac50e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234581445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3234581445
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.692597480
Short name T73
Test name
Test status
Simulation time 1876637210 ps
CPU time 45.6 seconds
Started Aug 13 05:42:42 PM PDT 24
Finished Aug 13 05:43:27 PM PDT 24
Peak memory 221636 kb
Host smart-b439efc7-1962-4b54-9c42-3b354e7b9981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692597480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.692597480
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.580414695
Short name T117
Test name
Test status
Simulation time 465789682 ps
CPU time 6.79 seconds
Started Aug 13 05:42:40 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 222984 kb
Host smart-6217ad20-007d-479b-8311-0e7220afbcb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580414695 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.580414695
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2560413583
Short name T103
Test name
Test status
Simulation time 234239061 ps
CPU time 3.27 seconds
Started Aug 13 05:42:44 PM PDT 24
Finished Aug 13 05:42:47 PM PDT 24
Peak memory 207592 kb
Host smart-966cd573-3636-4745-bceb-4dc28710ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560413583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2560413583
Directory /workspace/9.keymgr_sw_invalid_input/latest
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