Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	50	1			T44	1		T29	1		T45	1
auto[OpGenId]	21	1			T14	1		T51	1		T46	1
auto[OpGenSwOut]	18	1			T3	1		T53	1		T19	1
auto[OpGenHwOut]	9	1			T39	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1527	1			T3	2		T66	3		T46	1
auto[StInit]	78	1			T2	1		T51	1		T44	1
auto[StCreatorRootKey]	62	1			T14	1		T36	1		T52	1
auto[StOwnerIntKey]	41	1			T59	2		T60	1		T61	1
auto[StOwnerKey]	44	1			T3	1		T45	1		T62	1
auto[StDisabled]	482	1			T3	4		T65	1		T66	7
auto[StInvalid]	50	1			T35	1		T48	1		T57	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3270

1

T1

1

T2

2

T3

7

auto[1]

98

1

T3

1

T14

1

T51

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1523	1			T3	2		T66	3		T46	1
auto[StReset]	auto[1]	4	1			T19	1		T49	1		T196	1
auto[StInit]	auto[0]	35	1			T2	1		T37	1		T30	1
auto[StInit]	auto[1]	43	1			T51	1		T44	1		T29	1
auto[StCreatorRootKey]	auto[0]	46	1			T36	1		T52	1		T42	1
auto[StCreatorRootKey]	auto[1]	16	1			T14	1		T61	1		T213	1
auto[StOwnerIntKey]	auto[0]	29	1			T59	1		T61	1		T70	1
auto[StOwnerIntKey]	auto[1]	12	1			T59	1		T60	1		T76	1
auto[StOwnerKey]	auto[0]	32	1			T62	1		T53	1		T72	1
auto[StOwnerKey]	auto[1]	12	1			T3	1		T45	1		T142	1
auto[StDisabled]	auto[0]	471	1			T3	4		T65	1		T66	7
auto[StDisabled]	auto[1]	11	1			T53	1		T6	1		T76	2
auto[StInvalid]	auto[0]	50	1			T35	1		T48	1		T57	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	3	1			T49	1		T196	1		T50	1
auto[StReset]	auto[OpGenSwOut]	1	1			T19	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	24	1			T44	1		T29	1		T46	1
auto[StInit]	auto[OpGenId]	9	1			T51	1		T46	1		T9	1
auto[StInit]	auto[OpGenSwOut]	5	1			T144	1		T214	1		T215	1
auto[StInit]	auto[OpGenHwOut]	5	1			T39	1		T216	1		T217	1
auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T213	1		T218	1		T219	1
auto[StCreatorRootKey]	auto[OpGenId]	4	1			T14	1		T61	1		T220	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T221	1		T222	1		T223	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	1	1			T8	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T59	1		T76	1		T224	1
auto[StOwnerIntKey]	auto[OpGenId]	4	1			T60	1		T225	1		T226	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T213	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T7	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	5	1			T45	1		T142	1		T59	1
auto[StOwnerKey]	auto[OpGenId]	2	1			T227	1		T146	1		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T3	1		T228	1		T229	1
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T222	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T76	2		T230	1		T231	1
auto[StDisabled]	auto[OpGenId]	2	1			T232	1		T233	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T53	1		T231	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T6	1		-	-		-	-