Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4983

1

T3

11

T4

12

T5

5

auto[1]

604

1

T3

4

T15

2

T18

7

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4983

1

T3

11

T4

12

T5

5

auto[1]

604

1

T3

4

T15

2

T18

7

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5017

1

T3

15

T4

8

T5

5

auto[1]

570

1

T4

4

T15

2

T16

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5017

1

T3

15

T4

8

T5

5

auto[1]

570

1

T4

4

T15

2

T16

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	480	1			T3	2		T15	2		T18	7
auto[OpGenId]	1197	1			T3	6		T5	1		T15	1
auto[OpGenSwOut]	1230	1			T3	2		T5	2		T15	2
auto[OpGenHwOut]	2603	1			T3	3		T4	12		T5	2
auto[OpDisable]	77	1			T3	2		T34	1		T47	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	480	1			T3	2		T15	2		T18	7
auto[OpGenId]	1197	1			T3	6		T5	1		T15	1
auto[OpGenSwOut]	1230	1			T3	2		T5	2		T15	2
auto[OpGenHwOut]	2603	1			T3	3		T4	12		T5	2
auto[OpDisable]	77	1			T3	2		T34	1		T47	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4991

1

T3

14

T4

12

T5

5

auto[1]

596

1

T3

1

T15

4

T18

5

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4991

1

T3

14

T4

12

T5

5

auto[1]

596

1

T3

1

T15

4

T18

5

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5257

1

T3

15

T4

12

T5

5

auto[1]

330

1

T18

10

T143

6

T132

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1893	1			T3	6		T4	5		T5	2
auto[1]	753	1			T4	1		T15	3		T79	1
auto[2]	746	1			T3	2		T4	2		T15	1
auto[3]	729	1			T3	2		T4	2		T18	2
auto[4]	365	1			T3	1		T4	1		T18	4
auto[5]	359	1			T3	1		T35	1		T82	1
auto[6]	352	1			T5	1		T23	1		T83	1
auto[7]	390	1			T3	3		T4	1		T5	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1466	1			T3	5		T4	2		T5	3
clear_one[1]	753	1			T4	1		T15	3		T79	1
clear_one[2]	746	1			T3	2		T4	2		T15	1
clear_one[3]	729	1			T3	2		T4	2		T18	2
clear_none	1893	1			T3	6		T4	5		T5	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1000	1			T3	3		T4	4		T15	1
auto[StInit]	728	1			T3	2		T4	1		T14	1
auto[StCreatorRootKey]	589	1			T3	2		T4	1		T5	1
auto[StOwnerIntKey]	542	1			T3	2		T4	1		T18	2
auto[StOwnerKey]	499	1			T4	1		T5	1		T23	1
auto[StDisabled]	1947	1			T3	6		T4	4		T5	3
auto[StInvalid]	282	1			T35	4		T38	4		T48	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1000	1			T3	3		T4	4		T15	1
auto[StInit]	728	1			T3	2		T4	1		T14	1
auto[StCreatorRootKey]	589	1			T3	2		T4	1		T5	1
auto[StOwnerIntKey]	542	1			T3	2		T4	1		T18	2
auto[StOwnerKey]	499	1			T4	1		T5	1		T23	1
auto[StDisabled]	1947	1			T3	6		T4	4		T5	3
auto[StInvalid]	282	1			T35	4		T38	4		T48	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[4] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[4] - auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[4] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T234	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	150	1			T3	2		T18	1		T38	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	158	1			T15	1		T35	1		T65	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	268	1			T4	2		T35	2		T23	1
auto[0]	auto[StInit]	auto[OpAdvance]	55	1			T66	1		T72	1		T69	1
auto[0]	auto[StInit]	auto[OpGenId]	130	1			T34	1		T23	1		T82	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	91	1			T79	1		T45	1		T46	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	193	1			T3	1		T4	1		T14	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T3	1		T235	1		T76	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	46	1			T128	1		T127	1		T211	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	60	1			T3	1		T66	1		T55	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	78	1			T5	1		T16	1		T53	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	18	1			T80	1		T129	1		T131	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	39	1			T47	1		T72	1		T236	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	41	1			T46	1		T53	1		T59	3
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T66	1		T45	1		T125	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T237	1		T195	2		T97	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	21	1			T143	2		T134	1		T75	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T5	1		T66	1		T53	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	55	1			T66	1		T199	1		T108	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	31	1			T18	3		T238	1		T229	1
auto[0]	auto[StDisabled]	auto[OpGenId]	59	1			T3	1		T66	1		T52	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T66	1		T47	1		T71	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T4	2		T15	1		T18	1
auto[0]	auto[StDisabled]	auto[OpDisable]	21	1			T73	1		T75	1		T239	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	12	1			T201	1		T202	1		T240	2
auto[0]	auto[StInvalid]	auto[OpGenId]	20	1			T48	1		T201	1		T89	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	19	1			T48	2		T106	1		T241	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	21	1			T38	2		T126	1		T87	1
auto[1]	auto[StReset]	auto[OpGenId]	19	1			T44	1		T47	1		T242	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	18	1			T66	1		T133	1		T243	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	51	1			T244	1		T53	1		T201	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T15	1		T121	1		T245	1
auto[1]	auto[StInit]	auto[OpGenId]	11	1			T228	1		T246	1		T247	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	9	1			T61	1		T221	1		T248	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	22	1			T249	1		T250	1		T251	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T252	1		T253	1		T95	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T52	1		T59	1		T76	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T122	1		T254	1		T255	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T256	1		T199	1		T257	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T258	1		T259	1		T260	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	23	1			T128	1		T61	1		T254	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T108	1		T261	1		T73	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T4	1		T83	1		T208	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	14	1			T45	1		T61	1		T229	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	16	1			T262	1		T135	1		T74	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T128	1		T59	1		T237	2
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T125	1		T249	1		T263	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	26	1			T66	1		T132	1		T73	1
auto[1]	auto[StDisabled]	auto[OpGenId]	56	1			T15	1		T131	1		T66	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T15	1		T79	1		T26	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	167	1			T66	1		T125	1		T256	3
auto[1]	auto[StDisabled]	auto[OpDisable]	7	1			T73	1		T213	1		T264	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T101	1		T265	1		T266	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T38	1		T267	1		T268	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T85	1		T269	1		T270	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T101	1		T271	1		T58	1
auto[2]	auto[StReset]	auto[OpGenId]	16	1			T101	1		T88	1		T73	2
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T3	1		T66	1		T74	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	51	1			T23	1		T47	1		T263	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T7	1		T272	1		T273	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T65	1		T72	1		T133	4
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T213	1		T274	1		T275	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	29	1			T257	1		T107	1		T61	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T129	1		T134	1		T229	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T213	1		T96	1		T224	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T66	1		T276	1		T231	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T83	1		T212	1		T244	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T18	1		T61	1		T277	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T278	1		T276	1		T7	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T82	1		T235	1		T133	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T3	1		T257	1		T104	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T76	1		T49	1		T278	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	20	1			T131	1		T261	1		T190	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T229	1		T252	1		T7	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T4	1		T66	1		T52	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	33	1			T15	1		T133	1		T254	1
auto[2]	auto[StDisabled]	auto[OpGenId]	54	1			T46	1		T108	1		T59	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	83	1			T18	1		T26	1		T66	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T4	1		T18	2		T83	2
auto[2]	auto[StDisabled]	auto[OpDisable]	12	1			T34	1		T75	1		T61	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T88	1		T106	1		T279	1
auto[2]	auto[StInvalid]	auto[OpGenId]	13	1			T38	1		T101	1		T270	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T88	1		T280	1		T281	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T101	1		T88	1		T89	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T282	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	12	1			T18	1		T262	1		T53	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	25	1			T66	1		T46	1		T134	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	46	1			T4	1		T18	1		T83	2
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T44	1		T59	1		T283	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T7	1		T230	1		T284	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	11	1			T26	1		T285	1		T286	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T244	1		T72	1		T287	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T288	1		T278	1		T289	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	18	1			T53	1		T203	1		T59	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T53	1		T190	1		T76	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T4	1		T125	1		T290	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T291	1		T292	1		T293	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T55	1		T294	1		T135	2
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T195	1		T213	1		T295	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T244	1		T105	1		T134	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T260	1		T296	1		T297	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	7	1			T66	1		T59	1		T213	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T59	1		T134	1		T274	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T47	1		T204	1		T298	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	26	1			T134	1		T73	1		T229	2
auto[3]	auto[StDisabled]	auto[OpGenId]	52	1			T71	1		T72	1		T56	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T143	1		T134	1		T75	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T23	1		T83	1		T208	1
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T3	2		T47	1		T52	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	8	1			T85	1		T268	1		T299	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T101	1		T240	1		T267	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T126	1		T201	1		T85	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T35	1		T300	1		T240	1
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T76	1		T221	1		T301	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T65	1		T73	1		T76	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	14	1			T4	1		T53	1		T302	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T18	2		T58	1		T303	1
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T238	1		T73	1		T213	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T304	2		T305	1		T184	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	6	1			T306	1		T307	1		T308	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T18	1		T66	1		T132	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T66	1		T6	1		T309	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T294	1		T195	2		T276	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T72	1		T287	1		T263	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T76	1		T310	1		T311	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T3	1		T285	1		T132	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T18	1		T132	1		T134	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T302	1		T250	1		T312	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T23	1		T313	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T286	1		T49	1		T314	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T255	1		T76	1		T315	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T79	1		T290	1		T105	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T252	1		T282	1		T231	1
auto[4]	auto[StDisabled]	auto[OpGenId]	38	1			T69	1		T235	1		T134	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T59	1		T121	1		T73	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T208	1		T125	1		T69	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T277	1		T316	1		T226	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	6	1			T35	2		T88	1		T301	1
auto[4]	auto[StInvalid]	auto[OpGenId]	9	1			T48	1		T269	1		T317	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T48	1		T271	1		T301	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T240	1		T318	1		T319	1
auto[5]	auto[StReset]	auto[OpGenId]	15	1			T53	1		T71	1		T134	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	6	1			T65	1		T25	1		T196	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	19	1			T88	1		T125	1		T290	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T274	2		T320	1		T321	1
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T221	1		T322	1		T321	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	8	1			T211	1		T323	1		T324	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T125	1		T290	1		T71	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T49	1		T274	1		T221	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T194	1		T325	1		T197	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T70	1		T326	1		T221	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T82	1		T66	1		T59	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T262	1		T286	1		T76	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T327	1		T197	1		T226	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T134	1		T75	1		T222	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T84	1		T134	1		T263	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T121	1		T274	4		T328	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	5	1			T195	1		T329	1		T330	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T331	3		T332	1		T196	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T52	1		T107	1		T333	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	14	1			T134	1		T229	1		T234	2
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T3	1		T134	1		T190	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T66	2		T75	1		T122	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T131	1		T212	1		T66	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T334	1		T335	1		T336	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T337	1		T338	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T87	1		T300	1		T299	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T88	1		T242	1		T267	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T35	1		T89	1		T242	1
auto[6]	auto[StReset]	auto[OpAdvance]	1	1			T260	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T300	1		T229	2		T68	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T68	1		T264	1		T339	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T256	1		T302	2		T340	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T195	1		T182	1		T341	1
auto[6]	auto[StInit]	auto[OpGenId]	8	1			T122	1		T231	1		T342	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	12	1			T59	1		T343	1		T260	2
auto[6]	auto[StInit]	auto[OpGenHwOut]	13	1			T47	1		T260	1		T213	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T23	1		T243	1		T73	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T71	1		T229	1		T295	2
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T208	1		T71	1		T121	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T195	1		T344	1		T345	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T66	1		T73	1		T346	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T122	1		T252	1		T196	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T52	1		T347	1		T348	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T349	1		T350	1		T351	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	14	1			T132	1		T61	1		T229	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T26	1		T235	1		T275	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T84	1		T208	1		T212	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T76	1		T41	1		T196	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T5	1		T192	1		T73	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T71	1		T285	1		T74	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	59	1			T83	1		T84	1		T244	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T72	1		T315	1		T352	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T126	1		T300	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T87	1		T85	1		T240	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T25	1		T240	1		T324	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T353	2		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T61	1		T195	1		T213	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T121	1		T70	1		T260	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	30	1			T302	1		T250	1		T354	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T3	1		T50	1		T355	1
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T66	1		T122	1		T31	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	5	1			T70	1		T275	1		T356	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	9	1			T23	1		T189	1		T263	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T142	1		T73	1		T90	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T357	1		T73	1		T213	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T45	1		T358	1		T134	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T84	1		T298	1		T359	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T360	1		T361	2		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T53	1		T134	1		T61	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T362	1		T305	1		T363	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T212	1		T256	1		T199	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T288	1		T364	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T59	1		T49	1		T221	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T71	1		T275	1		T248	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T83	1		T365	1		T104	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	18	1			T133	1		T254	1		T288	1
auto[7]	auto[StDisabled]	auto[OpGenId]	33	1			T3	1		T71	1		T133	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	40	1			T5	1		T59	1		T133	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T3	1		T4	1		T5	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T75	1		T366	1		T367	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T85	1		T280	1		T368	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T271	2		T318	1		T369	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T126	1		T270	1		T58	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T201	1		T280	1		T324	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1466

1

T3

5

T4

2

T5

3

clear_one[1]

auto[0]

auto[0]

auto[0]

426

1

T15

1

T79

1

T44

1

clear_one[1]

auto[0]

auto[0]

auto[1]

152

1

T15

1

T26

1

T125

2

clear_one[1]

auto[0]

auto[1]

auto[0]

131

1

T4

1

T83

1

T128

2

clear_one[1]

auto[0]

auto[1]

auto[1]

44

1

T15

1

T66

2

T142

1

clear_one[2]

auto[0]

auto[0]

auto[0]

426

1

T3

1

T4

2

T18

1

clear_one[2]

auto[0]

auto[0]

auto[1]

125

1

T3

1

T34

1

T26

1

clear_one[2]

auto[1]

auto[0]

auto[0]

150

1

T18

2

T84

2

T131

1

clear_one[2]

auto[1]

auto[0]

auto[1]

45

1

T15

1

T18

1

T46

1

clear_one[3]

auto[0]

auto[0]

auto[0]

425

1

T4

1

T18

2

T35

1

clear_one[3]

auto[0]

auto[1]

auto[0]

125

1

T4

1

T83

1

T208

1

clear_one[3]

auto[1]

auto[0]

auto[0]

128

1

T3

2

T66

2

T204

1

clear_one[3]

auto[1]

auto[1]

auto[0]

51

1

T71

1

T69

1

T132

1

clear_none

auto[0]

auto[0]

auto[0]

1367

1

T3

4

T4

3

T5

2

clear_none

auto[0]

auto[0]

auto[1]

138

1

T26

1

T125

1

T47

1

clear_none

auto[0]

auto[1]

auto[0]

127

1

T4

2

T16

1

T66

2

clear_none

auto[0]

auto[1]

auto[1]

31

1

T53

1

T69

1

T243

1

clear_none

auto[1]

auto[0]

auto[0]

136

1

T3

2

T84

1

T66

2

clear_none

auto[1]

auto[0]

auto[1]

33

1

T18

4

T72

1

T59

2

clear_none

auto[1]

auto[1]

auto[0]

33

1

T66

1

T59

1

T238

6

clear_none

auto[1]

auto[1]

auto[1]

28

1

T15

1

T120

1

T229

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1375	1			T3	5		T4	2		T5	3
clear_all	auto[1]	91	1			T18	3		T132	3		T133	2
clear_one[1]	auto[0]	687	1			T4	1		T15	3		T79	1
clear_one[1]	auto[1]	66	1			T135	1		T237	2		T288	8
clear_one[2]	auto[0]	699	1			T3	2		T4	2		T15	1
clear_one[2]	auto[1]	47	1			T18	3		T133	4		T278	3
clear_one[3]	auto[0]	687	1			T3	2		T4	2		T18	2
clear_one[3]	auto[1]	42	1			T143	3		T238	2		T135	1
clear_none	auto[0]	1809	1			T3	6		T4	5		T5	2
clear_none	auto[1]	84	1			T18	4		T143	3		T132	1