Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11438

1

T2

5

T3

60

T4

11

auto[Attestation]

7910

1

T3

39

T4

4

T5

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2920	1			T3	27		T5	2		T15	6
auto[Aes]	3464	1			T2	3		T3	15		T5	2
auto[Kmac]	3443	1			T2	1		T3	14		T4	15
auto[Otbn]	3378	1			T2	1		T3	10		T5	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7853	1			T2	1		T3	35		T4	8
auto[OpGenId]	6143	1			T3	33		T5	2		T14	3
auto[OpGenSwOut]	6096	1			T2	2		T3	27		T5	3
auto[OpGenHwOut]	7109	1			T2	3		T3	39		T4	15
auto[OpDisable]	152	1			T3	2		T34	1		T47	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11045

1

T2

1

T3

65

T4

8

auto[OpDoneFail]

16308

1

T2

5

T3

71

T4

15

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6571	1			T2	4		T3	24		T4	8
auto[StInit]	3915	1			T2	2		T3	20		T4	2
auto[StCreatorRootKey]	3317	1			T3	15		T4	2		T5	2
auto[StOwnerIntKey]	2904	1			T3	21		T4	2		T5	2
auto[StOwnerKey]	2522	1			T3	17		T4	2		T5	2
auto[StDisabled]	8124	1			T3	39		T4	7		T5	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	346	1			T3	2		T18	2		T35	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	107	1			T18	1		T80	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	90	1			T46	2		T72	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	75	1			T15	1		T34	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	70	1			T80	1		T65	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	256	1			T3	3		T15	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	320	1			T14	1		T15	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	94	1			T2	1		T46	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	97	1			T34	1		T36	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	84	1			T3	1		T128	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	72	1			T3	2		T128	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	237	1			T3	2		T5	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	335	1			T2	1		T3	2		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	107	1			T3	1		T23	1		T128	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T3	1		T80	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	78	1			T34	1		T79	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	51	1			T47	1		T71	1		T59	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	214	1			T130	1		T131	1		T66	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	332	1			T3	1		T35	2		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	112	1			T5	1		T16	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T3	2		T65	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T59	2		T63	1		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	59	1			T66	1		T53	1		T59	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	222	1			T3	1		T26	2		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	75	1			T3	1		T66	2		T53	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	123	1			T36	1		T207	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	92	1			T16	1		T65	1		T66	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T3	3		T82	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	64	1			T128	1		T66	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	231	1			T3	1		T15	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	80	1			T3	1		T66	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	101	1			T18	1		T36	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	98	1			T3	1		T36	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	86	1			T66	1		T71	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	56	1			T26	1		T211	1		T143	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	190	1			T66	2		T124	2		T46	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	90	1			T46	1		T53	3		T71	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	104	1			T79	1		T82	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T26	1		T53	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T66	1		T211	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	53	1			T3	1		T5	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	243	1			T18	1		T23	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T53	1		T71	3		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	103	1			T16	1		T34	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	80	1			T42	1		T72	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T3	1		T18	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	45	1			T15	1		T53	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	219	1			T18	1		T26	3		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	300	1			T3	6		T44	1		T65	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	102	1			T3	2		T34	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T15	1		T80	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	73	1			T5	1		T23	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T79	1		T65	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	188	1			T3	2		T34	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	471	1			T2	1		T18	2		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	111	1			T2	1		T3	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	125	1			T3	1		T207	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	90	1			T82	1		T65	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	93	1			T3	2		T128	2		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	300	1			T3	1		T5	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	458	1			T3	1		T4	7		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	114	1			T14	1		T23	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	133	1			T4	1		T15	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T4	1		T129	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	93	1			T3	2		T4	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	276	1			T3	1		T4	1		T83	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	463	1			T2	1		T15	1		T23	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	122	1			T23	2		T66	1		T125	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	107	1			T15	1		T16	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	105	1			T3	2		T129	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	103	1			T3	1		T71	1		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	273	1			T15	1		T26	1		T66	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T46	2		T71	1		T72	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	84	1			T3	2		T36	1		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	59	1			T5	1		T18	1		T127	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T3	1		T47	2		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T66	2		T52	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	190	1			T3	4		T15	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	75	1			T53	1		T71	7		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	130	1			T37	1		T212	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	117	1			T16	1		T84	1		T207	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T3	1		T84	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	79	1			T3	1		T80	2		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	268	1			T3	1		T15	1		T84	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	61	1			T46	1		T53	3		T71	7
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	127	1			T3	1		T4	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T3	1		T15	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T3	1		T82	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	88	1			T83	1		T128	2		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	300	1			T3	2		T4	3		T83	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T66	1		T46	3		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T3	1		T57	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T18	1		T207	2		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T3	1		T129	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	101	1			T80	3		T65	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	257	1			T18	1		T26	1		T66	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	219	1			T15	1		T34	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	725	1			T3	5		T15	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	234	1			T3	3		T34	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	670	1			T2	1		T3	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	203	1			T3	1		T34	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	672	1			T2	1		T3	3		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T3	2		T65	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	686	1			T3	2		T5	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	221	1			T3	3		T16	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	441	1			T3	2		T15	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	226	1			T3	1		T36	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	385	1			T3	1		T18	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	189	1			T3	1		T5	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	447	1			T18	1		T23	1		T79	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	183	1			T3	1		T15	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	402	1			T16	1		T18	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	196	1			T5	1		T15	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	606	1			T3	10		T34	2		T23	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	299	1			T3	3		T82	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	891	1			T2	2		T3	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	283	1			T3	2		T4	3		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	865	1			T3	2		T4	8		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	301	1			T3	3		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	872	1			T2	1		T15	2		T23	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	167	1			T3	1		T5	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	345	1			T3	6		T15	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	275	1			T3	2		T16	1		T80	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	484	1			T3	1		T15	1		T84	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T3	2		T15	1		T82	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	504	1			T3	3		T4	4		T23	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	292	1			T3	1		T18	1		T80	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	449	1			T3	1		T18	1		T26	1