Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33477

1

T2

7

T3

160

T4

28

auto[1]

308

1

T18

7

T143

12

T132

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33487	1			T2	7		T3	160		T4	28
auto[134217728:268435455]	10	1			T143	1		T331	1		T260	1
auto[268435456:402653183]	11	1			T237	1		T260	1		T304	1
auto[402653184:536870911]	13	1			T143	1		T237	1		T260	3
auto[536870912:671088639]	12	1			T143	2		T132	1		T304	1
auto[671088640:805306367]	13	1			T18	1		T143	1		T237	2
auto[805306368:939524095]	4	1			T403	1		T385	1		T296	1
auto[939524096:1073741823]	7	1			T282	1		T304	1		T385	1
auto[1073741824:1207959551]	9	1			T18	1		T260	1		T274	2
auto[1207959552:1342177279]	13	1			T238	1		T383	1		T260	3
auto[1342177280:1476395007]	13	1			T331	1		T288	2		T325	1
auto[1476395008:1610612735]	12	1			T18	1		T133	1		T237	1
auto[1610612736:1744830463]	6	1			T132	1		T260	1		T296	1
auto[1744830464:1879048191]	13	1			T143	1		T237	3		T234	1
auto[1879048192:2013265919]	11	1			T132	1		T135	1		T288	1
auto[2013265920:2147483647]	10	1			T18	1		T237	1		T274	1
auto[2147483648:2281701375]	4	1			T238	1		T331	1		T260	1
auto[2281701376:2415919103]	9	1			T238	1		T288	1		T274	1
auto[2415919104:2550136831]	9	1			T18	1		T296	1		T404	1
auto[2550136832:2684354559]	7	1			T143	1		T237	1		T288	1
auto[2684354560:2818572287]	7	1			T238	1		T237	1		T331	1
auto[2818572288:2952790015]	11	1			T143	1		T132	1		T288	1
auto[2952790016:3087007743]	9	1			T18	1		T143	1		T278	1
auto[3087007744:3221225471]	13	1			T132	1		T331	3		T325	1
auto[3221225472:3355443199]	14	1			T143	1		T238	2		T234	1
auto[3355443200:3489660927]	10	1			T143	1		T238	2		T331	1
auto[3489660928:3623878655]	11	1			T237	1		T383	1		T260	1
auto[3623878656:3758096383]	8	1			T237	3		T260	1		T311	1
auto[3758096384:3892314111]	7	1			T143	1		T238	1		T274	1
auto[3892314112:4026531839]	9	1			T132	1		T260	1		T386	1
auto[4026531840:4160749567]	5	1			T18	1		T237	1		T234	1
auto[4160749568:4294967295]	8	1			T237	1		T234	2		T325	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33477	1			T2	7		T3	160		T4	28
auto[0:134217727]	auto[1]	10	1			T237	1		T234	1		T325	2
auto[134217728:268435455]	auto[1]	10	1			T143	1		T331	1		T260	1
auto[268435456:402653183]	auto[1]	11	1			T237	1		T260	1		T304	1
auto[402653184:536870911]	auto[1]	13	1			T143	1		T237	1		T260	3
auto[536870912:671088639]	auto[1]	12	1			T143	2		T132	1		T304	1
auto[671088640:805306367]	auto[1]	13	1			T18	1		T143	1		T237	2
auto[805306368:939524095]	auto[1]	4	1			T403	1		T385	1		T296	1
auto[939524096:1073741823]	auto[1]	7	1			T282	1		T304	1		T385	1
auto[1073741824:1207959551]	auto[1]	9	1			T18	1		T260	1		T274	2
auto[1207959552:1342177279]	auto[1]	13	1			T238	1		T383	1		T260	3
auto[1342177280:1476395007]	auto[1]	13	1			T331	1		T288	2		T325	1
auto[1476395008:1610612735]	auto[1]	12	1			T18	1		T133	1		T237	1
auto[1610612736:1744830463]	auto[1]	6	1			T132	1		T260	1		T296	1
auto[1744830464:1879048191]	auto[1]	13	1			T143	1		T237	3		T234	1
auto[1879048192:2013265919]	auto[1]	11	1			T132	1		T135	1		T288	1
auto[2013265920:2147483647]	auto[1]	10	1			T18	1		T237	1		T274	1
auto[2147483648:2281701375]	auto[1]	4	1			T238	1		T331	1		T260	1
auto[2281701376:2415919103]	auto[1]	9	1			T238	1		T288	1		T274	1
auto[2415919104:2550136831]	auto[1]	9	1			T18	1		T296	1		T404	1
auto[2550136832:2684354559]	auto[1]	7	1			T143	1		T237	1		T288	1
auto[2684354560:2818572287]	auto[1]	7	1			T238	1		T237	1		T331	1
auto[2818572288:2952790015]	auto[1]	11	1			T143	1		T132	1		T288	1
auto[2952790016:3087007743]	auto[1]	9	1			T18	1		T143	1		T278	1
auto[3087007744:3221225471]	auto[1]	13	1			T132	1		T331	3		T325	1
auto[3221225472:3355443199]	auto[1]	14	1			T143	1		T238	2		T234	1
auto[3355443200:3489660927]	auto[1]	10	1			T143	1		T238	2		T331	1
auto[3489660928:3623878655]	auto[1]	11	1			T237	1		T383	1		T260	1
auto[3623878656:3758096383]	auto[1]	8	1			T237	3		T260	1		T311	1
auto[3758096384:3892314111]	auto[1]	7	1			T143	1		T238	1		T274	1
auto[3892314112:4026531839]	auto[1]	9	1			T132	1		T260	1		T386	1
auto[4026531840:4160749567]	auto[1]	5	1			T18	1		T237	1		T234	1
auto[4160749568:4294967295]	auto[1]	8	1			T237	1		T234	2		T325	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1666

1

T3

12

T14

3

T15

1

auto[1]

1833

1

T3

10

T14

3

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T15	1		T18	1		T101	1
auto[134217728:268435455]	88	1			T3	1		T38	1		T101	1
auto[268435456:402653183]	110	1			T101	1		T66	1		T126	1
auto[402653184:536870911]	108	1			T3	1		T18	1		T35	1
auto[536870912:671088639]	104	1			T3	1		T14	1		T44	1
auto[671088640:805306367]	110	1			T14	1		T23	2		T65	1
auto[805306368:939524095]	110	1			T15	1		T82	1		T129	1
auto[939524096:1073741823]	107	1			T3	1		T15	1		T23	1
auto[1073741824:1207959551]	125	1			T14	1		T18	1		T44	1
auto[1207959552:1342177279]	99	1			T3	1		T14	1		T23	1
auto[1342177280:1476395007]	113	1			T88	1		T45	1		T53	2
auto[1476395008:1610612735]	110	1			T3	3		T44	1		T88	1
auto[1610612736:1744830463]	106	1			T35	1		T131	1		T46	1
auto[1744830464:1879048191]	108	1			T48	1		T52	2		T57	2
auto[1879048192:2013265919]	111	1			T18	1		T129	1		T66	1
auto[2013265920:2147483647]	98	1			T38	1		T30	1		T66	1
auto[2147483648:2281701375]	104	1			T3	1		T35	1		T88	1
auto[2281701376:2415919103]	112	1			T3	2		T18	1		T88	1
auto[2415919104:2550136831]	116	1			T44	1		T65	1		T48	1
auto[2550136832:2684354559]	122	1			T3	2		T101	1		T66	2
auto[2684354560:2818572287]	105	1			T3	1		T14	1		T65	1
auto[2818572288:2952790015]	100	1			T66	1		T46	1		T262	1
auto[2952790016:3087007743]	114	1			T18	1		T38	1		T26	1
auto[3087007744:3221225471]	115	1			T18	1		T48	1		T66	3
auto[3221225472:3355443199]	126	1			T30	1		T26	1		T262	1
auto[3355443200:3489660927]	111	1			T3	1		T14	1		T129	1
auto[3489660928:3623878655]	102	1			T3	3		T15	1		T18	1
auto[3623878656:3758096383]	114	1			T3	1		T35	1		T44	1
auto[3758096384:3892314111]	107	1			T3	1		T44	1		T128	1
auto[3892314112:4026531839]	123	1			T3	1		T131	1		T66	2
auto[4026531840:4160749567]	100	1			T48	1		T129	1		T47	1
auto[4160749568:4294967295]	115	1			T3	1		T35	1		T51	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T18	1		T101	1		T66	1
auto[0:134217727]	auto[1]	59	1			T15	1		T66	1		T72	2
auto[134217728:268435455]	auto[0]	49	1			T3	1		T38	1		T101	1
auto[134217728:268435455]	auto[1]	39	1			T57	1		T133	1		T121	1
auto[268435456:402653183]	auto[0]	50	1			T101	1		T126	1		T262	1
auto[268435456:402653183]	auto[1]	60	1			T66	1		T143	1		T405	1
auto[402653184:536870911]	auto[0]	49	1			T35	1		T45	1		T211	1
auto[402653184:536870911]	auto[1]	59	1			T3	1		T18	1		T51	1
auto[536870912:671088639]	auto[0]	38	1			T14	1		T38	1		T88	1
auto[536870912:671088639]	auto[1]	66	1			T3	1		T44	1		T106	1
auto[671088640:805306367]	auto[0]	49	1			T14	1		T65	1		T52	1
auto[671088640:805306367]	auto[1]	61	1			T23	2		T26	1		T66	1
auto[805306368:939524095]	auto[0]	62	1			T15	1		T129	1		T88	1
auto[805306368:939524095]	auto[1]	48	1			T82	1		T53	1		T72	1
auto[939524096:1073741823]	auto[0]	54	1			T23	1		T38	1		T101	1
auto[939524096:1073741823]	auto[1]	53	1			T3	1		T15	1		T101	1
auto[1073741824:1207959551]	auto[0]	58	1			T14	1		T47	1		T46	1
auto[1073741824:1207959551]	auto[1]	67	1			T18	1		T44	1		T52	2
auto[1207959552:1342177279]	auto[0]	46	1			T23	1		T101	1		T202	1
auto[1207959552:1342177279]	auto[1]	53	1			T3	1		T14	1		T131	1
auto[1342177280:1476395007]	auto[0]	56	1			T88	1		T45	1		T53	1
auto[1342177280:1476395007]	auto[1]	57	1			T53	1		T72	1		T261	1
auto[1476395008:1610612735]	auto[0]	58	1			T3	3		T44	1		T88	1
auto[1476395008:1610612735]	auto[1]	52	1			T26	1		T142	1		T285	1
auto[1610612736:1744830463]	auto[0]	48	1			T46	1		T262	1		T201	1
auto[1610612736:1744830463]	auto[1]	58	1			T35	1		T131	1		T53	1
auto[1744830464:1879048191]	auto[0]	55	1			T48	1		T52	1		T54	1
auto[1744830464:1879048191]	auto[1]	53	1			T52	1		T57	2		T72	2
auto[1879048192:2013265919]	auto[0]	63	1			T129	1		T66	1		T53	2
auto[1879048192:2013265919]	auto[1]	48	1			T18	1		T45	1		T71	1
auto[2013265920:2147483647]	auto[0]	48	1			T38	1		T203	1		T72	1
auto[2013265920:2147483647]	auto[1]	50	1			T30	1		T66	1		T53	1
auto[2147483648:2281701375]	auto[0]	39	1			T3	1		T35	1		T88	1
auto[2147483648:2281701375]	auto[1]	65	1			T66	3		T47	1		T235	1
auto[2281701376:2415919103]	auto[0]	52	1			T18	1		T88	1		T66	1
auto[2281701376:2415919103]	auto[1]	60	1			T3	2		T57	1		T53	1
auto[2415919104:2550136831]	auto[0]	58	1			T44	1		T65	1		T48	1
auto[2415919104:2550136831]	auto[1]	58	1			T26	1		T66	1		T46	1
auto[2550136832:2684354559]	auto[0]	55	1			T3	2		T101	1		T45	1
auto[2550136832:2684354559]	auto[1]	67	1			T66	2		T236	1		T143	1
auto[2684354560:2818572287]	auto[0]	48	1			T3	1		T72	1		T287	1
auto[2684354560:2818572287]	auto[1]	57	1			T14	1		T65	1		T46	1
auto[2818572288:2952790015]	auto[0]	47	1			T66	1		T262	1		T202	1
auto[2818572288:2952790015]	auto[1]	53	1			T46	1		T121	3		T73	2
auto[2952790016:3087007743]	auto[0]	55	1			T38	1		T46	2		T211	1
auto[2952790016:3087007743]	auto[1]	59	1			T18	1		T26	1		T53	2
auto[3087007744:3221225471]	auto[0]	57	1			T18	1		T48	1		T66	2
auto[3087007744:3221225471]	auto[1]	58	1			T66	1		T52	1		T72	2
auto[3221225472:3355443199]	auto[0]	63	1			T26	1		T262	1		T71	1
auto[3221225472:3355443199]	auto[1]	63	1			T30	1		T72	1		T106	1
auto[3355443200:3489660927]	auto[0]	61	1			T3	1		T129	1		T211	1
auto[3355443200:3489660927]	auto[1]	50	1			T14	1		T26	1		T54	1
auto[3489660928:3623878655]	auto[0]	47	1			T38	1		T88	1		T52	1
auto[3489660928:3623878655]	auto[1]	55	1			T3	3		T15	1		T18	1
auto[3623878656:3758096383]	auto[0]	55	1			T3	1		T35	1		T44	1
auto[3623878656:3758096383]	auto[1]	59	1			T45	1		T28	1		T120	1
auto[3758096384:3892314111]	auto[0]	47	1			T44	1		T128	1		T88	2
auto[3758096384:3892314111]	auto[1]	60	1			T3	1		T26	1		T66	1
auto[3892314112:4026531839]	auto[0]	56	1			T3	1		T131	1		T66	1
auto[3892314112:4026531839]	auto[1]	67	1			T66	1		T53	1		T201	1
auto[4026531840:4160749567]	auto[0]	50	1			T48	1		T46	1		T211	1
auto[4026531840:4160749567]	auto[1]	50	1			T129	1		T47	1		T27	1
auto[4160749568:4294967295]	auto[0]	46	1			T3	1		T35	1		T65	1
auto[4160749568:4294967295]	auto[1]	69	1			T51	1		T80	1		T88	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1641

1

T3

11

T14

3

T18

3

auto[1]

1858

1

T3

11

T14

3

T15

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	122	1			T3	1		T18	1		T44	1
auto[134217728:268435455]	98	1			T3	1		T101	1		T46	1
auto[268435456:402653183]	120	1			T35	2		T38	1		T101	1
auto[402653184:536870911]	110	1			T3	1		T18	1		T35	1
auto[536870912:671088639]	108	1			T3	1		T35	1		T88	1
auto[671088640:805306367]	103	1			T3	1		T129	1		T131	1
auto[805306368:939524095]	117	1			T3	1		T14	1		T35	1
auto[939524096:1073741823]	126	1			T3	2		T18	1		T88	1
auto[1073741824:1207959551]	132	1			T3	1		T51	1		T88	1
auto[1207959552:1342177279]	115	1			T14	2		T44	1		T26	1
auto[1342177280:1476395007]	132	1			T3	2		T15	1		T45	1
auto[1476395008:1610612735]	105	1			T3	1		T65	1		T38	1
auto[1610612736:1744830463]	119	1			T18	1		T23	1		T80	1
auto[1744830464:1879048191]	108	1			T3	1		T26	1		T52	1
auto[1879048192:2013265919]	107	1			T101	1		T66	1		T47	1
auto[2013265920:2147483647]	89	1			T3	2		T15	1		T65	1
auto[2147483648:2281701375]	113	1			T26	1		T66	1		T45	1
auto[2281701376:2415919103]	105	1			T18	1		T23	1		T101	1
auto[2415919104:2550136831]	106	1			T23	1		T44	1		T88	1
auto[2550136832:2684354559]	100	1			T18	1		T38	1		T66	1
auto[2684354560:2818572287]	106	1			T3	1		T18	1		T48	2
auto[2818572288:2952790015]	104	1			T3	1		T142	1		T143	1
auto[2952790016:3087007743]	105	1			T3	2		T14	1		T15	1
auto[3087007744:3221225471]	108	1			T3	1		T65	1		T66	1
auto[3221225472:3355443199]	95	1			T14	1		T38	1		T101	1
auto[3355443200:3489660927]	123	1			T44	1		T38	1		T48	1
auto[3489660928:3623878655]	103	1			T101	1		T88	1		T47	1
auto[3623878656:3758096383]	103	1			T82	1		T44	1		T38	1
auto[3758096384:3892314111]	105	1			T45	1		T126	1		T57	1
auto[3892314112:4026531839]	107	1			T3	1		T65	1		T30	1
auto[4026531840:4160749567]	101	1			T3	1		T14	1		T15	1
auto[4160749568:4294967295]	104	1			T26	1		T66	1		T46	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	62	1			T88	1		T262	1		T203	1
auto[0:134217727]	auto[1]	60	1			T3	1		T18	1		T44	1
auto[134217728:268435455]	auto[0]	40	1			T101	1		T46	1		T262	1
auto[134217728:268435455]	auto[1]	58	1			T3	1		T52	1		T57	1
auto[268435456:402653183]	auto[0]	62	1			T35	1		T38	1		T101	1
auto[268435456:402653183]	auto[1]	58	1			T35	1		T207	1		T66	1
auto[402653184:536870911]	auto[0]	53	1			T3	1		T18	1		T35	1
auto[402653184:536870911]	auto[1]	57	1			T23	1		T46	1		T132	1
auto[536870912:671088639]	auto[0]	50	1			T35	1		T88	1		T66	1
auto[536870912:671088639]	auto[1]	58	1			T3	1		T26	1		T66	2
auto[671088640:805306367]	auto[0]	51	1			T3	1		T131	1		T88	1
auto[671088640:805306367]	auto[1]	52	1			T129	1		T66	2		T59	3
auto[805306368:939524095]	auto[0]	54	1			T3	1		T35	1		T101	1
auto[805306368:939524095]	auto[1]	63	1			T14	1		T131	1		T52	1
auto[939524096:1073741823]	auto[0]	64	1			T3	2		T18	1		T88	1
auto[939524096:1073741823]	auto[1]	62	1			T30	1		T26	1		T66	3
auto[1073741824:1207959551]	auto[0]	66	1			T3	1		T88	1		T46	1
auto[1073741824:1207959551]	auto[1]	66	1			T51	1		T46	1		T71	1
auto[1207959552:1342177279]	auto[0]	48	1			T14	2		T44	1		T66	1
auto[1207959552:1342177279]	auto[1]	67	1			T26	1		T66	1		T53	1
auto[1342177280:1476395007]	auto[0]	71	1			T3	1		T47	1		T46	2
auto[1342177280:1476395007]	auto[1]	61	1			T3	1		T15	1		T45	1
auto[1476395008:1610612735]	auto[0]	43	1			T38	1		T129	1		T211	1
auto[1476395008:1610612735]	auto[1]	62	1			T3	1		T65	1		T66	1
auto[1610612736:1744830463]	auto[0]	46	1			T18	1		T80	1		T128	1
auto[1610612736:1744830463]	auto[1]	73	1			T23	1		T65	1		T53	1
auto[1744830464:1879048191]	auto[0]	37	1			T59	1		T85	1		T73	1
auto[1744830464:1879048191]	auto[1]	71	1			T3	1		T26	1		T52	1
auto[1879048192:2013265919]	auto[0]	47	1			T101	1		T47	1		T46	1
auto[1879048192:2013265919]	auto[1]	60	1			T66	1		T46	1		T53	2
auto[2013265920:2147483647]	auto[0]	40	1			T3	1		T65	1		T72	1
auto[2013265920:2147483647]	auto[1]	49	1			T3	1		T15	1		T27	1
auto[2147483648:2281701375]	auto[0]	46	1			T45	1		T46	1		T52	1
auto[2147483648:2281701375]	auto[1]	67	1			T26	1		T66	1		T52	1
auto[2281701376:2415919103]	auto[0]	55	1			T23	1		T101	1		T88	1
auto[2281701376:2415919103]	auto[1]	50	1			T18	1		T406	1		T235	1
auto[2415919104:2550136831]	auto[0]	52	1			T23	1		T88	1		T46	1
auto[2415919104:2550136831]	auto[1]	54	1			T44	1		T53	1		T236	1
auto[2550136832:2684354559]	auto[0]	53	1			T38	1		T71	2		T72	1
auto[2550136832:2684354559]	auto[1]	47	1			T18	1		T66	1		T9	1
auto[2684354560:2818572287]	auto[0]	52	1			T3	1		T48	2		T101	1
auto[2684354560:2818572287]	auto[1]	54	1			T18	1		T201	1		T143	1
auto[2818572288:2952790015]	auto[0]	47	1			T3	1		T142	1		T143	1
auto[2818572288:2952790015]	auto[1]	57	1			T147	1		T134	1		T242	1
auto[2952790016:3087007743]	auto[0]	57	1			T66	1		T45	1		T47	1
auto[2952790016:3087007743]	auto[1]	48	1			T3	2		T14	1		T15	1
auto[3087007744:3221225471]	auto[0]	54	1			T3	1		T65	1		T52	1
auto[3087007744:3221225471]	auto[1]	54	1			T66	1		T71	1		T389	1
auto[3221225472:3355443199]	auto[0]	50	1			T101	1		T46	1		T126	1
auto[3221225472:3355443199]	auto[1]	45	1			T14	1		T38	1		T133	1
auto[3355443200:3489660927]	auto[0]	56	1			T44	1		T38	1		T48	1
auto[3355443200:3489660927]	auto[1]	67	1			T66	1		T211	1		T27	1
auto[3489660928:3623878655]	auto[0]	50	1			T88	1		T126	1		T71	1
auto[3489660928:3623878655]	auto[1]	53	1			T101	1		T47	1		T53	2
auto[3623878656:3758096383]	auto[0]	54	1			T44	1		T38	1		T48	1
auto[3623878656:3758096383]	auto[1]	49	1			T82	1		T71	1		T59	2
auto[3758096384:3892314111]	auto[0]	46	1			T45	1		T126	1		T53	1
auto[3758096384:3892314111]	auto[1]	59	1			T57	1		T201	1		T142	1
auto[3892314112:4026531839]	auto[0]	46	1			T65	1		T66	2		T71	1
auto[3892314112:4026531839]	auto[1]	61	1			T3	1		T30	1		T66	1
auto[4026531840:4160749567]	auto[0]	45	1			T14	1		T129	1		T88	1
auto[4026531840:4160749567]	auto[1]	56	1			T3	1		T15	1		T18	1
auto[4160749568:4294967295]	auto[0]	44	1			T202	1		T203	1		T59	1
auto[4160749568:4294967295]	auto[1]	60	1			T26	1		T66	1		T46	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1621

1

T3

11

T14

3

T15

1

auto[1]

1878

1

T3

11

T14

3

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	131	1			T14	2		T65	1		T48	1
auto[134217728:268435455]	104	1			T3	2		T38	1		T26	1
auto[268435456:402653183]	113	1			T35	1		T23	1		T30	1
auto[402653184:536870911]	107	1			T3	1		T26	2		T66	1
auto[536870912:671088639]	105	1			T3	2		T38	1		T211	1
auto[671088640:805306367]	102	1			T3	1		T51	1		T129	1
auto[805306368:939524095]	116	1			T3	1		T15	1		T18	1
auto[939524096:1073741823]	104	1			T3	1		T88	1		T46	1
auto[1073741824:1207959551]	96	1			T3	1		T38	1		T48	1
auto[1207959552:1342177279]	107	1			T48	1		T66	1		T46	2
auto[1342177280:1476395007]	120	1			T3	1		T35	2		T44	1
auto[1476395008:1610612735]	102	1			T3	1		T66	1		T45	1
auto[1610612736:1744830463]	92	1			T18	1		T66	1		T262	1
auto[1744830464:1879048191]	112	1			T14	1		T82	1		T38	1
auto[1879048192:2013265919]	104	1			T15	2		T65	1		T46	1
auto[2013265920:2147483647]	118	1			T18	2		T23	2		T129	1
auto[2147483648:2281701375]	117	1			T35	1		T44	1		T129	1
auto[2281701376:2415919103]	106	1			T35	1		T65	1		T45	1
auto[2415919104:2550136831]	124	1			T3	1		T80	1		T101	2
auto[2550136832:2684354559]	107	1			T44	1		T88	1		T52	1
auto[2684354560:2818572287]	109	1			T46	2		T53	3		T201	1
auto[2818572288:2952790015]	121	1			T3	1		T14	1		T23	1
auto[2952790016:3087007743]	132	1			T44	1		T131	1		T88	1
auto[3087007744:3221225471]	116	1			T128	1		T66	1		T45	1
auto[3221225472:3355443199]	101	1			T18	2		T38	1		T66	1
auto[3355443200:3489660927]	107	1			T18	1		T44	1		T65	1
auto[3489660928:3623878655]	97	1			T3	3		T15	1		T51	1
auto[3623878656:3758096383]	108	1			T3	1		T14	1		T101	1
auto[3758096384:3892314111]	104	1			T3	2		T48	1		T47	1
auto[3892314112:4026531839]	125	1			T3	1		T18	1		T26	1
auto[4026531840:4160749567]	99	1			T3	1		T14	1		T44	1
auto[4160749568:4294967295]	93	1			T3	1		T65	1		T101	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	63	1			T48	1		T88	1		T211	1
auto[0:134217727]	auto[1]	68	1			T14	2		T65	1		T72	1
auto[134217728:268435455]	auto[0]	50	1			T3	1		T38	1		T52	1
auto[134217728:268435455]	auto[1]	54	1			T3	1		T26	1		T66	1
auto[268435456:402653183]	auto[0]	57	1			T35	1		T23	1		T66	1
auto[268435456:402653183]	auto[1]	56	1			T30	1		T66	1		T45	1
auto[402653184:536870911]	auto[0]	50	1			T3	1		T66	1		T52	1
auto[402653184:536870911]	auto[1]	57	1			T26	2		T9	1		T189	1
auto[536870912:671088639]	auto[0]	43	1			T3	2		T38	1		T211	1
auto[536870912:671088639]	auto[1]	62	1			T262	1		T53	1		T71	1
auto[671088640:805306367]	auto[0]	48	1			T129	1		T88	1		T52	1
auto[671088640:805306367]	auto[1]	54	1			T3	1		T51	1		T262	1
auto[805306368:939524095]	auto[0]	48	1			T15	1		T18	1		T101	1
auto[805306368:939524095]	auto[1]	68	1			T3	1		T131	1		T66	1
auto[939524096:1073741823]	auto[0]	53	1			T3	1		T88	1		T46	1
auto[939524096:1073741823]	auto[1]	51	1			T57	1		T236	1		T69	1
auto[1073741824:1207959551]	auto[0]	39	1			T3	1		T38	1		T48	1
auto[1073741824:1207959551]	auto[1]	57	1			T142	1		T72	1		T399	1
auto[1207959552:1342177279]	auto[0]	43	1			T48	1		T66	1		T46	1
auto[1207959552:1342177279]	auto[1]	64	1			T46	1		T262	1		T201	1
auto[1342177280:1476395007]	auto[0]	55	1			T35	2		T44	1		T26	1
auto[1342177280:1476395007]	auto[1]	65	1			T3	1		T30	1		T66	1
auto[1476395008:1610612735]	auto[0]	52	1			T45	1		T46	1		T202	1
auto[1476395008:1610612735]	auto[1]	50	1			T3	1		T66	1		T71	1
auto[1610612736:1744830463]	auto[0]	40	1			T59	2		T121	1		T189	1
auto[1610612736:1744830463]	auto[1]	52	1			T18	1		T66	1		T262	1
auto[1744830464:1879048191]	auto[0]	55	1			T14	1		T38	1		T101	2
auto[1744830464:1879048191]	auto[1]	57	1			T82	1		T26	1		T66	2
auto[1879048192:2013265919]	auto[0]	43	1			T126	1		T122	1		T76	1
auto[1879048192:2013265919]	auto[1]	61	1			T15	2		T65	1		T46	1
auto[2013265920:2147483647]	auto[0]	55	1			T18	1		T129	1		T59	1
auto[2013265920:2147483647]	auto[1]	63	1			T18	1		T23	2		T66	2
auto[2147483648:2281701375]	auto[0]	49	1			T35	1		T44	1		T66	2
auto[2147483648:2281701375]	auto[1]	68	1			T129	1		T207	1		T66	1
auto[2281701376:2415919103]	auto[0]	53	1			T35	1		T65	1		T45	1
auto[2281701376:2415919103]	auto[1]	53	1			T53	1		T285	1		T59	2
auto[2415919104:2550136831]	auto[0]	61	1			T101	2		T211	1		T53	2
auto[2415919104:2550136831]	auto[1]	63	1			T3	1		T80	1		T72	1
auto[2550136832:2684354559]	auto[0]	47	1			T44	1		T88	1		T201	1
auto[2550136832:2684354559]	auto[1]	60	1			T52	1		T57	1		T142	1
auto[2684354560:2818572287]	auto[0]	51	1			T46	2		T53	1		T59	1
auto[2684354560:2818572287]	auto[1]	58	1			T53	2		T201	1		T71	1
auto[2818572288:2952790015]	auto[0]	45	1			T88	1		T211	1		T71	1
auto[2818572288:2952790015]	auto[1]	76	1			T3	1		T14	1		T23	1
auto[2952790016:3087007743]	auto[0]	51	1			T44	1		T88	1		T66	1
auto[2952790016:3087007743]	auto[1]	81	1			T131	1		T66	1		T46	1
auto[3087007744:3221225471]	auto[0]	61	1			T128	1		T66	1		T46	1
auto[3087007744:3221225471]	auto[1]	55	1			T45	1		T52	1		T143	1
auto[3221225472:3355443199]	auto[0]	46	1			T18	1		T38	1		T52	1
auto[3221225472:3355443199]	auto[1]	55	1			T18	1		T66	1		T211	1
auto[3355443200:3489660927]	auto[0]	52	1			T65	1		T101	1		T88	1
auto[3355443200:3489660927]	auto[1]	55	1			T18	1		T44	1		T66	1
auto[3489660928:3623878655]	auto[0]	47	1			T3	2		T129	1		T131	1
auto[3489660928:3623878655]	auto[1]	50	1			T3	1		T15	1		T51	1
auto[3623878656:3758096383]	auto[0]	57	1			T14	1		T126	1		T261	1
auto[3623878656:3758096383]	auto[1]	51	1			T3	1		T101	1		T26	1
auto[3758096384:3892314111]	auto[0]	47	1			T3	1		T48	1		T47	1
auto[3758096384:3892314111]	auto[1]	57	1			T3	1		T236	1		T133	1
auto[3892314112:4026531839]	auto[0]	58	1			T3	1		T26	1		T21	1
auto[3892314112:4026531839]	auto[1]	67	1			T18	1		T52	1		T53	1
auto[4026531840:4160749567]	auto[0]	57	1			T3	1		T14	1		T71	1
auto[4026531840:4160749567]	auto[1]	42	1			T44	1		T66	1		T106	1
auto[4160749568:4294967295]	auto[0]	45	1			T101	1		T88	1		T46	1
auto[4160749568:4294967295]	auto[1]	48	1			T3	1		T65	1		T46	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1639

1

T3

12

T14

3

T15

1

auto[1]

1860

1

T3

10

T14

3

T15

3