Unified Coverage Report :: Group Instance : attest_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1625

1

T3

12

T14

3

T15

1

auto[1]

1874

1

T3

10

T14

3

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T46	1		T9	1		T53	1
auto[134217728:268435455]	109	1			T14	1		T15	1		T207	1
auto[268435456:402653183]	106	1			T3	1		T65	1		T46	1
auto[402653184:536870911]	109	1			T66	3		T46	2		T57	1
auto[536870912:671088639]	92	1			T3	1		T14	1		T52	1
auto[671088640:805306367]	115	1			T3	2		T66	1		T211	2
auto[805306368:939524095]	91	1			T3	1		T44	1		T101	1
auto[939524096:1073741823]	120	1			T46	1		T52	1		T53	2
auto[1073741824:1207959551]	116	1			T3	2		T18	1		T48	1
auto[1207959552:1342177279]	133	1			T3	1		T18	2		T35	1
auto[1342177280:1476395007]	96	1			T15	1		T38	2		T131	1
auto[1476395008:1610612735]	100	1			T3	1		T23	1		T51	1
auto[1610612736:1744830463]	105	1			T38	2		T53	1		T202	1
auto[1744830464:1879048191]	105	1			T23	1		T48	1		T128	1
auto[1879048192:2013265919]	106	1			T3	1		T80	1		T44	1
auto[2013265920:2147483647]	112	1			T3	1		T38	1		T101	1
auto[2147483648:2281701375]	98	1			T14	1		T101	1		T88	1
auto[2281701376:2415919103]	112	1			T3	1		T18	1		T48	1
auto[2415919104:2550136831]	104	1			T15	2		T35	1		T23	1
auto[2550136832:2684354559]	111	1			T3	1		T44	1		T26	1
auto[2684354560:2818572287]	114	1			T3	2		T65	1		T66	2
auto[2818572288:2952790015]	108	1			T44	1		T131	1		T26	1
auto[2952790016:3087007743]	118	1			T3	1		T35	1		T26	1
auto[3087007744:3221225471]	121	1			T3	2		T18	1		T35	1
auto[3221225472:3355443199]	111	1			T14	1		T18	1		T65	1
auto[3355443200:3489660927]	100	1			T18	1		T38	1		T88	1
auto[3489660928:3623878655]	101	1			T51	1		T66	1		T46	1
auto[3623878656:3758096383]	117	1			T88	1		T30	1		T66	1
auto[3758096384:3892314111]	122	1			T3	1		T14	1		T101	1
auto[3892314112:4026531839]	111	1			T48	1		T129	1		T126	1
auto[4026531840:4160749567]	115	1			T3	2		T18	1		T35	1
auto[4160749568:4294967295]	114	1			T3	1		T14	1		T82	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T46	1		T71	2		T203	2
auto[0:134217727]	auto[1]	55	1			T9	1		T53	1		T71	1
auto[134217728:268435455]	auto[0]	49	1			T14	1		T126	1		T54	1
auto[134217728:268435455]	auto[1]	60	1			T15	1		T207	1		T26	1
auto[268435456:402653183]	auto[0]	50	1			T3	1		T65	1		T53	1
auto[268435456:402653183]	auto[1]	56	1			T46	1		T59	1		T235	1
auto[402653184:536870911]	auto[0]	55	1			T66	2		T46	1		T71	1
auto[402653184:536870911]	auto[1]	54	1			T66	1		T46	1		T57	1
auto[536870912:671088639]	auto[0]	38	1			T3	1		T52	1		T143	1
auto[536870912:671088639]	auto[1]	54	1			T14	1		T53	1		T261	1
auto[671088640:805306367]	auto[0]	52	1			T3	1		T211	2		T262	1
auto[671088640:805306367]	auto[1]	63	1			T3	1		T66	1		T72	2
auto[805306368:939524095]	auto[0]	39	1			T101	1		T88	1		T262	1
auto[805306368:939524095]	auto[1]	52	1			T3	1		T44	1		T129	1
auto[939524096:1073741823]	auto[0]	53	1			T46	1		T53	1		T54	1
auto[939524096:1073741823]	auto[1]	67	1			T52	1		T53	1		T201	2
auto[1073741824:1207959551]	auto[0]	54	1			T3	1		T48	1		T45	1
auto[1073741824:1207959551]	auto[1]	62	1			T3	1		T18	1		T66	1
auto[1207959552:1342177279]	auto[0]	68	1			T3	1		T18	1		T88	1
auto[1207959552:1342177279]	auto[1]	65	1			T18	1		T35	1		T23	1
auto[1342177280:1476395007]	auto[0]	57	1			T38	2		T131	1		T45	1
auto[1342177280:1476395007]	auto[1]	39	1			T15	1		T406	1		T59	1
auto[1476395008:1610612735]	auto[0]	47	1			T3	1		T66	1		T45	1
auto[1476395008:1610612735]	auto[1]	53	1			T23	1		T51	1		T72	4
auto[1610612736:1744830463]	auto[0]	52	1			T38	2		T202	1		T142	1
auto[1610612736:1744830463]	auto[1]	53	1			T53	1		T190	1		T192	1
auto[1744830464:1879048191]	auto[0]	46	1			T23	1		T48	1		T128	1
auto[1744830464:1879048191]	auto[1]	59	1			T202	1		T285	1		T120	1
auto[1879048192:2013265919]	auto[0]	47	1			T44	1		T65	1		T129	1
auto[1879048192:2013265919]	auto[1]	59	1			T3	1		T80	1		T66	2
auto[2013265920:2147483647]	auto[0]	57	1			T3	1		T38	1		T101	1
auto[2013265920:2147483647]	auto[1]	55	1			T47	1		T53	1		T59	1
auto[2147483648:2281701375]	auto[0]	50	1			T14	1		T101	1		T88	1
auto[2147483648:2281701375]	auto[1]	48	1			T45	1		T46	1		T72	2
auto[2281701376:2415919103]	auto[0]	43	1			T3	1		T48	1		T46	2
auto[2281701376:2415919103]	auto[1]	69	1			T18	1		T101	1		T66	2
auto[2415919104:2550136831]	auto[0]	58	1			T15	1		T35	1		T23	1
auto[2415919104:2550136831]	auto[1]	46	1			T15	1		T88	1		T26	1
auto[2550136832:2684354559]	auto[0]	55	1			T59	1		T87	1		T73	1
auto[2550136832:2684354559]	auto[1]	56	1			T3	1		T44	1		T26	1
auto[2684354560:2818572287]	auto[0]	53	1			T3	1		T66	1		T47	1
auto[2684354560:2818572287]	auto[1]	61	1			T3	1		T65	1		T66	1
auto[2818572288:2952790015]	auto[0]	44	1			T71	1		T59	1		T134	1
auto[2818572288:2952790015]	auto[1]	64	1			T44	1		T131	1		T26	1
auto[2952790016:3087007743]	auto[0]	36	1			T53	1		T72	1		T122	1
auto[2952790016:3087007743]	auto[1]	82	1			T3	1		T35	1		T26	1
auto[3087007744:3221225471]	auto[0]	56	1			T3	1		T35	1		T101	2
auto[3087007744:3221225471]	auto[1]	65	1			T3	1		T18	1		T26	1
auto[3221225472:3355443199]	auto[0]	53	1			T18	1		T88	1		T66	1
auto[3221225472:3355443199]	auto[1]	58	1			T14	1		T65	1		T47	1
auto[3355443200:3489660927]	auto[0]	45	1			T18	1		T38	1		T88	1
auto[3355443200:3489660927]	auto[1]	55	1			T53	1		T71	1		T285	1
auto[3489660928:3623878655]	auto[0]	42	1			T46	1		T201	1		T203	1
auto[3489660928:3623878655]	auto[1]	59	1			T51	1		T66	1		T52	2
auto[3623878656:3758096383]	auto[0]	51	1			T88	1		T30	1		T45	1
auto[3623878656:3758096383]	auto[1]	66	1			T66	1		T53	1		T72	1
auto[3758096384:3892314111]	auto[0]	53	1			T101	1		T71	1		T59	1
auto[3758096384:3892314111]	auto[1]	69	1			T3	1		T14	1		T52	1
auto[3892314112:4026531839]	auto[0]	53	1			T48	1		T129	1		T126	1
auto[3892314112:4026531839]	auto[1]	58	1			T71	1		T142	1		T72	1
auto[4026531840:4160749567]	auto[0]	63	1			T3	1		T18	1		T35	1
auto[4026531840:4160749567]	auto[1]	52	1			T3	1		T65	1		T30	1
auto[4160749568:4294967295]	auto[0]	54	1			T3	1		T14	1		T53	1
auto[4160749568:4294967295]	auto[1]	60	1			T82	1		T66	1		T47	1