Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7165

1

T3

32

T14

3

T15

8

auto[1]

313

1

T18

2

T143

8

T132

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3004	1			T3	12		T14	1		T15	4
auto[134217728:268435455]	176	1			T88	1		T26	2		T66	3
auto[268435456:402653183]	155	1			T3	1		T26	1		T66	1
auto[402653184:536870911]	145	1			T3	1		T18	2		T101	1
auto[536870912:671088639]	157	1			T35	1		T23	1		T38	1
auto[671088640:805306367]	175	1			T3	2		T80	1		T38	2
auto[805306368:939524095]	149	1			T3	1		T14	1		T15	1
auto[939524096:1073741823]	157	1			T101	1		T66	1		T57	1
auto[1073741824:1207959551]	150	1			T18	1		T35	1		T26	1
auto[1207959552:1342177279]	137	1			T18	1		T101	1		T129	1
auto[1342177280:1476395007]	142	1			T51	1		T48	1		T26	2
auto[1476395008:1610612735]	156	1			T3	1		T18	1		T23	1
auto[1610612736:1744830463]	129	1			T3	2		T18	1		T26	2
auto[1744830464:1879048191]	141	1			T3	1		T44	1		T101	1
auto[1879048192:2013265919]	139	1			T66	1		T52	2		T53	1
auto[2013265920:2147483647]	145	1			T3	2		T15	1		T129	1
auto[2147483648:2281701375]	131	1			T66	2		T143	1		T59	2
auto[2281701376:2415919103]	145	1			T18	1		T38	1		T88	1
auto[2415919104:2550136831]	146	1			T35	1		T38	1		T52	1
auto[2550136832:2684354559]	147	1			T3	1		T15	1		T65	1
auto[2684354560:2818572287]	139	1			T23	1		T101	1		T26	1
auto[2818572288:2952790015]	135	1			T131	2		T26	1		T47	1
auto[2952790016:3087007743]	128	1			T3	2		T18	2		T23	1
auto[3087007744:3221225471]	128	1			T35	1		T23	1		T101	1
auto[3221225472:3355443199]	131	1			T80	1		T48	1		T131	1
auto[3355443200:3489660927]	128	1			T3	1		T35	1		T101	1
auto[3489660928:3623878655]	139	1			T14	1		T15	1		T23	1
auto[3623878656:3758096383]	152	1			T3	1		T44	2		T129	1
auto[3758096384:3892314111]	134	1			T3	1		T66	1		T53	2
auto[3892314112:4026531839]	133	1			T3	1		T18	1		T35	1
auto[4026531840:4160749567]	170	1			T3	1		T38	3		T88	1
auto[4160749568:4294967295]	135	1			T3	1		T35	1		T88	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2996	1			T3	12		T14	1		T15	4
auto[0:134217727]	auto[1]	8	1			T237	1		T383	1		T274	1
auto[134217728:268435455]	auto[0]	167	1			T88	1		T26	2		T66	3
auto[134217728:268435455]	auto[1]	9	1			T143	1		T288	1		T325	1
auto[268435456:402653183]	auto[0]	145	1			T3	1		T26	1		T66	1
auto[268435456:402653183]	auto[1]	10	1			T238	1		T234	1		T404	1
auto[402653184:536870911]	auto[0]	140	1			T3	1		T18	2		T101	1
auto[402653184:536870911]	auto[1]	5	1			T132	1		T237	1		T349	1
auto[536870912:671088639]	auto[0]	150	1			T35	1		T23	1		T38	1
auto[536870912:671088639]	auto[1]	7	1			T143	1		T237	2		T288	1
auto[671088640:805306367]	auto[0]	160	1			T3	2		T80	1		T38	2
auto[671088640:805306367]	auto[1]	15	1			T143	1		T237	1		T234	1
auto[805306368:939524095]	auto[0]	138	1			T3	1		T14	1		T15	1
auto[805306368:939524095]	auto[1]	11	1			T133	1		T349	1		T403	2
auto[939524096:1073741823]	auto[0]	147	1			T101	1		T66	1		T57	1
auto[939524096:1073741823]	auto[1]	10	1			T237	1		T274	2		T403	1
auto[1073741824:1207959551]	auto[0]	141	1			T18	1		T35	1		T26	1
auto[1073741824:1207959551]	auto[1]	9	1			T331	1		T325	1		T386	1
auto[1207959552:1342177279]	auto[0]	128	1			T18	1		T101	1		T129	1
auto[1207959552:1342177279]	auto[1]	9	1			T143	1		T238	1		T260	1
auto[1342177280:1476395007]	auto[0]	133	1			T51	1		T48	1		T26	2
auto[1342177280:1476395007]	auto[1]	9	1			T288	1		T403	1		T385	1
auto[1476395008:1610612735]	auto[0]	146	1			T3	1		T23	1		T82	1
auto[1476395008:1610612735]	auto[1]	10	1			T18	1		T132	1		T237	2
auto[1610612736:1744830463]	auto[0]	125	1			T3	2		T18	1		T26	2
auto[1610612736:1744830463]	auto[1]	4	1			T238	1		T403	1		T296	1
auto[1744830464:1879048191]	auto[0]	134	1			T3	1		T44	1		T101	1
auto[1744830464:1879048191]	auto[1]	7	1			T238	1		T304	1		T361	2
auto[1879048192:2013265919]	auto[0]	131	1			T66	1		T52	2		T53	1
auto[1879048192:2013265919]	auto[1]	8	1			T132	1		T238	1		T260	1
auto[2013265920:2147483647]	auto[0]	137	1			T3	2		T15	1		T129	1
auto[2013265920:2147483647]	auto[1]	8	1			T237	1		T288	1		T408	1
auto[2147483648:2281701375]	auto[0]	122	1			T66	2		T59	2		T24	1
auto[2147483648:2281701375]	auto[1]	9	1			T143	1		T133	1		T237	1
auto[2281701376:2415919103]	auto[0]	127	1			T18	1		T38	1		T88	1
auto[2281701376:2415919103]	auto[1]	18	1			T143	1		T237	2		T325	1
auto[2415919104:2550136831]	auto[0]	138	1			T35	1		T38	1		T52	1
auto[2415919104:2550136831]	auto[1]	8	1			T238	1		T237	1		T234	1
auto[2550136832:2684354559]	auto[0]	139	1			T3	1		T15	1		T65	1
auto[2550136832:2684354559]	auto[1]	8	1			T132	1		T325	1		T409	1
auto[2684354560:2818572287]	auto[0]	126	1			T23	1		T101	1		T26	1
auto[2684354560:2818572287]	auto[1]	13	1			T238	2		T135	1		T237	1
auto[2818572288:2952790015]	auto[0]	121	1			T131	2		T26	1		T47	1
auto[2818572288:2952790015]	auto[1]	14	1			T325	1		T274	1		T388	2
auto[2952790016:3087007743]	auto[0]	120	1			T3	2		T18	1		T23	1
auto[2952790016:3087007743]	auto[1]	8	1			T18	1		T237	2		T288	1
auto[3087007744:3221225471]	auto[0]	117	1			T35	1		T23	1		T101	1
auto[3087007744:3221225471]	auto[1]	11	1			T143	1		T132	1		T238	1
auto[3221225472:3355443199]	auto[0]	121	1			T80	1		T48	1		T131	1
auto[3221225472:3355443199]	auto[1]	10	1			T260	2		T304	1		T410	1
auto[3355443200:3489660927]	auto[0]	118	1			T3	1		T35	1		T101	1
auto[3355443200:3489660927]	auto[1]	10	1			T234	1		T385	1		T411	1
auto[3489660928:3623878655]	auto[0]	129	1			T14	1		T15	1		T23	1
auto[3489660928:3623878655]	auto[1]	10	1			T237	2		T234	1		T260	1
auto[3623878656:3758096383]	auto[0]	140	1			T3	1		T44	2		T129	1
auto[3623878656:3758096383]	auto[1]	12	1			T260	1		T349	2		T385	1
auto[3758096384:3892314111]	auto[0]	122	1			T3	1		T66	1		T53	2
auto[3758096384:3892314111]	auto[1]	12	1			T238	2		T325	1		T260	1
auto[3892314112:4026531839]	auto[0]	122	1			T3	1		T18	1		T35	1
auto[3892314112:4026531839]	auto[1]	11	1			T143	1		T133	1		T383	1
auto[4026531840:4160749567]	auto[0]	158	1			T3	1		T38	3		T88	1
auto[4026531840:4160749567]	auto[1]	12	1			T260	2		T274	1		T282	1
auto[4160749568:4294967295]	auto[0]	127	1			T3	1		T35	1		T88	1
auto[4160749568:4294967295]	auto[1]	8	1			T133	2		T331	2		T282	1