Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4656

1

T3

36

T14

8

T15

6

auto[1]

2342

1

T3

8

T14

4

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	204	1			T18	2		T38	2		T48	2
auto[134217728:268435455]	258	1			T44	2		T38	2		T26	2
auto[268435456:402653183]	214	1			T3	6		T14	2		T48	2
auto[402653184:536870911]	218	1			T14	4		T38	4		T52	2
auto[536870912:671088639]	206	1			T35	2		T46	2		T126	4
auto[671088640:805306367]	194	1			T3	2		T26	4		T72	4
auto[805306368:939524095]	258	1			T66	2		T45	2		T53	2
auto[939524096:1073741823]	218	1			T3	2		T14	2		T38	2
auto[1073741824:1207959551]	190	1			T3	4		T35	2		T23	2
auto[1207959552:1342177279]	166	1			T129	2		T46	2		T59	2
auto[1342177280:1476395007]	202	1			T3	2		T44	2		T65	2
auto[1476395008:1610612735]	234	1			T3	2		T129	2		T66	2
auto[1610612736:1744830463]	216	1			T3	2		T88	2		T30	2
auto[1744830464:1879048191]	212	1			T3	2		T18	4		T131	2
auto[1879048192:2013265919]	216	1			T3	2		T23	2		T88	2
auto[2013265920:2147483647]	252	1			T3	2		T15	2		T65	2
auto[2147483648:2281701375]	228	1			T44	2		T38	2		T101	4
auto[2281701376:2415919103]	244	1			T51	2		T101	2		T66	6
auto[2415919104:2550136831]	260	1			T3	4		T15	2		T18	2
auto[2550136832:2684354559]	244	1			T3	2		T14	2		T35	2
auto[2684354560:2818572287]	224	1			T44	2		T30	2		T66	6
auto[2818572288:2952790015]	236	1			T18	2		T51	2		T48	2
auto[2952790016:3087007743]	206	1			T3	2		T15	2		T35	2
auto[3087007744:3221225471]	180	1			T88	2		T66	4		T262	2
auto[3221225472:3355443199]	230	1			T3	2		T15	2		T35	2
auto[3355443200:3489660927]	194	1			T82	2		T44	2		T88	2
auto[3489660928:3623878655]	222	1			T18	2		T101	4		T26	2
auto[3623878656:3758096383]	194	1			T3	4		T14	2		T44	2
auto[3758096384:3892314111]	198	1			T23	4		T52	2		T71	2
auto[3892314112:4026531839]	226	1			T88	2		T66	2		T46	2
auto[4026531840:4160749567]	206	1			T65	2		T88	2		T66	2
auto[4160749568:4294967295]	248	1			T3	4		T18	4		T80	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	128	1			T18	2		T101	2		T129	2
auto[0:134217727]	auto[1]	76	1			T38	2		T48	2		T21	2
auto[134217728:268435455]	auto[0]	178	1			T44	2		T26	2		T66	4
auto[134217728:268435455]	auto[1]	80	1			T38	2		T46	2		T53	2
auto[268435456:402653183]	auto[0]	138	1			T3	4		T14	2		T26	2
auto[268435456:402653183]	auto[1]	76	1			T3	2		T48	2		T101	2
auto[402653184:536870911]	auto[0]	126	1			T14	2		T52	2		T54	2
auto[402653184:536870911]	auto[1]	92	1			T14	2		T38	4		T53	2
auto[536870912:671088639]	auto[0]	126	1			T9	2		T53	2		T236	2
auto[536870912:671088639]	auto[1]	80	1			T35	2		T46	2		T126	4
auto[671088640:805306367]	auto[0]	136	1			T3	2		T26	2		T72	4
auto[671088640:805306367]	auto[1]	58	1			T26	2		T261	2		T59	2
auto[805306368:939524095]	auto[0]	180	1			T66	2		T45	2		T53	2
auto[805306368:939524095]	auto[1]	78	1			T201	2		T142	2		T59	2
auto[939524096:1073741823]	auto[0]	144	1			T14	2		T66	2		T46	2
auto[939524096:1073741823]	auto[1]	74	1			T3	2		T38	2		T48	2
auto[1073741824:1207959551]	auto[0]	122	1			T3	4		T23	2		T47	2
auto[1073741824:1207959551]	auto[1]	68	1			T35	2		T45	2		T46	2
auto[1207959552:1342177279]	auto[0]	110	1			T59	2		T238	2		T189	2
auto[1207959552:1342177279]	auto[1]	56	1			T129	2		T46	2		T120	2
auto[1342177280:1476395007]	auto[0]	132	1			T3	2		T65	2		T47	2
auto[1342177280:1476395007]	auto[1]	70	1			T44	2		T26	2		T142	2
auto[1476395008:1610612735]	auto[0]	162	1			T3	2		T129	2		T66	2
auto[1476395008:1610612735]	auto[1]	72	1			T202	2		T72	2		T261	2
auto[1610612736:1744830463]	auto[0]	134	1			T3	2		T88	2		T26	2
auto[1610612736:1744830463]	auto[1]	82	1			T30	2		T57	2		T121	2
auto[1744830464:1879048191]	auto[0]	146	1			T3	2		T18	2		T131	2
auto[1744830464:1879048191]	auto[1]	66	1			T18	2		T287	4		T134	2
auto[1879048192:2013265919]	auto[0]	160	1			T3	2		T88	2		T66	2
auto[1879048192:2013265919]	auto[1]	56	1			T23	2		T52	2		T53	2
auto[2013265920:2147483647]	auto[0]	184	1			T3	2		T15	2		T65	2
auto[2013265920:2147483647]	auto[1]	68	1			T128	2		T55	2		T120	2
auto[2147483648:2281701375]	auto[0]	150	1			T44	2		T101	2		T88	2
auto[2147483648:2281701375]	auto[1]	78	1			T38	2		T101	2		T66	2
auto[2281701376:2415919103]	auto[0]	172	1			T101	2		T66	4		T47	2
auto[2281701376:2415919103]	auto[1]	72	1			T51	2		T66	2		T126	2
auto[2415919104:2550136831]	auto[0]	174	1			T3	4		T15	2		T66	2
auto[2415919104:2550136831]	auto[1]	86	1			T18	2		T39	2		T143	2
auto[2550136832:2684354559]	auto[0]	168	1			T3	2		T14	2		T35	2
auto[2550136832:2684354559]	auto[1]	76	1			T46	2		T52	2		T53	2
auto[2684354560:2818572287]	auto[0]	140	1			T44	2		T30	2		T66	2
auto[2684354560:2818572287]	auto[1]	84	1			T66	4		T52	2		T71	2
auto[2818572288:2952790015]	auto[0]	150	1			T51	2		T66	2		T46	2
auto[2818572288:2952790015]	auto[1]	86	1			T18	2		T48	2		T131	2
auto[2952790016:3087007743]	auto[0]	128	1			T101	2		T24	2		T87	2
auto[2952790016:3087007743]	auto[1]	78	1			T3	2		T15	2		T35	2
auto[3087007744:3221225471]	auto[0]	132	1			T66	4		T262	2		T56	2
auto[3087007744:3221225471]	auto[1]	48	1			T88	2		T72	2		T192	2
auto[3221225472:3355443199]	auto[0]	150	1			T3	2		T15	2		T66	4
auto[3221225472:3355443199]	auto[1]	80	1			T35	2		T88	2		T201	2
auto[3355443200:3489660927]	auto[0]	120	1			T44	2		T88	2		T53	2
auto[3355443200:3489660927]	auto[1]	74	1			T82	2		T47	2		T89	2
auto[3489660928:3623878655]	auto[0]	146	1			T101	4		T26	2		T66	2
auto[3489660928:3623878655]	auto[1]	76	1			T18	2		T52	2		T57	2
auto[3623878656:3758096383]	auto[0]	112	1			T3	2		T44	2		T65	2
auto[3623878656:3758096383]	auto[1]	82	1			T3	2		T14	2		T46	4
auto[3758096384:3892314111]	auto[0]	140	1			T23	4		T52	2		T71	2
auto[3758096384:3892314111]	auto[1]	58	1			T72	2		T190	4		T122	2
auto[3892314112:4026531839]	auto[0]	158	1			T88	2		T66	2		T46	2
auto[3892314112:4026531839]	auto[1]	68	1			T72	2		T287	2		T6	2
auto[4026531840:4160749567]	auto[0]	134	1			T65	2		T88	2		T66	2
auto[4026531840:4160749567]	auto[1]	72	1			T142	2		T89	2		T399	2
auto[4160749568:4294967295]	auto[0]	176	1			T3	4		T18	4		T66	4
auto[4160749568:4294967295]	auto[1]	72	1			T80	2		T126	4		T53	4