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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.04 97.95 98.47 100.00 99.02 98.41 91.27


Total test records in report: 1084
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T1007 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2646523084 Aug 14 04:32:46 PM PDT 24 Aug 14 04:32:52 PM PDT 24 20148539 ps
T1008 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.522448556 Aug 14 04:32:45 PM PDT 24 Aug 14 04:32:46 PM PDT 24 86506597 ps
T1009 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.822185257 Aug 14 04:32:44 PM PDT 24 Aug 14 04:32:45 PM PDT 24 23243685 ps
T1010 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3982342925 Aug 14 04:33:07 PM PDT 24 Aug 14 04:33:08 PM PDT 24 45959436 ps
T1011 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3445121201 Aug 14 04:32:35 PM PDT 24 Aug 14 04:32:37 PM PDT 24 362358273 ps
T1012 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3353319727 Aug 14 04:32:37 PM PDT 24 Aug 14 04:32:38 PM PDT 24 115501411 ps
T1013 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3899911646 Aug 14 04:32:28 PM PDT 24 Aug 14 04:32:31 PM PDT 24 238509224 ps
T1014 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2714689947 Aug 14 04:32:46 PM PDT 24 Aug 14 04:32:52 PM PDT 24 285421565 ps
T1015 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.163344714 Aug 14 04:32:43 PM PDT 24 Aug 14 04:32:58 PM PDT 24 1572434397 ps
T1016 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3752330092 Aug 14 04:32:45 PM PDT 24 Aug 14 04:32:49 PM PDT 24 506154445 ps
T1017 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1913301496 Aug 14 04:32:47 PM PDT 24 Aug 14 04:32:49 PM PDT 24 74525149 ps
T1018 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.672822491 Aug 14 04:32:22 PM PDT 24 Aug 14 04:32:24 PM PDT 24 92125694 ps
T1019 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3966555842 Aug 14 04:32:55 PM PDT 24 Aug 14 04:32:57 PM PDT 24 37988346 ps
T1020 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1169846433 Aug 14 04:32:20 PM PDT 24 Aug 14 04:32:25 PM PDT 24 440892679 ps
T1021 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1840425312 Aug 14 04:32:53 PM PDT 24 Aug 14 04:32:58 PM PDT 24 225934048 ps
T1022 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.581779302 Aug 14 04:33:07 PM PDT 24 Aug 14 04:33:09 PM PDT 24 13910082 ps
T1023 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.405138156 Aug 14 04:32:50 PM PDT 24 Aug 14 04:32:51 PM PDT 24 14451920 ps
T1024 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1724562493 Aug 14 04:32:44 PM PDT 24 Aug 14 04:32:46 PM PDT 24 139909608 ps
T1025 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.806612055 Aug 14 04:32:48 PM PDT 24 Aug 14 04:32:54 PM PDT 24 724489216 ps
T1026 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.916567270 Aug 14 04:33:03 PM PDT 24 Aug 14 04:33:13 PM PDT 24 20317016 ps
T1027 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4095348920 Aug 14 04:32:36 PM PDT 24 Aug 14 04:32:42 PM PDT 24 449157061 ps
T161 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2463187276 Aug 14 04:32:32 PM PDT 24 Aug 14 04:32:39 PM PDT 24 320066029 ps
T169 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.721575901 Aug 14 04:32:58 PM PDT 24 Aug 14 04:33:02 PM PDT 24 419267157 ps
T1028 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3817992914 Aug 14 04:32:38 PM PDT 24 Aug 14 04:32:40 PM PDT 24 84857273 ps
T178 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1735662257 Aug 14 04:32:18 PM PDT 24 Aug 14 04:32:22 PM PDT 24 437772775 ps
T1029 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.414331070 Aug 14 04:32:33 PM PDT 24 Aug 14 04:32:34 PM PDT 24 30407962 ps
T1030 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.882483924 Aug 14 04:33:08 PM PDT 24 Aug 14 04:33:10 PM PDT 24 118768947 ps
T1031 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2640074651 Aug 14 04:32:31 PM PDT 24 Aug 14 04:32:32 PM PDT 24 86802440 ps
T1032 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1529811822 Aug 14 04:32:54 PM PDT 24 Aug 14 04:32:54 PM PDT 24 114069027 ps
T1033 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3017766582 Aug 14 04:32:41 PM PDT 24 Aug 14 04:32:46 PM PDT 24 547844262 ps
T1034 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2649392589 Aug 14 04:32:40 PM PDT 24 Aug 14 04:32:41 PM PDT 24 7649387 ps
T1035 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1695773256 Aug 14 04:32:45 PM PDT 24 Aug 14 04:32:46 PM PDT 24 111193904 ps
T1036 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.843541804 Aug 14 04:32:30 PM PDT 24 Aug 14 04:32:35 PM PDT 24 285735122 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3893054155 Aug 14 04:32:19 PM PDT 24 Aug 14 04:32:20 PM PDT 24 23189074 ps
T1038 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3805273252 Aug 14 04:32:46 PM PDT 24 Aug 14 04:32:47 PM PDT 24 265323448 ps
T1039 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1306748126 Aug 14 04:32:38 PM PDT 24 Aug 14 04:32:40 PM PDT 24 56050419 ps
T1040 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1702858863 Aug 14 04:32:49 PM PDT 24 Aug 14 04:32:54 PM PDT 24 183484220 ps
T1041 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2863338562 Aug 14 04:32:20 PM PDT 24 Aug 14 04:32:21 PM PDT 24 40363087 ps
T1042 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.104996304 Aug 14 04:32:42 PM PDT 24 Aug 14 04:32:47 PM PDT 24 154978686 ps
T1043 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.65309769 Aug 14 04:32:58 PM PDT 24 Aug 14 04:33:02 PM PDT 24 211291214 ps
T1044 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1289239068 Aug 14 04:32:38 PM PDT 24 Aug 14 04:32:41 PM PDT 24 161828661 ps
T1045 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.727478533 Aug 14 04:32:21 PM PDT 24 Aug 14 04:32:23 PM PDT 24 101689453 ps
T1046 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4161283164 Aug 14 04:32:26 PM PDT 24 Aug 14 04:32:29 PM PDT 24 115186713 ps
T1047 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1968119319 Aug 14 04:32:39 PM PDT 24 Aug 14 04:32:42 PM PDT 24 37540199 ps
T1048 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3821368236 Aug 14 04:33:00 PM PDT 24 Aug 14 04:33:01 PM PDT 24 80647349 ps
T1049 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.938556702 Aug 14 04:32:38 PM PDT 24 Aug 14 04:32:40 PM PDT 24 154676969 ps
T1050 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1557016781 Aug 14 04:32:53 PM PDT 24 Aug 14 04:32:54 PM PDT 24 27044689 ps
T1051 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3460993589 Aug 14 04:32:51 PM PDT 24 Aug 14 04:32:56 PM PDT 24 121795041 ps
T1052 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2164598558 Aug 14 04:32:49 PM PDT 24 Aug 14 04:32:57 PM PDT 24 247023234 ps
T1053 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.308060458 Aug 14 04:32:45 PM PDT 24 Aug 14 04:32:47 PM PDT 24 120666521 ps
T1054 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3615305172 Aug 14 04:32:51 PM PDT 24 Aug 14 04:32:52 PM PDT 24 10765791 ps
T1055 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3339405694 Aug 14 04:32:48 PM PDT 24 Aug 14 04:32:49 PM PDT 24 17781855 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.911349247 Aug 14 04:32:22 PM PDT 24 Aug 14 04:32:28 PM PDT 24 111246805 ps
T1057 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2223060274 Aug 14 04:33:07 PM PDT 24 Aug 14 04:33:08 PM PDT 24 10659176 ps
T1058 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2441776442 Aug 14 04:32:40 PM PDT 24 Aug 14 04:32:42 PM PDT 24 44232888 ps
T1059 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1682224398 Aug 14 04:33:01 PM PDT 24 Aug 14 04:33:02 PM PDT 24 79875372 ps
T1060 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3297516083 Aug 14 04:32:50 PM PDT 24 Aug 14 04:32:51 PM PDT 24 93043133 ps
T1061 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3697168523 Aug 14 04:32:39 PM PDT 24 Aug 14 04:32:40 PM PDT 24 26115832 ps
T1062 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.32004386 Aug 14 04:33:07 PM PDT 24 Aug 14 04:33:08 PM PDT 24 13410597 ps
T1063 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.638475097 Aug 14 04:32:42 PM PDT 24 Aug 14 04:32:43 PM PDT 24 48912683 ps
T1064 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2074996632 Aug 14 04:32:52 PM PDT 24 Aug 14 04:32:54 PM PDT 24 51930754 ps
T162 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3682720932 Aug 14 04:32:20 PM PDT 24 Aug 14 04:32:24 PM PDT 24 398146733 ps
T1065 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2402777931 Aug 14 04:32:43 PM PDT 24 Aug 14 04:32:46 PM PDT 24 228893656 ps
T1066 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1889922166 Aug 14 04:32:20 PM PDT 24 Aug 14 04:32:23 PM PDT 24 138167389 ps
T1067 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2924317880 Aug 14 04:32:31 PM PDT 24 Aug 14 04:32:40 PM PDT 24 646658451 ps
T1068 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.952012974 Aug 14 04:32:47 PM PDT 24 Aug 14 04:32:51 PM PDT 24 544188262 ps
T1069 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.38463632 Aug 14 04:32:44 PM PDT 24 Aug 14 04:32:47 PM PDT 24 378124806 ps
T1070 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1526672177 Aug 14 04:32:34 PM PDT 24 Aug 14 04:32:38 PM PDT 24 218440643 ps
T1071 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2691622512 Aug 14 04:32:17 PM PDT 24 Aug 14 04:32:19 PM PDT 24 29690384 ps
T163 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1630723948 Aug 14 04:32:31 PM PDT 24 Aug 14 04:32:38 PM PDT 24 3627719481 ps
T165 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3845913790 Aug 14 04:32:38 PM PDT 24 Aug 14 04:32:46 PM PDT 24 1990542606 ps
T1072 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4083214786 Aug 14 04:33:00 PM PDT 24 Aug 14 04:33:01 PM PDT 24 28193106 ps
T1073 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.92564831 Aug 14 04:32:45 PM PDT 24 Aug 14 04:32:49 PM PDT 24 139148662 ps
T1074 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.455862838 Aug 14 04:32:38 PM PDT 24 Aug 14 04:32:40 PM PDT 24 44195744 ps
T1075 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2471457113 Aug 14 04:32:50 PM PDT 24 Aug 14 04:32:51 PM PDT 24 26913523 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1201065418 Aug 14 04:32:30 PM PDT 24 Aug 14 04:32:32 PM PDT 24 35322710 ps
T1077 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.177677146 Aug 14 04:32:50 PM PDT 24 Aug 14 04:32:55 PM PDT 24 575212306 ps
T1078 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.28963957 Aug 14 04:32:32 PM PDT 24 Aug 14 04:32:40 PM PDT 24 333310612 ps
T1079 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3964503840 Aug 14 04:33:06 PM PDT 24 Aug 14 04:33:07 PM PDT 24 43044903 ps
T1080 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3521861564 Aug 14 04:32:39 PM PDT 24 Aug 14 04:32:45 PM PDT 24 154766280 ps
T1081 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.772094509 Aug 14 04:32:53 PM PDT 24 Aug 14 04:32:54 PM PDT 24 24085174 ps
T1082 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4004369361 Aug 14 04:32:43 PM PDT 24 Aug 14 04:32:44 PM PDT 24 57321403 ps
T1083 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3879826112 Aug 14 04:32:31 PM PDT 24 Aug 14 04:32:32 PM PDT 24 47631283 ps
T1084 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3126551469 Aug 14 04:32:37 PM PDT 24 Aug 14 04:32:43 PM PDT 24 676287527 ps

Test location /workspace/coverage/default/19.keymgr_stress_all.1138649233
Short name T3
Test name
Test status
Simulation time 435262450 ps
CPU time 17.64 seconds
Started Aug 14 04:41:19 PM PDT 24
Finished Aug 14 04:41:37 PM PDT 24
Peak memory 220364 kb
Host smart-580f57f7-b850-4519-b615-f3dbc2924fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138649233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1138649233
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.195927852
Short name T59
Test name
Test status
Simulation time 2131210213 ps
CPU time 41.02 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:42:11 PM PDT 24
Peak memory 222992 kb
Host smart-cf62e9ff-6fb7-4064-8b61-92a1c63a4133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195927852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.195927852
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.830296852
Short name T74
Test name
Test status
Simulation time 3464839782 ps
CPU time 24.22 seconds
Started Aug 14 04:42:00 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 222304 kb
Host smart-b4e9865c-c0d2-4968-a7c8-37abc3a091dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830296852 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.830296852
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2130657205
Short name T11
Test name
Test status
Simulation time 530739197 ps
CPU time 12.84 seconds
Started Aug 14 04:40:33 PM PDT 24
Finished Aug 14 04:40:46 PM PDT 24
Peak memory 238072 kb
Host smart-d5702c86-671f-4883-9030-c795ab1480ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130657205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2130657205
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2103069444
Short name T18
Test name
Test status
Simulation time 1005975035 ps
CPU time 7.85 seconds
Started Aug 14 04:41:17 PM PDT 24
Finished Aug 14 04:41:25 PM PDT 24
Peak memory 215864 kb
Host smart-0117cb4e-7519-4669-a0e5-747d13a257e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103069444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2103069444
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3339198433
Short name T46
Test name
Test status
Simulation time 2379262705 ps
CPU time 13.71 seconds
Started Aug 14 04:42:10 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 220432 kb
Host smart-5ca67222-d854-4c5f-91c6-c192a5c1f609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339198433 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3339198433
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2802025370
Short name T53
Test name
Test status
Simulation time 2590627604 ps
CPU time 26.06 seconds
Started Aug 14 04:41:06 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 216332 kb
Host smart-3d8a49a2-34ac-4fe1-b04c-be54f85585ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802025370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2802025370
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.711230886
Short name T88
Test name
Test status
Simulation time 244518272 ps
CPU time 3.86 seconds
Started Aug 14 04:42:12 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 222912 kb
Host smart-fe73e2b3-b705-41ea-b558-93a5060065f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711230886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.711230886
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1384873720
Short name T9
Test name
Test status
Simulation time 88144459 ps
CPU time 3.32 seconds
Started Aug 14 04:40:53 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 223172 kb
Host smart-215521f8-5c4c-41f0-b8b8-0363f7b61545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384873720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1384873720
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1887236266
Short name T110
Test name
Test status
Simulation time 356219535 ps
CPU time 7.83 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:41 PM PDT 24
Peak memory 220940 kb
Host smart-e33c88df-1911-4db8-8d97-d352bfb6f0bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887236266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1887236266
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2777783927
Short name T7
Test name
Test status
Simulation time 4285567465 ps
CPU time 51.08 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:43:09 PM PDT 24
Peak memory 221864 kb
Host smart-97e3292d-1104-4c2c-9334-766472796275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777783927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2777783927
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.997566509
Short name T237
Test name
Test status
Simulation time 281842567 ps
CPU time 13.31 seconds
Started Aug 14 04:41:31 PM PDT 24
Finished Aug 14 04:41:44 PM PDT 24
Peak memory 215352 kb
Host smart-32993ad3-ce69-4895-9335-a88ac49bb5ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997566509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.997566509
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.698123107
Short name T66
Test name
Test status
Simulation time 397090130 ps
CPU time 25.88 seconds
Started Aug 14 04:42:49 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 223032 kb
Host smart-7c5054f7-5319-49ba-80c5-e605c09d16ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698123107 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.698123107
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1981911260
Short name T238
Test name
Test status
Simulation time 1780179192 ps
CPU time 14.21 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 215848 kb
Host smart-9a5301cc-cb0d-4bd1-893a-36e68e907c9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1981911260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1981911260
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1335985244
Short name T76
Test name
Test status
Simulation time 2054036584 ps
CPU time 38.43 seconds
Started Aug 14 04:41:15 PM PDT 24
Finished Aug 14 04:41:53 PM PDT 24
Peak memory 216044 kb
Host smart-673a304f-6a4c-4ad7-8008-c003b1212120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335985244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1335985244
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1742383258
Short name T274
Test name
Test status
Simulation time 1120116670 ps
CPU time 9.3 seconds
Started Aug 14 04:40:52 PM PDT 24
Finished Aug 14 04:41:01 PM PDT 24
Peak memory 215696 kb
Host smart-869d6e9f-b317-46b1-81ab-7e13b1f2ad76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742383258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1742383258
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2182214788
Short name T91
Test name
Test status
Simulation time 225501123 ps
CPU time 5.05 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 209756 kb
Host smart-a8281704-549d-4679-91d8-bae0ea2a909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182214788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2182214788
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2261861279
Short name T385
Test name
Test status
Simulation time 301403003 ps
CPU time 6.33 seconds
Started Aug 14 04:42:09 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 216204 kb
Host smart-89c3d306-38be-44a3-9744-a81116b6e9eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261861279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2261861279
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.177323672
Short name T36
Test name
Test status
Simulation time 473772809 ps
CPU time 7.21 seconds
Started Aug 14 04:41:34 PM PDT 24
Finished Aug 14 04:41:41 PM PDT 24
Peak memory 211496 kb
Host smart-fbac7a91-9bc5-46c9-b1b7-fdbbbf6b7103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177323672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.177323672
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4209809685
Short name T134
Test name
Test status
Simulation time 1590583523 ps
CPU time 33.51 seconds
Started Aug 14 04:41:20 PM PDT 24
Finished Aug 14 04:41:53 PM PDT 24
Peak memory 220768 kb
Host smart-c8dd460d-c4b0-4089-b4cc-aab0bb3b056d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209809685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4209809685
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3460789387
Short name T260
Test name
Test status
Simulation time 936379378 ps
CPU time 13.23 seconds
Started Aug 14 04:41:51 PM PDT 24
Finished Aug 14 04:42:05 PM PDT 24
Peak memory 214836 kb
Host smart-1ca59761-9e16-48ea-b30d-81dc1d18f228
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460789387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3460789387
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.29886486
Short name T19
Test name
Test status
Simulation time 153346669 ps
CPU time 2.45 seconds
Started Aug 14 04:40:37 PM PDT 24
Finished Aug 14 04:40:40 PM PDT 24
Peak memory 215732 kb
Host smart-b88d3aad-db82-4faf-ab5d-62d35333b038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29886486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.29886486
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3652404631
Short name T25
Test name
Test status
Simulation time 169250845 ps
CPU time 4.22 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 222956 kb
Host smart-c8d3407c-821f-4bbf-963f-f142f396b568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652404631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3652404631
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2369365700
Short name T39
Test name
Test status
Simulation time 1103512010 ps
CPU time 11.52 seconds
Started Aug 14 04:41:39 PM PDT 24
Finished Aug 14 04:41:51 PM PDT 24
Peak memory 210580 kb
Host smart-622ea9ff-9717-424a-946b-2ea7ded5ca14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369365700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2369365700
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.668117609
Short name T229
Test name
Test status
Simulation time 1298675256 ps
CPU time 51.08 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:42:08 PM PDT 24
Peak memory 216868 kb
Host smart-45ca494c-e9d8-460d-9bda-3df6bdab0121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668117609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.668117609
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.98255521
Short name T981
Test name
Test status
Simulation time 171629626 ps
CPU time 6.77 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:38 PM PDT 24
Peak memory 214772 kb
Host smart-26bba7b4-8eeb-4823-a913-9e5f7da24433
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98255521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke
ymgr_shadow_reg_errors_with_csr_rw.98255521
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3038174247
Short name T288
Test name
Test status
Simulation time 1988500298 ps
CPU time 27.85 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:31 PM PDT 24
Peak memory 222956 kb
Host smart-c9be202a-b89f-4352-a0d4-79633047703d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3038174247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3038174247
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3906797952
Short name T144
Test name
Test status
Simulation time 227366052 ps
CPU time 2.17 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:05 PM PDT 24
Peak memory 218228 kb
Host smart-77d508c5-d199-44da-a664-cf1dd3045416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906797952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3906797952
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.435665892
Short name T31
Test name
Test status
Simulation time 422050046 ps
CPU time 4.86 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:41:57 PM PDT 24
Peak memory 214692 kb
Host smart-95319c9a-b7d0-41ea-972d-68d270136830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435665892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.435665892
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2161090807
Short name T90
Test name
Test status
Simulation time 54375074 ps
CPU time 2.39 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 209800 kb
Host smart-d5495dc9-087e-4aee-9c52-d20cc95f0add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161090807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2161090807
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2221684220
Short name T61
Test name
Test status
Simulation time 3070370740 ps
CPU time 31.14 seconds
Started Aug 14 04:41:00 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 222880 kb
Host smart-f9232d44-50c1-4474-84c8-a92fb29192c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221684220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2221684220
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2154433164
Short name T101
Test name
Test status
Simulation time 223838263 ps
CPU time 2.72 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 222980 kb
Host smart-ed93b1b0-00ef-4f0f-8ac3-6f36ec81d383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154433164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2154433164
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.118712531
Short name T331
Test name
Test status
Simulation time 1786847839 ps
CPU time 39.56 seconds
Started Aug 14 04:41:17 PM PDT 24
Finished Aug 14 04:41:57 PM PDT 24
Peak memory 215036 kb
Host smart-fa7ca28e-5f85-4f57-8717-414c76b6b231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118712531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.118712531
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3150739969
Short name T213
Test name
Test status
Simulation time 3563493772 ps
CPU time 45.49 seconds
Started Aug 14 04:41:55 PM PDT 24
Finished Aug 14 04:42:40 PM PDT 24
Peak memory 222960 kb
Host smart-911a3bca-fa38-485e-a0dd-ae76bcf924e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150739969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3150739969
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4072942937
Short name T123
Test name
Test status
Simulation time 41700243 ps
CPU time 0.74 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:14 PM PDT 24
Peak memory 206304 kb
Host smart-2ac30ac9-bcf2-4e4b-b58a-684dd988a921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072942937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4072942937
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3428387195
Short name T52
Test name
Test status
Simulation time 1429242244 ps
CPU time 12.11 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:37 PM PDT 24
Peak memory 220460 kb
Host smart-ccf0924c-14af-43c3-a525-53e4e11d1ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428387195 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3428387195
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1508853150
Short name T154
Test name
Test status
Simulation time 146134109 ps
CPU time 4.78 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 214444 kb
Host smart-5b998473-9657-421f-808e-7812d1c4cc00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508853150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1508853150
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2860376701
Short name T413
Test name
Test status
Simulation time 11173956491 ps
CPU time 157.62 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:45:30 PM PDT 24
Peak memory 216384 kb
Host smart-7f4b3701-f48a-4c96-ae24-0f3345fbab01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2860376701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2860376701
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2926942990
Short name T808
Test name
Test status
Simulation time 389248235 ps
CPU time 4.07 seconds
Started Aug 14 04:40:59 PM PDT 24
Finished Aug 14 04:41:03 PM PDT 24
Peak memory 221856 kb
Host smart-25e4704a-3562-4d2d-ba07-1ccfb25127b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926942990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2926942990
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.333964059
Short name T133
Test name
Test status
Simulation time 46211681 ps
CPU time 3.37 seconds
Started Aug 14 04:41:37 PM PDT 24
Finished Aug 14 04:41:46 PM PDT 24
Peak memory 215980 kb
Host smart-50d74141-9ab5-4fe5-ae0a-8df2ce3d0a92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333964059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.333964059
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3883046070
Short name T216
Test name
Test status
Simulation time 562084486 ps
CPU time 28.03 seconds
Started Aug 14 04:40:43 PM PDT 24
Finished Aug 14 04:41:11 PM PDT 24
Peak memory 221900 kb
Host smart-1f555b1a-1f47-4f20-b63d-7d8e6d3601de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883046070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3883046070
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3078049533
Short name T158
Test name
Test status
Simulation time 360786598 ps
CPU time 4.43 seconds
Started Aug 14 04:32:55 PM PDT 24
Finished Aug 14 04:33:00 PM PDT 24
Peak memory 214484 kb
Host smart-cf6e1e86-9f76-43b4-b6fc-799d9f770358
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078049533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3078049533
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3403841304
Short name T50
Test name
Test status
Simulation time 1883398863 ps
CPU time 19.14 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:45 PM PDT 24
Peak memory 223088 kb
Host smart-90bc7d91-7fec-4ef5-b71d-266810782f7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403841304 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3403841304
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.4121206751
Short name T23
Test name
Test status
Simulation time 712189616 ps
CPU time 6.06 seconds
Started Aug 14 04:41:50 PM PDT 24
Finished Aug 14 04:41:56 PM PDT 24
Peak memory 222884 kb
Host smart-fd324fc5-c4c1-46dd-ba82-f0de8b98bf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121206751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.4121206751
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1367591817
Short name T62
Test name
Test status
Simulation time 862786285 ps
CPU time 3.14 seconds
Started Aug 14 04:41:23 PM PDT 24
Finished Aug 14 04:41:26 PM PDT 24
Peak memory 210912 kb
Host smart-ab153114-52f5-4ba5-b509-e44fc9e8ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367591817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1367591817
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3758160199
Short name T226
Test name
Test status
Simulation time 709216949 ps
CPU time 30.76 seconds
Started Aug 14 04:40:46 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 217468 kb
Host smart-dcc9e454-1978-44e7-9789-0d6eca73ec4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758160199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3758160199
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2286107971
Short name T252
Test name
Test status
Simulation time 471103888 ps
CPU time 10.36 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:36 PM PDT 24
Peak memory 222888 kb
Host smart-6c0f98b4-13e8-4670-9912-87bbcfab1a54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286107971 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2286107971
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2115853305
Short name T321
Test name
Test status
Simulation time 68348689 ps
CPU time 4.4 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 215956 kb
Host smart-92f5845e-c884-4457-8b35-1ac735920f82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115853305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2115853305
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3069642933
Short name T85
Test name
Test status
Simulation time 136362058 ps
CPU time 2.57 seconds
Started Aug 14 04:42:14 PM PDT 24
Finished Aug 14 04:42:17 PM PDT 24
Peak memory 214784 kb
Host smart-68eca8d3-f3e3-4e8b-8fad-c64d7560c674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069642933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3069642933
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2832142799
Short name T48
Test name
Test status
Simulation time 70686089 ps
CPU time 2.81 seconds
Started Aug 14 04:42:38 PM PDT 24
Finished Aug 14 04:42:40 PM PDT 24
Peak memory 214800 kb
Host smart-91c6a37b-d007-4967-b8a6-b7c1f2834df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832142799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2832142799
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2700427446
Short name T150
Test name
Test status
Simulation time 88494409 ps
CPU time 2.99 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 218836 kb
Host smart-946c2eeb-7cea-47ce-a33b-a23a661cc94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700427446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2700427446
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1378560254
Short name T145
Test name
Test status
Simulation time 150496207 ps
CPU time 4.55 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:22 PM PDT 24
Peak memory 218800 kb
Host smart-e5926ebb-b051-4e18-ad2f-45dc80548ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378560254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1378560254
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.205483569
Short name T195
Test name
Test status
Simulation time 5858223833 ps
CPU time 45.3 seconds
Started Aug 14 04:41:31 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 222988 kb
Host smart-6bc0464d-8dc8-4098-8ae6-bd2374fa086a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205483569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.205483569
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4152544085
Short name T71
Test name
Test status
Simulation time 63073611289 ps
CPU time 370.79 seconds
Started Aug 14 04:42:10 PM PDT 24
Finished Aug 14 04:48:21 PM PDT 24
Peak memory 223012 kb
Host smart-1c2e0620-1143-4440-980d-97ba0c091a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152544085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4152544085
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4262819588
Short name T116
Test name
Test status
Simulation time 250871201 ps
CPU time 3.32 seconds
Started Aug 14 04:32:56 PM PDT 24
Finished Aug 14 04:32:59 PM PDT 24
Peak memory 214824 kb
Host smart-4e3cef98-bdc6-44c9-9f0a-b99e42da82d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262819588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4262819588
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3973973147
Short name T157
Test name
Test status
Simulation time 473725274 ps
CPU time 3.76 seconds
Started Aug 14 04:32:47 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 214448 kb
Host smart-e7dc7c1e-7c0f-41bd-a33f-935f6c0bfb5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973973147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3973973147
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1526672177
Short name T1070
Test name
Test status
Simulation time 218440643 ps
CPU time 4.18 seconds
Started Aug 14 04:32:34 PM PDT 24
Finished Aug 14 04:32:38 PM PDT 24
Peak memory 214460 kb
Host smart-f9c12deb-4a9d-4e2c-872c-7e2bf13cc896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526672177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1526672177
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2153891597
Short name T151
Test name
Test status
Simulation time 321871717 ps
CPU time 3.47 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:27 PM PDT 24
Peak memory 223048 kb
Host smart-9efa6c4d-b1a5-4aaa-88d9-5cfa86c44355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153891597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2153891597
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.4276900667
Short name T146
Test name
Test status
Simulation time 973913658 ps
CPU time 26.06 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:42:18 PM PDT 24
Peak memory 223092 kb
Host smart-3f8cf88f-1d26-49e4-a83a-a3295e1e447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276900667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.4276900667
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3591807173
Short name T300
Test name
Test status
Simulation time 1246197307 ps
CPU time 3.99 seconds
Started Aug 14 04:40:53 PM PDT 24
Finished Aug 14 04:40:57 PM PDT 24
Peak memory 222888 kb
Host smart-45c450f4-ce1d-456b-9fe3-9ce7397c5e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591807173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3591807173
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.671393607
Short name T222
Test name
Test status
Simulation time 7430039693 ps
CPU time 54.34 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:42:09 PM PDT 24
Peak memory 222840 kb
Host smart-f91f98dc-b54e-41ee-9bbd-c677dc3802f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671393607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.671393607
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2724199458
Short name T882
Test name
Test status
Simulation time 168596149 ps
CPU time 8.63 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:36 PM PDT 24
Peak memory 214792 kb
Host smart-99635587-87d3-4574-8500-e189f163c255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724199458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2724199458
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3812808469
Short name T282
Test name
Test status
Simulation time 380568035 ps
CPU time 5.8 seconds
Started Aug 14 04:41:41 PM PDT 24
Finished Aug 14 04:41:47 PM PDT 24
Peak memory 214932 kb
Host smart-a1bba67a-ef8e-4886-afa8-dc27742fa125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812808469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3812808469
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2669825148
Short name T695
Test name
Test status
Simulation time 135118067 ps
CPU time 5.34 seconds
Started Aug 14 04:42:04 PM PDT 24
Finished Aug 14 04:42:10 PM PDT 24
Peak memory 218672 kb
Host smart-054136e7-7b2b-4288-91ee-5cf7e214d9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669825148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2669825148
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.177243978
Short name T267
Test name
Test status
Simulation time 202042277 ps
CPU time 2.21 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 214704 kb
Host smart-ae784e1d-e4cf-4dfe-b19e-4237f5900a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177243978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.177243978
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1293810757
Short name T98
Test name
Test status
Simulation time 61032405 ps
CPU time 2.29 seconds
Started Aug 14 04:40:54 PM PDT 24
Finished Aug 14 04:40:57 PM PDT 24
Peak memory 209956 kb
Host smart-f8a75c1b-fe15-484f-a7aa-1112ba761120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293810757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1293810757
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1735662257
Short name T178
Test name
Test status
Simulation time 437772775 ps
CPU time 4.2 seconds
Started Aug 14 04:32:18 PM PDT 24
Finished Aug 14 04:32:22 PM PDT 24
Peak memory 214440 kb
Host smart-73580808-e62b-433f-bc82-09e719f8d368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735662257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1735662257
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2455575781
Short name T42
Test name
Test status
Simulation time 697996420 ps
CPU time 2.06 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:28 PM PDT 24
Peak memory 210436 kb
Host smart-a39003c0-8211-4b82-9e2e-9536464e413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455575781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2455575781
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4208648253
Short name T12
Test name
Test status
Simulation time 1059249884 ps
CPU time 9.04 seconds
Started Aug 14 04:40:50 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 238000 kb
Host smart-6d526e60-3a04-4eac-a45a-ef1b20e6abed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208648253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4208648253
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.213514832
Short name T149
Test name
Test status
Simulation time 103751634 ps
CPU time 4.69 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:27 PM PDT 24
Peak memory 218728 kb
Host smart-e4e50286-1ccc-40b9-94d7-4e78dccef72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213514832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.213514832
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2554983767
Short name T147
Test name
Test status
Simulation time 45969356 ps
CPU time 2.28 seconds
Started Aug 14 04:41:43 PM PDT 24
Finished Aug 14 04:41:46 PM PDT 24
Peak memory 222976 kb
Host smart-5f3a451e-abdb-47eb-8df8-3c556c96597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554983767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2554983767
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2637477261
Short name T410
Test name
Test status
Simulation time 65722525 ps
CPU time 4.46 seconds
Started Aug 14 04:41:00 PM PDT 24
Finished Aug 14 04:41:05 PM PDT 24
Peak memory 214856 kb
Host smart-0a1365e7-f6ce-4a7c-9e97-57868d125fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637477261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2637477261
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2842602308
Short name T795
Test name
Test status
Simulation time 36102497 ps
CPU time 2.74 seconds
Started Aug 14 04:41:47 PM PDT 24
Finished Aug 14 04:41:50 PM PDT 24
Peak memory 221424 kb
Host smart-1954fd64-b806-4e0b-9c42-9e0768ca02fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842602308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2842602308
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3672440623
Short name T304
Test name
Test status
Simulation time 114978179 ps
CPU time 5.47 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:07 PM PDT 24
Peak memory 215708 kb
Host smart-78f7637c-c3e0-436a-83e4-678aaa7808bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672440623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3672440623
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2463187276
Short name T161
Test name
Test status
Simulation time 320066029 ps
CPU time 6.63 seconds
Started Aug 14 04:32:32 PM PDT 24
Finished Aug 14 04:32:39 PM PDT 24
Peak memory 214380 kb
Host smart-f9b709f3-21aa-41a1-9b31-9d677780c33b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463187276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2463187276
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1471948332
Short name T170
Test name
Test status
Simulation time 219448212 ps
CPU time 8.78 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 214448 kb
Host smart-566fc17f-a746-4da8-bd15-c7de73f83475
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471948332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1471948332
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3329264102
Short name T160
Test name
Test status
Simulation time 124596395 ps
CPU time 2.55 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:43 PM PDT 24
Peak memory 214312 kb
Host smart-cd554d07-41a5-4474-8107-c248eaceaf90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329264102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3329264102
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.646246645
Short name T153
Test name
Test status
Simulation time 229383768 ps
CPU time 7.21 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:38 PM PDT 24
Peak memory 206260 kb
Host smart-aa74d2a6-d5b0-4761-b2dc-8383739513da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646246645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
646246645
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2116620496
Short name T13
Test name
Test status
Simulation time 1007684615 ps
CPU time 22.49 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:36 PM PDT 24
Peak memory 232100 kb
Host smart-d14b7c27-3c86-4791-9f70-dd32c914b7db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116620496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2116620496
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3685760924
Short name T159
Test name
Test status
Simulation time 58522823 ps
CPU time 2.81 seconds
Started Aug 14 04:40:39 PM PDT 24
Finished Aug 14 04:40:42 PM PDT 24
Peak memory 210912 kb
Host smart-a6bfa127-7637-48a3-950c-3fc83eb27903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685760924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3685760924
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3752544830
Short name T152
Test name
Test status
Simulation time 4979145636 ps
CPU time 23.03 seconds
Started Aug 14 04:41:22 PM PDT 24
Finished Aug 14 04:41:45 PM PDT 24
Peak memory 218680 kb
Host smart-9aa2b46c-f91a-428a-ba8d-3760feade49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752544830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3752544830
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.348433876
Short name T148
Test name
Test status
Simulation time 87058948 ps
CPU time 3.23 seconds
Started Aug 14 04:40:37 PM PDT 24
Finished Aug 14 04:40:41 PM PDT 24
Peak memory 223096 kb
Host smart-4ea6a8c1-34a2-429d-9b5c-a217ec5fd7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348433876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.348433876
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.707758124
Short name T265
Test name
Test status
Simulation time 147855376 ps
CPU time 5.34 seconds
Started Aug 14 04:41:11 PM PDT 24
Finished Aug 14 04:41:16 PM PDT 24
Peak memory 214808 kb
Host smart-bc291117-7f52-4d87-86db-33d7bb938a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707758124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.707758124
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2471498417
Short name T6
Test name
Test status
Simulation time 850846487 ps
CPU time 13.49 seconds
Started Aug 14 04:41:17 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 210248 kb
Host smart-9f773c1d-0d9b-445a-bf48-70e60be02d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471498417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2471498417
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.451068085
Short name T292
Test name
Test status
Simulation time 204895270 ps
CPU time 3.3 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:15 PM PDT 24
Peak memory 215500 kb
Host smart-d98d9c5a-b66d-4e19-a439-920f26c7faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451068085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.451068085
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1311159589
Short name T370
Test name
Test status
Simulation time 2368127573 ps
CPU time 24.25 seconds
Started Aug 14 04:40:58 PM PDT 24
Finished Aug 14 04:41:23 PM PDT 24
Peak memory 222096 kb
Host smart-1c57d39f-059d-45e8-9da2-56bbe4679b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311159589 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1311159589
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3034492678
Short name T350
Test name
Test status
Simulation time 2269868691 ps
CPU time 23.09 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:37 PM PDT 24
Peak memory 214812 kb
Host smart-964ffdca-9361-4df9-b1fb-7d9124cd90c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034492678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3034492678
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3577087415
Short name T353
Test name
Test status
Simulation time 144884979 ps
CPU time 1.77 seconds
Started Aug 14 04:41:11 PM PDT 24
Finished Aug 14 04:41:12 PM PDT 24
Peak memory 214664 kb
Host smart-0febf565-c06a-430c-ad9e-2dc0972865b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577087415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3577087415
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2081777667
Short name T175
Test name
Test status
Simulation time 222965656 ps
CPU time 2.07 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:16 PM PDT 24
Peak memory 210160 kb
Host smart-f9cd111a-bfb8-41a6-8dbd-654d16c9a121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081777667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2081777667
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.743275887
Short name T471
Test name
Test status
Simulation time 483268623 ps
CPU time 1.92 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 214752 kb
Host smart-84d62371-69c0-4868-a636-1712f86b54e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743275887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.743275887
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3675424941
Short name T233
Test name
Test status
Simulation time 356005326 ps
CPU time 5.87 seconds
Started Aug 14 04:40:38 PM PDT 24
Finished Aug 14 04:40:44 PM PDT 24
Peak memory 219328 kb
Host smart-cc25149b-4071-4f88-965b-4123022d3625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675424941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3675424941
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3114708477
Short name T338
Test name
Test status
Simulation time 48126793 ps
CPU time 1.63 seconds
Started Aug 14 04:41:20 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 214564 kb
Host smart-e6de9565-e772-47cc-a720-e95c42ea08f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114708477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3114708477
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3160045917
Short name T324
Test name
Test status
Simulation time 56971953 ps
CPU time 3.7 seconds
Started Aug 14 04:41:24 PM PDT 24
Finished Aug 14 04:41:27 PM PDT 24
Peak memory 214656 kb
Host smart-04a2b651-d3bc-4b8e-8055-05e01f2ffac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160045917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3160045917
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3565090455
Short name T414
Test name
Test status
Simulation time 770913245 ps
CPU time 10.57 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:42:03 PM PDT 24
Peak memory 214796 kb
Host smart-75433b78-e539-4c9c-a4ab-ff88fddc174e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565090455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3565090455
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2279317909
Short name T318
Test name
Test status
Simulation time 127294156 ps
CPU time 4.36 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 223012 kb
Host smart-fee36853-e6ca-488c-9532-df0d6c33aded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279317909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2279317909
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.909582001
Short name T360
Test name
Test status
Simulation time 44011053 ps
CPU time 3.13 seconds
Started Aug 14 04:41:53 PM PDT 24
Finished Aug 14 04:41:56 PM PDT 24
Peak memory 215044 kb
Host smart-ad2ff774-75f0-4f73-be2d-8fad54664d66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909582001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.909582001
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.634968564
Short name T234
Test name
Test status
Simulation time 252674852 ps
CPU time 12.95 seconds
Started Aug 14 04:40:31 PM PDT 24
Finished Aug 14 04:40:45 PM PDT 24
Peak memory 214912 kb
Host smart-c124c4c5-9a26-4cad-81a4-da76d6000366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634968564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.634968564
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.4044141947
Short name T8
Test name
Test status
Simulation time 1503342363 ps
CPU time 2.64 seconds
Started Aug 14 04:41:06 PM PDT 24
Finished Aug 14 04:41:09 PM PDT 24
Peak memory 214760 kb
Host smart-086eb870-c2ee-406f-a948-8853df57dbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044141947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.4044141947
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1169846433
Short name T1020
Test name
Test status
Simulation time 440892679 ps
CPU time 4.51 seconds
Started Aug 14 04:32:20 PM PDT 24
Finished Aug 14 04:32:25 PM PDT 24
Peak memory 206328 kb
Host smart-ae27fcd9-2b80-4e36-b896-52fb385926f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169846433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
169846433
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3403323706
Short name T920
Test name
Test status
Simulation time 2078271626 ps
CPU time 11.87 seconds
Started Aug 14 04:32:29 PM PDT 24
Finished Aug 14 04:32:41 PM PDT 24
Peak memory 206232 kb
Host smart-6d0afc26-016e-4dc9-9299-a60c61d6fbe2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403323706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
403323706
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.234108911
Short name T929
Test name
Test status
Simulation time 77098142 ps
CPU time 0.97 seconds
Started Aug 14 04:32:41 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 206096 kb
Host smart-2a03697f-272e-4df5-93df-73aca0165bd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234108911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.234108911
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.266186649
Short name T951
Test name
Test status
Simulation time 29462696 ps
CPU time 1.24 seconds
Started Aug 14 04:32:18 PM PDT 24
Finished Aug 14 04:32:19 PM PDT 24
Peak memory 206332 kb
Host smart-2bc149d4-3f6f-457d-88f7-9c74adac69fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266186649 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.266186649
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.414331070
Short name T1029
Test name
Test status
Simulation time 30407962 ps
CPU time 1.24 seconds
Started Aug 14 04:32:33 PM PDT 24
Finished Aug 14 04:32:34 PM PDT 24
Peak memory 206264 kb
Host smart-3fc5b984-bda2-477e-afe7-b0cfd7b39132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414331070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.414331070
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3353319727
Short name T1012
Test name
Test status
Simulation time 115501411 ps
CPU time 0.66 seconds
Started Aug 14 04:32:37 PM PDT 24
Finished Aug 14 04:32:38 PM PDT 24
Peak memory 205960 kb
Host smart-a68086e9-bbad-44e5-8d28-bebcb70d5783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353319727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3353319727
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1201065418
Short name T1076
Test name
Test status
Simulation time 35322710 ps
CPU time 2.02 seconds
Started Aug 14 04:32:30 PM PDT 24
Finished Aug 14 04:32:32 PM PDT 24
Peak memory 206328 kb
Host smart-3d66d02a-a4bf-43a4-9593-93e523d50665
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201065418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1201065418
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1889922166
Short name T1066
Test name
Test status
Simulation time 138167389 ps
CPU time 2.47 seconds
Started Aug 14 04:32:20 PM PDT 24
Finished Aug 14 04:32:23 PM PDT 24
Peak memory 214820 kb
Host smart-d0cdd27c-4078-44d2-bc62-316d06e8a6f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889922166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1889922166
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2171165714
Short name T113
Test name
Test status
Simulation time 396466458 ps
CPU time 5 seconds
Started Aug 14 04:32:23 PM PDT 24
Finished Aug 14 04:32:28 PM PDT 24
Peak memory 214808 kb
Host smart-5798d961-82a4-494c-945c-86cfaf090013
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171165714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2171165714
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.727478533
Short name T1045
Test name
Test status
Simulation time 101689453 ps
CPU time 2.33 seconds
Started Aug 14 04:32:21 PM PDT 24
Finished Aug 14 04:32:23 PM PDT 24
Peak memory 216704 kb
Host smart-40324619-ae84-41d3-a5c6-93880ca7f168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727478533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.727478533
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.208136221
Short name T985
Test name
Test status
Simulation time 1843385059 ps
CPU time 5.59 seconds
Started Aug 14 04:32:36 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 206496 kb
Host smart-ccaa0235-f9e7-47a5-ab8a-8a20b56a6c43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208136221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.208136221
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4180828498
Short name T983
Test name
Test status
Simulation time 667824201 ps
CPU time 16.33 seconds
Started Aug 14 04:32:44 PM PDT 24
Finished Aug 14 04:33:01 PM PDT 24
Peak memory 206200 kb
Host smart-d51a146e-9138-4c6d-abcb-f65956619106
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180828498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4
180828498
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2691622512
Short name T1071
Test name
Test status
Simulation time 29690384 ps
CPU time 1.13 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:32:19 PM PDT 24
Peak memory 206244 kb
Host smart-c5c2fa44-2eda-4731-a109-dbf2e55b3450
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691622512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
691622512
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1695773256
Short name T1035
Test name
Test status
Simulation time 111193904 ps
CPU time 1.22 seconds
Started Aug 14 04:32:45 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 214548 kb
Host smart-5c734908-cb6e-4716-bc75-6881d430d06c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695773256 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1695773256
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.778669341
Short name T952
Test name
Test status
Simulation time 53366248 ps
CPU time 0.96 seconds
Started Aug 14 04:32:33 PM PDT 24
Finished Aug 14 04:32:34 PM PDT 24
Peak memory 206068 kb
Host smart-67d4a82a-43fd-4bc7-93ce-53de9f9953cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778669341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.778669341
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1887489286
Short name T1002
Test name
Test status
Simulation time 19575549 ps
CPU time 0.8 seconds
Started Aug 14 04:32:46 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 205956 kb
Host smart-0c330e08-1a1e-4501-b1d1-1da0c45344cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887489286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1887489286
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2044709501
Short name T141
Test name
Test status
Simulation time 336616434 ps
CPU time 4.64 seconds
Started Aug 14 04:32:34 PM PDT 24
Finished Aug 14 04:32:39 PM PDT 24
Peak memory 206276 kb
Host smart-09457b2f-d6a8-4c8e-9919-13a45337e26e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044709501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2044709501
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3126551469
Short name T1084
Test name
Test status
Simulation time 676287527 ps
CPU time 6.59 seconds
Started Aug 14 04:32:37 PM PDT 24
Finished Aug 14 04:32:43 PM PDT 24
Peak memory 214892 kb
Host smart-9f4f4ffe-579e-457b-a982-3ab41dd00a78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126551469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3126551469
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.938556702
Short name T1049
Test name
Test status
Simulation time 154676969 ps
CPU time 1.95 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 214472 kb
Host smart-31a245df-f151-4e71-b03c-f0d6f5e10363
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938556702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.938556702
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1435546970
Short name T925
Test name
Test status
Simulation time 101136866 ps
CPU time 1.52 seconds
Started Aug 14 04:32:54 PM PDT 24
Finished Aug 14 04:32:55 PM PDT 24
Peak memory 214560 kb
Host smart-2378357a-c9df-4927-b7df-3c2cf425fe42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435546970 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1435546970
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1100966717
Short name T136
Test name
Test status
Simulation time 24460402 ps
CPU time 1.37 seconds
Started Aug 14 04:32:42 PM PDT 24
Finished Aug 14 04:32:43 PM PDT 24
Peak memory 206244 kb
Host smart-b5662c2f-20a5-4a46-8d7f-7d38a6b00620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100966717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1100966717
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3982342925
Short name T1010
Test name
Test status
Simulation time 45959436 ps
CPU time 0.84 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 206024 kb
Host smart-2b414c86-c12d-4c97-8dd2-09ae9a8cfbcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982342925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3982342925
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4161283164
Short name T1046
Test name
Test status
Simulation time 115186713 ps
CPU time 2.71 seconds
Started Aug 14 04:32:26 PM PDT 24
Finished Aug 14 04:32:29 PM PDT 24
Peak memory 206280 kb
Host smart-db2eb386-0e65-4f8f-855f-8ffcbddfce47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161283164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4161283164
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.638475097
Short name T1063
Test name
Test status
Simulation time 48912683 ps
CPU time 1.6 seconds
Started Aug 14 04:32:42 PM PDT 24
Finished Aug 14 04:32:43 PM PDT 24
Peak memory 214788 kb
Host smart-54ef71b1-2aae-4988-b76a-57fe921ba04e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638475097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.638475097
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1977744013
Short name T993
Test name
Test status
Simulation time 1639637293 ps
CPU time 4.42 seconds
Started Aug 14 04:32:25 PM PDT 24
Finished Aug 14 04:32:29 PM PDT 24
Peak memory 214756 kb
Host smart-9a30d760-5582-4083-9ed3-9870fcc461a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977744013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1977744013
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1289239068
Short name T1044
Test name
Test status
Simulation time 161828661 ps
CPU time 2.92 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:41 PM PDT 24
Peak memory 215524 kb
Host smart-2b58caf3-803d-46f4-a5ec-1afbcd5d57a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289239068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1289239068
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3899911646
Short name T1013
Test name
Test status
Simulation time 238509224 ps
CPU time 2.17 seconds
Started Aug 14 04:32:28 PM PDT 24
Finished Aug 14 04:32:31 PM PDT 24
Peak memory 214500 kb
Host smart-a64d462d-f90a-41ec-9cca-6f139d0b8ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899911646 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3899911646
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3879826112
Short name T1083
Test name
Test status
Simulation time 47631283 ps
CPU time 1.17 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:32 PM PDT 24
Peak memory 206356 kb
Host smart-96291922-ebff-4d7a-90ca-152809214725
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879826112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3879826112
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3880520605
Short name T918
Test name
Test status
Simulation time 21655845 ps
CPU time 0.81 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:22 PM PDT 24
Peak memory 206012 kb
Host smart-251ab2ea-bafd-49a9-aac4-8ad0f99a747b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880520605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3880520605
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3736750303
Short name T935
Test name
Test status
Simulation time 84100216 ps
CPU time 3.5 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 206236 kb
Host smart-7030f505-542e-43a6-976c-337040b8ca9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736750303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3736750303
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.455862838
Short name T1074
Test name
Test status
Simulation time 44195744 ps
CPU time 1.74 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 214756 kb
Host smart-8335e440-6c1b-488e-a3b4-ba05b09d25c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455862838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.455862838
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4195468444
Short name T109
Test name
Test status
Simulation time 867922488 ps
CPU time 6.85 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 214820 kb
Host smart-75e0a118-dac8-4762-8fc2-03900441b9f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195468444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.4195468444
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1347095991
Short name T991
Test name
Test status
Simulation time 54479608 ps
CPU time 2.71 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 216912 kb
Host smart-601b89cf-ca63-445a-998b-c72671cd206c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347095991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1347095991
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1435662762
Short name T997
Test name
Test status
Simulation time 197953503 ps
CPU time 1.42 seconds
Started Aug 14 04:32:34 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 214460 kb
Host smart-577b1187-2e8f-4024-9232-40954af7a2ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435662762 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1435662762
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2863338562
Short name T1041
Test name
Test status
Simulation time 40363087 ps
CPU time 0.86 seconds
Started Aug 14 04:32:20 PM PDT 24
Finished Aug 14 04:32:21 PM PDT 24
Peak memory 206072 kb
Host smart-d7588cbf-04b7-4bd7-84a9-f215024fec92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863338562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2863338562
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4235096647
Short name T992
Test name
Test status
Simulation time 38536651 ps
CPU time 0.84 seconds
Started Aug 14 04:32:41 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 205996 kb
Host smart-6f3f88ce-afee-4ea6-8537-c6448c31851c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235096647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4235096647
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1615755029
Short name T138
Test name
Test status
Simulation time 366419116 ps
CPU time 1.49 seconds
Started Aug 14 04:32:37 PM PDT 24
Finished Aug 14 04:32:39 PM PDT 24
Peak memory 206236 kb
Host smart-dbfbfb16-a50a-4fec-9b17-fc06f3078004
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615755029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1615755029
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2895398605
Short name T118
Test name
Test status
Simulation time 61220577 ps
CPU time 2.2 seconds
Started Aug 14 04:32:45 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 214744 kb
Host smart-72ceb102-c9ed-490e-a8d5-9ae0b17002f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895398605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2895398605
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2661335277
Short name T975
Test name
Test status
Simulation time 192349671 ps
CPU time 4.46 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:43 PM PDT 24
Peak memory 214868 kb
Host smart-20c18369-e896-4292-b1e3-b750a33fd601
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661335277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2661335277
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1670595845
Short name T959
Test name
Test status
Simulation time 23840974 ps
CPU time 1.46 seconds
Started Aug 14 04:32:48 PM PDT 24
Finished Aug 14 04:32:49 PM PDT 24
Peak memory 215968 kb
Host smart-e23fbe1d-a43e-4b19-a458-3ce32581d6dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670595845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1670595845
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.413358433
Short name T168
Test name
Test status
Simulation time 549441000 ps
CPU time 9.42 seconds
Started Aug 14 04:32:29 PM PDT 24
Finished Aug 14 04:32:39 PM PDT 24
Peak memory 214444 kb
Host smart-3d554932-8ecf-4ba1-8b65-5c20b3ad6545
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413358433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.413358433
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1724562493
Short name T1024
Test name
Test status
Simulation time 139909608 ps
CPU time 1.83 seconds
Started Aug 14 04:32:44 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 218640 kb
Host smart-2e0bb8d8-bcd5-4282-9bc7-f1e10410f485
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724562493 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1724562493
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2471457113
Short name T1075
Test name
Test status
Simulation time 26913523 ps
CPU time 0.95 seconds
Started Aug 14 04:32:50 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 206084 kb
Host smart-1449d920-2acd-4cc1-87e0-79f607dd2165
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471457113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2471457113
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.106955566
Short name T945
Test name
Test status
Simulation time 8412234 ps
CPU time 0.68 seconds
Started Aug 14 04:32:50 PM PDT 24
Finished Aug 14 04:32:50 PM PDT 24
Peak memory 205964 kb
Host smart-fbf8d2f2-10c0-4906-888f-88603675b971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106955566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.106955566
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2559864300
Short name T949
Test name
Test status
Simulation time 699546291 ps
CPU time 4.41 seconds
Started Aug 14 04:32:42 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 206236 kb
Host smart-bef14991-94a2-423b-8eff-ff12416945ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559864300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2559864300
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2714689947
Short name T1014
Test name
Test status
Simulation time 285421565 ps
CPU time 5.25 seconds
Started Aug 14 04:32:46 PM PDT 24
Finished Aug 14 04:32:52 PM PDT 24
Peak memory 214760 kb
Host smart-a226f98c-9461-45b6-9d97-af98164a631f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714689947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2714689947
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1968952677
Short name T114
Test name
Test status
Simulation time 443685562 ps
CPU time 5.36 seconds
Started Aug 14 04:32:51 PM PDT 24
Finished Aug 14 04:32:57 PM PDT 24
Peak memory 220836 kb
Host smart-bf3d624a-8c63-4626-a0cd-e1cd102e89d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968952677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1968952677
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3413737651
Short name T936
Test name
Test status
Simulation time 275363536 ps
CPU time 2.49 seconds
Started Aug 14 04:32:41 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 217576 kb
Host smart-dd6c7c6c-7257-4028-bc89-3811ced8f7ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413737651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3413737651
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3682720932
Short name T162
Test name
Test status
Simulation time 398146733 ps
CPU time 3.19 seconds
Started Aug 14 04:32:20 PM PDT 24
Finished Aug 14 04:32:24 PM PDT 24
Peak memory 214384 kb
Host smart-f9ca5b36-4cec-47e3-9bfc-3c343c5ed5ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682720932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3682720932
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.759431636
Short name T186
Test name
Test status
Simulation time 98578867 ps
CPU time 2.08 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 214524 kb
Host smart-cd0d49ba-48b1-413d-ac5e-3293efaba05c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759431636 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.759431636
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.282557425
Short name T940
Test name
Test status
Simulation time 23277423 ps
CPU time 1.09 seconds
Started Aug 14 04:32:48 PM PDT 24
Finished Aug 14 04:32:49 PM PDT 24
Peak memory 206404 kb
Host smart-1b87b2b5-1b4b-41d5-9bfd-972e5dfd38a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282557425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.282557425
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1251566914
Short name T943
Test name
Test status
Simulation time 60564187 ps
CPU time 0.72 seconds
Started Aug 14 04:32:36 PM PDT 24
Finished Aug 14 04:32:37 PM PDT 24
Peak memory 205964 kb
Host smart-1667cdfa-acef-44dc-994a-4fa21a2a97a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251566914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1251566914
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2783063129
Short name T137
Test name
Test status
Simulation time 108068089 ps
CPU time 2.13 seconds
Started Aug 14 04:32:54 PM PDT 24
Finished Aug 14 04:32:56 PM PDT 24
Peak memory 206152 kb
Host smart-fea66d0c-6868-4534-8fd1-c945e7d20ee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783063129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2783063129
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.38463632
Short name T1069
Test name
Test status
Simulation time 378124806 ps
CPU time 3 seconds
Started Aug 14 04:32:44 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 219648 kb
Host smart-b0d6db27-3545-4a7d-9c8a-49f4392bfca0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38463632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow
_reg_errors.38463632
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.177677146
Short name T1077
Test name
Test status
Simulation time 575212306 ps
CPU time 4.42 seconds
Started Aug 14 04:32:50 PM PDT 24
Finished Aug 14 04:32:55 PM PDT 24
Peak memory 220700 kb
Host smart-6dd8213d-e89b-427b-bc68-3650c6290047
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177677146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.177677146
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.936941337
Short name T932
Test name
Test status
Simulation time 225657557 ps
CPU time 3.36 seconds
Started Aug 14 04:32:41 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 214468 kb
Host smart-505a67dd-cf65-46bb-bec8-514a09b4a412
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936941337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.936941337
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1295582813
Short name T177
Test name
Test status
Simulation time 275999700 ps
CPU time 5.31 seconds
Started Aug 14 04:32:58 PM PDT 24
Finished Aug 14 04:33:04 PM PDT 24
Peak memory 206384 kb
Host smart-c85a5da0-d95a-4f73-9ffd-70e22d54dd29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295582813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1295582813
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.672822491
Short name T1018
Test name
Test status
Simulation time 92125694 ps
CPU time 1.14 seconds
Started Aug 14 04:32:22 PM PDT 24
Finished Aug 14 04:32:24 PM PDT 24
Peak memory 214500 kb
Host smart-b2dca469-7bf7-4852-b88d-e37905abdfc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672822491 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.672822491
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.657708323
Short name T970
Test name
Test status
Simulation time 27094616 ps
CPU time 1.04 seconds
Started Aug 14 04:32:51 PM PDT 24
Finished Aug 14 04:32:52 PM PDT 24
Peak memory 206204 kb
Host smart-20c967d9-3b26-4b99-8c01-ad3b326e225b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657708323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.657708323
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2796696992
Short name T1005
Test name
Test status
Simulation time 25167976 ps
CPU time 0.75 seconds
Started Aug 14 04:32:32 PM PDT 24
Finished Aug 14 04:32:33 PM PDT 24
Peak memory 206020 kb
Host smart-d8994eb9-8ced-46a0-9e98-59f68e3cd4a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796696992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2796696992
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.882483924
Short name T1030
Test name
Test status
Simulation time 118768947 ps
CPU time 2.04 seconds
Started Aug 14 04:33:08 PM PDT 24
Finished Aug 14 04:33:10 PM PDT 24
Peak memory 206268 kb
Host smart-8d020d0d-3a62-4e34-aa4b-2b6a86c2bc6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882483924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.882483924
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.104996304
Short name T1042
Test name
Test status
Simulation time 154978686 ps
CPU time 4.45 seconds
Started Aug 14 04:32:42 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 214760 kb
Host smart-ea33193c-ce5e-4f8f-a3bf-9c85295f512c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104996304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.104996304
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.163344714
Short name T1015
Test name
Test status
Simulation time 1572434397 ps
CPU time 14.13 seconds
Started Aug 14 04:32:43 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 220908 kb
Host smart-ccb3920a-ba83-4d79-b938-192edc746557
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163344714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.163344714
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3903195932
Short name T976
Test name
Test status
Simulation time 56255975 ps
CPU time 3.11 seconds
Started Aug 14 04:32:43 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 214496 kb
Host smart-6e6697da-bb0a-418a-aaf1-23cf72b93519
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903195932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3903195932
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3833971887
Short name T171
Test name
Test status
Simulation time 2766738149 ps
CPU time 7.13 seconds
Started Aug 14 04:32:43 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 214580 kb
Host smart-561da0ff-078e-48da-b433-f08f8ae6c54e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833971887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3833971887
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1348898448
Short name T947
Test name
Test status
Simulation time 39071490 ps
CPU time 1.24 seconds
Started Aug 14 04:32:58 PM PDT 24
Finished Aug 14 04:32:59 PM PDT 24
Peak memory 214664 kb
Host smart-ff45f62b-8f7d-4b77-88d8-ddf664ee7aa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348898448 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1348898448
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1648535234
Short name T950
Test name
Test status
Simulation time 17334102 ps
CPU time 1.2 seconds
Started Aug 14 04:32:51 PM PDT 24
Finished Aug 14 04:32:52 PM PDT 24
Peak memory 206224 kb
Host smart-3113fdb2-cc7a-4987-b894-c6c4a0f1c3fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648535234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1648535234
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.544473923
Short name T958
Test name
Test status
Simulation time 16154338 ps
CPU time 0.72 seconds
Started Aug 14 04:32:47 PM PDT 24
Finished Aug 14 04:32:48 PM PDT 24
Peak memory 205980 kb
Host smart-714e9cdb-5566-4d2d-a75d-36caa3c706a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544473923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.544473923
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2023132832
Short name T1003
Test name
Test status
Simulation time 80127952 ps
CPU time 1.34 seconds
Started Aug 14 04:32:42 PM PDT 24
Finished Aug 14 04:32:43 PM PDT 24
Peak memory 206216 kb
Host smart-cc444e13-7e3a-438e-8b33-7d3d4419c3e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023132832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2023132832
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.243887117
Short name T967
Test name
Test status
Simulation time 371124764 ps
CPU time 4.38 seconds
Started Aug 14 04:32:51 PM PDT 24
Finished Aug 14 04:32:55 PM PDT 24
Peak memory 214744 kb
Host smart-dd5b52e7-a487-4c40-a236-bb0064ce11e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243887117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.243887117
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3717183903
Short name T960
Test name
Test status
Simulation time 357591215 ps
CPU time 7.52 seconds
Started Aug 14 04:32:58 PM PDT 24
Finished Aug 14 04:33:06 PM PDT 24
Peak memory 221404 kb
Host smart-8bd2c6fd-17e4-4206-9342-abd69be98170
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717183903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3717183903
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2074996632
Short name T1064
Test name
Test status
Simulation time 51930754 ps
CPU time 2.25 seconds
Started Aug 14 04:32:52 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 216448 kb
Host smart-39e115b4-4f3d-4c6c-9fbf-3095e6b9645c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074996632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2074996632
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.581779302
Short name T1022
Test name
Test status
Simulation time 13910082 ps
CPU time 1.29 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:09 PM PDT 24
Peak memory 206212 kb
Host smart-850e1098-41cd-4461-a727-059ca369a736
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581779302 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.581779302
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.295710493
Short name T937
Test name
Test status
Simulation time 136438384 ps
CPU time 1.16 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 206344 kb
Host smart-e95c149f-5ef8-460f-9481-9f90ddba70f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295710493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.295710493
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1529811822
Short name T1032
Test name
Test status
Simulation time 114069027 ps
CPU time 0.69 seconds
Started Aug 14 04:32:54 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 206012 kb
Host smart-c233563b-97db-4392-a8f5-69c5412c0fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529811822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1529811822
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3460993589
Short name T1051
Test name
Test status
Simulation time 121795041 ps
CPU time 4.2 seconds
Started Aug 14 04:32:51 PM PDT 24
Finished Aug 14 04:32:56 PM PDT 24
Peak memory 206176 kb
Host smart-07d97d83-98bc-40a4-867d-1f13309db57e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460993589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3460993589
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3752330092
Short name T1016
Test name
Test status
Simulation time 506154445 ps
CPU time 4.05 seconds
Started Aug 14 04:32:45 PM PDT 24
Finished Aug 14 04:32:49 PM PDT 24
Peak memory 214820 kb
Host smart-975fc0be-5f6b-44ce-a32a-32ce431bba3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752330092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3752330092
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1840425312
Short name T1021
Test name
Test status
Simulation time 225934048 ps
CPU time 4.92 seconds
Started Aug 14 04:32:53 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 214796 kb
Host smart-e105f7ef-10d5-475f-ad7f-c8ab49d7810e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840425312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1840425312
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2402777931
Short name T1065
Test name
Test status
Simulation time 228893656 ps
CPU time 3.19 seconds
Started Aug 14 04:32:43 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 214516 kb
Host smart-0541ffbc-b25f-415d-a783-284bd5e0e9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402777931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2402777931
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1968119319
Short name T1047
Test name
Test status
Simulation time 37540199 ps
CPU time 2.21 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 214460 kb
Host smart-c0aa74d0-133c-40d2-9485-5e68cab55531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968119319 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1968119319
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3697168523
Short name T1061
Test name
Test status
Simulation time 26115832 ps
CPU time 0.93 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 206184 kb
Host smart-5b9e2a19-bcdf-4d1c-abbd-1cf3ff72df8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697168523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3697168523
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2649392589
Short name T1034
Test name
Test status
Simulation time 7649387 ps
CPU time 0.73 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:41 PM PDT 24
Peak memory 205944 kb
Host smart-eba8ec55-45cb-4682-9ae9-ac65d1790eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649392589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2649392589
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4208622350
Short name T972
Test name
Test status
Simulation time 415069324 ps
CPU time 2.19 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 206284 kb
Host smart-fb1778c5-93c8-4084-8ee8-3c7e20911015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208622350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4208622350
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2273106880
Short name T978
Test name
Test status
Simulation time 121448051 ps
CPU time 2.27 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:33 PM PDT 24
Peak memory 214800 kb
Host smart-ef199f20-37f5-4fc1-a588-34175004bb00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273106880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2273106880
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.806612055
Short name T1025
Test name
Test status
Simulation time 724489216 ps
CPU time 5.68 seconds
Started Aug 14 04:32:48 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 217584 kb
Host smart-430a2844-02d1-4bc2-93a0-f9e864bd1627
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806612055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.806612055
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1630723948
Short name T163
Test name
Test status
Simulation time 3627719481 ps
CPU time 7.12 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:38 PM PDT 24
Peak memory 217500 kb
Host smart-e5859e0a-6f94-4f99-a460-757d242f4cba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630723948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1630723948
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2067406307
Short name T995
Test name
Test status
Simulation time 53617767 ps
CPU time 1.32 seconds
Started Aug 14 04:32:49 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 214524 kb
Host smart-1dbe0395-c490-4539-86b8-ce0717962747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067406307 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2067406307
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.697570088
Short name T941
Test name
Test status
Simulation time 38421694 ps
CPU time 0.94 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:39 PM PDT 24
Peak memory 206044 kb
Host smart-c3341267-390e-4f8f-aeed-a3781d471781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697570088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.697570088
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3615305172
Short name T1054
Test name
Test status
Simulation time 10765791 ps
CPU time 0.85 seconds
Started Aug 14 04:32:51 PM PDT 24
Finished Aug 14 04:32:52 PM PDT 24
Peak memory 206136 kb
Host smart-40e809a9-f20e-42f1-ad63-0db8fb9be62e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615305172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3615305172
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.240087359
Short name T953
Test name
Test status
Simulation time 92537363 ps
CPU time 3.63 seconds
Started Aug 14 04:32:49 PM PDT 24
Finished Aug 14 04:32:52 PM PDT 24
Peak memory 206256 kb
Host smart-b61ac1fd-e47f-4b4f-95fd-e90e2e6726fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240087359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.240087359
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3817992914
Short name T1028
Test name
Test status
Simulation time 84857273 ps
CPU time 1.71 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 214748 kb
Host smart-f074eeed-8538-487b-be0a-3cf7e9527921
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817992914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3817992914
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2782049691
Short name T139
Test name
Test status
Simulation time 142382063 ps
CPU time 4.33 seconds
Started Aug 14 04:32:37 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 220748 kb
Host smart-2ea89737-358d-4b4e-a78c-90cc2d4fba50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782049691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2782049691
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3401467810
Short name T964
Test name
Test status
Simulation time 36912206 ps
CPU time 2.3 seconds
Started Aug 14 04:32:26 PM PDT 24
Finished Aug 14 04:32:29 PM PDT 24
Peak memory 216924 kb
Host smart-f993126f-68d7-424f-a489-c22205d0441e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401467810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3401467810
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3419720044
Short name T1001
Test name
Test status
Simulation time 73190371 ps
CPU time 4.9 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:45 PM PDT 24
Peak memory 206284 kb
Host smart-265f99a0-f065-41c1-94e4-c934722c6a3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419720044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
419720044
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2924317880
Short name T1067
Test name
Test status
Simulation time 646658451 ps
CPU time 8.68 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 206160 kb
Host smart-f8ff84de-2c40-4497-bd74-70e93abf666c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924317880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
924317880
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.911349247
Short name T1056
Test name
Test status
Simulation time 111246805 ps
CPU time 1.12 seconds
Started Aug 14 04:32:22 PM PDT 24
Finished Aug 14 04:32:28 PM PDT 24
Peak memory 206220 kb
Host smart-b25bb7af-2ba3-4d6a-8057-f04e6fc49bdc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911349247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.911349247
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3850850917
Short name T926
Test name
Test status
Simulation time 65724513 ps
CPU time 1.32 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 214632 kb
Host smart-6e93b724-678c-417c-bef6-53ee03a598c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850850917 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3850850917
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3445121201
Short name T1011
Test name
Test status
Simulation time 362358273 ps
CPU time 1.44 seconds
Started Aug 14 04:32:35 PM PDT 24
Finished Aug 14 04:32:37 PM PDT 24
Peak memory 206284 kb
Host smart-a5ec2474-716a-4f78-b33c-097eccb968be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445121201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3445121201
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3893054155
Short name T1037
Test name
Test status
Simulation time 23189074 ps
CPU time 0.7 seconds
Started Aug 14 04:32:19 PM PDT 24
Finished Aug 14 04:32:20 PM PDT 24
Peak memory 206016 kb
Host smart-fb3c4922-8305-4024-8949-650b52bcde5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893054155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3893054155
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.4131673010
Short name T962
Test name
Test status
Simulation time 59935308 ps
CPU time 2.26 seconds
Started Aug 14 04:32:44 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 206184 kb
Host smart-d4143845-6081-4479-b05e-340830c7c4d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131673010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.4131673010
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.40136542
Short name T111
Test name
Test status
Simulation time 58469117 ps
CPU time 1.53 seconds
Started Aug 14 04:32:45 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 214744 kb
Host smart-0b5dbee3-3cca-495b-8ba2-3b9cb4b0eda3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40136542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_
reg_errors.40136542
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.843541804
Short name T1036
Test name
Test status
Simulation time 285735122 ps
CPU time 4.23 seconds
Started Aug 14 04:32:30 PM PDT 24
Finished Aug 14 04:32:35 PM PDT 24
Peak memory 220888 kb
Host smart-92d78b31-ee07-43e6-9119-a9c3c9e12c47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843541804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.843541804
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.92564831
Short name T1073
Test name
Test status
Simulation time 139148662 ps
CPU time 3.33 seconds
Started Aug 14 04:32:45 PM PDT 24
Finished Aug 14 04:32:49 PM PDT 24
Peak memory 217820 kb
Host smart-637a0a6b-da9f-4463-b490-19f5a3f81f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92564831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.92564831
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1461371717
Short name T155
Test name
Test status
Simulation time 53217452 ps
CPU time 2.54 seconds
Started Aug 14 04:32:23 PM PDT 24
Finished Aug 14 04:32:26 PM PDT 24
Peak memory 214444 kb
Host smart-fbca9b53-7612-4ff1-8fcb-c01edd56507c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461371717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1461371717
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.405138156
Short name T1023
Test name
Test status
Simulation time 14451920 ps
CPU time 0.72 seconds
Started Aug 14 04:32:50 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 206024 kb
Host smart-000ae995-50d3-47cb-999d-4a216baa9598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405138156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.405138156
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.316027557
Short name T927
Test name
Test status
Simulation time 37370117 ps
CPU time 0.72 seconds
Started Aug 14 04:32:55 PM PDT 24
Finished Aug 14 04:32:56 PM PDT 24
Peak memory 205976 kb
Host smart-3c1509e9-f920-463f-93ce-18160c64153e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316027557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.316027557
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.772094509
Short name T1081
Test name
Test status
Simulation time 24085174 ps
CPU time 0.68 seconds
Started Aug 14 04:32:53 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 206108 kb
Host smart-ce2d1ac4-296c-4986-9699-1168c3453a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772094509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.772094509
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.613773712
Short name T1004
Test name
Test status
Simulation time 27408587 ps
CPU time 0.7 seconds
Started Aug 14 04:32:49 PM PDT 24
Finished Aug 14 04:32:50 PM PDT 24
Peak memory 205928 kb
Host smart-a0ead77d-ef4b-44a9-a8a9-5939c767b6aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613773712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.613773712
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4152565747
Short name T996
Test name
Test status
Simulation time 10055301 ps
CPU time 0.74 seconds
Started Aug 14 04:32:59 PM PDT 24
Finished Aug 14 04:33:00 PM PDT 24
Peak memory 206108 kb
Host smart-07dcf5da-16be-4f78-9ff3-816eb102bed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152565747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.4152565747
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2075869830
Short name T931
Test name
Test status
Simulation time 24822065 ps
CPU time 0.72 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:41 PM PDT 24
Peak memory 205984 kb
Host smart-05ad1b12-388e-49ae-b881-facab83cdce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075869830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2075869830
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3280873070
Short name T924
Test name
Test status
Simulation time 11420205 ps
CPU time 0.8 seconds
Started Aug 14 04:32:49 PM PDT 24
Finished Aug 14 04:32:50 PM PDT 24
Peak memory 205928 kb
Host smart-ec62fdd7-1501-4649-97ef-49aa1275f878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280873070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3280873070
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2409076247
Short name T946
Test name
Test status
Simulation time 58389078 ps
CPU time 0.69 seconds
Started Aug 14 04:32:48 PM PDT 24
Finished Aug 14 04:32:49 PM PDT 24
Peak memory 205944 kb
Host smart-3ce7322c-0212-4bad-8f5b-3a9942896147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409076247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2409076247
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1270011764
Short name T963
Test name
Test status
Simulation time 14472367 ps
CPU time 0.89 seconds
Started Aug 14 04:33:00 PM PDT 24
Finished Aug 14 04:33:01 PM PDT 24
Peak memory 206180 kb
Host smart-da954856-d56d-4746-bb95-f78d5a051714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270011764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1270011764
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.822185257
Short name T1009
Test name
Test status
Simulation time 23243685 ps
CPU time 0.84 seconds
Started Aug 14 04:32:44 PM PDT 24
Finished Aug 14 04:32:45 PM PDT 24
Peak memory 206048 kb
Host smart-e4f98b13-1d61-4616-8c9b-da0cf6025d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822185257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.822185257
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.944399489
Short name T968
Test name
Test status
Simulation time 265261345 ps
CPU time 7.52 seconds
Started Aug 14 04:32:49 PM PDT 24
Finished Aug 14 04:32:57 PM PDT 24
Peak memory 206256 kb
Host smart-8029ae8e-18f2-4080-a168-8e8c978faf85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944399489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.944399489
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2304300581
Short name T969
Test name
Test status
Simulation time 1241973909 ps
CPU time 15.14 seconds
Started Aug 14 04:32:35 PM PDT 24
Finished Aug 14 04:32:50 PM PDT 24
Peak memory 206340 kb
Host smart-01fa438a-4857-4acc-964c-d5154c70c17e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304300581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
304300581
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.768274201
Short name T938
Test name
Test status
Simulation time 181197790 ps
CPU time 0.92 seconds
Started Aug 14 04:32:29 PM PDT 24
Finished Aug 14 04:32:30 PM PDT 24
Peak memory 206096 kb
Host smart-fbb431b4-537b-430c-98cd-6517b347269b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768274201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.768274201
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2441776442
Short name T1058
Test name
Test status
Simulation time 44232888 ps
CPU time 1.81 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 219480 kb
Host smart-58a557ec-32ae-4b45-bc44-15b409db7810
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441776442 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2441776442
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3964503840
Short name T1079
Test name
Test status
Simulation time 43044903 ps
CPU time 0.83 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:33:07 PM PDT 24
Peak memory 206156 kb
Host smart-93b9d3a3-0a6c-4962-b4d7-e22cb2c99d6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964503840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3964503840
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2420556399
Short name T961
Test name
Test status
Simulation time 40197814 ps
CPU time 0.82 seconds
Started Aug 14 04:32:41 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 206004 kb
Host smart-dd0cd42e-4d05-4749-a7d1-210e19239047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420556399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2420556399
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2163567414
Short name T982
Test name
Test status
Simulation time 84581106 ps
CPU time 1.66 seconds
Started Aug 14 04:32:35 PM PDT 24
Finished Aug 14 04:32:36 PM PDT 24
Peak memory 206252 kb
Host smart-bcfb3c85-5a39-4bf4-ac3a-2d3a2b921976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163567414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2163567414
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.164629678
Short name T987
Test name
Test status
Simulation time 171866893 ps
CPU time 2.24 seconds
Started Aug 14 04:32:30 PM PDT 24
Finished Aug 14 04:32:32 PM PDT 24
Peak memory 214728 kb
Host smart-c2b89b14-994d-4433-9f45-3a257a3e187e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164629678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.164629678
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1702858863
Short name T1040
Test name
Test status
Simulation time 183484220 ps
CPU time 4.49 seconds
Started Aug 14 04:32:49 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 214744 kb
Host smart-1a96b670-970e-4ff7-b9d4-73df0eceed87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702858863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1702858863
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1377484432
Short name T980
Test name
Test status
Simulation time 78411937 ps
CPU time 3.27 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:48 PM PDT 24
Peak memory 217564 kb
Host smart-f7f2e102-7459-4f85-8c18-4240db2bd3af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377484432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1377484432
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.588467039
Short name T174
Test name
Test status
Simulation time 179194434 ps
CPU time 4.41 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:35 PM PDT 24
Peak memory 206496 kb
Host smart-18763888-234e-4d6a-b015-91bf5692a811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588467039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
588467039
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3297516083
Short name T1060
Test name
Test status
Simulation time 93043133 ps
CPU time 0.78 seconds
Started Aug 14 04:32:50 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 205988 kb
Host smart-ff490ea0-57e9-4206-aae1-9c49479bfd7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297516083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3297516083
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2489626473
Short name T944
Test name
Test status
Simulation time 13884372 ps
CPU time 0.98 seconds
Started Aug 14 04:32:53 PM PDT 24
Finished Aug 14 04:32:59 PM PDT 24
Peak memory 206248 kb
Host smart-1e3090f0-e6f7-40dd-abd8-364d9ab049c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489626473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2489626473
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2223060274
Short name T1057
Test name
Test status
Simulation time 10659176 ps
CPU time 0.7 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 205944 kb
Host smart-3cc02dfb-6326-4a66-8845-efe52df5a30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223060274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2223060274
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1493904738
Short name T994
Test name
Test status
Simulation time 16375866 ps
CPU time 0.88 seconds
Started Aug 14 04:32:43 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 206156 kb
Host smart-f93af784-0537-414e-8824-4e72a282aa00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493904738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1493904738
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1891849783
Short name T928
Test name
Test status
Simulation time 42110996 ps
CPU time 0.81 seconds
Started Aug 14 04:33:22 PM PDT 24
Finished Aug 14 04:33:23 PM PDT 24
Peak memory 205928 kb
Host smart-587083aa-dd02-40f5-b91a-bcd9e94ca4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891849783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1891849783
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.916567270
Short name T1026
Test name
Test status
Simulation time 20317016 ps
CPU time 0.69 seconds
Started Aug 14 04:33:03 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 206108 kb
Host smart-984a58d9-476f-460f-a25b-51edb0e833bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916567270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.916567270
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4083214786
Short name T1072
Test name
Test status
Simulation time 28193106 ps
CPU time 0.7 seconds
Started Aug 14 04:33:00 PM PDT 24
Finished Aug 14 04:33:01 PM PDT 24
Peak memory 205936 kb
Host smart-0f548e5b-b3d9-4f1e-bc29-fec0553033ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083214786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4083214786
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1682224398
Short name T1059
Test name
Test status
Simulation time 79875372 ps
CPU time 0.83 seconds
Started Aug 14 04:33:01 PM PDT 24
Finished Aug 14 04:33:02 PM PDT 24
Peak memory 205964 kb
Host smart-a1decabb-1f41-417e-90a7-5b50d06eb2f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682224398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1682224398
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3259912546
Short name T922
Test name
Test status
Simulation time 10974235 ps
CPU time 0.7 seconds
Started Aug 14 04:32:56 PM PDT 24
Finished Aug 14 04:32:57 PM PDT 24
Peak memory 206092 kb
Host smart-47ce827a-b780-4853-ad94-ded635fb2af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259912546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3259912546
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3294226982
Short name T999
Test name
Test status
Simulation time 8260336 ps
CPU time 0.82 seconds
Started Aug 14 04:32:42 PM PDT 24
Finished Aug 14 04:32:43 PM PDT 24
Peak memory 206004 kb
Host smart-0c154e42-1e71-4a59-a2d6-654f87268272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294226982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3294226982
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2164598558
Short name T1052
Test name
Test status
Simulation time 247023234 ps
CPU time 7.15 seconds
Started Aug 14 04:32:49 PM PDT 24
Finished Aug 14 04:32:57 PM PDT 24
Peak memory 206248 kb
Host smart-ce5db5c7-f3cc-4ad6-80a0-ee32e47ed133
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164598558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
164598558
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.28963957
Short name T1078
Test name
Test status
Simulation time 333310612 ps
CPU time 7.59 seconds
Started Aug 14 04:32:32 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 206376 kb
Host smart-46eff1c7-f16d-4702-a3a8-d5eb88940f22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28963957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.28963957
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.798846030
Short name T939
Test name
Test status
Simulation time 146977701 ps
CPU time 1.08 seconds
Started Aug 14 04:32:50 PM PDT 24
Finished Aug 14 04:32:52 PM PDT 24
Peak memory 206256 kb
Host smart-37486a3d-d1e2-404f-8ec0-4278951b8d7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798846030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.798846030
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.393285984
Short name T934
Test name
Test status
Simulation time 117248723 ps
CPU time 1.85 seconds
Started Aug 14 04:32:28 PM PDT 24
Finished Aug 14 04:32:30 PM PDT 24
Peak memory 214488 kb
Host smart-316002f1-2215-4deb-9836-386453d4e35e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393285984 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.393285984
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1685236372
Short name T986
Test name
Test status
Simulation time 25015879 ps
CPU time 1.37 seconds
Started Aug 14 04:32:51 PM PDT 24
Finished Aug 14 04:32:53 PM PDT 24
Peak memory 206296 kb
Host smart-6ef4e364-d785-42cd-8509-a08140f90c91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685236372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1685236372
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2157608405
Short name T979
Test name
Test status
Simulation time 17089804 ps
CPU time 0.78 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 206024 kb
Host smart-2b65222c-66ce-423e-9689-39c01eaab5c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157608405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2157608405
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1041698435
Short name T140
Test name
Test status
Simulation time 239919150 ps
CPU time 2.69 seconds
Started Aug 14 04:32:25 PM PDT 24
Finished Aug 14 04:32:28 PM PDT 24
Peak memory 206216 kb
Host smart-8fe350f2-f358-4db3-a119-9a03da74f1b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041698435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1041698435
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1176213557
Short name T973
Test name
Test status
Simulation time 170275607 ps
CPU time 4.52 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 214756 kb
Host smart-41881972-f46f-499f-80b7-534382ad049c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176213557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1176213557
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3559050662
Short name T954
Test name
Test status
Simulation time 476583400 ps
CPU time 14.92 seconds
Started Aug 14 04:32:53 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 214816 kb
Host smart-a3d02d3b-265a-4eeb-a225-9f28b4fe4eac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559050662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3559050662
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1306748126
Short name T1039
Test name
Test status
Simulation time 56050419 ps
CPU time 1.79 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 214460 kb
Host smart-3499a2d1-f7e8-4da9-b1e9-48566f0d56b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306748126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1306748126
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4004369361
Short name T1082
Test name
Test status
Simulation time 57321403 ps
CPU time 0.73 seconds
Started Aug 14 04:32:43 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 206020 kb
Host smart-43b48c81-faf5-4906-a400-76f2a6e22355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004369361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4004369361
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.989732571
Short name T1000
Test name
Test status
Simulation time 9641450 ps
CPU time 0.8 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:03 PM PDT 24
Peak memory 205948 kb
Host smart-c8861e14-3bcc-4af2-9226-dd4960fb9921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989732571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.989732571
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.32004386
Short name T1062
Test name
Test status
Simulation time 13410597 ps
CPU time 0.85 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 205976 kb
Host smart-afe496b4-d4de-4b0c-910d-432d143501a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32004386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.32004386
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.200393354
Short name T919
Test name
Test status
Simulation time 40867884 ps
CPU time 0.85 seconds
Started Aug 14 04:32:34 PM PDT 24
Finished Aug 14 04:32:35 PM PDT 24
Peak memory 205904 kb
Host smart-a19f9917-b8d0-4558-a678-e9231494d03d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200393354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.200393354
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3408989114
Short name T1006
Test name
Test status
Simulation time 37660309 ps
CPU time 0.71 seconds
Started Aug 14 04:33:03 PM PDT 24
Finished Aug 14 04:33:04 PM PDT 24
Peak memory 206096 kb
Host smart-b07e946f-2076-4bea-ba6c-c7f7c2795029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408989114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3408989114
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3985387522
Short name T942
Test name
Test status
Simulation time 11816436 ps
CPU time 0.83 seconds
Started Aug 14 04:33:04 PM PDT 24
Finished Aug 14 04:33:05 PM PDT 24
Peak memory 206012 kb
Host smart-fa228f9c-e420-4cf7-b95e-3fa7a40b7e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985387522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3985387522
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2137259709
Short name T930
Test name
Test status
Simulation time 78979804 ps
CPU time 0.8 seconds
Started Aug 14 04:32:45 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 206004 kb
Host smart-7ad47a75-f9cb-4055-b088-a05d5fe455c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137259709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2137259709
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.224266409
Short name T966
Test name
Test status
Simulation time 27831718 ps
CPU time 0.7 seconds
Started Aug 14 04:32:48 PM PDT 24
Finished Aug 14 04:32:49 PM PDT 24
Peak memory 205996 kb
Host smart-4ed3b178-4df2-478e-9c91-4a339e096c67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224266409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.224266409
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2578917720
Short name T921
Test name
Test status
Simulation time 35269735 ps
CPU time 0.73 seconds
Started Aug 14 04:32:58 PM PDT 24
Finished Aug 14 04:32:59 PM PDT 24
Peak memory 205996 kb
Host smart-c8b3fc82-0bd4-478e-b0b0-5a76a672d025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578917720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2578917720
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2962633003
Short name T988
Test name
Test status
Simulation time 16993865 ps
CPU time 0.79 seconds
Started Aug 14 04:33:01 PM PDT 24
Finished Aug 14 04:33:02 PM PDT 24
Peak memory 206020 kb
Host smart-d43cc276-6abb-4339-94aa-618cee669d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962633003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2962633003
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3966555842
Short name T1019
Test name
Test status
Simulation time 37988346 ps
CPU time 1.84 seconds
Started Aug 14 04:32:55 PM PDT 24
Finished Aug 14 04:32:57 PM PDT 24
Peak memory 222532 kb
Host smart-8ef4c39b-5262-4f87-b120-d1c709bbf358
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966555842 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3966555842
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.522448556
Short name T1008
Test name
Test status
Simulation time 86506597 ps
CPU time 1.38 seconds
Started Aug 14 04:32:45 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 206252 kb
Host smart-a876438f-aa12-4127-be6f-03fa20b0ed77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522448556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.522448556
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3601107228
Short name T923
Test name
Test status
Simulation time 50685809 ps
CPU time 0.8 seconds
Started Aug 14 04:32:45 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 205960 kb
Host smart-49f94dfd-b9d4-41b9-b4f9-912c4cdaa601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601107228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3601107228
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.65309769
Short name T1043
Test name
Test status
Simulation time 211291214 ps
CPU time 4.12 seconds
Started Aug 14 04:32:58 PM PDT 24
Finished Aug 14 04:33:02 PM PDT 24
Peak memory 206272 kb
Host smart-59621de5-3a12-464b-b904-9fd979ab4c29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65309769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same
_csr_outstanding.65309769
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.952012974
Short name T1068
Test name
Test status
Simulation time 544188262 ps
CPU time 4.19 seconds
Started Aug 14 04:32:47 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 214852 kb
Host smart-f6e64c80-399b-4488-8446-85a805bb9a6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952012974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.952012974
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1780138944
Short name T971
Test name
Test status
Simulation time 377840130 ps
CPU time 3.6 seconds
Started Aug 14 04:32:56 PM PDT 24
Finished Aug 14 04:33:00 PM PDT 24
Peak memory 214536 kb
Host smart-b05d0a0d-b474-45ca-a652-8d0584488951
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780138944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1780138944
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2949993999
Short name T172
Test name
Test status
Simulation time 406014745 ps
CPU time 8.4 seconds
Started Aug 14 04:32:54 PM PDT 24
Finished Aug 14 04:33:02 PM PDT 24
Peak memory 214436 kb
Host smart-2e09b8d2-c6fd-444b-accd-e8e2922f71bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949993999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2949993999
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3771811178
Short name T956
Test name
Test status
Simulation time 119992632 ps
CPU time 2.15 seconds
Started Aug 14 04:32:29 PM PDT 24
Finished Aug 14 04:32:31 PM PDT 24
Peak memory 214524 kb
Host smart-daf84bb4-f74a-40b7-af1c-429c4f95304d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771811178 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3771811178
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3339405694
Short name T1055
Test name
Test status
Simulation time 17781855 ps
CPU time 0.96 seconds
Started Aug 14 04:32:48 PM PDT 24
Finished Aug 14 04:32:49 PM PDT 24
Peak memory 206268 kb
Host smart-ef63da2f-5417-4212-8144-4b1486d7fb45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339405694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3339405694
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3309394357
Short name T955
Test name
Test status
Simulation time 33619282 ps
CPU time 0.77 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 205900 kb
Host smart-6ea68631-15cd-4abc-b94d-fa1d6a058101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309394357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3309394357
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3805273252
Short name T1038
Test name
Test status
Simulation time 265323448 ps
CPU time 1.81 seconds
Started Aug 14 04:32:46 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 206344 kb
Host smart-136d5060-1302-472c-b54a-a6c93a2b4bc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805273252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3805273252
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3265167239
Short name T112
Test name
Test status
Simulation time 155193687 ps
CPU time 1.55 seconds
Started Aug 14 04:32:35 PM PDT 24
Finished Aug 14 04:32:37 PM PDT 24
Peak memory 214860 kb
Host smart-c4547466-b2c5-4c58-8004-52a4b5373073
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265167239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3265167239
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4095348920
Short name T1027
Test name
Test status
Simulation time 449157061 ps
CPU time 6.75 seconds
Started Aug 14 04:32:36 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 214732 kb
Host smart-7b3abebf-c51e-4b9b-952b-65b79c1820b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095348920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.4095348920
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3017766582
Short name T1033
Test name
Test status
Simulation time 547844262 ps
CPU time 4.79 seconds
Started Aug 14 04:32:41 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 216784 kb
Host smart-dfccaa35-b2d2-41f0-a55c-53c6d5693368
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017766582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3017766582
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3723270908
Short name T917
Test name
Test status
Simulation time 45079617 ps
CPU time 1.7 seconds
Started Aug 14 04:32:26 PM PDT 24
Finished Aug 14 04:32:28 PM PDT 24
Peak memory 214528 kb
Host smart-bfa50384-7c07-4f2c-8b02-2c8a44a57a7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723270908 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3723270908
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2640074651
Short name T1031
Test name
Test status
Simulation time 86802440 ps
CPU time 1.19 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:32 PM PDT 24
Peak memory 206316 kb
Host smart-4a7621f9-64d1-4b28-96e6-3b6f921b1f16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640074651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2640074651
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.446446554
Short name T977
Test name
Test status
Simulation time 12533466 ps
CPU time 0.73 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:40 PM PDT 24
Peak memory 205908 kb
Host smart-46ab3c4e-a7d8-4f99-9951-c50d8cd3efb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446446554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.446446554
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1998513991
Short name T989
Test name
Test status
Simulation time 248767979 ps
CPU time 2.21 seconds
Started Aug 14 04:32:46 PM PDT 24
Finished Aug 14 04:32:48 PM PDT 24
Peak memory 206240 kb
Host smart-55ed11ef-1ccd-4123-bd5a-5c6b4f674282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998513991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1998513991
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.829193148
Short name T990
Test name
Test status
Simulation time 66272703 ps
CPU time 2.23 seconds
Started Aug 14 04:32:26 PM PDT 24
Finished Aug 14 04:32:29 PM PDT 24
Peak memory 214768 kb
Host smart-01e9133a-0191-485e-a799-7ff5530ea227
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829193148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.829193148
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3521861564
Short name T1080
Test name
Test status
Simulation time 154766280 ps
CPU time 6.62 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:45 PM PDT 24
Peak memory 214896 kb
Host smart-917ca9e0-aee0-4333-bf52-0a80b266b0c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521861564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3521861564
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.846243019
Short name T974
Test name
Test status
Simulation time 302636653 ps
CPU time 2.04 seconds
Started Aug 14 04:32:39 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 214572 kb
Host smart-466c56f0-aee7-40e3-b927-0420400909f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846243019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.846243019
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.805603709
Short name T173
Test name
Test status
Simulation time 365797634 ps
CPU time 2.9 seconds
Started Aug 14 04:32:55 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 214404 kb
Host smart-6a083299-ea06-4f1e-8759-1a17065150b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805603709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
805603709
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.308060458
Short name T1053
Test name
Test status
Simulation time 120666521 ps
CPU time 1.5 seconds
Started Aug 14 04:32:45 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 222664 kb
Host smart-8b141247-01ad-4538-8706-f73c641025f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308060458 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.308060458
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1677883274
Short name T933
Test name
Test status
Simulation time 96723620 ps
CPU time 1.22 seconds
Started Aug 14 04:32:55 PM PDT 24
Finished Aug 14 04:32:56 PM PDT 24
Peak memory 206244 kb
Host smart-7466b7e7-aa94-4379-8aeb-51ad7a02a547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677883274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1677883274
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2646523084
Short name T1007
Test name
Test status
Simulation time 20148539 ps
CPU time 0.79 seconds
Started Aug 14 04:32:46 PM PDT 24
Finished Aug 14 04:32:52 PM PDT 24
Peak memory 206096 kb
Host smart-0f2aab13-0542-41a9-9495-3b3c030f7dcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646523084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2646523084
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3581683492
Short name T998
Test name
Test status
Simulation time 1737415832 ps
CPU time 2.55 seconds
Started Aug 14 04:32:32 PM PDT 24
Finished Aug 14 04:32:34 PM PDT 24
Peak memory 206200 kb
Host smart-444acfd5-a6ae-4ad6-8af5-35e5ebb5d711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581683492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3581683492
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2398229179
Short name T119
Test name
Test status
Simulation time 446871187 ps
CPU time 1.8 seconds
Started Aug 14 04:32:26 PM PDT 24
Finished Aug 14 04:32:28 PM PDT 24
Peak memory 214944 kb
Host smart-77c4d3dd-d011-4a8b-89c9-b9ad2a6df7a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398229179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2398229179
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2273543211
Short name T117
Test name
Test status
Simulation time 2505898024 ps
CPU time 5.42 seconds
Started Aug 14 04:32:41 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 214936 kb
Host smart-21be6029-723e-49fb-a36e-3ac095ee7f8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273543211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2273543211
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1676189777
Short name T984
Test name
Test status
Simulation time 277191060 ps
CPU time 1.93 seconds
Started Aug 14 04:33:03 PM PDT 24
Finished Aug 14 04:33:05 PM PDT 24
Peak memory 214628 kb
Host smart-dc7e1eeb-24e2-4202-bc2b-7eaa343d3429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676189777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1676189777
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3845913790
Short name T165
Test name
Test status
Simulation time 1990542606 ps
CPU time 7.81 seconds
Started Aug 14 04:32:38 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 216956 kb
Host smart-a437eecd-21e0-4ce5-9a74-fe58f37afe9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845913790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3845913790
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3821368236
Short name T1048
Test name
Test status
Simulation time 80647349 ps
CPU time 1.44 seconds
Started Aug 14 04:33:00 PM PDT 24
Finished Aug 14 04:33:01 PM PDT 24
Peak memory 214508 kb
Host smart-b88af3eb-e208-4225-849f-0f209141dc1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821368236 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3821368236
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1557016781
Short name T1050
Test name
Test status
Simulation time 27044689 ps
CPU time 1.19 seconds
Started Aug 14 04:32:53 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 206244 kb
Host smart-2d84ccd4-b71f-48a9-8fce-f924e547f69f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557016781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1557016781
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2314818567
Short name T965
Test name
Test status
Simulation time 36734718 ps
CPU time 0.73 seconds
Started Aug 14 04:32:36 PM PDT 24
Finished Aug 14 04:32:36 PM PDT 24
Peak memory 205936 kb
Host smart-1493ca46-7b80-47f4-924d-a3214c10fc19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314818567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2314818567
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4115604882
Short name T948
Test name
Test status
Simulation time 83012660 ps
CPU time 2.49 seconds
Started Aug 14 04:32:56 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 206328 kb
Host smart-aa363974-ad1e-45b2-a3b4-c73e3d6c660a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115604882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4115604882
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1913301496
Short name T1017
Test name
Test status
Simulation time 74525149 ps
CPU time 2.5 seconds
Started Aug 14 04:32:47 PM PDT 24
Finished Aug 14 04:32:49 PM PDT 24
Peak memory 219724 kb
Host smart-3a05458a-7dd7-46fb-b6a9-03e5847c000a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913301496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1913301496
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1948213900
Short name T115
Test name
Test status
Simulation time 129829660 ps
CPU time 5.18 seconds
Started Aug 14 04:32:26 PM PDT 24
Finished Aug 14 04:32:31 PM PDT 24
Peak memory 221348 kb
Host smart-8cf3c1bd-0ea9-4163-a0d7-1df149289b22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948213900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1948213900
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3355424158
Short name T957
Test name
Test status
Simulation time 1105925523 ps
CPU time 6.18 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 214588 kb
Host smart-117a0cd9-fad6-41d0-8fce-62f0093dfe0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355424158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3355424158
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.721575901
Short name T169
Test name
Test status
Simulation time 419267157 ps
CPU time 4.31 seconds
Started Aug 14 04:32:58 PM PDT 24
Finished Aug 14 04:33:02 PM PDT 24
Peak memory 206144 kb
Host smart-893f669a-0862-4922-9121-2dd2e73e99a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721575901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
721575901
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.138949475
Short name T452
Test name
Test status
Simulation time 12239352 ps
CPU time 0.71 seconds
Started Aug 14 04:40:48 PM PDT 24
Finished Aug 14 04:40:49 PM PDT 24
Peak memory 206344 kb
Host smart-5c11d860-cb5f-4c72-9e37-d36b495a2e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138949475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.138949475
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1850232756
Short name T296
Test name
Test status
Simulation time 1453152807 ps
CPU time 9.1 seconds
Started Aug 14 04:40:37 PM PDT 24
Finished Aug 14 04:40:46 PM PDT 24
Peak memory 215276 kb
Host smart-2b69f050-9000-4240-866b-2c6f9e554a52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850232756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1850232756
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2889135466
Short name T227
Test name
Test status
Simulation time 246974700 ps
CPU time 3.84 seconds
Started Aug 14 04:40:41 PM PDT 24
Finished Aug 14 04:40:50 PM PDT 24
Peak memory 209820 kb
Host smart-3c7511cd-dee9-47e2-9ed0-50a012001243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889135466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2889135466
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1595095665
Short name T78
Test name
Test status
Simulation time 29876767 ps
CPU time 1.42 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:04 PM PDT 24
Peak memory 207652 kb
Host smart-a383dd3a-ff7f-460f-b63f-2e7dd042b7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595095665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1595095665
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3566529156
Short name T371
Test name
Test status
Simulation time 1328910069 ps
CPU time 8.89 seconds
Started Aug 14 04:41:33 PM PDT 24
Finished Aug 14 04:41:42 PM PDT 24
Peak memory 220924 kb
Host smart-fdb59734-9ac5-4e30-8c3d-9a9033af3e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566529156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3566529156
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_random.4083896527
Short name T262
Test name
Test status
Simulation time 478693270 ps
CPU time 11.95 seconds
Started Aug 14 04:40:50 PM PDT 24
Finished Aug 14 04:41:02 PM PDT 24
Peak memory 210796 kb
Host smart-f2cfff36-3dee-4e08-81a5-af3fdad8e04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083896527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.4083896527
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2752795182
Short name T247
Test name
Test status
Simulation time 57152805 ps
CPU time 2.99 seconds
Started Aug 14 04:40:39 PM PDT 24
Finished Aug 14 04:40:42 PM PDT 24
Peak memory 209376 kb
Host smart-020fce93-0828-4c41-b7cb-2346b59528f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752795182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2752795182
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1634384972
Short name T641
Test name
Test status
Simulation time 3803981531 ps
CPU time 40.3 seconds
Started Aug 14 04:40:35 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 209592 kb
Host smart-0c852d1f-5c3d-45bb-9506-59ad529031c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634384972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1634384972
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.4144256226
Short name T782
Test name
Test status
Simulation time 33840008 ps
CPU time 2.35 seconds
Started Aug 14 04:40:33 PM PDT 24
Finished Aug 14 04:40:36 PM PDT 24
Peak memory 207224 kb
Host smart-fcad38ff-47e4-4dc0-a922-b2e037e3e3e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144256226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4144256226
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3008978612
Short name T902
Test name
Test status
Simulation time 3760032494 ps
CPU time 22.3 seconds
Started Aug 14 04:40:34 PM PDT 24
Finished Aug 14 04:40:57 PM PDT 24
Peak memory 208420 kb
Host smart-4a098f38-c1a3-4395-9737-63f0cb8820d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008978612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3008978612
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4278319713
Short name T128
Test name
Test status
Simulation time 93065346 ps
CPU time 2.93 seconds
Started Aug 14 04:40:34 PM PDT 24
Finished Aug 14 04:40:37 PM PDT 24
Peak memory 216420 kb
Host smart-146f9365-bc31-4e7d-a1c7-899580871f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278319713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4278319713
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.4154024042
Short name T210
Test name
Test status
Simulation time 298258613 ps
CPU time 7.2 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:43 PM PDT 24
Peak memory 207064 kb
Host smart-98075f2e-4667-42c0-ba4c-9b2933b79653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154024042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.4154024042
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.516987393
Short name T896
Test name
Test status
Simulation time 323423316 ps
CPU time 10.04 seconds
Started Aug 14 04:40:53 PM PDT 24
Finished Aug 14 04:41:04 PM PDT 24
Peak memory 216664 kb
Host smart-d70b6565-de14-48f1-bc46-24cff37ed993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516987393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.516987393
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3004405359
Short name T366
Test name
Test status
Simulation time 1961689310 ps
CPU time 20.23 seconds
Started Aug 14 04:40:35 PM PDT 24
Finished Aug 14 04:40:55 PM PDT 24
Peak memory 222972 kb
Host smart-597b3712-7a05-4bfe-9b70-4e50b5584bd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004405359 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3004405359
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1223207458
Short name T674
Test name
Test status
Simulation time 821867649 ps
CPU time 4.51 seconds
Started Aug 14 04:40:59 PM PDT 24
Finished Aug 14 04:41:04 PM PDT 24
Peak memory 210488 kb
Host smart-e831a87b-1400-40bb-a82c-d8f9193eff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223207458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1223207458
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1399726037
Short name T729
Test name
Test status
Simulation time 61660105 ps
CPU time 2.67 seconds
Started Aug 14 04:40:46 PM PDT 24
Finished Aug 14 04:40:49 PM PDT 24
Peak memory 210432 kb
Host smart-5a0f50bf-bff4-4c53-afc5-8f19bcb4b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399726037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1399726037
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.955496938
Short name T827
Test name
Test status
Simulation time 46002928 ps
CPU time 0.85 seconds
Started Aug 14 04:40:45 PM PDT 24
Finished Aug 14 04:40:46 PM PDT 24
Peak memory 206420 kb
Host smart-7562fef1-52fa-4235-8ebf-0018b8798aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955496938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.955496938
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.4180028551
Short name T272
Test name
Test status
Simulation time 44777663 ps
CPU time 2.93 seconds
Started Aug 14 04:40:49 PM PDT 24
Finished Aug 14 04:40:54 PM PDT 24
Peak memory 216008 kb
Host smart-fe9272a1-c91f-4e13-8937-c77459f8df4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180028551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4180028551
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.697147769
Short name T743
Test name
Test status
Simulation time 71238313 ps
CPU time 1.58 seconds
Started Aug 14 04:40:53 PM PDT 24
Finished Aug 14 04:40:55 PM PDT 24
Peak memory 208804 kb
Host smart-ac82d05f-5c07-4693-b746-137eb8360690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697147769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.697147769
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2026534268
Short name T319
Test name
Test status
Simulation time 97567142 ps
CPU time 2.25 seconds
Started Aug 14 04:40:37 PM PDT 24
Finished Aug 14 04:40:39 PM PDT 24
Peak memory 214796 kb
Host smart-79c74f39-4097-4e4d-a9b9-c302cec6100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026534268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2026534268
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.154259806
Short name T399
Test name
Test status
Simulation time 249799058 ps
CPU time 3.58 seconds
Started Aug 14 04:40:37 PM PDT 24
Finished Aug 14 04:40:41 PM PDT 24
Peak memory 219716 kb
Host smart-5edcaf2e-c245-46ea-8ccb-c0f143e6cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154259806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.154259806
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.170656527
Short name T735
Test name
Test status
Simulation time 640769734 ps
CPU time 5.67 seconds
Started Aug 14 04:40:50 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 207756 kb
Host smart-db786143-5c01-481f-8dc9-22e9d0808236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170656527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.170656527
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.703207599
Short name T689
Test name
Test status
Simulation time 224679958 ps
CPU time 2.72 seconds
Started Aug 14 04:40:33 PM PDT 24
Finished Aug 14 04:40:36 PM PDT 24
Peak memory 209260 kb
Host smart-4e591c06-df41-48cf-866e-a4f7ab705972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703207599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.703207599
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1159051352
Short name T760
Test name
Test status
Simulation time 1726186300 ps
CPU time 22.21 seconds
Started Aug 14 04:40:40 PM PDT 24
Finished Aug 14 04:41:03 PM PDT 24
Peak memory 208744 kb
Host smart-15590b56-71ba-4d9c-8b9a-6a11d3222a89
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159051352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1159051352
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2897859473
Short name T677
Test name
Test status
Simulation time 35817064 ps
CPU time 2.41 seconds
Started Aug 14 04:40:40 PM PDT 24
Finished Aug 14 04:40:43 PM PDT 24
Peak memory 207416 kb
Host smart-d6669532-a58a-4a61-bf7f-aff3ee1b512f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897859473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2897859473
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2754381064
Short name T661
Test name
Test status
Simulation time 231053774 ps
CPU time 3.86 seconds
Started Aug 14 04:40:38 PM PDT 24
Finished Aug 14 04:40:47 PM PDT 24
Peak memory 207484 kb
Host smart-ba88c767-dfa5-4964-ad36-14686b86efd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754381064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2754381064
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1188286571
Short name T418
Test name
Test status
Simulation time 60335675 ps
CPU time 2.37 seconds
Started Aug 14 04:41:15 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 208536 kb
Host smart-c47abd97-521e-4bc3-948f-1dd5091977fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188286571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1188286571
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2053293393
Short name T700
Test name
Test status
Simulation time 126275887 ps
CPU time 3.47 seconds
Started Aug 14 04:40:46 PM PDT 24
Finished Aug 14 04:40:54 PM PDT 24
Peak memory 208812 kb
Host smart-41916d83-13ff-482b-b9cc-fa95c8ce4c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053293393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2053293393
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3718137205
Short name T645
Test name
Test status
Simulation time 93724062 ps
CPU time 4.78 seconds
Started Aug 14 04:41:13 PM PDT 24
Finished Aug 14 04:41:18 PM PDT 24
Peak memory 209232 kb
Host smart-b59f4c3b-928f-406f-ac7e-0c192f3d34f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718137205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3718137205
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.926287042
Short name T205
Test name
Test status
Simulation time 303369958 ps
CPU time 1.94 seconds
Started Aug 14 04:40:47 PM PDT 24
Finished Aug 14 04:40:49 PM PDT 24
Peak memory 210456 kb
Host smart-46884529-8702-4e0a-bc2d-4605ea9be6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926287042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.926287042
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1942059144
Short name T711
Test name
Test status
Simulation time 49267366 ps
CPU time 0.8 seconds
Started Aug 14 04:41:07 PM PDT 24
Finished Aug 14 04:41:07 PM PDT 24
Peak memory 206416 kb
Host smart-33c77e17-b2bc-4eee-b17f-6a2f9feaa594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942059144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1942059144
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.4186423643
Short name T415
Test name
Test status
Simulation time 333213823 ps
CPU time 3.2 seconds
Started Aug 14 04:40:48 PM PDT 24
Finished Aug 14 04:40:51 PM PDT 24
Peak memory 214684 kb
Host smart-a7976127-3cd7-42ad-8ec6-ccc131096650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186423643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.4186423643
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.4182896864
Short name T214
Test name
Test status
Simulation time 3704439368 ps
CPU time 61.68 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 218692 kb
Host smart-91ae1246-fa1f-4182-92d1-c2bc0a97a449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182896864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4182896864
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3954480883
Short name T678
Test name
Test status
Simulation time 984449351 ps
CPU time 6.95 seconds
Started Aug 14 04:41:13 PM PDT 24
Finished Aug 14 04:41:21 PM PDT 24
Peak memory 214696 kb
Host smart-f84cff85-134b-40cb-ad52-d2b88d09e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954480883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3954480883
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4073526656
Short name T438
Test name
Test status
Simulation time 42348980 ps
CPU time 2.11 seconds
Started Aug 14 04:40:56 PM PDT 24
Finished Aug 14 04:40:58 PM PDT 24
Peak memory 220116 kb
Host smart-d2d3bce1-382d-4419-8449-e39be554c3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073526656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4073526656
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2904451928
Short name T192
Test name
Test status
Simulation time 1155594193 ps
CPU time 5.74 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:18 PM PDT 24
Peak memory 208540 kb
Host smart-3d9afd73-faa5-42f6-8003-8f73f0101143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904451928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2904451928
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1553062124
Short name T550
Test name
Test status
Simulation time 535478166 ps
CPU time 4.22 seconds
Started Aug 14 04:41:00 PM PDT 24
Finished Aug 14 04:41:04 PM PDT 24
Peak memory 207124 kb
Host smart-113f6f14-f568-407e-b057-51ef200a595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553062124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1553062124
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2452611931
Short name T501
Test name
Test status
Simulation time 144710113 ps
CPU time 1.75 seconds
Started Aug 14 04:41:21 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 207404 kb
Host smart-89f31017-f9a3-4d12-ae0d-cb35630fdc8c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452611931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2452611931
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2422363525
Short name T841
Test name
Test status
Simulation time 132936347 ps
CPU time 4.27 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:06 PM PDT 24
Peak memory 209152 kb
Host smart-ff7372c2-1c59-4385-8ab5-ffd3a001ac77
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422363525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2422363525
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3998840929
Short name T448
Test name
Test status
Simulation time 3571985858 ps
CPU time 24.86 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:39 PM PDT 24
Peak memory 207536 kb
Host smart-9f9675cf-3635-4691-b92c-6f7718107b30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998840929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3998840929
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2387587537
Short name T479
Test name
Test status
Simulation time 2799542793 ps
CPU time 27.41 seconds
Started Aug 14 04:40:58 PM PDT 24
Finished Aug 14 04:41:25 PM PDT 24
Peak memory 208724 kb
Host smart-24fdaede-9fc7-4959-aa83-6a746f17b32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387587537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2387587537
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2040632594
Short name T790
Test name
Test status
Simulation time 69609596 ps
CPU time 4.09 seconds
Started Aug 14 04:40:50 PM PDT 24
Finished Aug 14 04:40:54 PM PDT 24
Peak memory 220556 kb
Host smart-0f385d0d-1c14-4b9b-abb9-dd63cdff9a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040632594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2040632594
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1234856596
Short name T899
Test name
Test status
Simulation time 34032161 ps
CPU time 2.12 seconds
Started Aug 14 04:40:46 PM PDT 24
Finished Aug 14 04:40:53 PM PDT 24
Peak memory 210384 kb
Host smart-cf9257bc-0f2b-4139-b114-11577226aaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234856596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1234856596
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.4221065549
Short name T560
Test name
Test status
Simulation time 24478689 ps
CPU time 0.83 seconds
Started Aug 14 04:41:09 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 206420 kb
Host smart-60ad3045-5063-4dce-885f-6edffb85f150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221065549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.4221065549
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1246735593
Short name T387
Test name
Test status
Simulation time 66430000 ps
CPU time 4.48 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 216068 kb
Host smart-f4ddf3aa-8c00-4095-b674-797e1a89ba5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246735593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1246735593
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1382738759
Short name T68
Test name
Test status
Simulation time 1931372629 ps
CPU time 6.36 seconds
Started Aug 14 04:40:44 PM PDT 24
Finished Aug 14 04:40:50 PM PDT 24
Peak memory 223176 kb
Host smart-c45427a5-7f0a-4a44-b778-fef41e0989d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382738759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1382738759
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.408754425
Short name T635
Test name
Test status
Simulation time 1322538236 ps
CPU time 3.9 seconds
Started Aug 14 04:40:55 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 209896 kb
Host smart-5d48824a-f8b6-4252-8932-02db60e219c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408754425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.408754425
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.683087147
Short name T301
Test name
Test status
Simulation time 421499872 ps
CPU time 3.04 seconds
Started Aug 14 04:40:53 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 216160 kb
Host smart-f453051c-845b-4785-95c9-d157e2256678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683087147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.683087147
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.4160804948
Short name T578
Test name
Test status
Simulation time 354063610 ps
CPU time 3.33 seconds
Started Aug 14 04:41:10 PM PDT 24
Finished Aug 14 04:41:14 PM PDT 24
Peak memory 214736 kb
Host smart-d463cc1f-f674-422f-822b-f3dfafc512fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160804948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.4160804948
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2256498969
Short name T245
Test name
Test status
Simulation time 141650842 ps
CPU time 2.28 seconds
Started Aug 14 04:41:07 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 222976 kb
Host smart-1edaac8c-fac1-4a68-a1c0-dc9946cdd644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256498969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2256498969
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.342108253
Short name T727
Test name
Test status
Simulation time 213451695 ps
CPU time 6.07 seconds
Started Aug 14 04:40:44 PM PDT 24
Finished Aug 14 04:40:50 PM PDT 24
Peak memory 218532 kb
Host smart-f2f7bc6e-d4ba-430f-a45f-603773233869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342108253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.342108253
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3390679464
Short name T880
Test name
Test status
Simulation time 595196813 ps
CPU time 5.06 seconds
Started Aug 14 04:40:47 PM PDT 24
Finished Aug 14 04:40:52 PM PDT 24
Peak memory 208708 kb
Host smart-55d9dc60-2a48-44fd-b697-118c86b78579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390679464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3390679464
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1035612041
Short name T474
Test name
Test status
Simulation time 36969463 ps
CPU time 2.17 seconds
Started Aug 14 04:41:18 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 207364 kb
Host smart-0102329a-c45e-4c35-be7b-c1213d1e5f53
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035612041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1035612041
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1104192086
Short name T514
Test name
Test status
Simulation time 40243025 ps
CPU time 2.24 seconds
Started Aug 14 04:40:57 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 207404 kb
Host smart-6b957cb1-89d5-4690-95dc-2c33be6fac66
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104192086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1104192086
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3577973697
Short name T249
Test name
Test status
Simulation time 570414738 ps
CPU time 4.77 seconds
Started Aug 14 04:41:03 PM PDT 24
Finished Aug 14 04:41:07 PM PDT 24
Peak memory 209292 kb
Host smart-bf94dc95-9694-4489-89cf-027d2ac216cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577973697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3577973697
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2838036880
Short name T895
Test name
Test status
Simulation time 423205769 ps
CPU time 3.28 seconds
Started Aug 14 04:41:19 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 210148 kb
Host smart-c9e85d5e-dd4f-4a92-bf0d-acb7a985f4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838036880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2838036880
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.813650708
Short name T571
Test name
Test status
Simulation time 1149259408 ps
CPU time 4.82 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 208836 kb
Host smart-9359df52-7048-4511-b206-47b61723cfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813650708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.813650708
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3141591296
Short name T640
Test name
Test status
Simulation time 1698152420 ps
CPU time 12.47 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 217476 kb
Host smart-0442e923-1b6b-4ba8-82e9-c1130e02efec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141591296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3141591296
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1924431229
Short name T329
Test name
Test status
Simulation time 32420927 ps
CPU time 2.48 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:05 PM PDT 24
Peak memory 214736 kb
Host smart-139bcf96-ad4b-4336-a58b-8e2e4760bb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924431229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1924431229
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3562186806
Short name T382
Test name
Test status
Simulation time 302037650 ps
CPU time 2.36 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:19 PM PDT 24
Peak memory 210600 kb
Host smart-f0e8a168-b424-4b80-bb10-ca25d2f531bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562186806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3562186806
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2509320085
Short name T436
Test name
Test status
Simulation time 12230046 ps
CPU time 0.83 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:03 PM PDT 24
Peak memory 206384 kb
Host smart-2a8f6e00-e3d3-4aab-b490-3ee1620c0fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509320085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2509320085
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3688574820
Short name T384
Test name
Test status
Simulation time 65499632 ps
CPU time 2.6 seconds
Started Aug 14 04:41:03 PM PDT 24
Finished Aug 14 04:41:05 PM PDT 24
Peak memory 214756 kb
Host smart-1ecc530d-6b87-44d2-bca2-efc1db805796
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688574820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3688574820
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4239655215
Short name T34
Test name
Test status
Simulation time 32530760 ps
CPU time 2.14 seconds
Started Aug 14 04:41:07 PM PDT 24
Finished Aug 14 04:41:09 PM PDT 24
Peak memory 209312 kb
Host smart-939de862-d2d7-48b9-9806-4c1ae08740cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239655215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4239655215
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.710057601
Short name T24
Test name
Test status
Simulation time 94934416 ps
CPU time 3.73 seconds
Started Aug 14 04:40:57 PM PDT 24
Finished Aug 14 04:41:00 PM PDT 24
Peak memory 222896 kb
Host smart-9b14f855-8df3-4726-b28e-6e8c9df0f2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710057601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.710057601
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1553559610
Short name T646
Test name
Test status
Simulation time 462516598 ps
CPU time 9.7 seconds
Started Aug 14 04:41:13 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 214496 kb
Host smart-a3cbad79-d39d-4973-8a49-8334542b3f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553559610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1553559610
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1155946710
Short name T503
Test name
Test status
Simulation time 160054908 ps
CPU time 3.97 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:16 PM PDT 24
Peak memory 209932 kb
Host smart-e13ba866-b0db-4904-b2d6-726ffe64e794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155946710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1155946710
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2087215817
Short name T864
Test name
Test status
Simulation time 66045345 ps
CPU time 4.18 seconds
Started Aug 14 04:41:06 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 214720 kb
Host smart-b5153b06-3bed-4a8d-9e63-28c2a8f27042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087215817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2087215817
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.420375490
Short name T327
Test name
Test status
Simulation time 2898940204 ps
CPU time 36.09 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:55 PM PDT 24
Peak memory 208996 kb
Host smart-d48886a4-1b2a-4f94-95c8-185ab5002de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420375490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.420375490
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2855394140
Short name T620
Test name
Test status
Simulation time 1339043721 ps
CPU time 9.5 seconds
Started Aug 14 04:41:15 PM PDT 24
Finished Aug 14 04:41:25 PM PDT 24
Peak memory 209376 kb
Host smart-c1e6933c-463e-4c68-9162-a608a8bd3a6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855394140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2855394140
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.579927265
Short name T696
Test name
Test status
Simulation time 211262436 ps
CPU time 2.61 seconds
Started Aug 14 04:41:01 PM PDT 24
Finished Aug 14 04:41:04 PM PDT 24
Peak memory 208820 kb
Host smart-8113c4c3-6d3b-4ed8-86e8-0e4d77ea33ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579927265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.579927265
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2749406320
Short name T365
Test name
Test status
Simulation time 43579753 ps
CPU time 2.45 seconds
Started Aug 14 04:41:10 PM PDT 24
Finished Aug 14 04:41:12 PM PDT 24
Peak memory 206356 kb
Host smart-67c4675b-87a6-4fa1-86a0-6cffd8e61762
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749406320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2749406320
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1574284429
Short name T287
Test name
Test status
Simulation time 62664590 ps
CPU time 3.06 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:19 PM PDT 24
Peak memory 210324 kb
Host smart-d5e71cb9-e13d-47ec-88ff-e0d1c7cb710a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574284429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1574284429
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2169494964
Short name T614
Test name
Test status
Simulation time 175922669 ps
CPU time 2.59 seconds
Started Aug 14 04:41:01 PM PDT 24
Finished Aug 14 04:41:04 PM PDT 24
Peak memory 208856 kb
Host smart-77a26370-2b56-4540-8c20-33497d2ef384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169494964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2169494964
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.447711377
Short name T630
Test name
Test status
Simulation time 846013712 ps
CPU time 20.75 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 217384 kb
Host smart-1e4bfa16-fd94-4142-b815-fc20d0ff5851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447711377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.447711377
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.4157520033
Short name T742
Test name
Test status
Simulation time 1353872987 ps
CPU time 15.93 seconds
Started Aug 14 04:41:01 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 209952 kb
Host smart-0c68ec81-f3ab-450e-8316-9ebace473529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157520033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.4157520033
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4199127240
Short name T653
Test name
Test status
Simulation time 113523495 ps
CPU time 2.84 seconds
Started Aug 14 04:41:10 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 211056 kb
Host smart-9bbf73ab-69ef-4cb7-8347-9c456a388908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199127240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4199127240
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2112821265
Short name T802
Test name
Test status
Simulation time 67801887 ps
CPU time 2.86 seconds
Started Aug 14 04:40:56 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 214160 kb
Host smart-ba4a84dd-6309-437f-b7c7-6be6312ddf3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112821265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2112821265
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1840335149
Short name T27
Test name
Test status
Simulation time 1504442054 ps
CPU time 20.6 seconds
Started Aug 14 04:41:09 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 215104 kb
Host smart-12c847ef-d10d-4e97-8ad5-412ed5e77dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840335149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1840335149
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3821651908
Short name T819
Test name
Test status
Simulation time 69588267 ps
CPU time 2.14 seconds
Started Aug 14 04:41:05 PM PDT 24
Finished Aug 14 04:41:07 PM PDT 24
Peak memory 208144 kb
Host smart-144ad1b0-a91b-46d1-ab0a-65e4cf976e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821651908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3821651908
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2978396276
Short name T38
Test name
Test status
Simulation time 418282151 ps
CPU time 4.25 seconds
Started Aug 14 04:41:08 PM PDT 24
Finished Aug 14 04:41:12 PM PDT 24
Peak memory 214800 kb
Host smart-5e849d9a-a33f-41ac-8a50-502eddca848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978396276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2978396276
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.79827753
Short name T470
Test name
Test status
Simulation time 300556731 ps
CPU time 2.06 seconds
Started Aug 14 04:41:15 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 214648 kb
Host smart-dc518634-8ccd-4fb5-ac3a-21facbcca3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79827753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.79827753
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.964935002
Short name T343
Test name
Test status
Simulation time 149065974 ps
CPU time 2.31 seconds
Started Aug 14 04:40:59 PM PDT 24
Finished Aug 14 04:41:01 PM PDT 24
Peak memory 220072 kb
Host smart-3cb0b590-053e-479f-9924-228914e5a690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964935002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.964935002
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3453955626
Short name T890
Test name
Test status
Simulation time 1722323240 ps
CPU time 17.66 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 209976 kb
Host smart-a14b3e4a-c0fc-44e5-820a-7f90b29cd38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453955626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3453955626
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2448849801
Short name T672
Test name
Test status
Simulation time 447873722 ps
CPU time 3.33 seconds
Started Aug 14 04:41:03 PM PDT 24
Finished Aug 14 04:41:06 PM PDT 24
Peak memory 207164 kb
Host smart-9b668d54-4137-4cb7-bdba-81c77d085498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448849801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2448849801
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.158901038
Short name T609
Test name
Test status
Simulation time 1041174685 ps
CPU time 25.89 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:38 PM PDT 24
Peak memory 209264 kb
Host smart-e156449f-c19d-4ba1-852f-0db083f7e50a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158901038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.158901038
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1368434512
Short name T257
Test name
Test status
Simulation time 158894460 ps
CPU time 3.11 seconds
Started Aug 14 04:40:58 PM PDT 24
Finished Aug 14 04:41:06 PM PDT 24
Peak memory 209512 kb
Host smart-87d85f19-eec6-4566-8ae8-5b2860e2a4da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368434512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1368434512
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.58019051
Short name T551
Test name
Test status
Simulation time 83713165 ps
CPU time 3.33 seconds
Started Aug 14 04:41:03 PM PDT 24
Finished Aug 14 04:41:07 PM PDT 24
Peak memory 207352 kb
Host smart-de82fa68-9b95-4eb5-a61e-f24d02c44e8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58019051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.58019051
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.284148240
Short name T129
Test name
Test status
Simulation time 64520146 ps
CPU time 2.34 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:16 PM PDT 24
Peak memory 218576 kb
Host smart-bf651f09-dbaf-4bd2-a7e8-f23bbbeeab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284148240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.284148240
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3444545858
Short name T400
Test name
Test status
Simulation time 1191650386 ps
CPU time 30.05 seconds
Started Aug 14 04:41:00 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 208804 kb
Host smart-f0c6e848-7529-4acf-888a-db4055ad55ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444545858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3444545858
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1136360787
Short name T544
Test name
Test status
Simulation time 126356893 ps
CPU time 4.54 seconds
Started Aug 14 04:41:15 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 207672 kb
Host smart-2bbb8467-5954-4131-8500-6a7da80d6c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136360787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1136360787
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2113297766
Short name T379
Test name
Test status
Simulation time 125532414 ps
CPU time 2.65 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 210940 kb
Host smart-4972aabd-1350-4274-bdc0-fc18231b2533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113297766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2113297766
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2220389612
Short name T568
Test name
Test status
Simulation time 26263956 ps
CPU time 0.69 seconds
Started Aug 14 04:41:22 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 206416 kb
Host smart-20e46260-a510-4fd5-8b2a-56dac4f40688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220389612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2220389612
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2437289762
Short name T41
Test name
Test status
Simulation time 724614452 ps
CPU time 10.07 seconds
Started Aug 14 04:41:01 PM PDT 24
Finished Aug 14 04:41:11 PM PDT 24
Peak memory 209992 kb
Host smart-f20a1c3f-189c-485b-b977-3062d4246da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437289762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2437289762
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3551798592
Short name T55
Test name
Test status
Simulation time 1636091187 ps
CPU time 15.77 seconds
Started Aug 14 04:41:09 PM PDT 24
Finished Aug 14 04:41:25 PM PDT 24
Peak memory 209388 kb
Host smart-8fdb65e3-189a-4c9b-848b-37fce1ccd404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551798592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3551798592
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3818691176
Short name T590
Test name
Test status
Simulation time 90950797 ps
CPU time 3.74 seconds
Started Aug 14 04:40:53 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 222772 kb
Host smart-1358df59-3c0b-4492-988e-93acb8040228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818691176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3818691176
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2278231205
Short name T433
Test name
Test status
Simulation time 271686266 ps
CPU time 3.34 seconds
Started Aug 14 04:41:20 PM PDT 24
Finished Aug 14 04:41:23 PM PDT 24
Peak memory 220020 kb
Host smart-47cbae95-48c6-46b7-bbe3-2bcd54f4d3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278231205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2278231205
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3304462253
Short name T303
Test name
Test status
Simulation time 436051340 ps
CPU time 5.23 seconds
Started Aug 14 04:41:17 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 218792 kb
Host smart-255897ee-6b9b-4081-af41-fd1612a81f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304462253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3304462253
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.260757792
Short name T655
Test name
Test status
Simulation time 45641911 ps
CPU time 2.41 seconds
Started Aug 14 04:41:18 PM PDT 24
Finished Aug 14 04:41:21 PM PDT 24
Peak memory 208948 kb
Host smart-31411edc-4c6b-4880-bc3e-3ed1b8364c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260757792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.260757792
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3174813402
Short name T426
Test name
Test status
Simulation time 401722660 ps
CPU time 3.78 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:33 PM PDT 24
Peak memory 207680 kb
Host smart-1599e19a-abad-41f2-941c-20034a3e52fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174813402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3174813402
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3578153874
Short name T631
Test name
Test status
Simulation time 132939319 ps
CPU time 2.29 seconds
Started Aug 14 04:41:17 PM PDT 24
Finished Aug 14 04:41:19 PM PDT 24
Peak memory 207396 kb
Host smart-804c3f70-ce79-4b50-b302-3d8e00fe74e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578153874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3578153874
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1808147793
Short name T549
Test name
Test status
Simulation time 290366185 ps
CPU time 4.29 seconds
Started Aug 14 04:41:10 PM PDT 24
Finished Aug 14 04:41:14 PM PDT 24
Peak memory 207448 kb
Host smart-936b68b7-da40-4f23-a8df-42b260d71704
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808147793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1808147793
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3141614850
Short name T273
Test name
Test status
Simulation time 47781213 ps
CPU time 2.36 seconds
Started Aug 14 04:41:06 PM PDT 24
Finished Aug 14 04:41:08 PM PDT 24
Peak memory 210360 kb
Host smart-d90d3f92-9e6c-42c5-9205-eefedc5e3104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141614850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3141614850
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1424805608
Short name T188
Test name
Test status
Simulation time 142828093 ps
CPU time 2.58 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:05 PM PDT 24
Peak memory 207356 kb
Host smart-6b33a047-8b92-4263-aa92-166e294a0c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424805608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1424805608
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1286847838
Short name T888
Test name
Test status
Simulation time 86152005 ps
CPU time 2.84 seconds
Started Aug 14 04:40:53 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 208220 kb
Host smart-bc0db71f-8228-4211-8b62-69d7f50387d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286847838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1286847838
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1230798133
Short name T639
Test name
Test status
Simulation time 64557024 ps
CPU time 0.88 seconds
Started Aug 14 04:41:00 PM PDT 24
Finished Aug 14 04:41:01 PM PDT 24
Peak memory 206316 kb
Host smart-597a735c-d916-4526-a7c7-4871169f2aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230798133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1230798133
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3349002793
Short name T363
Test name
Test status
Simulation time 203477697 ps
CPU time 4.02 seconds
Started Aug 14 04:41:15 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 214736 kb
Host smart-6ceadd34-d4e7-4c7b-8f9c-98ee79cd5500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349002793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3349002793
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3675741159
Short name T849
Test name
Test status
Simulation time 1927175549 ps
CPU time 12.23 seconds
Started Aug 14 04:41:08 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 210040 kb
Host smart-579fe95e-d7a6-4890-a8e3-d11817c2a6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675741159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3675741159
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3053087542
Short name T320
Test name
Test status
Simulation time 231439483 ps
CPU time 4.71 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 214756 kb
Host smart-bb34253e-8f06-4f9e-bc11-ad20f46ea9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053087542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3053087542
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1061833948
Short name T35
Test name
Test status
Simulation time 210399500 ps
CPU time 3.05 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:28 PM PDT 24
Peak memory 214632 kb
Host smart-85180f37-7467-4950-a403-2ca3cd6eb66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061833948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1061833948
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.832123464
Short name T628
Test name
Test status
Simulation time 49602152 ps
CPU time 3.26 seconds
Started Aug 14 04:41:24 PM PDT 24
Finished Aug 14 04:41:27 PM PDT 24
Peak memory 208880 kb
Host smart-00951a32-11f7-4d80-9d83-e70ea731942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832123464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.832123464
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1608832760
Short name T840
Test name
Test status
Simulation time 138748378 ps
CPU time 4.25 seconds
Started Aug 14 04:41:06 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 209296 kb
Host smart-a014f922-2e25-44a8-b076-4cc6c538dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608832760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1608832760
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.15894139
Short name T698
Test name
Test status
Simulation time 108185381 ps
CPU time 3.6 seconds
Started Aug 14 04:41:21 PM PDT 24
Finished Aug 14 04:41:25 PM PDT 24
Peak memory 207360 kb
Host smart-62b0ccd2-7721-4867-91e0-d05a7d75f10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15894139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.15894139
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3346436566
Short name T598
Test name
Test status
Simulation time 3561252805 ps
CPU time 24.63 seconds
Started Aug 14 04:41:15 PM PDT 24
Finished Aug 14 04:41:40 PM PDT 24
Peak memory 209672 kb
Host smart-5084c322-1d81-4228-b12a-16c34d16a6bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346436566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3346436566
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.352998999
Short name T897
Test name
Test status
Simulation time 66447961 ps
CPU time 3.2 seconds
Started Aug 14 04:41:17 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 208468 kb
Host smart-9d3a5427-6ca0-430d-829e-da8f3ea039b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352998999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.352998999
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1664010312
Short name T435
Test name
Test status
Simulation time 105072123 ps
CPU time 3.16 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:15 PM PDT 24
Peak memory 208992 kb
Host smart-c39d74b0-9178-4479-bc07-3741a5ea90f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664010312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1664010312
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2515671182
Short name T16
Test name
Test status
Simulation time 65084583 ps
CPU time 1.43 seconds
Started Aug 14 04:41:03 PM PDT 24
Finished Aug 14 04:41:05 PM PDT 24
Peak memory 207860 kb
Host smart-bbbf2299-b599-4ffd-82db-d896a17902ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515671182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2515671182
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3381076044
Short name T130
Test name
Test status
Simulation time 53391861 ps
CPU time 1.88 seconds
Started Aug 14 04:41:21 PM PDT 24
Finished Aug 14 04:41:23 PM PDT 24
Peak memory 208976 kb
Host smart-74c16ba6-da23-4613-a9b6-51bb64e167a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381076044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3381076044
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3994908889
Short name T276
Test name
Test status
Simulation time 610176076 ps
CPU time 22.49 seconds
Started Aug 14 04:41:19 PM PDT 24
Finished Aug 14 04:41:42 PM PDT 24
Peak memory 216404 kb
Host smart-28030eb1-e799-4b7d-b156-87b47f12c7e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994908889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3994908889
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1503662251
Short name T407
Test name
Test status
Simulation time 201177440 ps
CPU time 5.74 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:21 PM PDT 24
Peak memory 209388 kb
Host smart-9f885a68-de3a-4f5e-9395-536592124b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503662251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1503662251
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3650904405
Short name T401
Test name
Test status
Simulation time 134418064 ps
CPU time 3.8 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:18 PM PDT 24
Peak memory 210964 kb
Host smart-5b86cfdd-18c4-4758-ba55-73f8e639dafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650904405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3650904405
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2654670699
Short name T1
Test name
Test status
Simulation time 12621604 ps
CPU time 0.74 seconds
Started Aug 14 04:41:09 PM PDT 24
Finished Aug 14 04:41:09 PM PDT 24
Peak memory 206416 kb
Host smart-c58ee5f6-18dc-4d05-9ae1-16c7c8217bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654670699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2654670699
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1948847522
Short name T291
Test name
Test status
Simulation time 101793566 ps
CPU time 2.93 seconds
Started Aug 14 04:41:13 PM PDT 24
Finished Aug 14 04:41:16 PM PDT 24
Peak memory 215004 kb
Host smart-da98e4f4-d531-44d9-a4e6-748d62ca001b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948847522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1948847522
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1497375093
Short name T22
Test name
Test status
Simulation time 74331515 ps
CPU time 2.14 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:19 PM PDT 24
Peak memory 217716 kb
Host smart-5279af48-dc29-4a24-ab4c-02b1cc884c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497375093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1497375093
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1438929467
Short name T913
Test name
Test status
Simulation time 94042561 ps
CPU time 1.92 seconds
Started Aug 14 04:41:19 PM PDT 24
Finished Aug 14 04:41:21 PM PDT 24
Peak memory 218644 kb
Host smart-09bf340c-67c3-492f-9194-d04cb7150d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438929467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1438929467
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3475437923
Short name T768
Test name
Test status
Simulation time 354111465 ps
CPU time 4.14 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:18 PM PDT 24
Peak memory 214764 kb
Host smart-c3270a77-8ccb-4299-b008-caac2f56070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475437923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3475437923
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3847700712
Short name T780
Test name
Test status
Simulation time 34746593 ps
CPU time 1.99 seconds
Started Aug 14 04:41:10 PM PDT 24
Finished Aug 14 04:41:12 PM PDT 24
Peak memory 214752 kb
Host smart-da67f9f4-132a-4f28-8d3a-fea8bf2d01d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847700712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3847700712
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1657479678
Short name T406
Test name
Test status
Simulation time 73269188 ps
CPU time 1.27 seconds
Started Aug 14 04:41:13 PM PDT 24
Finished Aug 14 04:41:15 PM PDT 24
Peak memory 206644 kb
Host smart-ae27ce64-94c4-4d36-b192-2e0a8a348c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657479678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1657479678
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.137055644
Short name T828
Test name
Test status
Simulation time 187335045 ps
CPU time 4.3 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 207912 kb
Host smart-bb8de381-0c5d-42c8-b999-cb43e6eada7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137055644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.137055644
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2157091562
Short name T617
Test name
Test status
Simulation time 972516714 ps
CPU time 9.67 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:24 PM PDT 24
Peak memory 207548 kb
Host smart-d4605582-d8ed-4979-b67e-8c35db7ef072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157091562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2157091562
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1190636666
Short name T572
Test name
Test status
Simulation time 89767132 ps
CPU time 1.85 seconds
Started Aug 14 04:41:11 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 207364 kb
Host smart-9b5d076f-6b86-4266-a914-f4aa928ba1d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190636666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1190636666
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3898377356
Short name T703
Test name
Test status
Simulation time 2329536853 ps
CPU time 23.4 seconds
Started Aug 14 04:41:13 PM PDT 24
Finished Aug 14 04:41:36 PM PDT 24
Peak memory 208936 kb
Host smart-5fda81a2-d9cc-4854-893b-695aab51d588
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898377356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3898377356
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.451799186
Short name T622
Test name
Test status
Simulation time 153454480 ps
CPU time 4.68 seconds
Started Aug 14 04:41:24 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 209192 kb
Host smart-8d7f2298-5d9f-4ed9-b7b8-ddf92fba3669
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451799186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.451799186
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1418399371
Short name T883
Test name
Test status
Simulation time 32215822 ps
CPU time 1.64 seconds
Started Aug 14 04:41:53 PM PDT 24
Finished Aug 14 04:41:55 PM PDT 24
Peak memory 215836 kb
Host smart-30a51525-90da-40f7-9f70-831c42f44dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418399371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1418399371
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1978603120
Short name T564
Test name
Test status
Simulation time 345886897 ps
CPU time 4.69 seconds
Started Aug 14 04:41:17 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 207308 kb
Host smart-56e83c29-a88b-4be5-9c42-289ca38df753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978603120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1978603120
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3424059711
Short name T248
Test name
Test status
Simulation time 2082081394 ps
CPU time 20.27 seconds
Started Aug 14 04:41:18 PM PDT 24
Finished Aug 14 04:41:38 PM PDT 24
Peak memory 222912 kb
Host smart-c13e662e-c872-419e-ace8-b0cb6f65200d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424059711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3424059711
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2034687943
Short name T713
Test name
Test status
Simulation time 1625494265 ps
CPU time 12.51 seconds
Started Aug 14 04:41:08 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 223020 kb
Host smart-49754cd5-2b72-46b9-8f08-d6629671637b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034687943 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2034687943
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1615880308
Short name T766
Test name
Test status
Simulation time 117165466 ps
CPU time 3.43 seconds
Started Aug 14 04:41:03 PM PDT 24
Finished Aug 14 04:41:07 PM PDT 24
Peak memory 207948 kb
Host smart-712bd89b-6517-4b60-b802-14a07ec3796b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615880308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1615880308
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2367283118
Short name T176
Test name
Test status
Simulation time 293426568 ps
CPU time 5.43 seconds
Started Aug 14 04:41:17 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 211044 kb
Host smart-ffd2b46f-d672-4dd0-b805-5564a13e7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367283118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2367283118
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.537382481
Short name T805
Test name
Test status
Simulation time 20439257 ps
CPU time 0.85 seconds
Started Aug 14 04:41:06 PM PDT 24
Finished Aug 14 04:41:07 PM PDT 24
Peak memory 206400 kb
Host smart-32d780ad-005c-4078-bfe9-10c738cff6cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537382481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.537382481
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3585456498
Short name T345
Test name
Test status
Simulation time 101254558 ps
CPU time 3.68 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 214748 kb
Host smart-356e9588-6d0e-4e67-b030-68fd0341fa2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585456498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3585456498
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.840197940
Short name T746
Test name
Test status
Simulation time 1174583871 ps
CPU time 15.26 seconds
Started Aug 14 04:41:05 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 221940 kb
Host smart-208f1c10-161d-4b7d-b891-36a79690dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840197940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.840197940
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.826530659
Short name T557
Test name
Test status
Simulation time 401760994 ps
CPU time 2.32 seconds
Started Aug 14 04:41:24 PM PDT 24
Finished Aug 14 04:41:26 PM PDT 24
Peak memory 208680 kb
Host smart-f58e8ff2-06b4-457e-9f59-e13145713665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826530659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.826530659
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3149064560
Short name T374
Test name
Test status
Simulation time 270331736 ps
CPU time 4.39 seconds
Started Aug 14 04:41:13 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 214768 kb
Host smart-c18a88bb-1e0c-4fd8-b87a-7b06a35b4f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149064560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3149064560
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1686748525
Short name T281
Test name
Test status
Simulation time 135463597 ps
CPU time 6.12 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:21 PM PDT 24
Peak memory 214880 kb
Host smart-434fd857-7c43-4ef4-be08-c623db4ca3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686748525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1686748525
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1705112349
Short name T806
Test name
Test status
Simulation time 83598737 ps
CPU time 3.7 seconds
Started Aug 14 04:41:09 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 222948 kb
Host smart-f111caa3-39c7-4620-a934-e8bf07d69d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705112349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1705112349
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2561249301
Short name T246
Test name
Test status
Simulation time 58944155 ps
CPU time 2.38 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:16 PM PDT 24
Peak memory 214760 kb
Host smart-7e197ec0-d180-4cae-b3be-6af3ea6d5b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561249301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2561249301
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1931745231
Short name T673
Test name
Test status
Simulation time 369715615 ps
CPU time 3.19 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:06 PM PDT 24
Peak memory 207360 kb
Host smart-94a78318-41cc-40ce-83d9-d628c93624de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931745231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1931745231
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1994671520
Short name T480
Test name
Test status
Simulation time 1403721929 ps
CPU time 9.2 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 209208 kb
Host smart-e35036e4-0505-4a9d-a12d-13873ca2602e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994671520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1994671520
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2725937068
Short name T251
Test name
Test status
Simulation time 789562554 ps
CPU time 23.05 seconds
Started Aug 14 04:41:18 PM PDT 24
Finished Aug 14 04:41:41 PM PDT 24
Peak memory 209040 kb
Host smart-d09a56c5-9728-4ae5-8b70-a781ca817cb2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725937068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2725937068
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2517464433
Short name T769
Test name
Test status
Simulation time 20693981 ps
CPU time 1.82 seconds
Started Aug 14 04:41:11 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 207416 kb
Host smart-2f8bdcd5-9654-412d-84cf-f188a10b1b11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517464433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2517464433
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.794319923
Short name T907
Test name
Test status
Simulation time 247625641 ps
CPU time 3 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 209560 kb
Host smart-3fff8ad2-d75c-4533-9bb6-da4650e248ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794319923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.794319923
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3568777017
Short name T623
Test name
Test status
Simulation time 412332655 ps
CPU time 6.49 seconds
Started Aug 14 04:41:04 PM PDT 24
Finished Aug 14 04:41:11 PM PDT 24
Peak memory 207692 kb
Host smart-8b086121-401c-45ff-bf97-ee675a40aab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568777017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3568777017
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2869159829
Short name T330
Test name
Test status
Simulation time 196757870 ps
CPU time 2.74 seconds
Started Aug 14 04:41:13 PM PDT 24
Finished Aug 14 04:41:15 PM PDT 24
Peak memory 220008 kb
Host smart-477bb411-e6d1-46b7-a033-032956082a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869159829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2869159829
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.101176274
Short name T763
Test name
Test status
Simulation time 45695089 ps
CPU time 0.72 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 206344 kb
Host smart-f5f298a2-08b6-471c-a584-d06755285646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101176274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.101176274
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1637890200
Short name T522
Test name
Test status
Simulation time 61079703 ps
CPU time 2.82 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:33 PM PDT 24
Peak memory 220008 kb
Host smart-19a323f6-0665-49fd-969d-a3c1be253b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637890200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1637890200
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2019927036
Short name T397
Test name
Test status
Simulation time 108839816 ps
CPU time 4.22 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 214832 kb
Host smart-40ce1093-ebb8-4239-90d3-8b5e3b025191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019927036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2019927036
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2747463541
Short name T92
Test name
Test status
Simulation time 2357642133 ps
CPU time 5.93 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 210012 kb
Host smart-17a00909-a5f5-4c15-979a-8e250ae3bd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747463541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2747463541
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.86093954
Short name T904
Test name
Test status
Simulation time 91516988 ps
CPU time 2.73 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:19 PM PDT 24
Peak memory 214720 kb
Host smart-da62240d-c7a4-4579-8058-6b5d0c63ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86093954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.86093954
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2082584483
Short name T567
Test name
Test status
Simulation time 438692483 ps
CPU time 4.37 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 220340 kb
Host smart-684f17e7-cd2d-47f5-b079-ba7be09c6e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082584483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2082584483
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1883923584
Short name T869
Test name
Test status
Simulation time 622113320 ps
CPU time 7.32 seconds
Started Aug 14 04:41:57 PM PDT 24
Finished Aug 14 04:42:05 PM PDT 24
Peak memory 208576 kb
Host smart-091070a7-0176-454b-a2f8-efa32c86f218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883923584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1883923584
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3498849063
Short name T704
Test name
Test status
Simulation time 25115351 ps
CPU time 1.98 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 208940 kb
Host smart-22703936-cb6e-4484-94ba-4d6f3a406758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498849063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3498849063
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1462014234
Short name T437
Test name
Test status
Simulation time 1233133060 ps
CPU time 6.02 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 209332 kb
Host smart-ea30f85a-032f-440b-bf6c-e5e7453e5522
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462014234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1462014234
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2580693316
Short name T298
Test name
Test status
Simulation time 74816798 ps
CPU time 1.76 seconds
Started Aug 14 04:41:22 PM PDT 24
Finished Aug 14 04:41:23 PM PDT 24
Peak memory 207388 kb
Host smart-c1a4db2d-8452-4c45-b77c-06091f4dfff0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580693316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2580693316
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.882951540
Short name T690
Test name
Test status
Simulation time 580410109 ps
CPU time 8.62 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:24 PM PDT 24
Peak memory 209088 kb
Host smart-53a92d00-e11f-4c45-86be-302172ae2f9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882951540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.882951540
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1319974659
Short name T856
Test name
Test status
Simulation time 608081195 ps
CPU time 6.22 seconds
Started Aug 14 04:41:24 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 208828 kb
Host smart-225703fe-1f9f-497f-8f36-646c8b0a1084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319974659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1319974659
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1899592562
Short name T867
Test name
Test status
Simulation time 688990887 ps
CPU time 4.18 seconds
Started Aug 14 04:41:31 PM PDT 24
Finished Aug 14 04:41:35 PM PDT 24
Peak memory 208876 kb
Host smart-d9f36884-5def-4471-92f5-c4a982096561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899592562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1899592562
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3415861477
Short name T26
Test name
Test status
Simulation time 491904017 ps
CPU time 5.74 seconds
Started Aug 14 04:41:21 PM PDT 24
Finished Aug 14 04:41:27 PM PDT 24
Peak memory 210700 kb
Host smart-1bc05807-17b4-415f-9aeb-c369948f7364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415861477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3415861477
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1243399074
Short name T699
Test name
Test status
Simulation time 69862777 ps
CPU time 0.77 seconds
Started Aug 14 04:41:33 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 206340 kb
Host smart-e93574aa-0fe2-40ba-8f29-4705ff027e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243399074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1243399074
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3804911349
Short name T409
Test name
Test status
Simulation time 114404413 ps
CPU time 4.21 seconds
Started Aug 14 04:41:24 PM PDT 24
Finished Aug 14 04:41:28 PM PDT 24
Peak memory 216064 kb
Host smart-6a57a94d-bd59-4f0a-8560-cc46f1a38a06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804911349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3804911349
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.202819756
Short name T94
Test name
Test status
Simulation time 141705909 ps
CPU time 3.54 seconds
Started Aug 14 04:41:20 PM PDT 24
Finished Aug 14 04:41:24 PM PDT 24
Peak memory 210068 kb
Host smart-c2af2544-0ae0-4164-8fcb-bece769e5887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202819756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.202819756
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2540499686
Short name T866
Test name
Test status
Simulation time 245038158 ps
CPU time 3.35 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:19 PM PDT 24
Peak memory 222012 kb
Host smart-a11c146f-9943-4ae2-bbd2-7a1fd15f4f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540499686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2540499686
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.235470724
Short name T839
Test name
Test status
Simulation time 112892129 ps
CPU time 3.76 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 218252 kb
Host smart-70fa33ad-0e8c-4c43-93a8-a2f3b7844b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235470724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.235470724
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.524446804
Short name T562
Test name
Test status
Simulation time 488574636 ps
CPU time 5.57 seconds
Started Aug 14 04:41:23 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 218624 kb
Host smart-41426edb-95fc-45d3-95af-8c2193fa5250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524446804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.524446804
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.716465785
Short name T559
Test name
Test status
Simulation time 125237314 ps
CPU time 2.36 seconds
Started Aug 14 04:41:33 PM PDT 24
Finished Aug 14 04:41:35 PM PDT 24
Peak memory 207900 kb
Host smart-075e65a5-71b7-42a7-9b52-44cfdf35da0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716465785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.716465785
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2464220146
Short name T432
Test name
Test status
Simulation time 181213203 ps
CPU time 5.24 seconds
Started Aug 14 04:41:18 PM PDT 24
Finished Aug 14 04:41:24 PM PDT 24
Peak memory 209196 kb
Host smart-f8abee8e-b3a5-41bd-a068-1888cf98f23a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464220146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2464220146
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3943433926
Short name T915
Test name
Test status
Simulation time 644473229 ps
CPU time 15.61 seconds
Started Aug 14 04:41:19 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 208440 kb
Host smart-7d5c90b4-023c-46e8-b84f-c3ab5cb41ee9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943433926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3943433926
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.731268809
Short name T594
Test name
Test status
Simulation time 631060735 ps
CPU time 4.82 seconds
Started Aug 14 04:41:18 PM PDT 24
Finished Aug 14 04:41:23 PM PDT 24
Peak memory 208540 kb
Host smart-149548d1-0e53-4771-9690-ef4db0ff2443
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731268809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.731268809
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2959870231
Short name T253
Test name
Test status
Simulation time 829999718 ps
CPU time 7.97 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:38 PM PDT 24
Peak memory 209708 kb
Host smart-7cce649f-d078-4ff7-a7a5-6ff8e09b5e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959870231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2959870231
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1626801815
Short name T510
Test name
Test status
Simulation time 408107561 ps
CPU time 3.14 seconds
Started Aug 14 04:41:19 PM PDT 24
Finished Aug 14 04:41:23 PM PDT 24
Peak memory 208648 kb
Host smart-2fcca747-455b-41b2-a544-4887e10a6f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626801815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1626801815
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2520048674
Short name T733
Test name
Test status
Simulation time 101320088 ps
CPU time 7 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:37 PM PDT 24
Peak memory 223104 kb
Host smart-bf9be142-4a67-4104-8026-b773480f0380
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520048674 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2520048674
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4140334827
Short name T740
Test name
Test status
Simulation time 204185054 ps
CPU time 5.55 seconds
Started Aug 14 04:41:19 PM PDT 24
Finished Aug 14 04:41:25 PM PDT 24
Peak memory 214820 kb
Host smart-42ef20ab-3c26-40f7-a244-59b527cc74d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140334827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4140334827
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1223109901
Short name T666
Test name
Test status
Simulation time 239626308 ps
CPU time 1.8 seconds
Started Aug 14 04:41:23 PM PDT 24
Finished Aug 14 04:41:25 PM PDT 24
Peak memory 210668 kb
Host smart-a805f264-1f12-4023-bcc4-b0873829eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223109901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1223109901
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2499090021
Short name T675
Test name
Test status
Simulation time 18976941 ps
CPU time 0.73 seconds
Started Aug 14 04:40:43 PM PDT 24
Finished Aug 14 04:40:44 PM PDT 24
Peak memory 206380 kb
Host smart-4043019f-ff98-4b3e-9871-cdcd5cace703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499090021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2499090021
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1652475527
Short name T412
Test name
Test status
Simulation time 708014534 ps
CPU time 10.1 seconds
Started Aug 14 04:40:38 PM PDT 24
Finished Aug 14 04:40:48 PM PDT 24
Peak memory 214740 kb
Host smart-9491fdaa-56cd-444e-bef1-8917fd8f1eea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652475527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1652475527
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1541232946
Short name T717
Test name
Test status
Simulation time 96751325 ps
CPU time 2.52 seconds
Started Aug 14 04:41:11 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 209800 kb
Host smart-dfd79e95-d998-43d3-abff-683c18120f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541232946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1541232946
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.307212610
Short name T721
Test name
Test status
Simulation time 47131574 ps
CPU time 1.92 seconds
Started Aug 14 04:40:30 PM PDT 24
Finished Aug 14 04:40:32 PM PDT 24
Peak memory 208616 kb
Host smart-aa8b0307-7c6e-4e94-a532-86c18b858aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307212610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.307212610
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1376757263
Short name T93
Test name
Test status
Simulation time 4107388429 ps
CPU time 64.9 seconds
Started Aug 14 04:40:40 PM PDT 24
Finished Aug 14 04:41:50 PM PDT 24
Peak memory 210852 kb
Host smart-b276039a-a45e-48a5-9f03-f54e605fa9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376757263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1376757263
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2475196139
Short name T829
Test name
Test status
Simulation time 827516335 ps
CPU time 4.21 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:41 PM PDT 24
Peak memory 214680 kb
Host smart-22a57d88-c93d-4ee0-b4a2-9c4ae3a9f9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475196139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2475196139
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.3420634334
Short name T905
Test name
Test status
Simulation time 574754621 ps
CPU time 10.78 seconds
Started Aug 14 04:40:43 PM PDT 24
Finished Aug 14 04:40:54 PM PDT 24
Peak memory 208624 kb
Host smart-d8dd947d-407c-44e4-aeab-20f34560f36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420634334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3420634334
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3857019608
Short name T103
Test name
Test status
Simulation time 347119463 ps
CPU time 7.16 seconds
Started Aug 14 04:40:48 PM PDT 24
Finished Aug 14 04:41:00 PM PDT 24
Peak memory 238332 kb
Host smart-d14f9ed8-d582-4a3e-b846-7b7c7c406cfb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857019608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3857019608
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.968091064
Short name T566
Test name
Test status
Simulation time 248582361 ps
CPU time 3.1 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:39 PM PDT 24
Peak memory 207212 kb
Host smart-3de10a5d-492a-4e5b-85fb-94e9637706e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968091064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.968091064
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3044178964
Short name T910
Test name
Test status
Simulation time 349183880 ps
CPU time 4.82 seconds
Started Aug 14 04:40:45 PM PDT 24
Finished Aug 14 04:40:50 PM PDT 24
Peak memory 209352 kb
Host smart-264d984c-c556-4d7a-ab5c-dfc04f66ada4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044178964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3044178964
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1445075162
Short name T667
Test name
Test status
Simulation time 151360091 ps
CPU time 2.81 seconds
Started Aug 14 04:40:38 PM PDT 24
Finished Aug 14 04:40:41 PM PDT 24
Peak memory 207264 kb
Host smart-371209cd-7e7f-4086-bd52-7877c7dc16dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445075162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1445075162
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3557184344
Short name T837
Test name
Test status
Simulation time 80390226 ps
CPU time 3.5 seconds
Started Aug 14 04:40:33 PM PDT 24
Finished Aug 14 04:40:37 PM PDT 24
Peak memory 209120 kb
Host smart-b00bd8b9-15ca-4992-bc26-48e80e376bf2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557184344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3557184344
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1650419546
Short name T858
Test name
Test status
Simulation time 385133203 ps
CPU time 8.88 seconds
Started Aug 14 04:41:03 PM PDT 24
Finished Aug 14 04:41:12 PM PDT 24
Peak memory 209724 kb
Host smart-b781f8c7-2959-4386-a5d4-289e4c6eba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650419546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1650419546
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3065883593
Short name T633
Test name
Test status
Simulation time 65954453 ps
CPU time 3.01 seconds
Started Aug 14 04:41:07 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 209092 kb
Host smart-edcb092b-dfff-42ea-a218-768fa8401afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065883593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3065883593
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2000292958
Short name T584
Test name
Test status
Simulation time 1978848231 ps
CPU time 48.54 seconds
Started Aug 14 04:41:08 PM PDT 24
Finished Aug 14 04:41:56 PM PDT 24
Peak memory 214908 kb
Host smart-f032bb0a-1a27-461c-a09d-0534930df6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000292958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2000292958
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.719813744
Short name T190
Test name
Test status
Simulation time 121066268 ps
CPU time 5.14 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:41 PM PDT 24
Peak memory 214824 kb
Host smart-ccab4a01-3b0a-4002-838d-cd05a7bbf27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719813744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.719813744
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2907170695
Short name T650
Test name
Test status
Simulation time 124927408 ps
CPU time 4.46 seconds
Started Aug 14 04:40:51 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 210896 kb
Host smart-b6b84078-b33b-46b9-9e63-48f4c2fc6ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907170695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2907170695
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1742522068
Short name T81
Test name
Test status
Simulation time 17500212 ps
CPU time 1.01 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:27 PM PDT 24
Peak memory 206472 kb
Host smart-bbe5fe4f-4248-4c84-b6e6-69107c5d5801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742522068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1742522068
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.128262482
Short name T180
Test name
Test status
Simulation time 65826516 ps
CPU time 1.3 seconds
Started Aug 14 04:41:17 PM PDT 24
Finished Aug 14 04:41:18 PM PDT 24
Peak memory 215096 kb
Host smart-74949643-45b5-4aad-954c-d4e273de3152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128262482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.128262482
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.226887522
Short name T685
Test name
Test status
Simulation time 362565126 ps
CPU time 4.08 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:19 PM PDT 24
Peak memory 214780 kb
Host smart-e3818260-83f3-4348-8bfe-31424e507522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226887522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.226887522
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1731952036
Short name T99
Test name
Test status
Simulation time 72080215 ps
CPU time 2.78 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 209076 kb
Host smart-57cc9eab-d742-4aa4-a4d1-01fc0d1f25f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731952036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1731952036
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3370127144
Short name T259
Test name
Test status
Simulation time 375782907 ps
CPU time 3.92 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 209472 kb
Host smart-a9a56eb6-dd6d-4b51-8f54-77a7358afa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370127144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3370127144
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.4104953020
Short name T656
Test name
Test status
Simulation time 2341398732 ps
CPU time 8.7 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 208784 kb
Host smart-492d9a3e-e0c3-4d16-bf71-bb339f742698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104953020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.4104953020
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2144776072
Short name T585
Test name
Test status
Simulation time 89273074 ps
CPU time 1.97 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 209008 kb
Host smart-74c5f8c3-636b-429c-8efd-bc7782ae81c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144776072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2144776072
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3230898545
Short name T691
Test name
Test status
Simulation time 522535184 ps
CPU time 3.66 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 209196 kb
Host smart-18ae2c5b-d44d-4524-a1eb-6fbc97ed6ae2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230898545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3230898545
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1921972835
Short name T865
Test name
Test status
Simulation time 3487190028 ps
CPU time 5.34 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 209460 kb
Host smart-35db5801-ee5f-40c2-a247-687d6d8c22fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921972835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1921972835
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1449166115
Short name T884
Test name
Test status
Simulation time 257508583 ps
CPU time 3.11 seconds
Started Aug 14 04:41:24 PM PDT 24
Finished Aug 14 04:41:28 PM PDT 24
Peak memory 208108 kb
Host smart-544ff22f-02a0-4850-a62a-ad79066854a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449166115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1449166115
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3105363722
Short name T127
Test name
Test status
Simulation time 168382282 ps
CPU time 2.22 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:28 PM PDT 24
Peak memory 208948 kb
Host smart-82ba5134-1cd5-4af2-9f2a-673c4e85b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105363722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3105363722
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3115369870
Short name T472
Test name
Test status
Simulation time 94867205 ps
CPU time 2.58 seconds
Started Aug 14 04:41:32 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 207500 kb
Host smart-8d89f6ed-fa86-4bf3-82a4-121a57a76a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115369870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3115369870
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3760982915
Short name T682
Test name
Test status
Simulation time 2841607711 ps
CPU time 15.43 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:43 PM PDT 24
Peak memory 221220 kb
Host smart-8978f56a-50a1-40fa-b05a-19a04ac67921
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760982915 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3760982915
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1774372940
Short name T389
Test name
Test status
Simulation time 285866207 ps
CPU time 9.64 seconds
Started Aug 14 04:41:20 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 214820 kb
Host smart-72217af7-345c-4f8b-99be-25cc1d864fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774372940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1774372940
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.396035401
Short name T497
Test name
Test status
Simulation time 119080184 ps
CPU time 3.8 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 210376 kb
Host smart-a054b509-e1ba-4c58-83c1-afcbe2df8563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396035401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.396035401
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3766885942
Short name T427
Test name
Test status
Simulation time 45475305 ps
CPU time 0.78 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 206380 kb
Host smart-3f885ed1-05fe-4366-8f25-dce3bbb830d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766885942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3766885942
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3349438179
Short name T814
Test name
Test status
Simulation time 69796254 ps
CPU time 2.64 seconds
Started Aug 14 04:41:18 PM PDT 24
Finished Aug 14 04:41:20 PM PDT 24
Peak memory 208204 kb
Host smart-d4f6a7b6-f522-47a7-a0b1-4eb668ab0609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349438179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3349438179
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3152807062
Short name T886
Test name
Test status
Simulation time 231769365 ps
CPU time 2.14 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 207900 kb
Host smart-d85b0f26-b985-4b1e-9d93-6f66eeba3ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152807062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3152807062
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2387509334
Short name T513
Test name
Test status
Simulation time 192172494 ps
CPU time 3.47 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 209596 kb
Host smart-47fbe002-5fa9-48c4-9237-3daf9b62dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387509334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2387509334
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1506797966
Short name T552
Test name
Test status
Simulation time 594613554 ps
CPU time 2.85 seconds
Started Aug 14 04:41:20 PM PDT 24
Finished Aug 14 04:41:23 PM PDT 24
Peak memory 214796 kb
Host smart-02f6e3a8-6ed5-42c3-b02d-6ce596b37792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506797966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1506797966
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3294776826
Short name T469
Test name
Test status
Simulation time 68237267 ps
CPU time 2.36 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 214892 kb
Host smart-859e7447-c02d-4c1d-bf22-b6db144cef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294776826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3294776826
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2644628069
Short name T332
Test name
Test status
Simulation time 429408054 ps
CPU time 3.17 seconds
Started Aug 14 04:41:37 PM PDT 24
Finished Aug 14 04:41:40 PM PDT 24
Peak memory 218808 kb
Host smart-8128a46f-abd8-4e7a-a5ce-e8c40a6c6cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644628069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2644628069
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3793109508
Short name T347
Test name
Test status
Simulation time 80464963 ps
CPU time 3.22 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 207268 kb
Host smart-e98f8361-9437-423f-910f-87bfe928cec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793109508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3793109508
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3653949266
Short name T107
Test name
Test status
Simulation time 58237849 ps
CPU time 2.89 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 209148 kb
Host smart-b2d35d70-aa14-4869-9bc5-e13a1e0d3524
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653949266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3653949266
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1910179541
Short name T83
Test name
Test status
Simulation time 418188142 ps
CPU time 3.54 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 209176 kb
Host smart-64f1693b-81e5-4f68-991c-7729c4aca843
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910179541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1910179541
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3634490260
Short name T392
Test name
Test status
Simulation time 156755870 ps
CPU time 3.38 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 209184 kb
Host smart-f8b946dd-179d-41d9-96f5-04b90f5c1ca0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634490260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3634490260
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3557027262
Short name T684
Test name
Test status
Simulation time 2587349259 ps
CPU time 6.7 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 209528 kb
Host smart-1b614390-7421-4add-8a48-b96142e62b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557027262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3557027262
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2519680322
Short name T124
Test name
Test status
Simulation time 87895510 ps
CPU time 2.76 seconds
Started Aug 14 04:41:47 PM PDT 24
Finished Aug 14 04:41:50 PM PDT 24
Peak memory 207304 kb
Host smart-098171bd-a377-444d-8533-ddad6b5e0452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519680322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2519680322
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2885561680
Short name T322
Test name
Test status
Simulation time 94951186 ps
CPU time 4.57 seconds
Started Aug 14 04:41:18 PM PDT 24
Finished Aug 14 04:41:23 PM PDT 24
Peak memory 214804 kb
Host smart-48656102-ea49-4993-b501-9ae37cc4b682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885561680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2885561680
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4082955143
Short name T37
Test name
Test status
Simulation time 95933037 ps
CPU time 1.62 seconds
Started Aug 14 04:41:23 PM PDT 24
Finished Aug 14 04:41:25 PM PDT 24
Peak memory 210472 kb
Host smart-cd32806c-540b-45a5-b206-20b935f8eb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082955143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4082955143
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.766101400
Short name T565
Test name
Test status
Simulation time 49782748 ps
CPU time 0.76 seconds
Started Aug 14 04:41:42 PM PDT 24
Finished Aug 14 04:41:43 PM PDT 24
Peak memory 206368 kb
Host smart-bfebbda0-f8dd-464d-a99a-171999809250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766101400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.766101400
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.981413515
Short name T356
Test name
Test status
Simulation time 73328965 ps
CPU time 3.04 seconds
Started Aug 14 04:41:23 PM PDT 24
Finished Aug 14 04:41:26 PM PDT 24
Peak memory 215304 kb
Host smart-dbf8224f-5b7f-4cc3-b24e-3a1c6c8ca005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981413515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.981413515
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2974867687
Short name T873
Test name
Test status
Simulation time 199564136 ps
CPU time 5.07 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:35 PM PDT 24
Peak memory 214728 kb
Host smart-895b227c-4715-44b2-a8f8-1aee2f9fd697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974867687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2974867687
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.267037016
Short name T502
Test name
Test status
Simulation time 354614269 ps
CPU time 4.2 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:33 PM PDT 24
Peak memory 210204 kb
Host smart-04ca4ee6-00e4-4450-b8bf-91b3766a7f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267037016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.267037016
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.4275500690
Short name T465
Test name
Test status
Simulation time 59756560 ps
CPU time 2.35 seconds
Started Aug 14 04:41:33 PM PDT 24
Finished Aug 14 04:41:35 PM PDT 24
Peak memory 214752 kb
Host smart-4ede5ffc-49d4-43ec-962b-bd23ca95b39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275500690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.4275500690
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.914580546
Short name T483
Test name
Test status
Simulation time 104309452 ps
CPU time 4.65 seconds
Started Aug 14 04:41:34 PM PDT 24
Finished Aug 14 04:41:38 PM PDT 24
Peak memory 210248 kb
Host smart-c7b6760e-c5fd-4e0b-90b4-04a3694043f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914580546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.914580546
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.991251420
Short name T659
Test name
Test status
Simulation time 59370498 ps
CPU time 2.62 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:28 PM PDT 24
Peak memory 207472 kb
Host smart-a29e62cd-49a6-4923-a701-21fb4a68bd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991251420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.991251420
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2020654682
Short name T756
Test name
Test status
Simulation time 40143225 ps
CPU time 1.7 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 207360 kb
Host smart-f8225a7b-92ac-4ae4-ae23-a204fdd62643
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020654682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2020654682
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.949443686
Short name T741
Test name
Test status
Simulation time 2503273354 ps
CPU time 10.13 seconds
Started Aug 14 04:41:43 PM PDT 24
Finished Aug 14 04:41:54 PM PDT 24
Peak memory 208392 kb
Host smart-df4755da-391c-44c7-b59a-c029fdf36bcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949443686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.949443686
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.993743639
Short name T822
Test name
Test status
Simulation time 141379220 ps
CPU time 3.97 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 208800 kb
Host smart-7a6571b2-2e0e-41f7-b42d-c95c1c0c5fc9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993743639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.993743639
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.200050063
Short name T875
Test name
Test status
Simulation time 73688905 ps
CPU time 1.58 seconds
Started Aug 14 04:41:45 PM PDT 24
Finished Aug 14 04:41:46 PM PDT 24
Peak memory 207388 kb
Host smart-1d54666f-92ba-4058-9b1e-18a3377a23c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200050063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.200050063
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1930048765
Short name T791
Test name
Test status
Simulation time 223455796 ps
CPU time 3.25 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 207252 kb
Host smart-f99d9176-b02b-435a-b6d1-c1cdbb92e6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930048765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1930048765
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.508259577
Short name T898
Test name
Test status
Simulation time 2329007113 ps
CPU time 69.76 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 217660 kb
Host smart-f6397833-e39a-4468-a59c-d694995414df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508259577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.508259577
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3183008732
Short name T185
Test name
Test status
Simulation time 2484107040 ps
CPU time 26.61 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:56 PM PDT 24
Peak memory 223100 kb
Host smart-2dfea1ba-6229-40ef-852a-5b6a6a26f7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183008732 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3183008732
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.901763635
Short name T906
Test name
Test status
Simulation time 870190444 ps
CPU time 3.45 seconds
Started Aug 14 04:41:40 PM PDT 24
Finished Aug 14 04:41:43 PM PDT 24
Peak memory 209852 kb
Host smart-8ce43fa5-030a-4021-97e5-b51428d56b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901763635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.901763635
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3350071212
Short name T164
Test name
Test status
Simulation time 41260555 ps
CPU time 2.32 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 210564 kb
Host smart-886d007d-ca99-43bf-9c0b-16cd74cf8184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350071212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3350071212
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1036060987
Short name T17
Test name
Test status
Simulation time 18959812 ps
CPU time 0.77 seconds
Started Aug 14 04:41:33 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 206380 kb
Host smart-7d22b418-7b68-45e0-94ff-00cb574ab91a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036060987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1036060987
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3092788548
Short name T383
Test name
Test status
Simulation time 34250263 ps
CPU time 2.53 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:33 PM PDT 24
Peak memory 215600 kb
Host smart-a50ef52e-aaaf-431b-9d39-e2a86ecaf514
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092788548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3092788548
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.79081412
Short name T824
Test name
Test status
Simulation time 386358536 ps
CPU time 3.14 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:28 PM PDT 24
Peak memory 218992 kb
Host smart-5854e312-8364-4bd6-8cd3-22a803a0aca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79081412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.79081412
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1178560663
Short name T255
Test name
Test status
Simulation time 100080854 ps
CPU time 2.04 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 208544 kb
Host smart-4bf62f7a-b1f8-4bc0-abb9-c31700b27cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178560663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1178560663
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4261398746
Short name T894
Test name
Test status
Simulation time 28090719 ps
CPU time 2.36 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:05 PM PDT 24
Peak memory 214868 kb
Host smart-7920aacb-0b51-4851-a1eb-1cb1c24b6100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261398746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4261398746
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.829579591
Short name T576
Test name
Test status
Simulation time 70947658 ps
CPU time 2.7 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:27 PM PDT 24
Peak memory 214512 kb
Host smart-2b2d0ba8-4e08-474d-bd9b-8e14ba6af772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829579591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.829579591
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2548914429
Short name T724
Test name
Test status
Simulation time 464235527 ps
CPU time 4.39 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 209676 kb
Host smart-a47c3257-e905-491c-9ed8-bc73f7ff39f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548914429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2548914429
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.186611335
Short name T784
Test name
Test status
Simulation time 74136908 ps
CPU time 3.65 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 208144 kb
Host smart-a7b28aaf-df6a-469a-9c63-f7ca10695911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186611335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.186611335
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.231614787
Short name T643
Test name
Test status
Simulation time 449452515 ps
CPU time 10.56 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:40 PM PDT 24
Peak memory 209220 kb
Host smart-a98892be-532d-41a7-b1bf-7dc9a4a4b832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231614787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.231614787
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2310794642
Short name T846
Test name
Test status
Simulation time 3278658703 ps
CPU time 22 seconds
Started Aug 14 04:41:42 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 209076 kb
Host smart-e254a78c-6456-4ddb-ad7b-56ca99dfbc22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310794642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2310794642
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1701457160
Short name T536
Test name
Test status
Simulation time 42294704 ps
CPU time 1.75 seconds
Started Aug 14 04:41:36 PM PDT 24
Finished Aug 14 04:41:42 PM PDT 24
Peak memory 207472 kb
Host smart-578d526d-51f1-43cf-8c61-c47aeb53273f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701457160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1701457160
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3825698434
Short name T440
Test name
Test status
Simulation time 1740224810 ps
CPU time 41.58 seconds
Started Aug 14 04:41:24 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 209032 kb
Host smart-262459b3-5b1d-4876-81e4-52a20bc1f4d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825698434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3825698434
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3647835830
Short name T283
Test name
Test status
Simulation time 45411585 ps
CPU time 2.2 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 219008 kb
Host smart-9012bcb0-250c-4a32-9ae0-abddfac2eb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647835830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3647835830
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3116543884
Short name T786
Test name
Test status
Simulation time 51288824 ps
CPU time 2.31 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 207396 kb
Host smart-3d60b450-f00f-4234-a6e3-9e109ac97cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116543884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3116543884
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1173476228
Short name T184
Test name
Test status
Simulation time 585024178 ps
CPU time 21.4 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:49 PM PDT 24
Peak memory 221828 kb
Host smart-7cc273df-fdf1-4373-a764-d66878af2e29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173476228 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1173476228
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3058070850
Short name T297
Test name
Test status
Simulation time 1216250553 ps
CPU time 11.41 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:37 PM PDT 24
Peak memory 209396 kb
Host smart-e9640bad-e4f5-47fd-91a1-cfbb01555fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058070850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3058070850
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1206120758
Short name T378
Test name
Test status
Simulation time 52524581 ps
CPU time 2.65 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 210776 kb
Host smart-c124ef55-b0a2-4aad-ba85-d19894b783a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206120758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1206120758
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3447906973
Short name T463
Test name
Test status
Simulation time 61414587 ps
CPU time 0.91 seconds
Started Aug 14 04:41:48 PM PDT 24
Finished Aug 14 04:41:49 PM PDT 24
Peak memory 206492 kb
Host smart-dd36e468-d0be-4983-b351-dd20ad73c08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447906973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3447906973
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2232859772
Short name T218
Test name
Test status
Simulation time 88684892 ps
CPU time 3.98 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 210476 kb
Host smart-b6989ef5-6046-44a0-82e6-097557affc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232859772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2232859772
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.4155124945
Short name T651
Test name
Test status
Simulation time 192362606 ps
CPU time 2.57 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 208320 kb
Host smart-1d04d8e4-71da-468b-ba65-646c287a1a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155124945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.4155124945
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2903415520
Short name T266
Test name
Test status
Simulation time 246075155 ps
CPU time 5.76 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 214692 kb
Host smart-ed03ea8a-5c04-4b4d-a354-792ceece706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903415520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2903415520
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.784325131
Short name T224
Test name
Test status
Simulation time 377126535 ps
CPU time 3.74 seconds
Started Aug 14 04:41:40 PM PDT 24
Finished Aug 14 04:41:44 PM PDT 24
Peak memory 214708 kb
Host smart-3d8b2582-2a53-4658-bebd-f92422092e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784325131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.784325131
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2237104639
Short name T309
Test name
Test status
Simulation time 93133664 ps
CPU time 3.2 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 208100 kb
Host smart-3ffe96c1-fad5-45b3-835b-28e4408b3283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237104639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2237104639
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3514653174
Short name T5
Test name
Test status
Simulation time 426763402 ps
CPU time 4.48 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 208492 kb
Host smart-b412ad9e-052e-40a3-917b-c48d80b2f570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514653174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3514653174
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1228494259
Short name T863
Test name
Test status
Simulation time 461213622 ps
CPU time 3.04 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 207360 kb
Host smart-2d23c635-54b7-4693-9df5-2969335a5345
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228494259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1228494259
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2433059798
Short name T244
Test name
Test status
Simulation time 182681877 ps
CPU time 2.76 seconds
Started Aug 14 04:41:43 PM PDT 24
Finished Aug 14 04:41:46 PM PDT 24
Peak memory 207900 kb
Host smart-a69675d3-3152-4b94-aa91-77b8ef9bef00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433059798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2433059798
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.249614975
Short name T312
Test name
Test status
Simulation time 432512534 ps
CPU time 4.99 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:36 PM PDT 24
Peak memory 207504 kb
Host smart-e19fc93b-5daf-4587-a666-10a2fe54ff8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249614975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.249614975
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2175468285
Short name T688
Test name
Test status
Simulation time 233537666 ps
CPU time 2.16 seconds
Started Aug 14 04:41:31 PM PDT 24
Finished Aug 14 04:41:33 PM PDT 24
Peak memory 208264 kb
Host smart-96cdae9b-d7ff-4739-bf89-4229bf2aa161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175468285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2175468285
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.768522591
Short name T764
Test name
Test status
Simulation time 425350403 ps
CPU time 5.14 seconds
Started Aug 14 04:41:38 PM PDT 24
Finished Aug 14 04:41:43 PM PDT 24
Peak memory 207224 kb
Host smart-365056b7-d492-4886-9308-004cf02be7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768522591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.768522591
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2965083639
Short name T687
Test name
Test status
Simulation time 3992377209 ps
CPU time 14.27 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:42 PM PDT 24
Peak memory 221224 kb
Host smart-fc7a7dde-34b1-4749-b76f-4f800e158741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965083639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2965083639
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2687616412
Short name T179
Test name
Test status
Simulation time 1592176890 ps
CPU time 23.59 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:50 PM PDT 24
Peak memory 222916 kb
Host smart-6010a7b4-a77e-413e-8433-de09b7ff9d4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687616412 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2687616412
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3027199244
Short name T781
Test name
Test status
Simulation time 2961396739 ps
CPU time 13.95 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:39 PM PDT 24
Peak memory 209376 kb
Host smart-8d409938-2ab3-4ddf-9acf-9f52ebe07e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027199244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3027199244
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1307067361
Short name T487
Test name
Test status
Simulation time 99297803 ps
CPU time 2.07 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:28 PM PDT 24
Peak memory 210460 kb
Host smart-0863c53b-1aa4-43e6-964b-53fea646dc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307067361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1307067361
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3624585186
Short name T439
Test name
Test status
Simulation time 17816068 ps
CPU time 0.75 seconds
Started Aug 14 04:41:38 PM PDT 24
Finished Aug 14 04:41:38 PM PDT 24
Peak memory 206332 kb
Host smart-f64eb41a-cbc2-4fb4-a10b-87c5b406a74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624585186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3624585186
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1006307195
Short name T388
Test name
Test status
Simulation time 390709702 ps
CPU time 4.02 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:33 PM PDT 24
Peak memory 215640 kb
Host smart-eae7e900-6b73-4d12-9971-79c1ffd643ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006307195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1006307195
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1449698547
Short name T751
Test name
Test status
Simulation time 68730784 ps
CPU time 4.11 seconds
Started Aug 14 04:41:36 PM PDT 24
Finished Aug 14 04:41:40 PM PDT 24
Peak memory 214772 kb
Host smart-1c15869e-4aa6-43b8-a84b-12df3f65b9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449698547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1449698547
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.953030848
Short name T336
Test name
Test status
Simulation time 211473065 ps
CPU time 2.78 seconds
Started Aug 14 04:42:13 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 209400 kb
Host smart-f515bd9d-9df1-4b22-83ad-7f3fe0bd8d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953030848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.953030848
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3277196943
Short name T545
Test name
Test status
Simulation time 261511720 ps
CPU time 8.74 seconds
Started Aug 14 04:41:38 PM PDT 24
Finished Aug 14 04:41:47 PM PDT 24
Peak memory 214724 kb
Host smart-0b8ca35c-b328-46d2-b81a-a54c6ef165f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277196943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3277196943
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1061828420
Short name T57
Test name
Test status
Simulation time 292568986 ps
CPU time 3.24 seconds
Started Aug 14 04:41:51 PM PDT 24
Finished Aug 14 04:41:55 PM PDT 24
Peak memory 221380 kb
Host smart-a8b6eabf-812e-4ae5-9477-c3d2f5a762e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061828420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1061828420
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.421490517
Short name T215
Test name
Test status
Simulation time 544287852 ps
CPU time 4.11 seconds
Started Aug 14 04:41:33 PM PDT 24
Finished Aug 14 04:41:37 PM PDT 24
Peak memory 222884 kb
Host smart-cde79400-cb11-42c9-9e20-01c6634569a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421490517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.421490517
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2151923153
Short name T235
Test name
Test status
Simulation time 362877884 ps
CPU time 7.97 seconds
Started Aug 14 04:41:33 PM PDT 24
Finished Aug 14 04:41:41 PM PDT 24
Peak memory 209684 kb
Host smart-4978a689-e0d0-4742-8754-4925836590b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151923153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2151923153
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3826364200
Short name T79
Test name
Test status
Simulation time 194483254 ps
CPU time 4.62 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 206276 kb
Host smart-97f99223-c427-408f-ad98-80ddda993890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826364200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3826364200
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.760169109
Short name T359
Test name
Test status
Simulation time 322170229 ps
CPU time 8.71 seconds
Started Aug 14 04:41:34 PM PDT 24
Finished Aug 14 04:41:42 PM PDT 24
Peak memory 209020 kb
Host smart-30538fb4-9a3d-4748-a45e-656b562c2aab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760169109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.760169109
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2395346905
Short name T256
Test name
Test status
Simulation time 60665165 ps
CPU time 3.13 seconds
Started Aug 14 04:41:42 PM PDT 24
Finished Aug 14 04:41:46 PM PDT 24
Peak memory 208188 kb
Host smart-72ea6466-ef48-477a-8447-b111ff751119
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395346905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2395346905
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1750148873
Short name T596
Test name
Test status
Simulation time 21727856 ps
CPU time 1.89 seconds
Started Aug 14 04:41:41 PM PDT 24
Finished Aug 14 04:41:43 PM PDT 24
Peak memory 207484 kb
Host smart-cacc673d-7be1-45e4-b6c5-e20a64e9efdf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750148873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1750148873
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3294233052
Short name T662
Test name
Test status
Simulation time 87478813 ps
CPU time 1.48 seconds
Started Aug 14 04:41:36 PM PDT 24
Finished Aug 14 04:41:37 PM PDT 24
Peak memory 209844 kb
Host smart-ac912c82-5493-4bea-bdc8-7f947a7fcc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294233052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3294233052
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.932170651
Short name T496
Test name
Test status
Simulation time 118074875 ps
CPU time 3.26 seconds
Started Aug 14 04:41:43 PM PDT 24
Finished Aug 14 04:41:46 PM PDT 24
Peak memory 208880 kb
Host smart-9d11f322-080d-4790-b622-f4073dcaa814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932170651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.932170651
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.4212219253
Short name T275
Test name
Test status
Simulation time 5973639968 ps
CPU time 72.65 seconds
Started Aug 14 04:41:46 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 222888 kb
Host smart-e67ddd6f-190a-46f8-b07a-45de88273082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212219253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4212219253
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1967689205
Short name T601
Test name
Test status
Simulation time 116257333 ps
CPU time 5.09 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 208396 kb
Host smart-4982bd2b-9cfc-4946-9957-774b2c819737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967689205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1967689205
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4139601141
Short name T553
Test name
Test status
Simulation time 124805957 ps
CPU time 3.95 seconds
Started Aug 14 04:41:37 PM PDT 24
Finished Aug 14 04:41:41 PM PDT 24
Peak memory 210928 kb
Host smart-61510b45-befd-4e1d-8a2a-79c33890cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139601141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4139601141
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.378749613
Short name T788
Test name
Test status
Simulation time 9375320 ps
CPU time 0.78 seconds
Started Aug 14 04:41:35 PM PDT 24
Finished Aug 14 04:41:36 PM PDT 24
Peak memory 206316 kb
Host smart-f7d72af7-56f3-47f9-a0b4-021f96ca9bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378749613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.378749613
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3786829155
Short name T797
Test name
Test status
Simulation time 313808881 ps
CPU time 4.56 seconds
Started Aug 14 04:41:31 PM PDT 24
Finished Aug 14 04:41:36 PM PDT 24
Peak memory 214880 kb
Host smart-9ed554ad-6800-4228-864a-958142c74006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3786829155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3786829155
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3476382572
Short name T261
Test name
Test status
Simulation time 1931452259 ps
CPU time 20.04 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:48 PM PDT 24
Peak memory 208368 kb
Host smart-c972102b-5207-4520-ad56-99c7ba5e93c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476382572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3476382572
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3587472823
Short name T810
Test name
Test status
Simulation time 239116380 ps
CPU time 2.1 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 214776 kb
Host smart-3fbe6ce6-f41f-4cc6-a1ed-6b00d15fd62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587472823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3587472823
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3730343159
Short name T44
Test name
Test status
Simulation time 129091954 ps
CPU time 3.95 seconds
Started Aug 14 04:41:41 PM PDT 24
Finished Aug 14 04:41:45 PM PDT 24
Peak memory 220316 kb
Host smart-419d3032-f4f9-477a-b94a-0f8298e3a275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730343159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3730343159
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.630545719
Short name T701
Test name
Test status
Simulation time 413625300 ps
CPU time 6.12 seconds
Started Aug 14 04:41:25 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 210888 kb
Host smart-e712c569-47bd-4fe3-89e4-5b44e3f01f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630545719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.630545719
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.703410192
Short name T569
Test name
Test status
Simulation time 183015557 ps
CPU time 4.49 seconds
Started Aug 14 04:41:42 PM PDT 24
Finished Aug 14 04:41:47 PM PDT 24
Peak memory 208964 kb
Host smart-a8100048-54d9-4cfc-8792-24ea96dbf7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703410192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.703410192
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.332819596
Short name T508
Test name
Test status
Simulation time 655100958 ps
CPU time 8.07 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 208736 kb
Host smart-c33a6da5-d4fd-440c-ad28-bfd0bc835661
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332819596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.332819596
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1383362299
Short name T498
Test name
Test status
Simulation time 472004365 ps
CPU time 5.75 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 209424 kb
Host smart-83c3ca1c-bb50-4563-a2c3-d9f976640a03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383362299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1383362299
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1032963263
Short name T340
Test name
Test status
Simulation time 329312050 ps
CPU time 3.75 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 209244 kb
Host smart-581a3e1f-c4a6-42c1-8783-a7c5c86cd3d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032963263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1032963263
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2236132905
Short name T449
Test name
Test status
Simulation time 254145253 ps
CPU time 3.41 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:33 PM PDT 24
Peak memory 218580 kb
Host smart-75f9e14e-5e67-41d2-8eb0-3d47615305d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236132905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2236132905
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1232563010
Short name T484
Test name
Test status
Simulation time 33011032 ps
CPU time 2.39 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 208896 kb
Host smart-e1d99bae-cca7-4e7d-b2ef-0bacd25f53a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232563010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1232563010
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2894107659
Short name T75
Test name
Test status
Simulation time 12758768168 ps
CPU time 71.25 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:42:41 PM PDT 24
Peak memory 221116 kb
Host smart-f71c09b5-3fb6-47fc-b27d-3f5e8647410b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894107659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2894107659
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3808220098
Short name T524
Test name
Test status
Simulation time 28166230 ps
CPU time 2.12 seconds
Started Aug 14 04:41:32 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 207860 kb
Host smart-b57caf28-44a5-48ae-8f35-3b5cb63de987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808220098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3808220098
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2545694446
Short name T377
Test name
Test status
Simulation time 115513145 ps
CPU time 1.97 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 210356 kb
Host smart-c3136cd3-d4a8-4a07-8863-d1811ef870d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545694446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2545694446
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1963694609
Short name T627
Test name
Test status
Simulation time 12642376 ps
CPU time 0.91 seconds
Started Aug 14 04:41:31 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 206596 kb
Host smart-e792bb55-8598-4709-92f2-cafa76a2c8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963694609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1963694609
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1062725562
Short name T132
Test name
Test status
Simulation time 342609908 ps
CPU time 8.33 seconds
Started Aug 14 04:41:51 PM PDT 24
Finished Aug 14 04:42:00 PM PDT 24
Peak memory 214812 kb
Host smart-0891c48e-185e-406b-904b-afe7c11f975f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062725562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1062725562
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.657587857
Short name T67
Test name
Test status
Simulation time 71974523 ps
CPU time 2.44 seconds
Started Aug 14 04:41:32 PM PDT 24
Finished Aug 14 04:41:35 PM PDT 24
Peak memory 215012 kb
Host smart-e01ad062-a471-4c65-89a9-633377c1a72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657587857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.657587857
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1675087331
Short name T909
Test name
Test status
Simulation time 20404939 ps
CPU time 1.61 seconds
Started Aug 14 04:41:26 PM PDT 24
Finished Aug 14 04:41:27 PM PDT 24
Peak memory 214772 kb
Host smart-eed90eb8-88f3-49d2-8ab8-9901c673e09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675087331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1675087331
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2172738174
Short name T97
Test name
Test status
Simulation time 590619462 ps
CPU time 4.04 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:33 PM PDT 24
Peak memory 214768 kb
Host smart-222efef4-77e7-419b-b440-e6fe87447533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172738174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2172738174
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2190506464
Short name T202
Test name
Test status
Simulation time 352886364 ps
CPU time 4.24 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:41:56 PM PDT 24
Peak memory 221696 kb
Host smart-aef2dfc3-26b9-417e-a3a5-158e4a38762d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190506464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2190506464
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1881758650
Short name T225
Test name
Test status
Simulation time 915893920 ps
CPU time 7.23 seconds
Started Aug 14 04:41:39 PM PDT 24
Finished Aug 14 04:41:47 PM PDT 24
Peak memory 210512 kb
Host smart-62f0a6b5-656e-4d03-901d-f9bfbda783c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881758650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1881758650
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2241953135
Short name T458
Test name
Test status
Simulation time 2560743268 ps
CPU time 41.16 seconds
Started Aug 14 04:41:41 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 209628 kb
Host smart-c28e3cf7-5128-4a44-aab9-6169f0bee57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241953135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2241953135
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.654828172
Short name T577
Test name
Test status
Simulation time 972810207 ps
CPU time 6.1 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:41:59 PM PDT 24
Peak memory 207416 kb
Host smart-630d1968-4eaf-4255-9d9f-09b8be150ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654828172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.654828172
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1680270215
Short name T250
Test name
Test status
Simulation time 7394506221 ps
CPU time 59.38 seconds
Started Aug 14 04:41:35 PM PDT 24
Finished Aug 14 04:42:35 PM PDT 24
Peak memory 209180 kb
Host smart-08047eda-22a7-402d-b88d-d8c9cc5951ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680270215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1680270215
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3965683707
Short name T608
Test name
Test status
Simulation time 274879862 ps
CPU time 3.63 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 208988 kb
Host smart-792d7e2d-dda4-42d6-bd2e-fc4e89a5ffe3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965683707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3965683707
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4076436982
Short name T354
Test name
Test status
Simulation time 41372552 ps
CPU time 2.41 seconds
Started Aug 14 04:42:12 PM PDT 24
Finished Aug 14 04:42:14 PM PDT 24
Peak memory 208884 kb
Host smart-0dd8fa3e-6e5e-428d-89d3-92c653e9c1c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076436982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4076436982
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.714346544
Short name T528
Test name
Test status
Simulation time 74528703 ps
CPU time 1.47 seconds
Started Aug 14 04:41:40 PM PDT 24
Finished Aug 14 04:41:41 PM PDT 24
Peak memory 208312 kb
Host smart-819c1faa-d704-4fab-a570-71e2389c74b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714346544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.714346544
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.681372940
Short name T652
Test name
Test status
Simulation time 23888038 ps
CPU time 1.73 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 207576 kb
Host smart-f7c97c6e-38d7-49bf-b036-3045f906de6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681372940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.681372940
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3223581376
Short name T351
Test name
Test status
Simulation time 1285719757 ps
CPU time 26.01 seconds
Started Aug 14 04:41:54 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 222908 kb
Host smart-505298b1-3317-4fcf-b0c4-dbf6223d2b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223581376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3223581376
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3278895143
Short name T69
Test name
Test status
Simulation time 1453942496 ps
CPU time 14.69 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:43 PM PDT 24
Peak memory 220488 kb
Host smart-f5d07dd8-30c6-49a5-a5ce-17a4bd62154c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278895143 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3278895143
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2359669698
Short name T254
Test name
Test status
Simulation time 3940674305 ps
CPU time 54.4 seconds
Started Aug 14 04:41:46 PM PDT 24
Finished Aug 14 04:42:40 PM PDT 24
Peak memory 214840 kb
Host smart-6358ed2c-b8b3-47f8-af30-e1e065487b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359669698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2359669698
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2031228380
Short name T200
Test name
Test status
Simulation time 79360612 ps
CPU time 0.79 seconds
Started Aug 14 04:41:57 PM PDT 24
Finished Aug 14 04:41:58 PM PDT 24
Peak memory 206356 kb
Host smart-c69464da-0b45-4ad7-a5d3-11242d6ff038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031228380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2031228380
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1693685002
Short name T723
Test name
Test status
Simulation time 68114967 ps
CPU time 3.32 seconds
Started Aug 14 04:41:55 PM PDT 24
Finished Aug 14 04:41:59 PM PDT 24
Peak memory 217984 kb
Host smart-59c991be-a352-4097-8f59-4f725ee74e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693685002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1693685002
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2570518388
Short name T629
Test name
Test status
Simulation time 60049298 ps
CPU time 2.12 seconds
Started Aug 14 04:42:01 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 218564 kb
Host smart-50163df1-44cd-4afa-96fc-db0646778ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570518388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2570518388
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2175389342
Short name T372
Test name
Test status
Simulation time 1263336432 ps
CPU time 28.04 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:59 PM PDT 24
Peak memory 214768 kb
Host smart-1cd2608b-334b-46e3-883d-2d1c753a8154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175389342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2175389342
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1294245947
Short name T299
Test name
Test status
Simulation time 396679143 ps
CPU time 4.02 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 214612 kb
Host smart-52c4fde7-825c-4599-80a7-f3d1d4ded379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294245947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1294245947
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2825903675
Short name T621
Test name
Test status
Simulation time 74712069 ps
CPU time 2.74 seconds
Started Aug 14 04:41:38 PM PDT 24
Finished Aug 14 04:41:41 PM PDT 24
Peak memory 220412 kb
Host smart-542a8686-58ad-4d4c-b68c-040d108a28c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825903675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2825903675
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4082310589
Short name T774
Test name
Test status
Simulation time 859223156 ps
CPU time 25.38 seconds
Started Aug 14 04:42:00 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 209336 kb
Host smart-d46f7807-9a97-4252-b28e-6081288e47f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082310589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4082310589
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3979316821
Short name T527
Test name
Test status
Simulation time 140336626 ps
CPU time 3.37 seconds
Started Aug 14 04:41:31 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 209416 kb
Host smart-fb5817b2-eddc-4c25-9185-9d35327903ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979316821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3979316821
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3754468058
Short name T453
Test name
Test status
Simulation time 650935596 ps
CPU time 5.3 seconds
Started Aug 14 04:41:42 PM PDT 24
Finished Aug 14 04:41:47 PM PDT 24
Peak memory 209368 kb
Host smart-e3f1cf60-7334-410b-a500-7f41e4959781
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754468058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3754468058
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2617760101
Short name T777
Test name
Test status
Simulation time 197147855 ps
CPU time 2.91 seconds
Started Aug 14 04:42:07 PM PDT 24
Finished Aug 14 04:42:10 PM PDT 24
Peak memory 209168 kb
Host smart-cddb9921-bc4d-4c2a-a4f5-0d8f03f6bfef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617760101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2617760101
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2408924705
Short name T615
Test name
Test status
Simulation time 338308883 ps
CPU time 3.89 seconds
Started Aug 14 04:41:31 PM PDT 24
Finished Aug 14 04:41:35 PM PDT 24
Peak memory 209400 kb
Host smart-f0fcfd8f-d89f-4ff4-909a-4e888db4ef4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408924705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2408924705
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2325581894
Short name T430
Test name
Test status
Simulation time 233993924 ps
CPU time 2.09 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 209476 kb
Host smart-7ba29832-e9ac-4b0a-91db-c99b283475fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325581894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2325581894
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.674794632
Short name T450
Test name
Test status
Simulation time 3945815342 ps
CPU time 34.88 seconds
Started Aug 14 04:41:36 PM PDT 24
Finished Aug 14 04:42:11 PM PDT 24
Peak memory 208732 kb
Host smart-b8883c7e-a34c-443e-be4e-375f7b9179ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674794632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.674794632
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2114479691
Short name T277
Test name
Test status
Simulation time 409483524 ps
CPU time 18.51 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:27 PM PDT 24
Peak memory 215872 kb
Host smart-a2c2669b-d2b8-4867-aa43-baf98f225ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114479691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2114479691
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2874394948
Short name T293
Test name
Test status
Simulation time 183381514 ps
CPU time 3.82 seconds
Started Aug 14 04:41:44 PM PDT 24
Finished Aug 14 04:41:48 PM PDT 24
Peak memory 218740 kb
Host smart-b9109b8b-6383-4c22-9796-94f2cee36294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874394948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2874394948
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2844500482
Short name T166
Test name
Test status
Simulation time 73020923 ps
CPU time 2.88 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:01 PM PDT 24
Peak memory 210600 kb
Host smart-d17a9bf9-75e3-446b-80cf-bf449326a9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844500482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2844500482
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2022127276
Short name T597
Test name
Test status
Simulation time 14326142 ps
CPU time 0.76 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 206428 kb
Host smart-6a4eead2-5b12-4129-97da-cbf47270ec5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022127276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2022127276
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1604442405
Short name T762
Test name
Test status
Simulation time 299473553 ps
CPU time 7.04 seconds
Started Aug 14 04:41:41 PM PDT 24
Finished Aug 14 04:41:48 PM PDT 24
Peak memory 208996 kb
Host smart-677c4bd2-f603-416b-ac51-b11449064573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604442405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1604442405
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.192320699
Short name T801
Test name
Test status
Simulation time 94742535 ps
CPU time 1.63 seconds
Started Aug 14 04:41:49 PM PDT 24
Finished Aug 14 04:41:51 PM PDT 24
Peak memory 218772 kb
Host smart-08461da6-ee1f-4817-993f-fa6a2575bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192320699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.192320699
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.297539164
Short name T106
Test name
Test status
Simulation time 189657837 ps
CPU time 2.69 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 214760 kb
Host smart-c0a3de49-c06f-4789-8b40-d2bfb9519829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297539164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.297539164
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1699570267
Short name T228
Test name
Test status
Simulation time 89888388 ps
CPU time 4.19 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 214744 kb
Host smart-0ba02109-067b-42c9-a984-3d7d810b7f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699570267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1699570267
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1244207554
Short name T285
Test name
Test status
Simulation time 34649193 ps
CPU time 2.52 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:01 PM PDT 24
Peak memory 208416 kb
Host smart-62b949fc-c012-4eb8-8c87-699e3ab7aff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244207554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1244207554
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2224880738
Short name T459
Test name
Test status
Simulation time 26306216 ps
CPU time 2.11 seconds
Started Aug 14 04:41:27 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 208856 kb
Host smart-79e42ed4-bf0e-4769-878a-bd96ed9d0913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224880738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2224880738
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1282119702
Short name T613
Test name
Test status
Simulation time 689803444 ps
CPU time 16.12 seconds
Started Aug 14 04:42:00 PM PDT 24
Finished Aug 14 04:42:17 PM PDT 24
Peak memory 209312 kb
Host smart-bdb6e3b6-a5cb-4181-b065-f39334d37df7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282119702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1282119702
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1065393816
Short name T558
Test name
Test status
Simulation time 74933792 ps
CPU time 3.7 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 209420 kb
Host smart-5ea6f8df-b164-4cb6-a169-58dcc171dcdc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065393816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1065393816
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2297092366
Short name T647
Test name
Test status
Simulation time 557542639 ps
CPU time 4.41 seconds
Started Aug 14 04:41:51 PM PDT 24
Finished Aug 14 04:41:55 PM PDT 24
Peak memory 208564 kb
Host smart-d223e5a5-2d85-4e7a-a5a8-aafff0e3c17f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297092366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2297092366
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2860025897
Short name T637
Test name
Test status
Simulation time 395674308 ps
CPU time 2.08 seconds
Started Aug 14 04:41:41 PM PDT 24
Finished Aug 14 04:41:44 PM PDT 24
Peak memory 208332 kb
Host smart-79e12db5-cb5e-46e7-9e88-e7ab48629a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860025897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2860025897
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.686724603
Short name T193
Test name
Test status
Simulation time 263029238 ps
CPU time 2.57 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 207264 kb
Host smart-759c3e4b-1a46-4427-a680-cb0ae1d115c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686724603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.686724603
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2893846874
Short name T595
Test name
Test status
Simulation time 733945079 ps
CPU time 4.88 seconds
Started Aug 14 04:41:40 PM PDT 24
Finished Aug 14 04:41:45 PM PDT 24
Peak memory 207456 kb
Host smart-a64a02d0-55d1-4c49-a1fc-2989c5dbae55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893846874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2893846874
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1135252081
Short name T120
Test name
Test status
Simulation time 988466580 ps
CPU time 9.15 seconds
Started Aug 14 04:41:41 PM PDT 24
Finished Aug 14 04:41:51 PM PDT 24
Peak memory 223124 kb
Host smart-33ce2780-3b75-4773-96fa-e4bdb2fc5a32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135252081 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1135252081
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2168876420
Short name T512
Test name
Test status
Simulation time 487911438 ps
CPU time 5.35 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:35 PM PDT 24
Peak memory 219020 kb
Host smart-02aebab8-79c0-4b75-b1d2-4ffbe1a08b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168876420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2168876420
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1265260876
Short name T156
Test name
Test status
Simulation time 50573887 ps
CPU time 2.64 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:32 PM PDT 24
Peak memory 210600 kb
Host smart-b4d7e39f-1c95-4173-b7b7-8a9d9fed2c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265260876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1265260876
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2188390907
Short name T719
Test name
Test status
Simulation time 27173023 ps
CPU time 0.8 seconds
Started Aug 14 04:40:41 PM PDT 24
Finished Aug 14 04:40:42 PM PDT 24
Peak memory 206352 kb
Host smart-5b0ca941-eccc-4294-a8a7-5de0353620e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188390907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2188390907
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.9572794
Short name T416
Test name
Test status
Simulation time 214949556 ps
CPU time 4.04 seconds
Started Aug 14 04:40:54 PM PDT 24
Finished Aug 14 04:40:58 PM PDT 24
Peak memory 215888 kb
Host smart-9326943a-fb15-492e-9bf0-9855cc6ec1f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9572794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.9572794
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1129231781
Short name T757
Test name
Test status
Simulation time 82654671 ps
CPU time 3.06 seconds
Started Aug 14 04:40:34 PM PDT 24
Finished Aug 14 04:40:38 PM PDT 24
Peak memory 208548 kb
Host smart-c8fa68aa-4503-454d-a661-b60bf445be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129231781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1129231781
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.733022817
Short name T95
Test name
Test status
Simulation time 1355948598 ps
CPU time 8.64 seconds
Started Aug 14 04:40:34 PM PDT 24
Finished Aug 14 04:40:42 PM PDT 24
Peak memory 214660 kb
Host smart-ac4e6ee8-145d-4b00-9890-da7d1cfc6d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733022817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.733022817
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3098760514
Short name T269
Test name
Test status
Simulation time 191946346 ps
CPU time 4.25 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:41 PM PDT 24
Peak memory 214600 kb
Host smart-9fc25d41-23af-4454-a82c-da960a9ddce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098760514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3098760514
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2030049163
Short name T885
Test name
Test status
Simulation time 473629899 ps
CPU time 12.75 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:49 PM PDT 24
Peak memory 219124 kb
Host smart-51397fcc-6020-4a29-980c-fe472e3d44af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030049163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2030049163
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.446093148
Short name T131
Test name
Test status
Simulation time 490365336 ps
CPU time 6.52 seconds
Started Aug 14 04:40:37 PM PDT 24
Finished Aug 14 04:40:44 PM PDT 24
Peak memory 208964 kb
Host smart-7a6e1470-65bf-4757-a62f-bf5fd653d21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446093148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.446093148
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1991312531
Short name T102
Test name
Test status
Simulation time 1444323925 ps
CPU time 7.12 seconds
Started Aug 14 04:40:52 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 229916 kb
Host smart-89b3f0b1-6795-4a3f-8d7a-f7ef24b5cd71
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991312531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1991312531
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3737162638
Short name T358
Test name
Test status
Simulation time 42726665 ps
CPU time 1.88 seconds
Started Aug 14 04:40:54 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 208056 kb
Host smart-abd140ac-1bda-4a35-b8ae-10d92c5f7e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737162638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3737162638
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1842490287
Short name T830
Test name
Test status
Simulation time 357943946 ps
CPU time 3.26 seconds
Started Aug 14 04:40:33 PM PDT 24
Finished Aug 14 04:40:36 PM PDT 24
Peak memory 208760 kb
Host smart-3812db01-cac7-4281-b82c-2cafaa02d3a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842490287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1842490287
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.890173214
Short name T530
Test name
Test status
Simulation time 190933422 ps
CPU time 6.97 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:43 PM PDT 24
Peak memory 209904 kb
Host smart-ff84204f-8378-43a9-ab8b-eeeb25761419
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890173214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.890173214
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2475917252
Short name T807
Test name
Test status
Simulation time 1789228073 ps
CPU time 18.16 seconds
Started Aug 14 04:40:46 PM PDT 24
Finished Aug 14 04:41:04 PM PDT 24
Peak memory 209296 kb
Host smart-993faaa6-eff0-446f-a1cf-3ef28dfcfb23
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475917252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2475917252
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2576980865
Short name T346
Test name
Test status
Simulation time 2730093230 ps
CPU time 28.35 seconds
Started Aug 14 04:40:39 PM PDT 24
Finished Aug 14 04:41:08 PM PDT 24
Peak memory 208816 kb
Host smart-edb017e2-1e8b-4502-a7b7-400ddad78be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576980865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2576980865
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1441080901
Short name T511
Test name
Test status
Simulation time 1574039985 ps
CPU time 6.08 seconds
Started Aug 14 04:40:46 PM PDT 24
Finished Aug 14 04:40:57 PM PDT 24
Peak memory 207220 kb
Host smart-af507c95-4700-477d-b10d-af3306bcab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441080901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1441080901
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.463702890
Short name T221
Test name
Test status
Simulation time 11977267046 ps
CPU time 116.39 seconds
Started Aug 14 04:40:38 PM PDT 24
Finished Aug 14 04:42:34 PM PDT 24
Peak memory 216556 kb
Host smart-67325967-f599-4d74-a12e-77db27b75bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463702890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.463702890
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.4028595004
Short name T223
Test name
Test status
Simulation time 1459403755 ps
CPU time 14.99 seconds
Started Aug 14 04:40:43 PM PDT 24
Finished Aug 14 04:40:58 PM PDT 24
Peak memory 220156 kb
Host smart-aefc52f0-db24-40d8-b98f-cac816220a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028595004 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.4028595004
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2480423298
Short name T599
Test name
Test status
Simulation time 656145964 ps
CPU time 4.03 seconds
Started Aug 14 04:40:31 PM PDT 24
Finished Aug 14 04:40:36 PM PDT 24
Peak memory 208052 kb
Host smart-4ab4b152-e558-4b13-8405-a6eaff4180c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480423298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2480423298
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2309747002
Short name T775
Test name
Test status
Simulation time 92993057 ps
CPU time 3.59 seconds
Started Aug 14 04:40:46 PM PDT 24
Finished Aug 14 04:40:50 PM PDT 24
Peak memory 210448 kb
Host smart-fcd6d038-7385-4264-91a7-1cac591c2425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309747002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2309747002
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1566015071
Short name T848
Test name
Test status
Simulation time 38784061 ps
CPU time 0.75 seconds
Started Aug 14 04:41:50 PM PDT 24
Finished Aug 14 04:41:51 PM PDT 24
Peak memory 206396 kb
Host smart-195b76ce-7e99-405e-b491-72089842f824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566015071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1566015071
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3806801623
Short name T28
Test name
Test status
Simulation time 288105922 ps
CPU time 4.13 seconds
Started Aug 14 04:41:59 PM PDT 24
Finished Aug 14 04:42:03 PM PDT 24
Peak memory 223212 kb
Host smart-fe47bc25-f9ab-4128-a179-971cfcb6be74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806801623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3806801623
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2143591923
Short name T316
Test name
Test status
Simulation time 66813029 ps
CPU time 3.25 seconds
Started Aug 14 04:41:53 PM PDT 24
Finished Aug 14 04:41:57 PM PDT 24
Peak memory 218840 kb
Host smart-994830da-dc6a-4096-973e-dd4454508710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143591923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2143591923
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1325617192
Short name T900
Test name
Test status
Simulation time 308530069 ps
CPU time 2.94 seconds
Started Aug 14 04:41:30 PM PDT 24
Finished Aug 14 04:41:33 PM PDT 24
Peak memory 214708 kb
Host smart-381fbeb2-bf72-4be1-a95d-889cd5500dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325617192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1325617192
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.4103759156
Short name T816
Test name
Test status
Simulation time 95536036 ps
CPU time 3.02 seconds
Started Aug 14 04:41:46 PM PDT 24
Finished Aug 14 04:41:49 PM PDT 24
Peak memory 218972 kb
Host smart-eddd5aa3-0259-4841-b1a5-921639cb8fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103759156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.4103759156
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2432216912
Short name T230
Test name
Test status
Simulation time 339857265 ps
CPU time 4.27 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 210744 kb
Host smart-4749eafc-982e-4dad-9dcc-39eb9020384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432216912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2432216912
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3457619879
Short name T612
Test name
Test status
Simulation time 489924748 ps
CPU time 7.08 seconds
Started Aug 14 04:41:45 PM PDT 24
Finished Aug 14 04:41:52 PM PDT 24
Peak memory 208404 kb
Host smart-cc628756-49b9-4365-9a57-239f12c29517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457619879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3457619879
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3283316999
Short name T755
Test name
Test status
Simulation time 1153721435 ps
CPU time 19.22 seconds
Started Aug 14 04:41:42 PM PDT 24
Finished Aug 14 04:42:01 PM PDT 24
Peak memory 209168 kb
Host smart-280378b7-69f9-4ecf-bc16-1f6de86226ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283316999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3283316999
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2503260567
Short name T348
Test name
Test status
Simulation time 308785457 ps
CPU time 4.49 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:34 PM PDT 24
Peak memory 208288 kb
Host smart-7731e01e-a458-4ea0-b1df-d587db32c2d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503260567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2503260567
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1293103619
Short name T654
Test name
Test status
Simulation time 66697849 ps
CPU time 3.17 seconds
Started Aug 14 04:41:44 PM PDT 24
Finished Aug 14 04:41:47 PM PDT 24
Peak memory 207468 kb
Host smart-87739e8d-0973-483b-9552-f38764559051
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293103619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1293103619
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.18880526
Short name T833
Test name
Test status
Simulation time 1153672461 ps
CPU time 9.87 seconds
Started Aug 14 04:41:49 PM PDT 24
Finished Aug 14 04:41:59 PM PDT 24
Peak memory 209156 kb
Host smart-0431cd5c-ceb5-47da-a5f4-a21733420134
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18880526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.18880526
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2202393336
Short name T80
Test name
Test status
Simulation time 229903327 ps
CPU time 4.61 seconds
Started Aug 14 04:41:53 PM PDT 24
Finished Aug 14 04:41:57 PM PDT 24
Peak memory 209080 kb
Host smart-3a00b38e-df15-406b-a550-f61e03fcf445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202393336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2202393336
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.18936971
Short name T632
Test name
Test status
Simulation time 252626906 ps
CPU time 2.87 seconds
Started Aug 14 04:41:36 PM PDT 24
Finished Aug 14 04:41:39 PM PDT 24
Peak memory 207276 kb
Host smart-97b846e2-6721-4d95-81b5-a4c57e5894a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18936971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.18936971
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2683342989
Short name T624
Test name
Test status
Simulation time 89497016 ps
CPU time 3.26 seconds
Started Aug 14 04:41:47 PM PDT 24
Finished Aug 14 04:41:51 PM PDT 24
Peak memory 207396 kb
Host smart-c66acdaa-f8c2-487e-8ddb-04377bc9c7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683342989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2683342989
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1910805544
Short name T747
Test name
Test status
Simulation time 107830682 ps
CPU time 4.69 seconds
Started Aug 14 04:41:57 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 209856 kb
Host smart-bf2f6971-1b78-41c5-9f5c-7f27e8b5e989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910805544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1910805544
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1665950189
Short name T770
Test name
Test status
Simulation time 197272820 ps
CPU time 2.17 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:30 PM PDT 24
Peak memory 210204 kb
Host smart-957b9d65-6628-456a-ac17-edc650d1c178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665950189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1665950189
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1035244595
Short name T434
Test name
Test status
Simulation time 13475321 ps
CPU time 0.74 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 206448 kb
Host smart-dddc0b97-9da6-4206-a6ae-fc1505966d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035244595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1035244595
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4223585664
Short name T878
Test name
Test status
Simulation time 7339457897 ps
CPU time 32.88 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 215064 kb
Host smart-3f723ded-43ed-4a74-b550-f546506b6c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223585664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4223585664
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2406329401
Short name T315
Test name
Test status
Simulation time 992457291 ps
CPU time 6.03 seconds
Started Aug 14 04:41:48 PM PDT 24
Finished Aug 14 04:41:59 PM PDT 24
Peak memory 207324 kb
Host smart-91cb5871-90ee-4804-b3b4-62380e9dc291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406329401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2406329401
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2044647596
Short name T86
Test name
Test status
Simulation time 389300671 ps
CPU time 6.05 seconds
Started Aug 14 04:42:07 PM PDT 24
Finished Aug 14 04:42:13 PM PDT 24
Peak memory 222776 kb
Host smart-a0b0939a-061b-4fa3-a664-f3ca44701245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044647596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2044647596
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2455753356
Short name T241
Test name
Test status
Simulation time 100559848 ps
CPU time 2.01 seconds
Started Aug 14 04:41:51 PM PDT 24
Finished Aug 14 04:41:53 PM PDT 24
Peak memory 214680 kb
Host smart-6fffd7c9-8808-40f3-a0a5-fa40a0275880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455753356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2455753356
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1940858625
Short name T754
Test name
Test status
Simulation time 693456068 ps
CPU time 3.23 seconds
Started Aug 14 04:41:42 PM PDT 24
Finished Aug 14 04:41:45 PM PDT 24
Peak memory 208860 kb
Host smart-30368837-690e-43de-8144-b525c5dfdbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940858625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1940858625
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2113961233
Short name T803
Test name
Test status
Simulation time 173715586 ps
CPU time 5.83 seconds
Started Aug 14 04:41:36 PM PDT 24
Finished Aug 14 04:41:42 PM PDT 24
Peak memory 207724 kb
Host smart-8c557b3e-54fa-4374-94f8-18e4aac185a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113961233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2113961233
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3131817601
Short name T702
Test name
Test status
Simulation time 147502298 ps
CPU time 2.46 seconds
Started Aug 14 04:42:14 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 207468 kb
Host smart-2289b5c9-2c2a-423c-aee0-7e1e55d68aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131817601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3131817601
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1133163407
Short name T575
Test name
Test status
Simulation time 116141404 ps
CPU time 4.34 seconds
Started Aug 14 04:41:57 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 209440 kb
Host smart-e85c7bc6-82ce-48dc-8c9c-f1e8e3a76284
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133163407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1133163407
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1256012950
Short name T681
Test name
Test status
Simulation time 172150074 ps
CPU time 4.96 seconds
Started Aug 14 04:41:51 PM PDT 24
Finished Aug 14 04:42:01 PM PDT 24
Peak memory 208364 kb
Host smart-91435fd7-aa36-49e7-93f6-d87d53f5d178
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256012950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1256012950
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2216460376
Short name T579
Test name
Test status
Simulation time 689620551 ps
CPU time 8.2 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:42:00 PM PDT 24
Peak memory 209712 kb
Host smart-82fd6556-1d36-42b1-92f3-222b6628c3f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216460376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2216460376
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.150232721
Short name T492
Test name
Test status
Simulation time 101073855 ps
CPU time 2.96 seconds
Started Aug 14 04:41:51 PM PDT 24
Finished Aug 14 04:41:54 PM PDT 24
Peak memory 214860 kb
Host smart-f2a68a3e-53d4-47ee-b820-f49e7a3750ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150232721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.150232721
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3839883195
Short name T461
Test name
Test status
Simulation time 22250871 ps
CPU time 1.64 seconds
Started Aug 14 04:41:49 PM PDT 24
Finished Aug 14 04:41:51 PM PDT 24
Peak memory 207252 kb
Host smart-5865cb5a-ee14-4788-a0de-adecc5389cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839883195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3839883195
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.145822722
Short name T73
Test name
Test status
Simulation time 2902861167 ps
CPU time 26.21 seconds
Started Aug 14 04:41:51 PM PDT 24
Finished Aug 14 04:42:17 PM PDT 24
Peak memory 221540 kb
Host smart-8c8e5f57-e6c6-41af-a7a2-eb1d381ffc62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145822722 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.145822722
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2968516404
Short name T485
Test name
Test status
Simulation time 449573384 ps
CPU time 11.58 seconds
Started Aug 14 04:41:46 PM PDT 24
Finished Aug 14 04:41:58 PM PDT 24
Peak memory 214748 kb
Host smart-5071b55d-ec1c-4893-b7df-5fc7f94cab24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968516404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2968516404
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.628596383
Short name T167
Test name
Test status
Simulation time 426550845 ps
CPU time 2.79 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:11 PM PDT 24
Peak memory 210604 kb
Host smart-f6f50d63-1c51-4d0e-a33a-f78e322f306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628596383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.628596383
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1000698973
Short name T451
Test name
Test status
Simulation time 11818419 ps
CPU time 0.81 seconds
Started Aug 14 04:41:53 PM PDT 24
Finished Aug 14 04:41:54 PM PDT 24
Peak memory 206464 kb
Host smart-091419eb-76d3-40fa-b77d-d7080abb8fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000698973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1000698973
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3865257232
Short name T243
Test name
Test status
Simulation time 114277021 ps
CPU time 3.23 seconds
Started Aug 14 04:41:50 PM PDT 24
Finished Aug 14 04:41:54 PM PDT 24
Peak memory 218612 kb
Host smart-5770b8db-4547-4699-9eba-df290d997fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865257232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3865257232
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.116787495
Short name T270
Test name
Test status
Simulation time 49345245 ps
CPU time 2.51 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:05 PM PDT 24
Peak memory 214816 kb
Host smart-14d3d707-ad2e-43f2-b496-dc48ee591956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116787495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.116787495
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1389688791
Short name T731
Test name
Test status
Simulation time 314209536 ps
CPU time 3.34 seconds
Started Aug 14 04:42:05 PM PDT 24
Finished Aug 14 04:42:08 PM PDT 24
Peak memory 214796 kb
Host smart-8901b08c-974b-4723-aae8-bdc5d80b4b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389688791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1389688791
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4228783231
Short name T546
Test name
Test status
Simulation time 1188244656 ps
CPU time 20.4 seconds
Started Aug 14 04:42:02 PM PDT 24
Finished Aug 14 04:42:22 PM PDT 24
Peak memory 214836 kb
Host smart-d67f70c4-db64-44f6-baa1-0c02c760b028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228783231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4228783231
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.21557581
Short name T518
Test name
Test status
Simulation time 114547136 ps
CPU time 2.39 seconds
Started Aug 14 04:41:29 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 207180 kb
Host smart-c55f7ca3-6a4f-4edf-a924-a3663559f7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21557581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.21557581
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4222399728
Short name T538
Test name
Test status
Simulation time 105193263 ps
CPU time 2.12 seconds
Started Aug 14 04:41:50 PM PDT 24
Finished Aug 14 04:41:57 PM PDT 24
Peak memory 209480 kb
Host smart-7d49e32a-1b82-49fd-ad38-bc326b2fd2f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222399728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4222399728
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1385250081
Short name T844
Test name
Test status
Simulation time 203390112 ps
CPU time 5.46 seconds
Started Aug 14 04:41:48 PM PDT 24
Finished Aug 14 04:41:53 PM PDT 24
Peak memory 209140 kb
Host smart-23d35f1f-b382-4b63-8f17-10840f11efc6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385250081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1385250081
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2167222419
Short name T125
Test name
Test status
Simulation time 366823339 ps
CPU time 3.24 seconds
Started Aug 14 04:42:04 PM PDT 24
Finished Aug 14 04:42:08 PM PDT 24
Peak memory 209184 kb
Host smart-e4b0fd61-7bd2-4765-ac6d-94e38e64a203
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167222419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2167222419
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1309809483
Short name T606
Test name
Test status
Simulation time 130613772 ps
CPU time 5.14 seconds
Started Aug 14 04:42:13 PM PDT 24
Finished Aug 14 04:42:18 PM PDT 24
Peak memory 221200 kb
Host smart-968045b1-7157-4a54-9dd5-687b2fed0e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309809483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1309809483
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1113760171
Short name T625
Test name
Test status
Simulation time 87831503 ps
CPU time 2.04 seconds
Started Aug 14 04:42:13 PM PDT 24
Finished Aug 14 04:42:15 PM PDT 24
Peak memory 207348 kb
Host smart-8e9cb567-1747-4ad3-ba33-cf008fae6d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113760171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1113760171
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.562094505
Short name T236
Test name
Test status
Simulation time 98914316 ps
CPU time 4.4 seconds
Started Aug 14 04:41:33 PM PDT 24
Finished Aug 14 04:41:37 PM PDT 24
Peak memory 209652 kb
Host smart-8099c450-72af-4a97-9af1-23f3599a8334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562094505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.562094505
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.889782384
Short name T2
Test name
Test status
Simulation time 486748779 ps
CPU time 1.53 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:10 PM PDT 24
Peak memory 210324 kb
Host smart-ed977290-8c72-4379-aa63-c97582a4834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889782384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.889782384
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2912300575
Short name T187
Test name
Test status
Simulation time 15199703 ps
CPU time 0.68 seconds
Started Aug 14 04:42:09 PM PDT 24
Finished Aug 14 04:42:10 PM PDT 24
Peak memory 206440 kb
Host smart-ed5f5474-5195-4c4f-aea9-5b85c3fbb0ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912300575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2912300575
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.479708117
Short name T657
Test name
Test status
Simulation time 136625999 ps
CPU time 4.13 seconds
Started Aug 14 04:41:57 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 210016 kb
Host smart-92cfa4b2-8cdb-4f54-b094-b2eed20d1ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479708117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.479708117
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3910607948
Short name T373
Test name
Test status
Simulation time 58762437 ps
CPU time 3.37 seconds
Started Aug 14 04:41:54 PM PDT 24
Finished Aug 14 04:41:58 PM PDT 24
Peak memory 209816 kb
Host smart-ce2ea563-a4b6-42bb-87b5-4f4eb809e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910607948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3910607948
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1481312802
Short name T242
Test name
Test status
Simulation time 442267400 ps
CPU time 3.74 seconds
Started Aug 14 04:41:46 PM PDT 24
Finished Aug 14 04:41:50 PM PDT 24
Peak memory 215312 kb
Host smart-dfa41211-fb5e-4e65-994f-89a14531d2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481312802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1481312802
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1197386967
Short name T60
Test name
Test status
Simulation time 61357822 ps
CPU time 3.2 seconds
Started Aug 14 04:41:49 PM PDT 24
Finished Aug 14 04:41:52 PM PDT 24
Peak memory 210172 kb
Host smart-40731b37-3fda-4607-8e6e-725f813dfc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197386967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1197386967
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.847580220
Short name T707
Test name
Test status
Simulation time 213052042 ps
CPU time 4.61 seconds
Started Aug 14 04:42:07 PM PDT 24
Finished Aug 14 04:42:12 PM PDT 24
Peak memory 218888 kb
Host smart-24be3cff-b7e6-4ec6-8e7f-105697ebfdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847580220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.847580220
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3137611142
Short name T339
Test name
Test status
Simulation time 84869753 ps
CPU time 3.4 seconds
Started Aug 14 04:42:04 PM PDT 24
Finished Aug 14 04:42:08 PM PDT 24
Peak memory 209036 kb
Host smart-b56a7b5f-18a3-4c14-887f-8b7a3641b4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137611142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3137611142
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3685702097
Short name T706
Test name
Test status
Simulation time 404166733 ps
CPU time 3.77 seconds
Started Aug 14 04:42:09 PM PDT 24
Finished Aug 14 04:42:13 PM PDT 24
Peak memory 207596 kb
Host smart-1b481d69-9ee5-4e45-9ca1-40d4e667804d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685702097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3685702097
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2602875908
Short name T486
Test name
Test status
Simulation time 29447103 ps
CPU time 2.08 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:10 PM PDT 24
Peak memory 207460 kb
Host smart-5891c3ce-f422-4f4e-b554-c8f92c5608d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602875908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2602875908
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1933630276
Short name T889
Test name
Test status
Simulation time 136162999 ps
CPU time 2.4 seconds
Started Aug 14 04:41:28 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 207200 kb
Host smart-88ed525c-0b03-4783-ada0-ec385e2cace3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933630276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1933630276
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4022150202
Short name T417
Test name
Test status
Simulation time 1118085238 ps
CPU time 10.8 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:19 PM PDT 24
Peak memory 209472 kb
Host smart-e81bff2e-03ff-44b2-9f59-1393589bd93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022150202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4022150202
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3290795200
Short name T424
Test name
Test status
Simulation time 70168236 ps
CPU time 2.96 seconds
Started Aug 14 04:41:40 PM PDT 24
Finished Aug 14 04:41:43 PM PDT 24
Peak memory 208596 kb
Host smart-681d5a9e-5386-43ba-ad6d-475685009e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290795200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3290795200
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.331823169
Short name T593
Test name
Test status
Simulation time 624705905 ps
CPU time 3.26 seconds
Started Aug 14 04:42:05 PM PDT 24
Finished Aug 14 04:42:08 PM PDT 24
Peak memory 217976 kb
Host smart-5349c991-d752-45e4-8398-e055f73236f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331823169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.331823169
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2933711822
Short name T464
Test name
Test status
Simulation time 4094390374 ps
CPU time 56.78 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 214868 kb
Host smart-c2803005-13f8-4c6b-8163-2fae5b889730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933711822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2933711822
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3310436896
Short name T778
Test name
Test status
Simulation time 165706873 ps
CPU time 4.43 seconds
Started Aug 14 04:41:49 PM PDT 24
Finished Aug 14 04:41:53 PM PDT 24
Peak memory 210928 kb
Host smart-140c2e79-f92e-4d72-a8dd-77063aba0a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310436896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3310436896
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.444831375
Short name T191
Test name
Test status
Simulation time 49640708 ps
CPU time 0.77 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:09 PM PDT 24
Peak memory 206360 kb
Host smart-6c94140b-528f-4c23-aa1e-e367082d2044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444831375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.444831375
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1251379574
Short name T29
Test name
Test status
Simulation time 279761042 ps
CPU time 4.39 seconds
Started Aug 14 04:41:41 PM PDT 24
Finished Aug 14 04:41:51 PM PDT 24
Peak memory 220824 kb
Host smart-39f7a144-4930-4649-bdd0-9ce830790bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251379574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1251379574
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.814959894
Short name T859
Test name
Test status
Simulation time 272302098 ps
CPU time 7.07 seconds
Started Aug 14 04:42:05 PM PDT 24
Finished Aug 14 04:42:12 PM PDT 24
Peak memory 214708 kb
Host smart-a1ee7ebb-7806-460f-8d95-1637e98bdb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814959894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.814959894
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.41218913
Short name T376
Test name
Test status
Simulation time 423793729 ps
CPU time 8.25 seconds
Started Aug 14 04:42:05 PM PDT 24
Finished Aug 14 04:42:13 PM PDT 24
Peak memory 209268 kb
Host smart-f9d79cd1-1d09-41db-9460-d539a84f4a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41218913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.41218913
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3110227893
Short name T271
Test name
Test status
Simulation time 586270824 ps
CPU time 4.59 seconds
Started Aug 14 04:42:09 PM PDT 24
Finished Aug 14 04:42:14 PM PDT 24
Peak memory 215788 kb
Host smart-2e49dacd-5991-4c74-9ad6-019506a7dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110227893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3110227893
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1208405301
Short name T189
Test name
Test status
Simulation time 57168595 ps
CPU time 2.54 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:41:55 PM PDT 24
Peak memory 220596 kb
Host smart-8a3c29b4-4024-4c0c-ab7a-26b063dc9437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208405301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1208405301
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.4039403738
Short name T286
Test name
Test status
Simulation time 2334700699 ps
CPU time 42.26 seconds
Started Aug 14 04:42:01 PM PDT 24
Finished Aug 14 04:42:43 PM PDT 24
Peak memory 214784 kb
Host smart-0540f4d5-b38b-4448-8982-76ee8c5760ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039403738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.4039403738
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.234274159
Short name T642
Test name
Test status
Simulation time 93633119 ps
CPU time 3 seconds
Started Aug 14 04:41:56 PM PDT 24
Finished Aug 14 04:41:59 PM PDT 24
Peak memory 207848 kb
Host smart-6304c5ce-19f1-47e7-a8e9-f68ea72bae5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234274159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.234274159
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1291806985
Short name T105
Test name
Test status
Simulation time 57101778 ps
CPU time 2.77 seconds
Started Aug 14 04:41:56 PM PDT 24
Finished Aug 14 04:41:59 PM PDT 24
Peak memory 207424 kb
Host smart-3a8c7778-b245-4eae-9fda-504444a829b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291806985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1291806985
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1520419418
Short name T520
Test name
Test status
Simulation time 809679915 ps
CPU time 7.11 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 209044 kb
Host smart-70ba8489-74d4-4a3b-b5b2-26534a0e3af3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520419418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1520419418
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.341832985
Short name T854
Test name
Test status
Simulation time 51348650 ps
CPU time 2.76 seconds
Started Aug 14 04:41:53 PM PDT 24
Finished Aug 14 04:41:56 PM PDT 24
Peak memory 207420 kb
Host smart-8be817e6-0d21-4645-8460-d380338893ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341832985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.341832985
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.885583184
Short name T294
Test name
Test status
Simulation time 70545923 ps
CPU time 2.8 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 214664 kb
Host smart-144fda85-66c7-4934-b75b-9a916a8e0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885583184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.885583184
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3898851257
Short name T592
Test name
Test status
Simulation time 572824314 ps
CPU time 2.73 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 209144 kb
Host smart-76b6e37f-c8fe-4770-a350-08d818733958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898851257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3898851257
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1256040956
Short name T219
Test name
Test status
Simulation time 4764419939 ps
CPU time 46.31 seconds
Started Aug 14 04:42:07 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 222908 kb
Host smart-b9ae60ec-2ec8-449b-93f0-a3aa8314a289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256040956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1256040956
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3852690860
Short name T121
Test name
Test status
Simulation time 2184576667 ps
CPU time 23.12 seconds
Started Aug 14 04:42:05 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 223088 kb
Host smart-9e337821-fc61-4209-940f-95f69e59d4fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852690860 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3852690860
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2634409535
Short name T441
Test name
Test status
Simulation time 432761096 ps
CPU time 6.23 seconds
Started Aug 14 04:42:06 PM PDT 24
Finished Aug 14 04:42:12 PM PDT 24
Peak memory 207928 kb
Host smart-f219cd36-d2fd-4111-8a58-0c9a77497408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634409535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2634409535
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2839349935
Short name T529
Test name
Test status
Simulation time 32706062 ps
CPU time 2.08 seconds
Started Aug 14 04:42:07 PM PDT 24
Finished Aug 14 04:42:09 PM PDT 24
Peak memory 210568 kb
Host smart-a31413b7-78f8-40ab-ad07-99224a5f4ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839349935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2839349935
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3586727277
Short name T603
Test name
Test status
Simulation time 7518004 ps
CPU time 0.8 seconds
Started Aug 14 04:42:09 PM PDT 24
Finished Aug 14 04:42:10 PM PDT 24
Peak memory 206304 kb
Host smart-79fcd49b-b942-4132-8421-4c337a7fd71d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586727277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3586727277
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.994780075
Short name T836
Test name
Test status
Simulation time 95308394 ps
CPU time 1.65 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:19 PM PDT 24
Peak memory 210232 kb
Host smart-aa8cc37a-7b9d-4301-9f48-6a71b8af505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994780075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.994780075
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3735448079
Short name T240
Test name
Test status
Simulation time 584052240 ps
CPU time 4.95 seconds
Started Aug 14 04:42:01 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 221704 kb
Host smart-1eeea510-5e6b-4d34-8585-e3bb2c26007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735448079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3735448079
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2891479545
Short name T671
Test name
Test status
Simulation time 61317852 ps
CPU time 4.09 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:03 PM PDT 24
Peak memory 214784 kb
Host smart-2bf6a13b-fefa-4823-86c1-4894d53b8349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891479545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2891479545
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.581773636
Short name T789
Test name
Test status
Simulation time 91003886 ps
CPU time 4.06 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:12 PM PDT 24
Peak memory 208656 kb
Host smart-d9edc87b-9fb7-45d1-ae5e-3ccace5c65f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581773636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.581773636
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1589353343
Short name T428
Test name
Test status
Simulation time 62429820 ps
CPU time 2.82 seconds
Started Aug 14 04:41:41 PM PDT 24
Finished Aug 14 04:41:44 PM PDT 24
Peak memory 208392 kb
Host smart-342a25f8-046d-4410-b324-650770e18805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589353343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1589353343
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1532312285
Short name T491
Test name
Test status
Simulation time 626297122 ps
CPU time 5.43 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 208940 kb
Host smart-463a47e1-a2d5-44c6-938f-4aca1d83906a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532312285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1532312285
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3651066052
Short name T752
Test name
Test status
Simulation time 235267296 ps
CPU time 3.16 seconds
Started Aug 14 04:42:04 PM PDT 24
Finished Aug 14 04:42:07 PM PDT 24
Peak memory 207316 kb
Host smart-1e32fd4c-e9b0-4406-be2d-28b866adbc2a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651066052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3651066052
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3458958648
Short name T574
Test name
Test status
Simulation time 90910795 ps
CPU time 4.11 seconds
Started Aug 14 04:41:42 PM PDT 24
Finished Aug 14 04:41:46 PM PDT 24
Peak memory 209332 kb
Host smart-c6a180d5-4875-478e-bff1-8c8f819d6e4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458958648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3458958648
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1508812047
Short name T811
Test name
Test status
Simulation time 83240467 ps
CPU time 3.46 seconds
Started Aug 14 04:42:25 PM PDT 24
Finished Aug 14 04:42:29 PM PDT 24
Peak memory 210692 kb
Host smart-196609ed-3dd0-4a76-b0c9-7e9d2971e5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508812047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1508812047
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3833640481
Short name T396
Test name
Test status
Simulation time 77514289 ps
CPU time 2.16 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:19 PM PDT 24
Peak memory 207744 kb
Host smart-5fffc621-9730-44d4-b080-f43462a8447f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833640481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3833640481
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.462181463
Short name T481
Test name
Test status
Simulation time 330830519 ps
CPU time 4.42 seconds
Started Aug 14 04:42:01 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 209004 kb
Host smart-1ec8632d-b5cf-48ba-bc57-241a31d269fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462181463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.462181463
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2506455983
Short name T393
Test name
Test status
Simulation time 43181524 ps
CPU time 1.52 seconds
Started Aug 14 04:42:10 PM PDT 24
Finished Aug 14 04:42:12 PM PDT 24
Peak memory 210140 kb
Host smart-373d1e1c-f433-4279-b199-b7c8d10edce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506455983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2506455983
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3739349605
Short name T477
Test name
Test status
Simulation time 57609815 ps
CPU time 0.95 seconds
Started Aug 14 04:42:02 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 206376 kb
Host smart-3585f094-dc09-4814-99e4-c9e25a199be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739349605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3739349605
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2805995557
Short name T325
Test name
Test status
Simulation time 460141590 ps
CPU time 3.71 seconds
Started Aug 14 04:41:47 PM PDT 24
Finished Aug 14 04:41:50 PM PDT 24
Peak memory 214780 kb
Host smart-e6321e1c-87e1-470b-96e6-40f98c814925
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805995557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2805995557
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1257255541
Short name T697
Test name
Test status
Simulation time 1292363509 ps
CPU time 3.48 seconds
Started Aug 14 04:41:57 PM PDT 24
Finished Aug 14 04:42:01 PM PDT 24
Peak memory 208836 kb
Host smart-c16106b0-e41a-4a64-a2a5-54f2b5daac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257255541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1257255541
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3220665123
Short name T855
Test name
Test status
Simulation time 262478400 ps
CPU time 1.66 seconds
Started Aug 14 04:41:59 PM PDT 24
Finished Aug 14 04:42:01 PM PDT 24
Peak memory 214708 kb
Host smart-cea3dbdb-f3e5-47f8-9252-1b67b1bb109e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220665123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3220665123
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4221863025
Short name T835
Test name
Test status
Simulation time 64120123 ps
CPU time 2.58 seconds
Started Aug 14 04:41:53 PM PDT 24
Finished Aug 14 04:41:56 PM PDT 24
Peak memory 221404 kb
Host smart-30a609bb-411b-46c9-a9f4-b3eb5d202ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221863025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4221863025
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3466365605
Short name T14
Test name
Test status
Simulation time 122841077 ps
CPU time 3.82 seconds
Started Aug 14 04:42:10 PM PDT 24
Finished Aug 14 04:42:14 PM PDT 24
Peak memory 209512 kb
Host smart-b8593184-0860-4fd7-ad21-fe1faf616f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466365605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3466365605
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1242753779
Short name T547
Test name
Test status
Simulation time 1055284519 ps
CPU time 8.51 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:42:00 PM PDT 24
Peak memory 209424 kb
Host smart-f5ebf83e-8056-4239-aacf-90645308ffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242753779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1242753779
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1025291189
Short name T779
Test name
Test status
Simulation time 36996993 ps
CPU time 2.53 seconds
Started Aug 14 04:42:06 PM PDT 24
Finished Aug 14 04:42:09 PM PDT 24
Peak memory 209336 kb
Host smart-f35e776b-25cc-4e6f-9646-9de6154da21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025291189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1025291189
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1080885417
Short name T857
Test name
Test status
Simulation time 261504080 ps
CPU time 3.09 seconds
Started Aug 14 04:42:13 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 208980 kb
Host smart-dab9e0f0-0535-41db-b137-7cc759939b37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080885417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1080885417
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.542710803
Short name T871
Test name
Test status
Simulation time 191259847 ps
CPU time 2.57 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:01 PM PDT 24
Peak memory 207392 kb
Host smart-2013b440-e1c2-4bcf-b01a-cf960e52f73d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542710803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.542710803
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1620453292
Short name T852
Test name
Test status
Simulation time 49882375 ps
CPU time 2.89 seconds
Started Aug 14 04:42:13 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 207752 kb
Host smart-0d9a6def-bbb2-4ceb-92f7-c385074fe6f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620453292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1620453292
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3720461891
Short name T82
Test name
Test status
Simulation time 42796013 ps
CPU time 2.27 seconds
Started Aug 14 04:42:01 PM PDT 24
Finished Aug 14 04:42:03 PM PDT 24
Peak memory 215784 kb
Host smart-c55c6cf2-f2f3-4863-838d-0b96ff9b49b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720461891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3720461891
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1558606187
Short name T605
Test name
Test status
Simulation time 80791858 ps
CPU time 3.14 seconds
Started Aug 14 04:42:04 PM PDT 24
Finished Aug 14 04:42:07 PM PDT 24
Peak memory 209236 kb
Host smart-137a128b-89d6-4617-9c73-4ee30ad5efc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558606187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1558606187
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2114238858
Short name T217
Test name
Test status
Simulation time 606910444 ps
CPU time 21.16 seconds
Started Aug 14 04:41:57 PM PDT 24
Finished Aug 14 04:42:19 PM PDT 24
Peak memory 217504 kb
Host smart-73bec32f-aa42-4d8b-9343-4964b17888b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114238858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2114238858
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1810654670
Short name T335
Test name
Test status
Simulation time 3253864408 ps
CPU time 13.01 seconds
Started Aug 14 04:42:07 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 223140 kb
Host smart-5b305674-5ff3-4f43-a8c2-5a38e0163099
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810654670 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1810654670
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1220199898
Short name T636
Test name
Test status
Simulation time 466568436 ps
CPU time 8.61 seconds
Started Aug 14 04:42:06 PM PDT 24
Finished Aug 14 04:42:15 PM PDT 24
Peak memory 209864 kb
Host smart-90e4136f-b2f8-4c26-9b75-d28214688152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220199898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1220199898
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2641766568
Short name T43
Test name
Test status
Simulation time 80742446 ps
CPU time 1.71 seconds
Started Aug 14 04:42:05 PM PDT 24
Finished Aug 14 04:42:07 PM PDT 24
Peak memory 210284 kb
Host smart-c36c6db9-50dd-40e6-8057-cea7437b9233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641766568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2641766568
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2764156597
Short name T468
Test name
Test status
Simulation time 25771878 ps
CPU time 1.06 seconds
Started Aug 14 04:42:05 PM PDT 24
Finished Aug 14 04:42:07 PM PDT 24
Peak memory 206552 kb
Host smart-f43e8e3a-c68a-43bd-92f0-9724d6b8c587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764156597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2764156597
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.497733098
Short name T542
Test name
Test status
Simulation time 56486571 ps
CPU time 2.37 seconds
Started Aug 14 04:42:10 PM PDT 24
Finished Aug 14 04:42:12 PM PDT 24
Peak memory 210556 kb
Host smart-5963cfd3-5457-425d-96d8-e473386eae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497733098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.497733098
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2280182570
Short name T362
Test name
Test status
Simulation time 502833415 ps
CPU time 4.89 seconds
Started Aug 14 04:42:03 PM PDT 24
Finished Aug 14 04:42:08 PM PDT 24
Peak memory 218620 kb
Host smart-ed9a2708-d033-4085-b041-16d6313fe43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280182570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2280182570
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3518646205
Short name T815
Test name
Test status
Simulation time 46899289 ps
CPU time 3.03 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:42:00 PM PDT 24
Peak memory 214872 kb
Host smart-28262ff7-f7f5-4024-972c-79ce208d79ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518646205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3518646205
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.807272529
Short name T680
Test name
Test status
Simulation time 114898870 ps
CPU time 5.34 seconds
Started Aug 14 04:41:59 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 222692 kb
Host smart-78fdd07f-aec7-4ed9-8471-4b60a384cdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807272529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.807272529
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3947713068
Short name T142
Test name
Test status
Simulation time 76380723 ps
CPU time 3.1 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:01 PM PDT 24
Peak memory 217364 kb
Host smart-21872e67-be03-4483-a9a2-6e3576f5b01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947713068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3947713068
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1921705326
Short name T813
Test name
Test status
Simulation time 1018852756 ps
CPU time 7.43 seconds
Started Aug 14 04:42:13 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 209768 kb
Host smart-693e9c67-5eb5-431e-b9da-29795f93eb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921705326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1921705326
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1620648795
Short name T314
Test name
Test status
Simulation time 2986683279 ps
CPU time 15.24 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:33 PM PDT 24
Peak memory 208376 kb
Host smart-2dcfc07e-783b-4f3b-8ed2-5644109b9188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620648795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1620648795
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4187766533
Short name T473
Test name
Test status
Simulation time 122160385 ps
CPU time 2.27 seconds
Started Aug 14 04:42:26 PM PDT 24
Finished Aug 14 04:42:29 PM PDT 24
Peak memory 207192 kb
Host smart-9b50c5c5-6bdf-4c83-99c0-f1af55476ef3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187766533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4187766533
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.801042682
Short name T876
Test name
Test status
Simulation time 216195649 ps
CPU time 2.87 seconds
Started Aug 14 04:42:06 PM PDT 24
Finished Aug 14 04:42:09 PM PDT 24
Peak memory 207384 kb
Host smart-95be501a-7e9e-45d3-be8e-99b0d370fda3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801042682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.801042682
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3187031149
Short name T745
Test name
Test status
Simulation time 629879008 ps
CPU time 4.97 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 208500 kb
Host smart-e20d0736-df7b-4cf0-b7d7-371f7e598f97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187031149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3187031149
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.510645966
Short name T310
Test name
Test status
Simulation time 757452654 ps
CPU time 6.46 seconds
Started Aug 14 04:41:57 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 210536 kb
Host smart-76caa0c9-d153-4b64-a994-ae5371a82486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510645966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.510645966
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.542169966
Short name T589
Test name
Test status
Simulation time 147896739 ps
CPU time 3.49 seconds
Started Aug 14 04:41:56 PM PDT 24
Finished Aug 14 04:41:59 PM PDT 24
Peak memory 207132 kb
Host smart-a93cec6f-70b6-4fda-992c-d3b19b26bfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542169966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.542169966
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3981810683
Short name T664
Test name
Test status
Simulation time 73172599 ps
CPU time 3.37 seconds
Started Aug 14 04:41:59 PM PDT 24
Finished Aug 14 04:42:03 PM PDT 24
Peak memory 209024 kb
Host smart-78d8abf5-d3cd-4c4c-b0d8-f0a60367dbfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981810683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3981810683
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1591612943
Short name T390
Test name
Test status
Simulation time 1026097665 ps
CPU time 7.55 seconds
Started Aug 14 04:41:56 PM PDT 24
Finished Aug 14 04:42:03 PM PDT 24
Peak memory 214808 kb
Host smart-915fc0ff-179e-46aa-b530-58f70790aa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591612943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1591612943
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.697023801
Short name T381
Test name
Test status
Simulation time 63253165 ps
CPU time 3.13 seconds
Started Aug 14 04:41:59 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 210812 kb
Host smart-b8877a6b-c4bc-4318-8140-9f0b609a2aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697023801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.697023801
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2223453744
Short name T543
Test name
Test status
Simulation time 13668750 ps
CPU time 0.73 seconds
Started Aug 14 04:41:52 PM PDT 24
Finished Aug 14 04:41:53 PM PDT 24
Peak memory 206308 kb
Host smart-90a31b6f-7092-47c0-a650-75bde2cac00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223453744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2223453744
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2322812072
Short name T40
Test name
Test status
Simulation time 205528729 ps
CPU time 4.4 seconds
Started Aug 14 04:41:54 PM PDT 24
Finished Aug 14 04:41:58 PM PDT 24
Peak memory 210140 kb
Host smart-f9465770-9f0f-4913-9dcb-69f19a05b7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322812072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2322812072
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.647365847
Short name T352
Test name
Test status
Simulation time 107765884 ps
CPU time 3.58 seconds
Started Aug 14 04:42:12 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 208104 kb
Host smart-9a499585-8787-4d72-be80-7baef5d63e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647365847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.647365847
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3319898718
Short name T58
Test name
Test status
Simulation time 42780053 ps
CPU time 2.91 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:18 PM PDT 24
Peak memory 222784 kb
Host smart-90776228-5bbd-476b-aad6-fb09cc9dea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319898718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3319898718
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3285633772
Short name T45
Test name
Test status
Simulation time 72913709 ps
CPU time 4.3 seconds
Started Aug 14 04:42:24 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 214636 kb
Host smart-775fcb6a-99cb-47fd-ae5a-194cdcf062a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285633772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3285633772
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1114364521
Short name T749
Test name
Test status
Simulation time 368033145 ps
CPU time 4.66 seconds
Started Aug 14 04:41:55 PM PDT 24
Finished Aug 14 04:42:00 PM PDT 24
Peak memory 218764 kb
Host smart-1dd18c8f-fdfd-4986-b816-5f74ddc877da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114364521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1114364521
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1966924958
Short name T357
Test name
Test status
Simulation time 302451703 ps
CPU time 2.51 seconds
Started Aug 14 04:42:16 PM PDT 24
Finished Aug 14 04:42:18 PM PDT 24
Peak memory 207664 kb
Host smart-1e789cbe-2791-47f7-b0e9-4cc2ab7a1215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966924958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1966924958
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1670539061
Short name T212
Test name
Test status
Simulation time 113454293 ps
CPU time 4.02 seconds
Started Aug 14 04:42:26 PM PDT 24
Finished Aug 14 04:42:30 PM PDT 24
Peak memory 207268 kb
Host smart-82af1b65-d90b-4cce-b1dd-2bc6fcdb164a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670539061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1670539061
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2031299335
Short name T446
Test name
Test status
Simulation time 113536627 ps
CPU time 4.44 seconds
Started Aug 14 04:42:04 PM PDT 24
Finished Aug 14 04:42:09 PM PDT 24
Peak memory 209560 kb
Host smart-ac21e999-486e-4695-88f0-325f1b0b20c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031299335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2031299335
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1100989995
Short name T302
Test name
Test status
Simulation time 67548671 ps
CPU time 3 seconds
Started Aug 14 04:42:02 PM PDT 24
Finished Aug 14 04:42:05 PM PDT 24
Peak memory 209312 kb
Host smart-46c3c671-4234-4434-9ebd-7fc7ecec572b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100989995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1100989995
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1081951666
Short name T901
Test name
Test status
Simulation time 311185409 ps
CPU time 3.5 seconds
Started Aug 14 04:42:05 PM PDT 24
Finished Aug 14 04:42:08 PM PDT 24
Peak memory 209968 kb
Host smart-d76b9e8d-e9cd-457d-b097-a693def706e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081951666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1081951666
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3684647781
Short name T429
Test name
Test status
Simulation time 73734180 ps
CPU time 2.92 seconds
Started Aug 14 04:41:54 PM PDT 24
Finished Aug 14 04:41:57 PM PDT 24
Peak memory 207544 kb
Host smart-1ecc685b-02ab-4111-860e-0f9c380a70fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684647781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3684647781
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3229597162
Short name T49
Test name
Test status
Simulation time 4737610496 ps
CPU time 22.35 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:31 PM PDT 24
Peak memory 216668 kb
Host smart-4b249c61-8638-4b0a-8e3d-edc84f282520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229597162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3229597162
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.719406348
Short name T313
Test name
Test status
Simulation time 1504261239 ps
CPU time 21.11 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 222040 kb
Host smart-b0c689d2-572a-4e9e-a9e8-c60fd5a5d141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719406348 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.719406348
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3254324835
Short name T586
Test name
Test status
Simulation time 348640284 ps
CPU time 4.37 seconds
Started Aug 14 04:42:09 PM PDT 24
Finished Aug 14 04:42:14 PM PDT 24
Peak memory 207984 kb
Host smart-d95e22c6-7757-4d2c-bfb8-9f08715543ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254324835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3254324835
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3971789201
Short name T402
Test name
Test status
Simulation time 158733110 ps
CPU time 3.36 seconds
Started Aug 14 04:42:06 PM PDT 24
Finished Aug 14 04:42:09 PM PDT 24
Peak memory 211092 kb
Host smart-d5eb2407-3929-446f-88ab-aedd3307cb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971789201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3971789201
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.641289403
Short name T602
Test name
Test status
Simulation time 31604718 ps
CPU time 0.85 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:19 PM PDT 24
Peak memory 206360 kb
Host smart-1d5b8a55-d3db-44a8-a180-b46dc79546d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641289403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.641289403
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.631908876
Short name T143
Test name
Test status
Simulation time 440033354 ps
CPU time 11.92 seconds
Started Aug 14 04:42:01 PM PDT 24
Finished Aug 14 04:42:13 PM PDT 24
Peak memory 214984 kb
Host smart-2fa206a2-e957-46d1-a272-920fe38f691d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631908876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.631908876
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2264571800
Short name T765
Test name
Test status
Simulation time 320464609 ps
CPU time 2.08 seconds
Started Aug 14 04:42:12 PM PDT 24
Finished Aug 14 04:42:14 PM PDT 24
Peak memory 209300 kb
Host smart-63beeb12-8e67-4b3c-b6a9-14fe09e04dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264571800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2264571800
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1489322586
Short name T887
Test name
Test status
Simulation time 751118824 ps
CPU time 6.61 seconds
Started Aug 14 04:41:59 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 209772 kb
Host smart-3a88d7df-9e4e-4b9e-b84e-d0f196bf5267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489322586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1489322586
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2549127030
Short name T739
Test name
Test status
Simulation time 248128792 ps
CPU time 3.01 seconds
Started Aug 14 04:42:00 PM PDT 24
Finished Aug 14 04:42:03 PM PDT 24
Peak memory 214796 kb
Host smart-4fbbac7b-8c49-4636-88d1-2699fc39bce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549127030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2549127030
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4268576595
Short name T862
Test name
Test status
Simulation time 64573551 ps
CPU time 2.67 seconds
Started Aug 14 04:42:00 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 214820 kb
Host smart-d18ee63b-2d19-4c06-9e7a-b7b6f1e93e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268576595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4268576595
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.828076729
Short name T787
Test name
Test status
Simulation time 59402583 ps
CPU time 3.56 seconds
Started Aug 14 04:42:09 PM PDT 24
Finished Aug 14 04:42:13 PM PDT 24
Peak memory 210940 kb
Host smart-156360b6-a55c-418f-9bcc-a7a189e5f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828076729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.828076729
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1773677804
Short name T342
Test name
Test status
Simulation time 279332715 ps
CPU time 4.68 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:13 PM PDT 24
Peak memory 214776 kb
Host smart-0e3232ac-e03b-4e88-b595-b889c4c54c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773677804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1773677804
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3441102661
Short name T744
Test name
Test status
Simulation time 479278712 ps
CPU time 16.18 seconds
Started Aug 14 04:42:00 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 208900 kb
Host smart-e37028da-72ca-4b27-8bc2-60874dbdd4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441102661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3441102661
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1861809699
Short name T454
Test name
Test status
Simulation time 369499141 ps
CPU time 5.49 seconds
Started Aug 14 04:42:11 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 207284 kb
Host smart-bfb85e61-b539-426d-b893-5db8a60df718
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861809699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1861809699
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3895057052
Short name T861
Test name
Test status
Simulation time 344048103 ps
CPU time 3.65 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 209268 kb
Host smart-6590367b-fb4d-4ae4-9247-a98c5ba1afc1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895057052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3895057052
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1320019123
Short name T792
Test name
Test status
Simulation time 3032174548 ps
CPU time 22.13 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:45 PM PDT 24
Peak memory 209128 kb
Host smart-8bebb5cc-a4fc-4a1c-a68c-3224828c51b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320019123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1320019123
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2355403175
Short name T207
Test name
Test status
Simulation time 56622989 ps
CPU time 1.47 seconds
Started Aug 14 04:42:12 PM PDT 24
Finished Aug 14 04:42:13 PM PDT 24
Peak memory 208468 kb
Host smart-b7191953-e294-4743-9fd5-019562d66a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355403175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2355403175
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.192270358
Short name T443
Test name
Test status
Simulation time 302548671 ps
CPU time 5.49 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:14 PM PDT 24
Peak memory 207944 kb
Host smart-9a452adc-0b7f-4d5e-a219-dfb494f51706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192270358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.192270358
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.494590154
Short name T183
Test name
Test status
Simulation time 343192195 ps
CPU time 12.27 seconds
Started Aug 14 04:42:10 PM PDT 24
Finished Aug 14 04:42:22 PM PDT 24
Peak memory 223060 kb
Host smart-e475de17-7fcf-41d7-828b-9c89ca255aef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494590154 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.494590154
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2992098074
Short name T344
Test name
Test status
Simulation time 209254318 ps
CPU time 3.65 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:12 PM PDT 24
Peak memory 208636 kb
Host smart-dc19933c-fcdd-4ff5-b771-b4cc176a106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992098074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2992098074
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.311430230
Short name T676
Test name
Test status
Simulation time 540425805 ps
CPU time 3.61 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:19 PM PDT 24
Peak memory 210576 kb
Host smart-5db408f0-c77f-4a6e-8f72-896a781db9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311430230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.311430230
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1944666134
Short name T420
Test name
Test status
Simulation time 62374271 ps
CPU time 0.7 seconds
Started Aug 14 04:40:51 PM PDT 24
Finished Aug 14 04:40:51 PM PDT 24
Peak memory 206392 kb
Host smart-778aefd6-2ac5-4cd6-ad0e-3a3b83c62198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944666134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1944666134
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2994589347
Short name T403
Test name
Test status
Simulation time 4276074771 ps
CPU time 54.24 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:42:06 PM PDT 24
Peak memory 215164 kb
Host smart-ce8b2587-3ff0-49d3-b030-f9ec28296747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994589347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2994589347
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1127571561
Short name T616
Test name
Test status
Simulation time 57089136 ps
CPU time 2.26 seconds
Started Aug 14 04:40:42 PM PDT 24
Finished Aug 14 04:40:44 PM PDT 24
Peak memory 210228 kb
Host smart-4c042444-8175-415e-8553-525864c770ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127571561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1127571561
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.806131149
Short name T783
Test name
Test status
Simulation time 65237867 ps
CPU time 3.29 seconds
Started Aug 14 04:40:45 PM PDT 24
Finished Aug 14 04:40:49 PM PDT 24
Peak memory 209872 kb
Host smart-6517fc92-44f1-4899-81c5-3321c96ee47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806131149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.806131149
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3722316325
Short name T87
Test name
Test status
Simulation time 32061320 ps
CPU time 2.12 seconds
Started Aug 14 04:40:47 PM PDT 24
Finished Aug 14 04:40:49 PM PDT 24
Peak memory 214776 kb
Host smart-b1054028-063d-4d78-acd9-53feccd1a78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722316325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3722316325
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.690090383
Short name T868
Test name
Test status
Simulation time 980539596 ps
CPU time 7.37 seconds
Started Aug 14 04:40:51 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 222884 kb
Host smart-6e79501f-3d51-4f98-9858-b55ea0132d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690090383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.690090383
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2417493849
Short name T500
Test name
Test status
Simulation time 27538276 ps
CPU time 2.16 seconds
Started Aug 14 04:40:53 PM PDT 24
Finished Aug 14 04:40:55 PM PDT 24
Peak memory 215176 kb
Host smart-31231d46-c142-4ba0-8e20-d7c4bd180cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417493849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2417493849
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2706616210
Short name T911
Test name
Test status
Simulation time 102068371 ps
CPU time 3.54 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:40 PM PDT 24
Peak memory 210420 kb
Host smart-945d6586-3c73-42ce-b22b-d04031b03bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706616210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2706616210
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.98413954
Short name T826
Test name
Test status
Simulation time 195608276 ps
CPU time 1.81 seconds
Started Aug 14 04:40:35 PM PDT 24
Finished Aug 14 04:40:37 PM PDT 24
Peak memory 207280 kb
Host smart-b8d6ff90-321a-4389-a428-d543f4cd2d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98413954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.98413954
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2250165073
Short name T307
Test name
Test status
Simulation time 110460932 ps
CPU time 3.62 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:40 PM PDT 24
Peak memory 209152 kb
Host smart-d53ff2e2-2c55-4cd1-b9d1-4fcb8f6f7017
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250165073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2250165073
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1456910823
Short name T532
Test name
Test status
Simulation time 420402860 ps
CPU time 3.24 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:39 PM PDT 24
Peak memory 207216 kb
Host smart-fad5eb68-6026-4594-bfce-59b997654944
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456910823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1456910823
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1797479495
Short name T534
Test name
Test status
Simulation time 2228346236 ps
CPU time 13.74 seconds
Started Aug 14 04:40:32 PM PDT 24
Finished Aug 14 04:40:51 PM PDT 24
Peak memory 208376 kb
Host smart-a9feac38-c80f-4a12-a6a3-db1a8ecdf3c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797479495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1797479495
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1372539083
Short name T405
Test name
Test status
Simulation time 746003965 ps
CPU time 4.58 seconds
Started Aug 14 04:40:49 PM PDT 24
Finished Aug 14 04:40:54 PM PDT 24
Peak memory 208828 kb
Host smart-4435cd7c-013d-483c-b82e-6f64a3b44b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372539083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1372539083
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.887241259
Short name T478
Test name
Test status
Simulation time 150523399 ps
CPU time 2.27 seconds
Started Aug 14 04:40:30 PM PDT 24
Finished Aug 14 04:40:33 PM PDT 24
Peak memory 207292 kb
Host smart-58b1bcaa-648e-4870-b4f5-a1e8495ec11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887241259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.887241259
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2297465461
Short name T122
Test name
Test status
Simulation time 248291603 ps
CPU time 16.01 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:29 PM PDT 24
Peak memory 221344 kb
Host smart-745ad845-06d0-4483-9a7c-e924c9dc4b84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297465461 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2297465461
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3140369676
Short name T692
Test name
Test status
Simulation time 197591188 ps
CPU time 3.41 seconds
Started Aug 14 04:40:41 PM PDT 24
Finished Aug 14 04:40:44 PM PDT 24
Peak memory 208512 kb
Host smart-4e4c6416-4fa3-4cb8-9c03-e7080564db61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140369676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3140369676
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3168258788
Short name T209
Test name
Test status
Simulation time 31400734 ps
CPU time 1.75 seconds
Started Aug 14 04:40:56 PM PDT 24
Finished Aug 14 04:40:58 PM PDT 24
Peak memory 210456 kb
Host smart-eaf4f66c-d7bf-487b-b549-325c58810ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168258788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3168258788
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2805752067
Short name T198
Test name
Test status
Simulation time 66813482 ps
CPU time 1.01 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 206604 kb
Host smart-ea04b85b-368b-4364-80e1-54f8be7d2f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805752067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2805752067
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2050907469
Short name T408
Test name
Test status
Simulation time 994392520 ps
CPU time 53.32 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:43:02 PM PDT 24
Peak memory 214808 kb
Host smart-67d81f01-5b36-43ed-a726-f52b5347236f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050907469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2050907469
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1078698081
Short name T447
Test name
Test status
Simulation time 2177094212 ps
CPU time 6.96 seconds
Started Aug 14 04:42:26 PM PDT 24
Finished Aug 14 04:42:33 PM PDT 24
Peak memory 215092 kb
Host smart-3c223f16-f1f4-431b-aee6-594432028f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078698081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1078698081
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1437477233
Short name T264
Test name
Test status
Simulation time 75502946 ps
CPU time 3.16 seconds
Started Aug 14 04:42:16 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 210240 kb
Host smart-d5effb34-3445-443c-b472-7985dacea69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437477233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1437477233
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4226363915
Short name T89
Test name
Test status
Simulation time 157267213 ps
CPU time 2.36 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:18 PM PDT 24
Peak memory 214708 kb
Host smart-3171dabe-085a-48d9-9d92-901208b92f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226363915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4226363915
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1165634783
Short name T903
Test name
Test status
Simulation time 42605588 ps
CPU time 2.95 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:22 PM PDT 24
Peak memory 214812 kb
Host smart-0b3d9420-beac-4953-ae36-0e426d3009ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165634783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1165634783
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1231637904
Short name T591
Test name
Test status
Simulation time 380804657 ps
CPU time 2.84 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:22 PM PDT 24
Peak memory 208008 kb
Host smart-31e4e3e3-ffd2-49c6-866d-92f24292a080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231637904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1231637904
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2112742151
Short name T539
Test name
Test status
Simulation time 124872713 ps
CPU time 2.57 seconds
Started Aug 14 04:42:01 PM PDT 24
Finished Aug 14 04:42:05 PM PDT 24
Peak memory 210664 kb
Host smart-2b164e07-dca5-4752-b4db-20dba3a43ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112742151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2112742151
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.611444441
Short name T892
Test name
Test status
Simulation time 748983493 ps
CPU time 8.16 seconds
Started Aug 14 04:41:49 PM PDT 24
Finished Aug 14 04:41:57 PM PDT 24
Peak memory 207616 kb
Host smart-c4ebf306-62e0-465f-aa8e-251b53a9acd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611444441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.611444441
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1068923133
Short name T563
Test name
Test status
Simulation time 221831963 ps
CPU time 2.85 seconds
Started Aug 14 04:42:07 PM PDT 24
Finished Aug 14 04:42:10 PM PDT 24
Peak memory 207500 kb
Host smart-c9b791a3-9910-418f-8897-b2a6c79837f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068923133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1068923133
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3224668634
Short name T879
Test name
Test status
Simulation time 532265571 ps
CPU time 6.46 seconds
Started Aug 14 04:41:56 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 209080 kb
Host smart-c3825020-75a7-407d-8c8e-52c165219bfc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224668634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3224668634
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1706475658
Short name T850
Test name
Test status
Simulation time 71649454 ps
CPU time 1.71 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 207260 kb
Host smart-e13e888b-74b1-45cb-b7ed-f0888fe12695
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706475658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1706475658
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3046958681
Short name T391
Test name
Test status
Simulation time 418657900 ps
CPU time 2.98 seconds
Started Aug 14 04:42:16 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 210496 kb
Host smart-6a0f0bfb-deec-495a-acfb-e96615f896ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046958681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3046958681
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3917269716
Short name T600
Test name
Test status
Simulation time 1436781452 ps
CPU time 4.86 seconds
Started Aug 14 04:42:16 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 207292 kb
Host smart-5ec5ad4f-7dd8-4e2a-95e8-0bbcaa445d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917269716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3917269716
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1851454428
Short name T722
Test name
Test status
Simulation time 677650697 ps
CPU time 2.98 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 208132 kb
Host smart-afaca8ba-8904-4bb6-b4bf-a99e401bda89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851454428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1851454428
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3008395544
Short name T380
Test name
Test status
Simulation time 600541742 ps
CPU time 10.42 seconds
Started Aug 14 04:41:54 PM PDT 24
Finished Aug 14 04:42:04 PM PDT 24
Peak memory 210700 kb
Host smart-c0d4857e-9de4-45eb-92b6-26533dd139f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008395544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3008395544
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2497155111
Short name T794
Test name
Test status
Simulation time 47632778 ps
CPU time 0.81 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 206300 kb
Host smart-ebb88992-282e-4dd0-9456-f037fd600d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497155111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2497155111
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2702704973
Short name T404
Test name
Test status
Simulation time 596155225 ps
CPU time 7.35 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:29 PM PDT 24
Peak memory 215064 kb
Host smart-83110f50-dd2c-4ec9-adce-76c81e31312c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702704973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2702704973
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2569472460
Short name T32
Test name
Test status
Simulation time 122669048 ps
CPU time 3.14 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 223188 kb
Host smart-14cc9f6a-ed93-488b-9bc6-747975806927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569472460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2569472460
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1742642099
Short name T47
Test name
Test status
Simulation time 228512539 ps
CPU time 4.71 seconds
Started Aug 14 04:42:16 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 218844 kb
Host smart-9867e8cd-d0b8-4887-8614-0c806fa67673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742642099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1742642099
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3196675652
Short name T280
Test name
Test status
Simulation time 74938822 ps
CPU time 2.69 seconds
Started Aug 14 04:42:12 PM PDT 24
Finished Aug 14 04:42:14 PM PDT 24
Peak memory 214776 kb
Host smart-48e8d0f6-ea11-474e-b785-f1269a032779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196675652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3196675652
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1047747811
Short name T368
Test name
Test status
Simulation time 142985951 ps
CPU time 4.95 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:13 PM PDT 24
Peak memory 214716 kb
Host smart-2d8cfebb-8c61-4023-b185-5e1fbd5dd1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047747811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1047747811
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1685847789
Short name T65
Test name
Test status
Simulation time 792723107 ps
CPU time 24.03 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:46 PM PDT 24
Peak memory 223008 kb
Host smart-1bfd6ef3-33d6-49d3-95cf-87d0f1245512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685847789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1685847789
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.404534911
Short name T658
Test name
Test status
Simulation time 353385612 ps
CPU time 3.97 seconds
Started Aug 14 04:42:14 PM PDT 24
Finished Aug 14 04:42:18 PM PDT 24
Peak memory 209768 kb
Host smart-9e397ac3-439c-4ea2-b022-84f17d0bb58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404534911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.404534911
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3773019043
Short name T705
Test name
Test status
Simulation time 915549948 ps
CPU time 4.23 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 208704 kb
Host smart-74d00e9a-23be-4800-a0c6-29ac3f6b9913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773019043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3773019043
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1430808811
Short name T506
Test name
Test status
Simulation time 277467039 ps
CPU time 3.54 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 209560 kb
Host smart-01d1bebe-20cd-4f29-aa13-441e0c65f3ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430808811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1430808811
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.755054553
Short name T525
Test name
Test status
Simulation time 858439401 ps
CPU time 6.78 seconds
Started Aug 14 04:42:13 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 207384 kb
Host smart-e6da7611-a329-4d71-ab33-dd458a9f3106
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755054553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.755054553
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.747652319
Short name T860
Test name
Test status
Simulation time 98495678 ps
CPU time 3.4 seconds
Started Aug 14 04:42:25 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 207312 kb
Host smart-c773bc4f-539d-4e54-a78a-7a59fb0a73d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747652319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.747652319
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1509236543
Short name T908
Test name
Test status
Simulation time 91984886 ps
CPU time 3.34 seconds
Started Aug 14 04:42:11 PM PDT 24
Finished Aug 14 04:42:15 PM PDT 24
Peak memory 207388 kb
Host smart-73af3b15-262d-469d-a46b-4f76fff92072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509236543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1509236543
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2606058729
Short name T422
Test name
Test status
Simulation time 2765271392 ps
CPU time 14.14 seconds
Started Aug 14 04:42:10 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 208544 kb
Host smart-59c0c8a1-01a4-4097-be8b-efde5cd0ce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606058729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2606058729
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1362378491
Short name T196
Test name
Test status
Simulation time 25454758128 ps
CPU time 64.56 seconds
Started Aug 14 04:42:14 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 223008 kb
Host smart-3bc7a531-499f-4970-8fda-2e495b868e08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362378491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1362378491
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.289978546
Short name T767
Test name
Test status
Simulation time 1986298127 ps
CPU time 30.32 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 209024 kb
Host smart-f9c28fe2-1ba9-4361-8829-7e179f282d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289978546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.289978546
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.272104178
Short name T817
Test name
Test status
Simulation time 1704993356 ps
CPU time 8.75 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 211412 kb
Host smart-dda31219-7961-4746-b229-4dd89f35be64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272104178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.272104178
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1118840217
Short name T509
Test name
Test status
Simulation time 101184651 ps
CPU time 0.74 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:22 PM PDT 24
Peak memory 206200 kb
Host smart-b1a552ee-a4c8-42d2-93e5-3fe61748ddbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118840217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1118840217
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3576812389
Short name T364
Test name
Test status
Simulation time 784732334 ps
CPU time 7.08 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 215504 kb
Host smart-2347bf0f-1f9c-43cc-989f-00b5425b88ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576812389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3576812389
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1685230706
Short name T796
Test name
Test status
Simulation time 238888036 ps
CPU time 4.2 seconds
Started Aug 14 04:42:24 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 214728 kb
Host smart-a63e320e-5caa-4752-a438-62e17082e102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685230706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1685230706
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3239383258
Short name T77
Test name
Test status
Simulation time 291602557 ps
CPU time 3.35 seconds
Started Aug 14 04:42:08 PM PDT 24
Finished Aug 14 04:42:12 PM PDT 24
Peak memory 218608 kb
Host smart-d1925ed3-0fce-4f53-a3cb-1f4e536fe26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239383258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3239383258
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3512138587
Short name T369
Test name
Test status
Simulation time 84231111 ps
CPU time 1.91 seconds
Started Aug 14 04:42:14 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 214500 kb
Host smart-459bc0bd-a9c5-46f6-8b43-11f26d1ed19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512138587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3512138587
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2826566228
Short name T758
Test name
Test status
Simulation time 768297245 ps
CPU time 3.92 seconds
Started Aug 14 04:42:11 PM PDT 24
Finished Aug 14 04:42:15 PM PDT 24
Peak memory 214724 kb
Host smart-314e56d3-a88c-43b1-a2cb-a8cd33417747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826566228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2826566228
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.4145054093
Short name T728
Test name
Test status
Simulation time 5951129199 ps
CPU time 54.02 seconds
Started Aug 14 04:42:14 PM PDT 24
Finished Aug 14 04:43:09 PM PDT 24
Peak memory 209212 kb
Host smart-83255487-c2aa-4393-b091-706355ecb103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145054093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.4145054093
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1927807228
Short name T204
Test name
Test status
Simulation time 214399219 ps
CPU time 4.05 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:22 PM PDT 24
Peak memory 207312 kb
Host smart-cdf3969e-a535-4e92-80f5-36405de5d276
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927807228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1927807228
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.53418746
Short name T199
Test name
Test status
Simulation time 186538871 ps
CPU time 3.2 seconds
Started Aug 14 04:42:10 PM PDT 24
Finished Aug 14 04:42:13 PM PDT 24
Peak memory 207356 kb
Host smart-b6dd4ce3-9b22-4576-8206-c36102751956
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53418746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.53418746
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.733088426
Short name T104
Test name
Test status
Simulation time 1612177221 ps
CPU time 3.74 seconds
Started Aug 14 04:42:35 PM PDT 24
Finished Aug 14 04:42:39 PM PDT 24
Peak memory 207392 kb
Host smart-e03cb490-0303-4e63-ba94-4dc9b31027a3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733088426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.733088426
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2122309892
Short name T460
Test name
Test status
Simulation time 144776970 ps
CPU time 3.18 seconds
Started Aug 14 04:41:58 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 218744 kb
Host smart-a0ada32f-1bb1-486a-89ed-4c9b794ca562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122309892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2122309892
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.485345858
Short name T507
Test name
Test status
Simulation time 51112339 ps
CPU time 2.53 seconds
Started Aug 14 04:42:16 PM PDT 24
Finished Aug 14 04:42:19 PM PDT 24
Peak memory 207296 kb
Host smart-d8c1a014-959c-4589-883e-0dc28684b72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485345858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.485345858
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2603970359
Short name T367
Test name
Test status
Simulation time 254159466 ps
CPU time 12.56 seconds
Started Aug 14 04:42:14 PM PDT 24
Finished Aug 14 04:42:27 PM PDT 24
Peak memory 222176 kb
Host smart-8533884a-9f6a-4083-bb95-cb06fd443434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603970359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2603970359
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1919425991
Short name T258
Test name
Test status
Simulation time 113798567 ps
CPU time 3.93 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 209180 kb
Host smart-2bf07b47-4e27-44b6-ac33-3fb94e86700d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919425991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1919425991
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.47131371
Short name T490
Test name
Test status
Simulation time 49833101 ps
CPU time 1.96 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:17 PM PDT 24
Peak memory 210464 kb
Host smart-5df42cc0-8e87-4233-9e9a-ab4c07c9627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47131371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.47131371
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3676393516
Short name T504
Test name
Test status
Simulation time 51481711 ps
CPU time 0.76 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 206376 kb
Host smart-8d8bab55-b55e-4f3d-8d58-7f7cd227ba02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676393516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3676393516
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3320415865
Short name T411
Test name
Test status
Simulation time 137145779 ps
CPU time 6.51 seconds
Started Aug 14 04:42:36 PM PDT 24
Finished Aug 14 04:42:43 PM PDT 24
Peak memory 215128 kb
Host smart-e8d4f400-5d2e-4bf4-b02f-9ea07b9a8604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320415865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3320415865
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.880862103
Short name T334
Test name
Test status
Simulation time 54547062 ps
CPU time 1.67 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:17 PM PDT 24
Peak memory 208068 kb
Host smart-eeb2a17b-8c9e-4c17-8ff8-080937348759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880862103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.880862103
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2858011109
Short name T201
Test name
Test status
Simulation time 233504391 ps
CPU time 4.74 seconds
Started Aug 14 04:42:28 PM PDT 24
Finished Aug 14 04:42:33 PM PDT 24
Peak memory 215092 kb
Host smart-4d04fb23-8888-4449-8bf3-eacd6b0ce638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858011109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2858011109
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1009983429
Short name T337
Test name
Test status
Simulation time 191007815 ps
CPU time 2.85 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 211372 kb
Host smart-70ab0d97-2513-4409-9761-ee93bab7b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009983429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1009983429
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3081874900
Short name T515
Test name
Test status
Simulation time 124656588 ps
CPU time 6.11 seconds
Started Aug 14 04:42:47 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 219572 kb
Host smart-2cbae3a7-315a-4975-86ad-82db58f69284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081874900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3081874900
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2749514186
Short name T710
Test name
Test status
Simulation time 471031140 ps
CPU time 5.33 seconds
Started Aug 14 04:42:11 PM PDT 24
Finished Aug 14 04:42:16 PM PDT 24
Peak memory 214780 kb
Host smart-420fb9de-4323-4727-9d78-f7708205d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749514186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2749514186
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.873185554
Short name T556
Test name
Test status
Simulation time 33934194 ps
CPU time 2.52 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 209200 kb
Host smart-3757173e-2e7f-4699-9a40-4b010a1974c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873185554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.873185554
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1966149722
Short name T799
Test name
Test status
Simulation time 2594833713 ps
CPU time 7.67 seconds
Started Aug 14 04:42:14 PM PDT 24
Finished Aug 14 04:42:22 PM PDT 24
Peak memory 207472 kb
Host smart-90a261cf-43d0-4156-b996-d639b12e208f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966149722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1966149722
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1438574527
Short name T573
Test name
Test status
Simulation time 248336645 ps
CPU time 3 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 207368 kb
Host smart-981d47e0-2b01-4424-b33b-228d95b5bc2a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438574527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1438574527
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1155756116
Short name T669
Test name
Test status
Simulation time 73221081 ps
CPU time 2.76 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 207244 kb
Host smart-b7055753-d01d-46a7-98e2-34bec791d04b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155756116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1155756116
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1915823195
Short name T714
Test name
Test status
Simulation time 619571064 ps
CPU time 14.3 seconds
Started Aug 14 04:42:13 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 214796 kb
Host smart-f33dce1e-2fbe-4903-aa20-c3dc04add645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915823195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1915823195
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.366281444
Short name T442
Test name
Test status
Simulation time 65993958 ps
CPU time 2.93 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:18 PM PDT 24
Peak memory 208560 kb
Host smart-766c361c-9184-47cf-a18c-de79217207b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366281444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.366281444
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1127379828
Short name T231
Test name
Test status
Simulation time 645117374 ps
CPU time 24.49 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:42 PM PDT 24
Peak memory 223048 kb
Host smart-6f4e249c-38ea-44f5-95ba-370d1c4ce2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127379828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1127379828
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3277225594
Short name T644
Test name
Test status
Simulation time 53715599 ps
CPU time 3.41 seconds
Started Aug 14 04:42:34 PM PDT 24
Finished Aug 14 04:42:37 PM PDT 24
Peak memory 207968 kb
Host smart-46aebde9-b31a-4e23-aa38-f29c4b67cbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277225594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3277225594
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.706622516
Short name T206
Test name
Test status
Simulation time 52131020 ps
CPU time 1.43 seconds
Started Aug 14 04:42:26 PM PDT 24
Finished Aug 14 04:42:32 PM PDT 24
Peak memory 209984 kb
Host smart-3b418025-1856-404c-923e-0754cba36b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706622516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.706622516
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.4023382440
Short name T649
Test name
Test status
Simulation time 12952139 ps
CPU time 0.79 seconds
Started Aug 14 04:42:16 PM PDT 24
Finished Aug 14 04:42:17 PM PDT 24
Peak memory 206416 kb
Host smart-c98792a1-8703-48b0-b11b-8e8c81985114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023382440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.4023382440
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.94730246
Short name T311
Test name
Test status
Simulation time 374809364 ps
CPU time 10.15 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:30 PM PDT 24
Peak memory 215732 kb
Host smart-929cc901-0377-4d68-a379-f0423c0655a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94730246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.94730246
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.512465252
Short name T638
Test name
Test status
Simulation time 521265580 ps
CPU time 4.05 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 219016 kb
Host smart-a06bf8d1-0f40-4a9e-b7c8-fdbffedb7299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512465252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.512465252
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4176885140
Short name T457
Test name
Test status
Simulation time 114499934 ps
CPU time 2.52 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 208176 kb
Host smart-3f2ed3af-1ec9-46b7-86ed-c68f797c372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176885140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4176885140
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4169276702
Short name T738
Test name
Test status
Simulation time 54697659 ps
CPU time 1.99 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:19 PM PDT 24
Peak memory 214768 kb
Host smart-53beb329-0708-48b9-8d6c-5dc49f4e8ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169276702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4169276702
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3848171686
Short name T853
Test name
Test status
Simulation time 122031666 ps
CPU time 2.34 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 214656 kb
Host smart-fb5ef244-8c0a-49f7-8caa-d8f9cb67b6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848171686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3848171686
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3090744902
Short name T194
Test name
Test status
Simulation time 56278999 ps
CPU time 3.44 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:18 PM PDT 24
Peak memory 208676 kb
Host smart-0178f17c-8acd-4ff6-9823-2a329c8cddba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090744902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3090744902
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3441959325
Short name T517
Test name
Test status
Simulation time 316336955 ps
CPU time 8.04 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:30 PM PDT 24
Peak memory 218868 kb
Host smart-10e77dd5-232c-4f1f-b24c-5f9a04a06b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441959325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3441959325
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3790268984
Short name T108
Test name
Test status
Simulation time 19544634 ps
CPU time 1.7 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 207468 kb
Host smart-11e8f5dc-bc74-4509-b004-2fbe71198d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790268984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3790268984
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3970798852
Short name T444
Test name
Test status
Simulation time 307799282 ps
CPU time 2.97 seconds
Started Aug 14 04:42:25 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 207236 kb
Host smart-9e0f5286-dc00-4c33-9430-41d821b71f57
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970798852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3970798852
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3545085157
Short name T891
Test name
Test status
Simulation time 55556459 ps
CPU time 2.79 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:31 PM PDT 24
Peak memory 207456 kb
Host smart-fad86ca4-288c-41be-bbde-5f6930068cc7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545085157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3545085157
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.319260083
Short name T581
Test name
Test status
Simulation time 401138368 ps
CPU time 3.4 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 209408 kb
Host smart-9d236efc-db83-4460-9b62-8d753b9accf4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319260083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.319260083
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1833447279
Short name T203
Test name
Test status
Simulation time 452389901 ps
CPU time 2.73 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 210600 kb
Host smart-04af4438-4f6b-4976-ba2f-a43dd951d778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833447279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1833447279
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.4259659049
Short name T825
Test name
Test status
Simulation time 701844436 ps
CPU time 3.02 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 209108 kb
Host smart-9c9f4c85-72c2-40b7-a7a0-b845c20dcc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259659049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.4259659049
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2231407078
Short name T70
Test name
Test status
Simulation time 1035059928 ps
CPU time 23.52 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:43 PM PDT 24
Peak memory 215864 kb
Host smart-c449c192-bf71-4a66-b0ba-458aa841ed47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231407078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2231407078
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.367215780
Short name T548
Test name
Test status
Simulation time 533796915 ps
CPU time 13.16 seconds
Started Aug 14 04:42:33 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 223024 kb
Host smart-2231abe2-77e2-4073-9dd6-31dc9b627f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367215780 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.367215780
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1031217583
Short name T838
Test name
Test status
Simulation time 196352970 ps
CPU time 3.5 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 210380 kb
Host smart-72a5b1aa-f61b-4683-add5-281199c50d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031217583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1031217583
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3858481274
Short name T63
Test name
Test status
Simulation time 97935000 ps
CPU time 2.33 seconds
Started Aug 14 04:42:27 PM PDT 24
Finished Aug 14 04:42:30 PM PDT 24
Peak memory 210828 kb
Host smart-fabeab8e-709d-407f-bef2-16771ccd098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858481274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3858481274
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.522679161
Short name T570
Test name
Test status
Simulation time 21735098 ps
CPU time 0.86 seconds
Started Aug 14 04:42:34 PM PDT 24
Finished Aug 14 04:42:35 PM PDT 24
Peak memory 206364 kb
Host smart-3a11b211-a2bb-4cc1-955f-d11c5553d547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522679161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.522679161
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3364031044
Short name T135
Test name
Test status
Simulation time 38210991 ps
CPU time 3.06 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 214708 kb
Host smart-be69e9ee-c18f-4f33-97b9-33a43b731f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364031044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3364031044
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1038031625
Short name T239
Test name
Test status
Simulation time 94187394 ps
CPU time 2.24 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 214728 kb
Host smart-bfec7168-498a-497e-9aff-dc57f56b5d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038031625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1038031625
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1606624224
Short name T96
Test name
Test status
Simulation time 39138006 ps
CPU time 2.9 seconds
Started Aug 14 04:42:33 PM PDT 24
Finished Aug 14 04:42:36 PM PDT 24
Peak memory 209656 kb
Host smart-e66d2061-edbd-4c76-b77f-a5ec4e50807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606624224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1606624224
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.692346401
Short name T317
Test name
Test status
Simulation time 437163859 ps
CPU time 3.38 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 214728 kb
Host smart-73c59ee7-e2c4-4ecd-9cee-85b37be43160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692346401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.692346401
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1905938036
Short name T220
Test name
Test status
Simulation time 183550842 ps
CPU time 2.87 seconds
Started Aug 14 04:42:25 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 214708 kb
Host smart-a2b3189f-12de-4e85-ad8d-8144265a8086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905938036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1905938036
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2184624975
Short name T15
Test name
Test status
Simulation time 260783036 ps
CPU time 4.51 seconds
Started Aug 14 04:42:32 PM PDT 24
Finished Aug 14 04:42:37 PM PDT 24
Peak memory 210324 kb
Host smart-f3bca0e6-1ce5-48a6-b4ac-3925f8b3986c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184624975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2184624975
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.4011756593
Short name T284
Test name
Test status
Simulation time 74776451 ps
CPU time 2.57 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 207888 kb
Host smart-0a9b98ce-1c6b-42cf-ae9a-ebd9ed5b7b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011756593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4011756593
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1498536521
Short name T333
Test name
Test status
Simulation time 522861786 ps
CPU time 6.28 seconds
Started Aug 14 04:42:24 PM PDT 24
Finished Aug 14 04:42:30 PM PDT 24
Peak memory 208420 kb
Host smart-48d7a232-8b4d-42cc-be04-9ae3adc20528
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498536521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1498536521
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3833201269
Short name T847
Test name
Test status
Simulation time 87364871 ps
CPU time 3.29 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:31 PM PDT 24
Peak memory 209420 kb
Host smart-0755aff2-45bb-45c8-b860-9ecd825a27d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833201269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3833201269
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2725790152
Short name T785
Test name
Test status
Simulation time 15409399959 ps
CPU time 26.48 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:48 PM PDT 24
Peak memory 208736 kb
Host smart-e802b5e7-53c0-48a0-bdcf-dcae6ba15998
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725790152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2725790152
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2490160791
Short name T773
Test name
Test status
Simulation time 93985477 ps
CPU time 2.07 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 210484 kb
Host smart-1c5ff387-0f26-4e45-8569-dc17b3b67fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490160791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2490160791
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3884634218
Short name T732
Test name
Test status
Simulation time 866940912 ps
CPU time 13.92 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:37 PM PDT 24
Peak memory 208884 kb
Host smart-78937ee7-7cfe-4cf5-9dfe-c836a108e018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884634218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3884634218
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2212676352
Short name T488
Test name
Test status
Simulation time 2870435515 ps
CPU time 27.17 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 220580 kb
Host smart-687d92b8-1c1e-4b80-b051-7bc1adf61eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212676352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2212676352
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.992316591
Short name T211
Test name
Test status
Simulation time 9224319351 ps
CPU time 55.83 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 210360 kb
Host smart-d6989d7d-6188-4eab-b359-2dcc96fc466c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992316591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.992316591
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3945547194
Short name T793
Test name
Test status
Simulation time 267666247 ps
CPU time 3.3 seconds
Started Aug 14 04:42:33 PM PDT 24
Finished Aug 14 04:42:36 PM PDT 24
Peak memory 211552 kb
Host smart-3285f189-b708-4341-96c7-e22d1c2f1e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945547194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3945547194
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4082183936
Short name T431
Test name
Test status
Simulation time 38027786 ps
CPU time 0.73 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 206280 kb
Host smart-384698a3-72ac-46ab-ba40-7dec6eb3c055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082183936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4082183936
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2884400246
Short name T278
Test name
Test status
Simulation time 109647573 ps
CPU time 2.51 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 215140 kb
Host smart-6b0933b8-a0d4-4591-a8c5-b32da3a31e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884400246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2884400246
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.4033769857
Short name T516
Test name
Test status
Simulation time 73445469 ps
CPU time 2.09 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 208592 kb
Host smart-2a15641b-1bca-47a5-ac29-8e9d7b0ee42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033769857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4033769857
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2658805351
Short name T663
Test name
Test status
Simulation time 75245674 ps
CPU time 3.58 seconds
Started Aug 14 04:42:33 PM PDT 24
Finished Aug 14 04:42:37 PM PDT 24
Peak memory 214772 kb
Host smart-542cd4d7-5f4f-443b-99f8-d7f538cfa563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658805351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2658805351
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.613689547
Short name T398
Test name
Test status
Simulation time 195937521 ps
CPU time 4.42 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 214876 kb
Host smart-a165a0df-fcbf-4e31-8ac2-a992bb3e9491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613689547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.613689547
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1238990599
Short name T456
Test name
Test status
Simulation time 185342444 ps
CPU time 3 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 220216 kb
Host smart-f0a6bca1-32d8-4cf7-a0c9-948cbfde1990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238990599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1238990599
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2529790450
Short name T493
Test name
Test status
Simulation time 186293664 ps
CPU time 3.57 seconds
Started Aug 14 04:42:34 PM PDT 24
Finished Aug 14 04:42:38 PM PDT 24
Peak memory 208304 kb
Host smart-10680eb1-ea9a-4907-92e8-d821ca1dbf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529790450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2529790450
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1080183384
Short name T734
Test name
Test status
Simulation time 239207267 ps
CPU time 3.79 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 208608 kb
Host smart-8abf0eef-3840-42da-8cd2-921959daa62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080183384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1080183384
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3227502734
Short name T804
Test name
Test status
Simulation time 131129020 ps
CPU time 2.42 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 207384 kb
Host smart-6ec55dbc-b0e6-4de0-b612-009dac63af90
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227502734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3227502734
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.538396649
Short name T208
Test name
Test status
Simulation time 130338966 ps
CPU time 4.27 seconds
Started Aug 14 04:42:15 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 207376 kb
Host smart-5e48a2a2-5cef-45f1-b806-d27d9f6bcc0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538396649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.538396649
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3830097788
Short name T718
Test name
Test status
Simulation time 175712986 ps
CPU time 6.86 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:31 PM PDT 24
Peak memory 209020 kb
Host smart-37bd4c8c-7ef1-4741-a56c-9ca9a88dd709
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830097788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3830097788
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1061078986
Short name T540
Test name
Test status
Simulation time 33476970 ps
CPU time 1.86 seconds
Started Aug 14 04:42:25 PM PDT 24
Finished Aug 14 04:42:27 PM PDT 24
Peak memory 210336 kb
Host smart-96d92c58-29cd-47c2-bd44-9c026571f0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061078986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1061078986
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1497134682
Short name T455
Test name
Test status
Simulation time 234523527 ps
CPU time 2.73 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 208724 kb
Host smart-dbde836c-edf7-404f-95cc-98faadb6866e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497134682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1497134682
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.18142776
Short name T308
Test name
Test status
Simulation time 95811045001 ps
CPU time 582.48 seconds
Started Aug 14 04:42:30 PM PDT 24
Finished Aug 14 04:52:13 PM PDT 24
Peak memory 222904 kb
Host smart-0bb1bf08-85bf-40dc-be7f-40b611216b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18142776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.18142776
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1303961480
Short name T482
Test name
Test status
Simulation time 759031828 ps
CPU time 8.41 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:29 PM PDT 24
Peak memory 222876 kb
Host smart-dd3358d0-646a-426b-980b-ed9c39a23451
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303961480 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1303961480
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1659967703
Short name T881
Test name
Test status
Simulation time 95812267 ps
CPU time 3.08 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 208716 kb
Host smart-ad14f8d6-c368-4dd9-b19a-2c0b33cb9377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659967703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1659967703
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1828526439
Short name T776
Test name
Test status
Simulation time 201577517 ps
CPU time 2.54 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 210308 kb
Host smart-68dd27f6-8eb6-4e5c-8de9-38f9cf109d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828526439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1828526439
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2574092630
Short name T670
Test name
Test status
Simulation time 26079085 ps
CPU time 0.87 seconds
Started Aug 14 04:42:28 PM PDT 24
Finished Aug 14 04:42:29 PM PDT 24
Peak memory 206420 kb
Host smart-2f13bb74-b89e-4a44-8f83-eecd87f7ee82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574092630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2574092630
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.571250761
Short name T832
Test name
Test status
Simulation time 642496164 ps
CPU time 9.92 seconds
Started Aug 14 04:42:44 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 215072 kb
Host smart-62dfd785-3106-4e74-9148-aa7cbd572210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571250761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.571250761
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.4037155245
Short name T20
Test name
Test status
Simulation time 93627574 ps
CPU time 3.93 seconds
Started Aug 14 04:42:31 PM PDT 24
Finished Aug 14 04:42:35 PM PDT 24
Peak memory 219420 kb
Host smart-bcfdeae4-41ea-48a6-b0df-c59cb6be7982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037155245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4037155245
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3129207557
Short name T56
Test name
Test status
Simulation time 513566372 ps
CPU time 14.21 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:36 PM PDT 24
Peak memory 209056 kb
Host smart-6753e27c-f9b7-43b4-97bd-2154445ed336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129207557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3129207557
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1251502352
Short name T375
Test name
Test status
Simulation time 1361034108 ps
CPU time 5.56 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:27 PM PDT 24
Peak memory 209384 kb
Host smart-6ad49b48-e65b-4e91-b945-8c71be246214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251502352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1251502352
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.740551199
Short name T54
Test name
Test status
Simulation time 142090482 ps
CPU time 4.2 seconds
Started Aug 14 04:42:27 PM PDT 24
Finished Aug 14 04:42:32 PM PDT 24
Peak memory 220160 kb
Host smart-6c386687-9030-444d-8daa-8934d65f3823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740551199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.740551199
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1533149631
Short name T328
Test name
Test status
Simulation time 439104041 ps
CPU time 4.85 seconds
Started Aug 14 04:42:29 PM PDT 24
Finished Aug 14 04:42:34 PM PDT 24
Peak memory 210060 kb
Host smart-cb8e6b6a-9a1d-4d26-a342-99525bfa9904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533149631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1533149631
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.937626297
Short name T326
Test name
Test status
Simulation time 130807224 ps
CPU time 5 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 208676 kb
Host smart-39aed924-3c2c-4bbe-a811-fd4d1c0acb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937626297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.937626297
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3700062744
Short name T893
Test name
Test status
Simulation time 53046370 ps
CPU time 2.31 seconds
Started Aug 14 04:42:41 PM PDT 24
Finished Aug 14 04:42:43 PM PDT 24
Peak memory 209024 kb
Host smart-b058b19f-2224-4016-9751-67d4104c2f1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700062744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3700062744
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1000951266
Short name T683
Test name
Test status
Simulation time 11641456454 ps
CPU time 29 seconds
Started Aug 14 04:42:27 PM PDT 24
Finished Aug 14 04:42:56 PM PDT 24
Peak memory 209500 kb
Host smart-a88048ea-083e-4f21-a986-ef50c4db70f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000951266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1000951266
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.4229988021
Short name T665
Test name
Test status
Simulation time 260705520 ps
CPU time 5.55 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:43:03 PM PDT 24
Peak memory 208444 kb
Host smart-493baa07-0574-4bbe-a8a8-38cef0f898b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229988021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.4229988021
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1540620132
Short name T845
Test name
Test status
Simulation time 38004908 ps
CPU time 2.25 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:20 PM PDT 24
Peak memory 208908 kb
Host smart-854b53ea-c64b-480f-b4a1-af2709c2a53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540620132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1540620132
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3651399795
Short name T445
Test name
Test status
Simulation time 208706985 ps
CPU time 2.96 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 207184 kb
Host smart-013b0d0f-fac4-49c0-8f4a-bdc2aef4f33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651399795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3651399795
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3586804278
Short name T611
Test name
Test status
Simulation time 75278087 ps
CPU time 4.51 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:27 PM PDT 24
Peak memory 220244 kb
Host smart-9d78bed8-8c5c-4ce5-80a2-b83462f61ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586804278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3586804278
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1154092504
Short name T72
Test name
Test status
Simulation time 513372427 ps
CPU time 19.18 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:43 PM PDT 24
Peak memory 221940 kb
Host smart-d7f2621c-7a9b-4f9c-8681-af7d99796ecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154092504 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1154092504
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4180980954
Short name T726
Test name
Test status
Simulation time 601543315 ps
CPU time 7.52 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:30 PM PDT 24
Peak memory 209740 kb
Host smart-e28469a0-53fa-4e06-be7c-d8b003058107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180980954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4180980954
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3877419370
Short name T753
Test name
Test status
Simulation time 31812313 ps
CPU time 1.96 seconds
Started Aug 14 04:42:49 PM PDT 24
Finished Aug 14 04:42:51 PM PDT 24
Peak memory 210496 kb
Host smart-3cf7802b-bcad-4aa5-9c98-3f949960ff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877419370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3877419370
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3643056421
Short name T421
Test name
Test status
Simulation time 13575852 ps
CPU time 0.82 seconds
Started Aug 14 04:42:34 PM PDT 24
Finished Aug 14 04:42:35 PM PDT 24
Peak memory 206376 kb
Host smart-1c994649-7dec-44b3-9929-b3afe03776c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643056421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3643056421
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2346907355
Short name T349
Test name
Test status
Simulation time 110894191 ps
CPU time 5.95 seconds
Started Aug 14 04:42:38 PM PDT 24
Finished Aug 14 04:42:44 PM PDT 24
Peak memory 215836 kb
Host smart-51b9af13-93ec-4cc5-b0a7-1ed0af58e651
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346907355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2346907355
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1064413109
Short name T30
Test name
Test status
Simulation time 168016340 ps
CPU time 1.71 seconds
Started Aug 14 04:42:54 PM PDT 24
Finished Aug 14 04:42:56 PM PDT 24
Peak memory 209808 kb
Host smart-b40071e1-bcb0-4f7d-9919-97bee7699bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064413109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1064413109
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2875815459
Short name T494
Test name
Test status
Simulation time 87821655 ps
CPU time 1.74 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 207888 kb
Host smart-f0568a23-7873-421f-b1a4-61edbf886f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875815459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2875815459
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2884413672
Short name T771
Test name
Test status
Simulation time 79362882 ps
CPU time 3.37 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 222872 kb
Host smart-e91dcd6d-aa70-4857-9a9b-c503a483f68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884413672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2884413672
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2664782440
Short name T660
Test name
Test status
Simulation time 132557265 ps
CPU time 5.36 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 209784 kb
Host smart-32c3cba8-981a-4cab-a938-7052eae32205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664782440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2664782440
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.8637805
Short name T499
Test name
Test status
Simulation time 75988275 ps
CPU time 2.2 seconds
Started Aug 14 04:42:18 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 207280 kb
Host smart-3828f6b4-ce1c-4e4e-972c-48645b8ae99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8637805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.8637805
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1016652502
Short name T821
Test name
Test status
Simulation time 1086525825 ps
CPU time 36 seconds
Started Aug 14 04:42:48 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 209304 kb
Host smart-99fe60e5-9396-435b-bc39-f7570d342ecb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016652502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1016652502
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4077373404
Short name T679
Test name
Test status
Simulation time 80095678 ps
CPU time 2.4 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:42:55 PM PDT 24
Peak memory 207488 kb
Host smart-168c309c-48fb-4f42-8ab0-754130658447
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077373404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4077373404
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2637561579
Short name T580
Test name
Test status
Simulation time 3801094788 ps
CPU time 24.24 seconds
Started Aug 14 04:42:17 PM PDT 24
Finished Aug 14 04:42:42 PM PDT 24
Peak memory 208968 kb
Host smart-6f53fbbf-a680-4a74-9b69-c1ba4a03ae52
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637561579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2637561579
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1266448591
Short name T505
Test name
Test status
Simulation time 168713092 ps
CPU time 3.2 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 218524 kb
Host smart-9e6424bf-98ee-4e21-b0d9-c17e8ec577f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266448591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1266448591
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1338322113
Short name T476
Test name
Test status
Simulation time 41484285 ps
CPU time 1.69 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 207052 kb
Host smart-230e7de2-571e-48ef-8167-942c6671ca2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338322113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1338322113
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2541714950
Short name T197
Test name
Test status
Simulation time 1778079299 ps
CPU time 17.32 seconds
Started Aug 14 04:42:19 PM PDT 24
Finished Aug 14 04:42:36 PM PDT 24
Peak memory 218552 kb
Host smart-9cc60705-c551-4f72-8872-35a7342d05dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541714950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2541714950
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1495553038
Short name T523
Test name
Test status
Simulation time 968668334 ps
CPU time 8.85 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:43:01 PM PDT 24
Peak memory 207284 kb
Host smart-0b823878-9eab-4524-b6bb-1d15a011e1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495553038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1495553038
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3130837050
Short name T64
Test name
Test status
Simulation time 306128686 ps
CPU time 2.3 seconds
Started Aug 14 04:42:46 PM PDT 24
Finished Aug 14 04:42:49 PM PDT 24
Peak memory 210556 kb
Host smart-03d8a708-15cb-4a1a-90e6-21b396edf376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130837050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3130837050
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2708183346
Short name T425
Test name
Test status
Simulation time 28250847 ps
CPU time 1.11 seconds
Started Aug 14 04:42:38 PM PDT 24
Finished Aug 14 04:42:39 PM PDT 24
Peak memory 206648 kb
Host smart-1694f5ee-e0ea-45d6-b040-3151dae54700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708183346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2708183346
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.610520344
Short name T33
Test name
Test status
Simulation time 124706362 ps
CPU time 2.42 seconds
Started Aug 14 04:42:39 PM PDT 24
Finished Aug 14 04:42:42 PM PDT 24
Peak memory 215144 kb
Host smart-e5ceb350-4583-4995-a705-2f3f84e778e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610520344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.610520344
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1942737566
Short name T693
Test name
Test status
Simulation time 134148702 ps
CPU time 2.35 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 208736 kb
Host smart-cfcdcfba-7c66-46fb-9517-5675e348bd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942737566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1942737566
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1814596351
Short name T100
Test name
Test status
Simulation time 440666420 ps
CPU time 3.4 seconds
Started Aug 14 04:42:26 PM PDT 24
Finished Aug 14 04:42:30 PM PDT 24
Peak memory 219868 kb
Host smart-6cdb126d-d728-4a65-801a-b4be4860327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814596351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1814596351
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.307606410
Short name T554
Test name
Test status
Simulation time 119901108 ps
CPU time 4.78 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 214712 kb
Host smart-25f26c2e-3c76-4ba7-9dd3-0320065bd805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307606410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.307606410
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3821863620
Short name T750
Test name
Test status
Simulation time 484584864 ps
CPU time 3.56 seconds
Started Aug 14 04:42:55 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 219304 kb
Host smart-11f97c64-d5b8-408c-9557-4aea8aec1b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821863620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3821863620
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3146759176
Short name T916
Test name
Test status
Simulation time 423231126 ps
CPU time 5.01 seconds
Started Aug 14 04:42:51 PM PDT 24
Finished Aug 14 04:42:56 PM PDT 24
Peak memory 207772 kb
Host smart-50bdef4a-88e0-4063-9f57-cc4cefd9a693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146759176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3146759176
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1413698036
Short name T798
Test name
Test status
Simulation time 1014166913 ps
CPU time 13.4 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:35 PM PDT 24
Peak memory 209064 kb
Host smart-4a38ff77-b8be-4636-a668-20bc01bfd4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413698036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1413698036
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1797025572
Short name T831
Test name
Test status
Simulation time 81079900 ps
CPU time 3.85 seconds
Started Aug 14 04:43:02 PM PDT 24
Finished Aug 14 04:43:06 PM PDT 24
Peak memory 209244 kb
Host smart-7bd92936-28f3-40d1-9b1f-c08a0fd97826
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797025572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1797025572
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3704459838
Short name T555
Test name
Test status
Simulation time 158567682 ps
CPU time 3.08 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 207400 kb
Host smart-131df09f-ba42-4284-8706-427d093e963c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704459838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3704459838
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2063524350
Short name T709
Test name
Test status
Simulation time 170388074 ps
CPU time 2.5 seconds
Started Aug 14 04:42:45 PM PDT 24
Finished Aug 14 04:42:48 PM PDT 24
Peak memory 207488 kb
Host smart-df5d93dd-60f6-4a97-85ed-d18382021082
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063524350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2063524350
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2574933146
Short name T914
Test name
Test status
Simulation time 47586678 ps
CPU time 2 seconds
Started Aug 14 04:43:01 PM PDT 24
Finished Aug 14 04:43:03 PM PDT 24
Peak memory 215956 kb
Host smart-c6dd463a-1c52-47fa-a5ff-af79a17c1ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574933146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2574933146
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3845709608
Short name T626
Test name
Test status
Simulation time 627040221 ps
CPU time 3.11 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 207340 kb
Host smart-64d71664-c361-4b0a-b5de-5852b995afa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845709608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3845709608
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2928294376
Short name T877
Test name
Test status
Simulation time 6807760370 ps
CPU time 34.92 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:58 PM PDT 24
Peak memory 222928 kb
Host smart-b3929359-4319-4082-8bcd-0cdf25153141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928294376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2928294376
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.820840885
Short name T730
Test name
Test status
Simulation time 1711254710 ps
CPU time 12.51 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:34 PM PDT 24
Peak memory 220244 kb
Host smart-465d6f43-e7a3-4258-8d06-359e0179d886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820840885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.820840885
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.4213853839
Short name T761
Test name
Test status
Simulation time 92158297 ps
CPU time 2.77 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 210408 kb
Host smart-b2f80fc2-94c9-4b1e-9874-9515a6fce34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213853839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.4213853839
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.550495701
Short name T531
Test name
Test status
Simulation time 29391592 ps
CPU time 0.71 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:40:37 PM PDT 24
Peak memory 206352 kb
Host smart-d2fdf7f5-5b2f-438a-8451-e05bfa1ccb80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550495701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.550495701
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1693258782
Short name T533
Test name
Test status
Simulation time 1318555085 ps
CPU time 32.38 seconds
Started Aug 14 04:40:58 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 219144 kb
Host smart-a616127a-d26d-4225-8627-7689b1918c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693258782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1693258782
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1440654496
Short name T843
Test name
Test status
Simulation time 120932763 ps
CPU time 1.65 seconds
Started Aug 14 04:40:35 PM PDT 24
Finished Aug 14 04:40:42 PM PDT 24
Peak memory 208316 kb
Host smart-e4d3c907-8da4-47a5-9ac5-b0f8e4dea393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440654496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1440654496
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.951236798
Short name T279
Test name
Test status
Simulation time 227650334 ps
CPU time 2.36 seconds
Started Aug 14 04:40:51 PM PDT 24
Finished Aug 14 04:40:54 PM PDT 24
Peak memory 214712 kb
Host smart-2650368a-b800-45b1-a796-29764c00ed40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951236798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.951236798
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2386074481
Short name T51
Test name
Test status
Simulation time 71281356 ps
CPU time 2.23 seconds
Started Aug 14 04:40:49 PM PDT 24
Finished Aug 14 04:40:52 PM PDT 24
Peak memory 222872 kb
Host smart-386c1742-45c4-44c9-ad88-143d2ed35b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386074481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2386074481
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.130187424
Short name T812
Test name
Test status
Simulation time 212339043 ps
CPU time 4.41 seconds
Started Aug 14 04:40:30 PM PDT 24
Finished Aug 14 04:40:34 PM PDT 24
Peak memory 208724 kb
Host smart-0825eec5-aa0a-46f5-b109-cb910246d59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130187424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.130187424
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3913924280
Short name T607
Test name
Test status
Simulation time 130638912 ps
CPU time 2.59 seconds
Started Aug 14 04:41:00 PM PDT 24
Finished Aug 14 04:41:03 PM PDT 24
Peak memory 209192 kb
Host smart-4c0a0036-301a-4f24-ab07-fa8483c26f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913924280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3913924280
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3415510861
Short name T462
Test name
Test status
Simulation time 202179744 ps
CPU time 6.89 seconds
Started Aug 14 04:40:48 PM PDT 24
Finished Aug 14 04:40:55 PM PDT 24
Peak memory 208552 kb
Host smart-6713fadd-58ab-4081-94ab-9c8342453ce1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415510861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3415510861
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1742279269
Short name T290
Test name
Test status
Simulation time 414807986 ps
CPU time 4.29 seconds
Started Aug 14 04:40:52 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 208912 kb
Host smart-fcf7edef-be7f-4c37-8419-381daa012814
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742279269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1742279269
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.481700424
Short name T263
Test name
Test status
Simulation time 387053084 ps
CPU time 5.87 seconds
Started Aug 14 04:40:32 PM PDT 24
Finished Aug 14 04:40:38 PM PDT 24
Peak memory 209104 kb
Host smart-753de240-560e-408b-bf08-2a763841f518
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481700424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.481700424
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2256940292
Short name T561
Test name
Test status
Simulation time 483546832 ps
CPU time 3.62 seconds
Started Aug 14 04:40:35 PM PDT 24
Finished Aug 14 04:40:39 PM PDT 24
Peak memory 218764 kb
Host smart-f49ad503-f952-45f6-bafb-88b76c8595b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256940292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2256940292
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.399332656
Short name T872
Test name
Test status
Simulation time 427268702 ps
CPU time 4.61 seconds
Started Aug 14 04:40:57 PM PDT 24
Finished Aug 14 04:41:02 PM PDT 24
Peak memory 209192 kb
Host smart-85ee81e8-9085-49e1-a2cf-d3e8201771de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399332656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.399332656
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1937742773
Short name T648
Test name
Test status
Simulation time 16572929 ps
CPU time 0.9 seconds
Started Aug 14 04:40:55 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 206560 kb
Host smart-0c0b989a-d963-47ff-9020-e705150f7540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937742773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1937742773
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1525113554
Short name T834
Test name
Test status
Simulation time 255774889 ps
CPU time 10.48 seconds
Started Aug 14 04:41:03 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 222948 kb
Host smart-1c974803-1145-41a9-a86b-18d202d25999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525113554 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1525113554
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.772554143
Short name T809
Test name
Test status
Simulation time 70681018 ps
CPU time 3.64 seconds
Started Aug 14 04:40:48 PM PDT 24
Finished Aug 14 04:40:57 PM PDT 24
Peak memory 208032 kb
Host smart-79eb428a-64c7-426e-9c8a-75af0b3ed630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772554143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.772554143
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1860969471
Short name T535
Test name
Test status
Simulation time 31872505 ps
CPU time 0.79 seconds
Started Aug 14 04:40:38 PM PDT 24
Finished Aug 14 04:40:39 PM PDT 24
Peak memory 206416 kb
Host smart-4f6944ce-5f19-4277-a669-efbf02891924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860969471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1860969471
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3493996635
Short name T21
Test name
Test status
Simulation time 134936751 ps
CPU time 2.7 seconds
Started Aug 14 04:41:09 PM PDT 24
Finished Aug 14 04:41:12 PM PDT 24
Peak memory 215088 kb
Host smart-b9d96810-377e-4ee8-8bc2-589d7a6ca041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493996635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3493996635
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3099156080
Short name T720
Test name
Test status
Simulation time 143350082 ps
CPU time 3.76 seconds
Started Aug 14 04:41:09 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 209900 kb
Host smart-16dd04ce-bc64-49bc-b24b-1576852fbe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099156080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3099156080
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4184589154
Short name T126
Test name
Test status
Simulation time 106122151 ps
CPU time 2.06 seconds
Started Aug 14 04:40:39 PM PDT 24
Finished Aug 14 04:40:41 PM PDT 24
Peak memory 214748 kb
Host smart-bab7e9a0-c1dc-423f-825f-b740e97b7bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184589154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.4184589154
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3482610118
Short name T587
Test name
Test status
Simulation time 335384438 ps
CPU time 4.11 seconds
Started Aug 14 04:40:47 PM PDT 24
Finished Aug 14 04:40:51 PM PDT 24
Peak memory 214684 kb
Host smart-33934ba2-c452-4dd9-b794-f107db198a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482610118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3482610118
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3991788515
Short name T851
Test name
Test status
Simulation time 58523123 ps
CPU time 3.68 seconds
Started Aug 14 04:41:09 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 210108 kb
Host smart-7670bc30-27b3-485c-8208-84652d1aca6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991788515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3991788515
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1089320190
Short name T541
Test name
Test status
Simulation time 258320997 ps
CPU time 4.59 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 207772 kb
Host smart-75c10ea4-d0a9-4700-bf1c-79f8b55a585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089320190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1089320190
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2824400164
Short name T610
Test name
Test status
Simulation time 280230514 ps
CPU time 3.6 seconds
Started Aug 14 04:41:01 PM PDT 24
Finished Aug 14 04:41:05 PM PDT 24
Peak memory 207220 kb
Host smart-7246da6e-1574-4a63-9100-fb444fcd562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824400164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2824400164
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1817361955
Short name T84
Test name
Test status
Simulation time 211893346 ps
CPU time 6.94 seconds
Started Aug 14 04:40:49 PM PDT 24
Finished Aug 14 04:41:06 PM PDT 24
Peak memory 208436 kb
Host smart-c96d8b84-e0dd-4174-9243-a87d78896441
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817361955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1817361955
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1730859943
Short name T772
Test name
Test status
Simulation time 318494932 ps
CPU time 3.06 seconds
Started Aug 14 04:40:42 PM PDT 24
Finished Aug 14 04:40:45 PM PDT 24
Peak memory 207348 kb
Host smart-5698878a-3e21-46b2-b7ff-75713e1ace85
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730859943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1730859943
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2047408556
Short name T715
Test name
Test status
Simulation time 60096576 ps
CPU time 3.18 seconds
Started Aug 14 04:40:51 PM PDT 24
Finished Aug 14 04:40:54 PM PDT 24
Peak memory 208952 kb
Host smart-54fe76f6-1915-4d0b-a5e6-c4a18dbf933d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047408556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2047408556
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4184476976
Short name T604
Test name
Test status
Simulation time 49801004 ps
CPU time 1.75 seconds
Started Aug 14 04:40:55 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 208376 kb
Host smart-7c69d4af-1b34-4532-92c7-3640033f7463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184476976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4184476976
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3600811522
Short name T423
Test name
Test status
Simulation time 179002309 ps
CPU time 3.64 seconds
Started Aug 14 04:41:15 PM PDT 24
Finished Aug 14 04:41:19 PM PDT 24
Peak memory 208508 kb
Host smart-ed02691a-2e2c-4dda-b065-01b9c700d431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600811522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3600811522
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3963577383
Short name T305
Test name
Test status
Simulation time 1476148292 ps
CPU time 29.87 seconds
Started Aug 14 04:40:36 PM PDT 24
Finished Aug 14 04:41:06 PM PDT 24
Peak memory 215620 kb
Host smart-c41a3f2c-6246-485a-a75b-86044b262870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963577383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3963577383
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3275539422
Short name T489
Test name
Test status
Simulation time 244014081 ps
CPU time 4.62 seconds
Started Aug 14 04:40:54 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 209456 kb
Host smart-eee9aa38-f2d6-4568-abb0-59252fa0bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275539422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3275539422
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2660012258
Short name T394
Test name
Test status
Simulation time 113246637 ps
CPU time 3.51 seconds
Started Aug 14 04:40:51 PM PDT 24
Finished Aug 14 04:40:55 PM PDT 24
Peak memory 210696 kb
Host smart-b530914d-a6cb-4268-b34b-da1d988b9394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660012258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2660012258
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3699601793
Short name T467
Test name
Test status
Simulation time 134667640 ps
CPU time 0.74 seconds
Started Aug 14 04:41:00 PM PDT 24
Finished Aug 14 04:41:01 PM PDT 24
Peak memory 206420 kb
Host smart-147264f4-f0e7-411b-83c7-dee3fe38d7e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699601793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3699601793
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1216404093
Short name T10
Test name
Test status
Simulation time 190084215 ps
CPU time 1.67 seconds
Started Aug 14 04:40:52 PM PDT 24
Finished Aug 14 04:40:54 PM PDT 24
Peak memory 219268 kb
Host smart-e6a872e4-54a0-4e79-afbd-3cfb80496d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216404093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1216404093
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1260168576
Short name T618
Test name
Test status
Simulation time 63480070 ps
CPU time 2.47 seconds
Started Aug 14 04:41:11 PM PDT 24
Finished Aug 14 04:41:14 PM PDT 24
Peak memory 214800 kb
Host smart-515924f7-1872-4e10-b3d9-4b323bb52775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260168576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1260168576
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.41150609
Short name T694
Test name
Test status
Simulation time 1304135918 ps
CPU time 5.19 seconds
Started Aug 14 04:40:41 PM PDT 24
Finished Aug 14 04:40:46 PM PDT 24
Peak memory 214496 kb
Host smart-edbc17ff-1432-4ce9-83f2-9870f40a912b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41150609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.41150609
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.664146615
Short name T759
Test name
Test status
Simulation time 645207191 ps
CPU time 4.11 seconds
Started Aug 14 04:40:48 PM PDT 24
Finished Aug 14 04:40:55 PM PDT 24
Peak memory 221284 kb
Host smart-adc53e97-2924-4732-a64d-882b04af5bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664146615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.664146615
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_random.3661143756
Short name T355
Test name
Test status
Simulation time 61457183 ps
CPU time 3.65 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:06 PM PDT 24
Peak memory 218892 kb
Host smart-043882f8-35be-4b12-b350-8a227eaa305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661143756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3661143756
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2425032960
Short name T870
Test name
Test status
Simulation time 83898460 ps
CPU time 2.4 seconds
Started Aug 14 04:40:54 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 207408 kb
Host smart-0bf1d548-8616-45c3-80c1-6c4f7392b992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425032960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2425032960
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2441425830
Short name T583
Test name
Test status
Simulation time 261092797 ps
CPU time 3.52 seconds
Started Aug 14 04:41:05 PM PDT 24
Finished Aug 14 04:41:09 PM PDT 24
Peak memory 209140 kb
Host smart-0aa98b3f-822c-4636-9779-adb7437f33cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441425830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2441425830
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.263821687
Short name T818
Test name
Test status
Simulation time 3140288777 ps
CPU time 18.95 seconds
Started Aug 14 04:40:49 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 208728 kb
Host smart-686d23e4-5ae2-48c0-b51b-d63802bba743
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263821687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.263821687
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.607540131
Short name T588
Test name
Test status
Simulation time 617853206 ps
CPU time 4.28 seconds
Started Aug 14 04:40:55 PM PDT 24
Finished Aug 14 04:41:00 PM PDT 24
Peak memory 209132 kb
Host smart-a8cc47a1-06d7-4476-88ac-55cd952add36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607540131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.607540131
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1437430136
Short name T466
Test name
Test status
Simulation time 393459154 ps
CPU time 3.34 seconds
Started Aug 14 04:40:55 PM PDT 24
Finished Aug 14 04:40:58 PM PDT 24
Peak memory 216280 kb
Host smart-1036f7a6-3cd3-4e78-a1a7-6f68be24cdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437430136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1437430136
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.4067578389
Short name T708
Test name
Test status
Simulation time 60607385 ps
CPU time 2.7 seconds
Started Aug 14 04:40:35 PM PDT 24
Finished Aug 14 04:40:37 PM PDT 24
Peak memory 208324 kb
Host smart-bf2d8c73-d50b-43ab-ab19-95da9fc7fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067578389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.4067578389
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1468968930
Short name T712
Test name
Test status
Simulation time 891137930 ps
CPU time 12.25 seconds
Started Aug 14 04:41:05 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 215652 kb
Host smart-d85efc0f-9a21-486c-b001-de636228cf7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468968930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1468968930
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1562506714
Short name T181
Test name
Test status
Simulation time 2700172641 ps
CPU time 9.46 seconds
Started Aug 14 04:40:55 PM PDT 24
Finished Aug 14 04:41:05 PM PDT 24
Peak memory 217944 kb
Host smart-db1ac604-4b09-411f-919f-4b9d59dece56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562506714 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1562506714
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.303152649
Short name T289
Test name
Test status
Simulation time 2506491849 ps
CPU time 6.17 seconds
Started Aug 14 04:41:02 PM PDT 24
Finished Aug 14 04:41:08 PM PDT 24
Peak memory 209204 kb
Host smart-f823fc2b-7bb5-4970-8820-3d24f3547dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303152649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.303152649
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1872050674
Short name T634
Test name
Test status
Simulation time 130943477 ps
CPU time 4.21 seconds
Started Aug 14 04:41:05 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 211432 kb
Host smart-f692b25e-860a-4ff7-acb1-a442f0e07cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872050674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1872050674
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1042807167
Short name T419
Test name
Test status
Simulation time 16549959 ps
CPU time 0.78 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 206348 kb
Host smart-3a10b177-76e0-464d-b2de-5282621635e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042807167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1042807167
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3053839633
Short name T361
Test name
Test status
Simulation time 393845862 ps
CPU time 4.21 seconds
Started Aug 14 04:40:33 PM PDT 24
Finished Aug 14 04:40:38 PM PDT 24
Peak memory 214808 kb
Host smart-58eb9041-7700-4b71-ad08-ecbf7c452390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053839633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3053839633
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1274187840
Short name T737
Test name
Test status
Simulation time 110593072 ps
CPU time 1.53 seconds
Started Aug 14 04:41:16 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 208464 kb
Host smart-2f5b1df1-3e34-4f99-a8c1-16e62c8eda85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274187840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1274187840
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.637001318
Short name T341
Test name
Test status
Simulation time 352653843 ps
CPU time 7.09 seconds
Started Aug 14 04:40:52 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 221120 kb
Host smart-e8621b16-7e49-491e-8f53-a41e0db57623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637001318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.637001318
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.133899784
Short name T842
Test name
Test status
Simulation time 104147227 ps
CPU time 3.64 seconds
Started Aug 14 04:40:44 PM PDT 24
Finished Aug 14 04:40:48 PM PDT 24
Peak memory 221924 kb
Host smart-c601f9e8-575c-4122-8cd7-9e7e1b8ea1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133899784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.133899784
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2478500743
Short name T232
Test name
Test status
Simulation time 153204020 ps
CPU time 4.38 seconds
Started Aug 14 04:41:05 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 209396 kb
Host smart-ffebf634-0662-447e-b9df-3d8b7183bc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478500743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2478500743
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2821750741
Short name T582
Test name
Test status
Simulation time 116489401 ps
CPU time 4.77 seconds
Started Aug 14 04:41:11 PM PDT 24
Finished Aug 14 04:41:16 PM PDT 24
Peak memory 214904 kb
Host smart-09a2bc24-c307-4fe5-be6c-d4a60102f973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821750741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2821750741
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3879888097
Short name T748
Test name
Test status
Simulation time 107021553 ps
CPU time 2.82 seconds
Started Aug 14 04:41:08 PM PDT 24
Finished Aug 14 04:41:11 PM PDT 24
Peak memory 209072 kb
Host smart-369e1ec4-df80-4154-9069-85480e5bea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879888097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3879888097
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1172094711
Short name T475
Test name
Test status
Simulation time 85980931 ps
CPU time 3.66 seconds
Started Aug 14 04:40:50 PM PDT 24
Finished Aug 14 04:40:54 PM PDT 24
Peak memory 208676 kb
Host smart-97ff226b-029b-42ce-a59c-cd0e778c7ef4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172094711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1172094711
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.262518005
Short name T306
Test name
Test status
Simulation time 934629653 ps
CPU time 6.43 seconds
Started Aug 14 04:41:07 PM PDT 24
Finished Aug 14 04:41:13 PM PDT 24
Peak memory 209092 kb
Host smart-492dedf4-9212-419a-af22-b42485289fed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262518005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.262518005
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.179138833
Short name T668
Test name
Test status
Simulation time 114447620 ps
CPU time 2.37 seconds
Started Aug 14 04:40:58 PM PDT 24
Finished Aug 14 04:41:00 PM PDT 24
Peak memory 207204 kb
Host smart-1cae80ca-28b4-4cd5-b6b4-c1af7cbac4f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179138833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.179138833
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1172694369
Short name T495
Test name
Test status
Simulation time 89152374 ps
CPU time 3.35 seconds
Started Aug 14 04:40:54 PM PDT 24
Finished Aug 14 04:40:57 PM PDT 24
Peak memory 218912 kb
Host smart-1e32e280-dccf-479b-beb2-60b0ebd12cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172694369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1172694369
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3868394119
Short name T519
Test name
Test status
Simulation time 93749043 ps
CPU time 3.26 seconds
Started Aug 14 04:40:37 PM PDT 24
Finished Aug 14 04:40:41 PM PDT 24
Peak memory 208788 kb
Host smart-2b34254f-01d0-46e9-b3e7-9106add2017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868394119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3868394119
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3529465920
Short name T725
Test name
Test status
Simulation time 2217869621 ps
CPU time 52.02 seconds
Started Aug 14 04:40:39 PM PDT 24
Finished Aug 14 04:41:31 PM PDT 24
Peak memory 222956 kb
Host smart-bb228664-1e1e-4f81-9264-bcb66eaea589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529465920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3529465920
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.4239701762
Short name T182
Test name
Test status
Simulation time 622507664 ps
CPU time 23.12 seconds
Started Aug 14 04:41:00 PM PDT 24
Finished Aug 14 04:41:23 PM PDT 24
Peak memory 222992 kb
Host smart-4429c220-b21b-4331-b0be-53044e5743fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239701762 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.4239701762
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3396877927
Short name T874
Test name
Test status
Simulation time 42940050 ps
CPU time 2.69 seconds
Started Aug 14 04:40:53 PM PDT 24
Finished Aug 14 04:40:56 PM PDT 24
Peak memory 208112 kb
Host smart-214b0cc6-3aa1-490b-84e3-21de977c9f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396877927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3396877927
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2457950245
Short name T537
Test name
Test status
Simulation time 305519915 ps
CPU time 2.92 seconds
Started Aug 14 04:40:45 PM PDT 24
Finished Aug 14 04:40:48 PM PDT 24
Peak memory 210732 kb
Host smart-ed70bc64-d083-4a0f-bf29-057761e769b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457950245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2457950245
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.540201772
Short name T800
Test name
Test status
Simulation time 19843211 ps
CPU time 0.84 seconds
Started Aug 14 04:40:45 PM PDT 24
Finished Aug 14 04:40:46 PM PDT 24
Peak memory 206284 kb
Host smart-bda52443-32d5-44b6-985c-5b0c539c1daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540201772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.540201772
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2820758041
Short name T386
Test name
Test status
Simulation time 1044985367 ps
CPU time 54 seconds
Started Aug 14 04:41:08 PM PDT 24
Finished Aug 14 04:42:02 PM PDT 24
Peak memory 215052 kb
Host smart-b2ff798d-1d7e-4948-a291-756d88b6cb3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2820758041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2820758041
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.503606180
Short name T323
Test name
Test status
Simulation time 1027184340 ps
CPU time 3.43 seconds
Started Aug 14 04:40:56 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 214836 kb
Host smart-0d924477-0549-4a9c-b3d9-3d6103f2ef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503606180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.503606180
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2843008141
Short name T268
Test name
Test status
Simulation time 85954806 ps
CPU time 2.81 seconds
Started Aug 14 04:41:00 PM PDT 24
Finished Aug 14 04:41:03 PM PDT 24
Peak memory 215784 kb
Host smart-584e354a-5330-464a-96a9-bffce45de4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843008141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2843008141
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1187272861
Short name T619
Test name
Test status
Simulation time 660430511 ps
CPU time 4.72 seconds
Started Aug 14 04:40:57 PM PDT 24
Finished Aug 14 04:41:02 PM PDT 24
Peak memory 222792 kb
Host smart-ecfd8828-bdda-404e-80dc-1a54fc64bc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187272861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1187272861
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2321518403
Short name T820
Test name
Test status
Simulation time 181703030 ps
CPU time 4.65 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 210148 kb
Host smart-36ddf64c-8dad-4770-916d-ab78c4885245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321518403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2321518403
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3874132354
Short name T823
Test name
Test status
Simulation time 277618419 ps
CPU time 3.72 seconds
Started Aug 14 04:40:44 PM PDT 24
Finished Aug 14 04:40:48 PM PDT 24
Peak memory 209908 kb
Host smart-13c0c747-256d-413d-8030-40efe33c0e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874132354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3874132354
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1948210326
Short name T521
Test name
Test status
Simulation time 69579566 ps
CPU time 2.22 seconds
Started Aug 14 04:41:07 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 207428 kb
Host smart-78b34abf-0c27-4cd1-9a8a-30450e909b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948210326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1948210326
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.465100471
Short name T686
Test name
Test status
Simulation time 192452138 ps
CPU time 3.02 seconds
Started Aug 14 04:41:13 PM PDT 24
Finished Aug 14 04:41:17 PM PDT 24
Peak memory 207352 kb
Host smart-f6ea1a58-810f-4445-8dd3-ad3285c84388
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465100471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.465100471
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2401078068
Short name T4
Test name
Test status
Simulation time 2183658691 ps
CPU time 17.61 seconds
Started Aug 14 04:40:41 PM PDT 24
Finished Aug 14 04:40:59 PM PDT 24
Peak memory 209404 kb
Host smart-b613acac-9863-43a9-b217-195f8302f637
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401078068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2401078068
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2276955397
Short name T395
Test name
Test status
Simulation time 40810789 ps
CPU time 1.81 seconds
Started Aug 14 04:40:45 PM PDT 24
Finished Aug 14 04:40:52 PM PDT 24
Peak memory 207272 kb
Host smart-dd05b1bb-981c-4c42-b277-e3d0cf930745
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276955397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2276955397
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1054559643
Short name T912
Test name
Test status
Simulation time 1400966537 ps
CPU time 8.56 seconds
Started Aug 14 04:41:19 PM PDT 24
Finished Aug 14 04:41:28 PM PDT 24
Peak memory 210420 kb
Host smart-2a95988a-656b-4a9e-b939-599ff64af2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054559643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1054559643
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2495170530
Short name T716
Test name
Test status
Simulation time 125209468 ps
CPU time 4.38 seconds
Started Aug 14 04:41:05 PM PDT 24
Finished Aug 14 04:41:10 PM PDT 24
Peak memory 209408 kb
Host smart-00bffaa1-f9b4-467a-b890-c7e868432d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495170530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2495170530
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1112734775
Short name T295
Test name
Test status
Simulation time 3186869309 ps
CPU time 32.01 seconds
Started Aug 14 04:41:14 PM PDT 24
Finished Aug 14 04:41:46 PM PDT 24
Peak memory 215624 kb
Host smart-50545d54-7609-4709-9da2-40dfb5d80e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112734775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1112734775
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2148299569
Short name T736
Test name
Test status
Simulation time 425928397 ps
CPU time 10.13 seconds
Started Aug 14 04:41:12 PM PDT 24
Finished Aug 14 04:41:22 PM PDT 24
Peak memory 208188 kb
Host smart-31de4dcb-5a6f-4ca2-83b7-25773377600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148299569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2148299569
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2689331537
Short name T526
Test name
Test status
Simulation time 47731530 ps
CPU time 2.28 seconds
Started Aug 14 04:41:19 PM PDT 24
Finished Aug 14 04:41:21 PM PDT 24
Peak memory 210168 kb
Host smart-f576e9bf-68cc-48d5-9b4d-4e4fec20d860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689331537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2689331537
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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