Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4556

1

T2

4

T4

1

T5

11

auto[1]

470

1

T4

2

T15

3

T16

5

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4556

1

T2

4

T4

1

T5

11

auto[1]

470

1

T4

2

T15

3

T16

5

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4464

1

T2

4

T4

1

T5

7

auto[1]

562

1

T4

2

T5

4

T38

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4464

1

T2

4

T4

1

T5

7

auto[1]

562

1

T4

2

T5

4

T38

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	388	1			T2	2		T16	2		T38	1
auto[OpGenId]	1053	1			T2	1		T4	1		T16	4
auto[OpGenSwOut]	1010	1			T2	1		T4	1		T16	1
auto[OpGenHwOut]	2520	1			T4	1		T5	11		T15	12
auto[OpDisable]	55	1			T65	2		T59	1		T66	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	388	1			T2	2		T16	2		T38	1
auto[OpGenId]	1053	1			T2	1		T4	1		T16	4
auto[OpGenSwOut]	1010	1			T2	1		T4	1		T16	1
auto[OpGenHwOut]	2520	1			T4	1		T5	11		T15	12
auto[OpDisable]	55	1			T65	2		T59	1		T66	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4498

1

T2

4

T4

3

T5

11

auto[1]

528

1

T17

1

T18

4

T39

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4498

1

T2

4

T4

3

T5

11

auto[1]

528

1

T17

1

T18

4

T39

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4749

1

T2

4

T4

3

T5

11

auto[1]

277

1

T16

5

T38

11

T150

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1736	1			T2	1		T4	2		T5	1
auto[1]	673	1			T5	4		T15	3		T17	1
auto[2]	600	1			T2	1		T15	2		T17	1
auto[3]	697	1			T4	1		T5	2		T15	1
auto[4]	320	1			T5	2		T15	1		T39	1
auto[5]	332	1			T2	2		T5	1		T15	1
auto[6]	320	1			T15	1		T16	3		T39	1
auto[7]	348	1			T5	1		T98	1		T99	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1320	1			T2	2		T5	4		T15	3
clear_one[1]	673	1			T5	4		T15	3		T17	1
clear_one[2]	600	1			T2	1		T15	2		T17	1
clear_one[3]	697	1			T4	1		T5	2		T15	1
clear_none	1736	1			T2	1		T4	2		T5	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	953	1			T5	3		T15	4		T17	1
auto[StInit]	622	1			T2	1		T4	1		T5	1
auto[StCreatorRootKey]	531	1			T2	1		T5	1		T15	1
auto[StOwnerIntKey]	476	1			T2	1		T4	1		T5	1
auto[StOwnerKey]	431	1			T2	1		T4	1		T5	1
auto[StDisabled]	1715	1			T5	4		T15	4		T16	6
auto[StInvalid]	298	1			T41	5		T28	1		T51	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	953	1			T5	3		T15	4		T17	1
auto[StInit]	622	1			T2	1		T4	1		T5	1
auto[StCreatorRootKey]	531	1			T2	1		T5	1		T15	1
auto[StOwnerIntKey]	476	1			T2	1		T4	1		T5	1
auto[StOwnerKey]	431	1			T2	1		T4	1		T5	1
auto[StDisabled]	1715	1			T5	4		T15	4		T16	6
auto[StInvalid]	298	1			T41	5		T28	1		T51	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	15
[auto[0] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[3] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[3] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T38	1		T245	1		T246	1
auto[0]	auto[StReset]	auto[OpGenId]	153	1			T39	1		T26	1		T27	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	117	1			T39	1		T23	1		T152	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	262	1			T5	1		T15	1		T17	1
auto[0]	auto[StInit]	auto[OpAdvance]	42	1			T40	1		T66	1		T247	1
auto[0]	auto[StInit]	auto[OpGenId]	93	1			T2	1		T16	1		T39	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	78	1			T38	1		T66	1		T67	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	184	1			T4	1		T18	1		T99	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T145	1		T66	1		T152	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	58	1			T26	1		T70	1		T59	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	38	1			T69	1		T248	1		T64	3
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	73	1			T39	1		T220	1		T216	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T249	1		T80	1		T250	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	32	1			T65	1		T210	1		T113	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	26	1			T50	1		T150	1		T151	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	56	1			T15	1		T142	1		T220	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T39	1		T66	1		T245	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	15	1			T7	1		T77	1		T136	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	23	1			T4	1		T213	1		T71	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T220	1		T106	1		T120	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T16	2		T150	1		T245	1
auto[0]	auto[StDisabled]	auto[OpGenId]	55	1			T18	2		T38	1		T39	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T38	3		T39	1		T150	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T15	1		T38	2		T39	1
auto[0]	auto[StDisabled]	auto[OpDisable]	17	1			T65	1		T66	1		T80	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	9	1			T41	1		T56	1		T251	2
auto[0]	auto[StInvalid]	auto[OpGenId]	27	1			T115	1		T252	1		T253	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	21	1			T51	1		T103	1		T254	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	20	1			T56	1		T255	1		T256	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T257	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	25	1			T113	1		T60	1		T71	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	25	1			T64	1		T258	1		T155	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	47	1			T15	1		T100	1		T220	2
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T75	1		T259	1		T260	1
auto[1]	auto[StInit]	auto[OpGenId]	12	1			T261	1		T262	1		T8	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T17	1		T53	1		T263	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	29	1			T5	1		T50	1		T201	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T65	1		T155	1		T165	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T64	1		T87	1		T264	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T80	1		T265	1		T73	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T15	1		T66	1		T222	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T205	1		T266	1		T267	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T70	1		T65	1		T212	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T71	1		T155	1		T138	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T5	1		T27	1		T71	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T205	1		T268	1		T55	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T66	1		T64	1		T269	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T65	1		T8	1		T270	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T5	1		T271	1		T272	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	17	1			T71	1		T273	1		T8	1
auto[1]	auto[StDisabled]	auto[OpGenId]	42	1			T18	1		T26	1		T50	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T38	1		T249	1		T80	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T5	1		T15	1		T39	1
auto[1]	auto[StDisabled]	auto[OpDisable]	7	1			T274	1		T75	1		T275	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T41	1		T51	1		T115	1
auto[1]	auto[StInvalid]	auto[OpGenId]	13	1			T103	1		T104	1		T62	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T276	1		T277	1		T278	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T251	1		T105	1		T279	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T280	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	13	1			T64	1		T154	1		T281	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T39	1		T28	1		T217	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	41	1			T15	1		T220	1		T282	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T26	1		T283	1		T284	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T154	1		T155	2		T86	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T65	1		T23	1		T24	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	22	1			T100	1		T220	1		T210	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T71	1		T285	1		T286	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T150	1		T287	1		T73	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T73	1		T288	1		T289	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T100	1		T290	1		T211	2
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T205	1		T280	1		T206	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T135	1		T53	1		T195	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T2	1		T80	1		T291	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T118	1		T290	1		T80	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T71	1		T153	2		T53	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T18	1		T71	1		T292	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T155	1		T8	1		T91	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	27	1			T147	1		T216	1		T113	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T80	1		T245	1		T250	3
auto[2]	auto[StDisabled]	auto[OpGenId]	34	1			T147	1		T148	1		T66	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T17	1		T66	1		T80	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T15	1		T98	1		T220	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T113	1		T73	1		T293	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	11	1			T115	1		T252	1		T294	2
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T254	1		T251	1		T295	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T41	1		T52	1		T296	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T51	1		T296	1		T114	1
auto[3]	auto[StReset]	auto[OpGenId]	24	1			T58	1		T136	1		T297	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	19	1			T50	1		T217	1		T52	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	51	1			T5	1		T220	1		T147	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T156	1		T298	1		T299	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T107	1		T91	1		T300	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	14	1			T231	1		T258	1		T73	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	22	1			T15	1		T98	1		T142	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T67	1		T211	1		T73	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T39	1		T28	1		T71	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T7	1		T301	1		T302	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T221	1		T271	1		T118	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T211	1		T165	1		T303	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T4	1		T20	1		T155	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T287	1		T195	1		T304	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	47	1			T99	1		T221	1		T305	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T306	2		T307	2		T285	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T66	1		T201	1		T71	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T150	1		T308	1		T250	3
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T16	1		T142	1		T71	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	25	1			T80	1		T92	1		T95	2
auto[3]	auto[StDisabled]	auto[OpGenId]	51	1			T16	3		T27	1		T106	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T148	1		T106	1		T218	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T5	1		T38	1		T98	2
auto[3]	auto[StDisabled]	auto[OpDisable]	14	1			T71	1		T61	1		T81	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	1	1			T295	1		-	-		-	-
auto[3]	auto[StInvalid]	auto[OpGenId]	14	1			T28	1		T309	1		T310	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T52	1		T252	1		T104	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T52	1		T115	1		T104	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T52	1		T87	1		T54	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	7	1			T39	1		T48	1		T311	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	18	1			T5	1		T27	1		T23	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T312	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T137	1		T87	1		T313	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T80	1		T64	1		T314	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T305	1		T64	1		T315	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T316	1		T264	1		T317	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T71	1		T318	1		T319	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T210	1		T66	1		T25	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T120	1		T80	1		T297	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T320	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T321	1		T232	1		T322	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T71	1		T155	1		T241	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T120	1		T323	1		T324	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T95	2		T311	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T95	1		T139	1		T54	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T80	1		T325	1		T326	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T99	1		T222	1		T123	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	12	1			T151	1		T153	1		T75	2
auto[4]	auto[StDisabled]	auto[OpGenId]	23	1			T71	1		T153	1		T155	2
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T59	1		T210	1		T66	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T5	1		T15	1		T216	1
auto[4]	auto[StDisabled]	auto[OpDisable]	1	1			T80	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T253	1		T327	1		T328	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T52	1		T329	1		T330	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T331	1		T332	1		T333	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T41	1		T51	2		T252	2
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T64	1		T136	1		T297	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	13	1			T80	1		T7	1		T75	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	24	1			T98	1		T308	1		T136	1
auto[5]	auto[StInit]	auto[OpGenId]	1	1			T334	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T241	1		T335	1		T336	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T337	1		T338	1		T339	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T2	1		T113	1		T314	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T38	3		T340	1		T334	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T18	1		T23	1		T341	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T5	1		T38	1		T212	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T63	1		T341	1		T334	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T38	1		T75	1		T232	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T66	1		T77	1		T342	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T80	1		T343	1		T339	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T2	1		T344	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	4	1			T300	1		T320	1		T345	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T27	1		T80	1		T346	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T15	1		T38	2		T347	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	17	1			T211	2		T273	1		T261	1
auto[5]	auto[StDisabled]	auto[OpGenId]	32	1			T213	1		T71	2		T211	2
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T147	1		T150	1		T348	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T26	1		T142	1		T151	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T65	1		T64	1		T304	1
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T103	1		T276	1		T349	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T350	1		T351	1		T352	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T52	1		T329	1		T353	2
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T212	1		T318	1		T284	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T26	1		T28	1		T7	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T15	1		T65	1		T51	1
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T80	1		T110	1		T354	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	2	1			T65	1		T110	1		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	13	1			T123	1		T347	1		T355	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T152	1		T356	1		T357	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T235	1		T358	1		T268	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T138	1		T359	1		T360	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T98	1		T142	1		T361	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T245	2		T314	1		T318	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T362	1		T363	1		T364	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T80	1		T245	1		T155	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T16	2		T98	1		T216	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T108	1		T264	1		T365	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	8	1			T50	1		T249	1		T7	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T241	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T70	1		T221	1		T337	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T106	1		T20	1		T53	1
auto[6]	auto[StDisabled]	auto[OpGenId]	23	1			T65	1		T80	1		T20	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T16	1		T64	1		T155	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T39	1		T99	1		T220	1
auto[6]	auto[StDisabled]	auto[OpDisable]	1	1			T366	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T349	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T276	1		T294	1		T330	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T309	1		T367	2		T368	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T41	1		T295	2		T369	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T48	1		T136	1		T223	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T63	1		T87	1		T241	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	19	1			T100	1		T217	1		T113	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T80	1		T53	1		T370	1
auto[7]	auto[StInit]	auto[OpGenId]	3	1			T217	1		T371	1		T372	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T373	1		T374	1		T375	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T24	1		T120	1		T376	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T153	2		T348	2		T306	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T80	1		T75	1		T377	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T61	1		T155	1		T53	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T99	1		T153	1		T378	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T153	1		T306	1		T307	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	2	1			T348	1		T92	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T147	1		T8	1		T91	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T100	1		T271	1		T337	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T365	1		T379	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T380	1		T304	1		T381	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T212	1		T382	1		T75	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T98	1		T100	1		T26	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	12	1			T152	2		T7	1		T383	3
auto[7]	auto[StDisabled]	auto[OpGenId]	33	1			T65	1		T71	2		T7	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T106	1		T66	1		T213	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	88	1			T5	1		T99	1		T142	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T59	1		T334	1		T381	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T384	1		T369	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T255	1		T295	1		T329	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T56	1		T115	1		T276	3
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T256	1		T385	1		T332	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1320

1

T2

2

T5

4

T15

3

clear_one[1]

auto[0]

auto[0]

auto[0]

386

1

T5

1

T15

3

T17

1

clear_one[1]

auto[0]

auto[0]

auto[1]

120

1

T18

1

T26

1

T216

1

clear_one[1]

auto[0]

auto[1]

auto[0]

124

1

T5

3

T38

1

T39

1

clear_one[1]

auto[0]

auto[1]

auto[1]

43

1

T71

1

T249

2

T8

1

clear_one[2]

auto[0]

auto[0]

auto[0]

354

1

T2

1

T15

1

T39

1

clear_one[2]

auto[0]

auto[0]

auto[1]

116

1

T17

1

T18

1

T148

1

clear_one[2]

auto[1]

auto[0]

auto[0]

96

1

T15

1

T100

1

T220

1

clear_one[2]

auto[1]

auto[0]

auto[1]

34

1

T147

2

T245

1

T250

1

clear_one[3]

auto[0]

auto[0]

auto[0]

415

1

T5

1

T15

1

T16

1

clear_one[3]

auto[0]

auto[1]

auto[0]

142

1

T5

1

T98

2

T99

2

clear_one[3]

auto[1]

auto[0]

auto[0]

110

1

T16

3

T100

3

T142

2

clear_one[3]

auto[1]

auto[1]

auto[0]

30

1

T4

1

T38

1

T23

1

clear_none

auto[0]

auto[0]

auto[0]

1241

1

T2

1

T4

1

T5

1

clear_none

auto[0]

auto[0]

auto[1]

127

1

T18

2

T148

1

T216

2

clear_none

auto[0]

auto[1]

auto[0]

140

1

T38

1

T39

2

T98

1

clear_none

auto[0]

auto[1]

auto[1]

28

1

T7

1

T108

1

T155

1

clear_none

auto[1]

auto[0]

auto[0]

114

1

T15

2

T16

2

T39

1

clear_none

auto[1]

auto[0]

auto[1]

31

1

T66

1

T215

1

T201

1

clear_none

auto[1]

auto[1]

auto[0]

26

1

T4

1

T80

1

T386

1

clear_none

auto[1]

auto[1]

auto[1]

29

1

T39

1

T50

1

T218

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1231	1			T2	2		T5	4		T15	3
clear_all	auto[1]	89	1			T16	1		T38	5		T151	1
clear_one[1]	auto[0]	662	1			T5	4		T15	3		T17	1
clear_one[1]	auto[1]	11	1			T311	2		T268	1		T246	2
clear_one[2]	auto[0]	570	1			T2	1		T15	2		T17	1
clear_one[2]	auto[1]	30	1			T245	4		T250	5		T211	1
clear_one[3]	auto[0]	626	1			T4	1		T5	2		T15	1
clear_one[3]	auto[1]	71	1			T16	3		T250	2		T211	1
clear_none	auto[0]	1660	1			T2	1		T4	2		T5	1
clear_none	auto[1]	76	1			T16	1		T38	6		T150	3