Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10425

1

T2

4

T4

10

T5

10

auto[Attestation]

7150

1

T4

5

T5

4

T15

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2568	1			T2	1		T4	3		T16	5
auto[Aes]	3124	1			T2	1		T4	2		T15	15
auto[Kmac]	3255	1			T2	1		T4	6		T5	14
auto[Otbn]	3190	1			T16	1		T17	7		T18	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7050	1			T2	4		T3	1		T4	5
auto[OpGenId]	5438	1			T2	1		T4	4		T16	3
auto[OpGenSwOut]	5358	1			T2	1		T4	6		T16	6
auto[OpGenHwOut]	6779	1			T2	2		T4	5		T5	14
auto[OpDisable]	125	1			T17	1		T39	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9896

1

T2

7

T3

1

T4

13

auto[OpDoneFail]

14854

1

T2

1

T4

7

T5

14

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5931	1			T2	1		T3	1		T4	1
auto[StInit]	3628	1			T2	2		T4	3		T5	2
auto[StCreatorRootKey]	3002	1			T2	1		T4	5		T5	2
auto[StOwnerIntKey]	2545	1			T2	2		T4	4		T5	2
auto[StOwnerKey]	2322	1			T2	2		T4	2		T5	2
auto[StDisabled]	7322	1			T4	5		T5	7		T15	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	269	1			T39	1		T26	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T39	1		T65	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	88	1			T4	2		T106	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T2	1		T39	1		T66	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T4	1		T16	1		T113	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	188	1			T39	1		T65	2		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	276	1			T17	2		T39	2		T28	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	85	1			T38	1		T28	2		T145	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	90	1			T18	1		T40	1		T210	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	60	1			T150	1		T203	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T16	1		T147	1		T66	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	178	1			T4	1		T16	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	299	1			T17	1		T39	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	107	1			T67	1		T80	2		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T4	1		T39	1		T149	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	55	1			T50	1		T66	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	54	1			T39	1		T65	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	205	1			T38	2		T39	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	277	1			T17	1		T39	5		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	101	1			T23	1		T66	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	89	1			T39	1		T27	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T147	1		T149	1		T212	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	54	1			T70	1		T150	1		T66	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	209	1			T38	2		T26	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	80	1			T39	5		T65	3		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	89	1			T17	1		T27	1		T65	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T27	1		T66	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T65	1		T42	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	73	1			T16	1		T213	1		T113	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	197	1			T16	1		T17	1		T147	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	61	1			T65	1		T71	1		T80	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	107	1			T28	2		T70	1		T65	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	88	1			T65	1		T148	1		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	69	1			T27	1		T148	1		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	38	1			T65	1		T71	2		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	194	1			T39	1		T26	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	69	1			T39	3		T65	2		T64	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	83	1			T39	1		T70	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T50	2		T148	1		T66	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	59	1			T16	1		T65	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	48	1			T147	1		T43	1		T121	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	200	1			T4	1		T18	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	55	1			T65	2		T113	2		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	110	1			T17	1		T39	1		T147	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	67	1			T147	1		T42	1		T66	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	59	1			T50	1		T148	1		T150	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	69	1			T27	1		T28	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	190	1			T38	2		T26	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	248	1			T17	2		T39	1		T27	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	91	1			T50	1		T148	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T148	1		T151	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T27	1		T106	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T70	2		T65	1		T147	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	180	1			T16	1		T17	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	447	1			T15	7		T100	6		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	106	1			T38	1		T50	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	100	1			T4	1		T100	1		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	86	1			T15	1		T16	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	88	1			T2	1		T15	1		T100	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	268	1			T15	3		T16	1		T100	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	471	1			T5	6		T17	1		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T4	1		T5	1		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T5	1		T98	1		T145	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	96	1			T39	1		T99	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	95	1			T2	1		T98	1		T99	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	280	1			T4	1		T5	2		T38	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	445	1			T17	3		T39	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	130	1			T17	1		T212	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	103	1			T216	1		T217	1		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T18	1		T50	1		T147	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	84	1			T38	1		T216	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	266	1			T17	1		T27	1		T216	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	53	1			T39	3		T65	3		T64	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	86	1			T27	1		T28	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T39	1		T65	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	47	1			T26	1		T28	2		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T66	1		T71	1		T219	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	188	1			T16	1		T39	2		T26	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	47	1			T39	3		T65	4		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	138	1			T15	1		T18	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T15	1		T50	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	95	1			T100	1		T142	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	87	1			T16	1		T142	1		T214	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	247	1			T15	1		T16	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T39	1		T65	2		T80	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	119	1			T4	1		T39	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T99	1		T50	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	96	1			T4	1		T5	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	83	1			T5	1		T39	1		T147	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	268	1			T5	2		T39	1		T98	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	59	1			T39	1		T71	2		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T65	2		T216	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T38	1		T145	2		T217	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T39	1		T147	1		T148	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	85	1			T26	2		T221	1		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	249	1			T16	1		T26	1		T65	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	194	1			T2	1		T4	3		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	570	1			T39	3		T26	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	200	1			T16	1		T18	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	551	1			T4	1		T16	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	184	1			T4	1		T39	2		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	620	1			T17	1		T38	2		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	199	1			T39	1		T27	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	603	1			T17	1		T38	2		T39	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	211	1			T16	1		T65	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	383	1			T16	1		T17	2		T39	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	179	1			T27	1		T65	1		T148	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	378	1			T39	1		T26	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	168	1			T16	1		T50	2		T147	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	368	1			T4	1		T18	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	179	1			T28	1		T50	2		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	371	1			T17	1		T38	2		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	178	1			T70	2		T147	1		T148	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	539	1			T16	1		T17	3		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	260	1			T2	1		T4	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	835	1			T15	10		T16	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	278	1			T2	1		T5	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	894	1			T4	2		T5	9		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T18	1		T38	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	854	1			T17	5		T39	2		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	150	1			T39	1		T26	1		T28	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	343	1			T16	1		T39	5		T26	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	271	1			T15	1		T16	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	450	1			T15	2		T16	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T4	1		T5	2		T39	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	463	1			T4	1		T5	2		T39	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	283	1			T38	1		T39	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	434	1			T16	1		T39	1		T26	2