Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30561

1

T2

10

T3

2

T4

23

auto[1]

323

1

T16

6

T38

16

T150

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30578	1			T2	10		T3	2		T4	23
auto[134217728:268435455]	14	1			T16	1		T250	2		T156	1
auto[268435456:402653183]	6	1			T16	1		T156	1		T306	1
auto[402653184:536870911]	11	1			T245	1		T211	1		T95	1
auto[536870912:671088639]	6	1			T245	1		T156	1		T311	1
auto[671088640:805306367]	17	1			T250	1		T153	1		T348	1
auto[805306368:939524095]	8	1			T16	1		T211	1		T153	1
auto[939524096:1073741823]	9	1			T38	1		T245	1		T211	4
auto[1073741824:1207959551]	11	1			T245	2		T211	1		T246	1
auto[1207959552:1342177279]	13	1			T16	1		T38	1		T152	1
auto[1342177280:1476395007]	12	1			T150	1		T156	1		T407	1
auto[1476395008:1610612735]	4	1			T38	1		T151	1		T408	2
auto[1610612736:1744830463]	11	1			T38	2		T250	3		T409	1
auto[1744830464:1879048191]	8	1			T150	1		T211	1		T156	1
auto[1879048192:2013265919]	9	1			T245	1		T250	1		T306	1
auto[2013265920:2147483647]	7	1			T38	1		T156	1		T407	1
auto[2147483648:2281701375]	11	1			T38	1		T150	1		T250	2
auto[2281701376:2415919103]	15	1			T152	2		T250	2		T280	1
auto[2415919104:2550136831]	15	1			T16	1		T38	1		T150	1
auto[2550136832:2684354559]	11	1			T16	1		T38	1		T211	1
auto[2684354560:2818572287]	10	1			T211	1		T153	1		T156	1
auto[2818572288:2952790015]	10	1			T38	2		T250	1		T211	2
auto[2952790016:3087007743]	5	1			T95	1		T268	1		T307	1
auto[3087007744:3221225471]	10	1			T38	1		T95	1		T311	1
auto[3221225472:3355443199]	8	1			T38	1		T153	1		T246	1
auto[3355443200:3489660927]	13	1			T152	1		T245	1		T211	1
auto[3489660928:3623878655]	8	1			T152	1		T245	1		T268	1
auto[3623878656:3758096383]	11	1			T38	1		T150	1		T250	1
auto[3758096384:3892314111]	8	1			T150	1		T348	1		T409	2
auto[3892314112:4026531839]	7	1			T156	1		T306	1		T246	1
auto[4026531840:4160749567]	8	1			T150	1		T280	1		T407	1
auto[4160749568:4294967295]	10	1			T38	1		T211	2		T348	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30561	1			T2	10		T3	2		T4	23
auto[0:134217727]	auto[1]	17	1			T38	1		T150	1		T250	1
auto[134217728:268435455]	auto[1]	14	1			T16	1		T250	2		T156	1
auto[268435456:402653183]	auto[1]	6	1			T16	1		T156	1		T306	1
auto[402653184:536870911]	auto[1]	11	1			T245	1		T211	1		T95	1
auto[536870912:671088639]	auto[1]	6	1			T245	1		T156	1		T311	1
auto[671088640:805306367]	auto[1]	17	1			T250	1		T153	1		T348	1
auto[805306368:939524095]	auto[1]	8	1			T16	1		T211	1		T153	1
auto[939524096:1073741823]	auto[1]	9	1			T38	1		T245	1		T211	4
auto[1073741824:1207959551]	auto[1]	11	1			T245	2		T211	1		T246	1
auto[1207959552:1342177279]	auto[1]	13	1			T16	1		T38	1		T152	1
auto[1342177280:1476395007]	auto[1]	12	1			T150	1		T156	1		T407	1
auto[1476395008:1610612735]	auto[1]	4	1			T38	1		T151	1		T408	2
auto[1610612736:1744830463]	auto[1]	11	1			T38	2		T250	3		T409	1
auto[1744830464:1879048191]	auto[1]	8	1			T150	1		T211	1		T156	1
auto[1879048192:2013265919]	auto[1]	9	1			T245	1		T250	1		T306	1
auto[2013265920:2147483647]	auto[1]	7	1			T38	1		T156	1		T407	1
auto[2147483648:2281701375]	auto[1]	11	1			T38	1		T150	1		T250	2
auto[2281701376:2415919103]	auto[1]	15	1			T152	2		T250	2		T280	1
auto[2415919104:2550136831]	auto[1]	15	1			T16	1		T38	1		T150	1
auto[2550136832:2684354559]	auto[1]	11	1			T16	1		T38	1		T211	1
auto[2684354560:2818572287]	auto[1]	10	1			T211	1		T153	1		T156	1
auto[2818572288:2952790015]	auto[1]	10	1			T38	2		T250	1		T211	2
auto[2952790016:3087007743]	auto[1]	5	1			T95	1		T268	1		T307	1
auto[3087007744:3221225471]	auto[1]	10	1			T38	1		T95	1		T311	1
auto[3221225472:3355443199]	auto[1]	8	1			T38	1		T153	1		T246	1
auto[3355443200:3489660927]	auto[1]	13	1			T152	1		T245	1		T211	1
auto[3489660928:3623878655]	auto[1]	8	1			T152	1		T245	1		T268	1
auto[3623878656:3758096383]	auto[1]	11	1			T38	1		T150	1		T250	1
auto[3758096384:3892314111]	auto[1]	8	1			T150	1		T348	1		T409	2
auto[3892314112:4026531839]	auto[1]	7	1			T156	1		T306	1		T246	1
auto[4026531840:4160749567]	auto[1]	8	1			T150	1		T280	1		T407	1
auto[4160749568:4294967295]	auto[1]	10	1			T38	1		T211	2		T348	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1539

1

T2

1

T4

2

T17

6

auto[1]

1636

1

T2

2

T3

2

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T39	1		T26	1		T50	1
auto[134217728:268435455]	93	1			T17	1		T28	1		T148	1
auto[268435456:402653183]	94	1			T4	1		T39	1		T150	1
auto[402653184:536870911]	98	1			T41	1		T65	3		T151	1
auto[536870912:671088639]	90	1			T39	1		T19	1		T145	1
auto[671088640:805306367]	102	1			T65	1		T59	1		T23	1
auto[805306368:939524095]	102	1			T4	1		T28	1		T148	1
auto[939524096:1073741823]	101	1			T2	2		T65	1		T217	2
auto[1073741824:1207959551]	117	1			T50	1		T65	1		T217	1
auto[1207959552:1342177279]	90	1			T39	1		T27	1		T65	1
auto[1342177280:1476395007]	98	1			T51	1		T152	1		T76	1
auto[1476395008:1610612735]	109	1			T145	1		T65	1		T51	1
auto[1610612736:1744830463]	88	1			T38	2		T50	1		T65	1
auto[1744830464:1879048191]	89	1			T3	1		T113	2		T69	1
auto[1879048192:2013265919]	94	1			T17	1		T50	1		T65	1
auto[2013265920:2147483647]	112	1			T38	1		T39	2		T26	1
auto[2147483648:2281701375]	79	1			T19	1		T65	1		T51	1
auto[2281701376:2415919103]	95	1			T28	1		T66	1		T113	1
auto[2415919104:2550136831]	78	1			T17	1		T65	1		T66	1
auto[2550136832:2684354559]	105	1			T4	1		T39	1		T28	1
auto[2684354560:2818572287]	124	1			T2	1		T4	1		T16	1
auto[2818572288:2952790015]	95	1			T152	1		T247	1		T113	1
auto[2952790016:3087007743]	89	1			T17	2		T38	1		T39	1
auto[3087007744:3221225471]	101	1			T17	1		T28	1		T65	1
auto[3221225472:3355443199]	101	1			T26	1		T27	1		T28	1
auto[3355443200:3489660927]	109	1			T16	1		T41	1		T26	1
auto[3489660928:3623878655]	94	1			T4	1		T39	2		T41	1
auto[3623878656:3758096383]	108	1			T28	1		T19	1		T151	1
auto[3758096384:3892314111]	113	1			T39	1		T50	1		T70	1
auto[3892314112:4026531839]	111	1			T3	1		T4	1		T39	1
auto[4026531840:4160749567]	112	1			T41	1		T26	1		T147	1
auto[4160749568:4294967295]	85	1			T51	1		T23	1		T202	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T39	1		T26	1		T50	1
auto[0:134217727]	auto[1]	49	1			T152	1		T226	1		T61	1
auto[134217728:268435455]	auto[0]	47	1			T17	1		T203	1		T211	1
auto[134217728:268435455]	auto[1]	46	1			T28	1		T148	1		T212	1
auto[268435456:402653183]	auto[0]	60	1			T4	1		T39	1		T23	1
auto[268435456:402653183]	auto[1]	34	1			T150	1		T23	1		T66	1
auto[402653184:536870911]	auto[0]	44	1			T65	1		T23	1		T210	1
auto[402653184:536870911]	auto[1]	54	1			T41	1		T65	2		T151	1
auto[536870912:671088639]	auto[0]	47	1			T19	1		T145	1		T48	1
auto[536870912:671088639]	auto[1]	43	1			T39	1		T113	1		T25	1
auto[671088640:805306367]	auto[0]	49	1			T23	1		T210	1		T66	1
auto[671088640:805306367]	auto[1]	53	1			T65	1		T59	1		T66	1
auto[805306368:939524095]	auto[0]	48	1			T66	2		T64	1		T8	1
auto[805306368:939524095]	auto[1]	54	1			T4	1		T28	1		T148	1
auto[939524096:1073741823]	auto[0]	54	1			T65	1		T217	2		T51	1
auto[939524096:1073741823]	auto[1]	47	1			T2	2		T215	1		T113	1
auto[1073741824:1207959551]	auto[0]	61	1			T65	1		T24	1		T76	1
auto[1073741824:1207959551]	auto[1]	56	1			T50	1		T217	1		T203	1
auto[1207959552:1342177279]	auto[0]	47	1			T39	1		T113	1		T226	1
auto[1207959552:1342177279]	auto[1]	43	1			T27	1		T65	1		T201	1
auto[1342177280:1476395007]	auto[0]	52	1			T51	1		T76	1		T71	1
auto[1342177280:1476395007]	auto[1]	46	1			T152	1		T80	1		T155	1
auto[1476395008:1610612735]	auto[0]	52	1			T145	1		T65	1		T51	1
auto[1476395008:1610612735]	auto[1]	57	1			T113	1		T115	1		T249	1
auto[1610612736:1744830463]	auto[0]	44	1			T38	1		T65	1		T6	1
auto[1610612736:1744830463]	auto[1]	44	1			T38	1		T50	1		T410	1
auto[1744830464:1879048191]	auto[0]	45	1			T113	1		T69	1		T24	1
auto[1744830464:1879048191]	auto[1]	44	1			T3	1		T113	1		T203	1
auto[1879048192:2013265919]	auto[0]	51	1			T17	1		T51	1		T66	1
auto[1879048192:2013265919]	auto[1]	43	1			T50	1		T65	1		T108	1
auto[2013265920:2147483647]	auto[0]	48	1			T38	1		T39	2		T26	1
auto[2013265920:2147483647]	auto[1]	64	1			T212	1		T66	2		T71	2
auto[2147483648:2281701375]	auto[0]	29	1			T19	1		T113	1		T69	1
auto[2147483648:2281701375]	auto[1]	50	1			T65	1		T51	1		T66	1
auto[2281701376:2415919103]	auto[0]	40	1			T28	1		T113	1		T58	1
auto[2281701376:2415919103]	auto[1]	55	1			T66	1		T250	1		T211	1
auto[2415919104:2550136831]	auto[0]	40	1			T17	1		T65	1		T66	1
auto[2415919104:2550136831]	auto[1]	38	1			T8	1		T137	1		T73	1
auto[2550136832:2684354559]	auto[0]	46	1			T215	1		T71	1		T80	1
auto[2550136832:2684354559]	auto[1]	59	1			T4	1		T39	1		T28	1
auto[2684354560:2818572287]	auto[0]	57	1			T2	1		T152	1		T60	1
auto[2684354560:2818572287]	auto[1]	67	1			T4	1		T16	1		T28	1
auto[2818572288:2952790015]	auto[0]	44	1			T113	1		T24	1		T76	1
auto[2818572288:2952790015]	auto[1]	51	1			T152	1		T247	1		T71	2
auto[2952790016:3087007743]	auto[0]	40	1			T17	2		T39	1		T27	1
auto[2952790016:3087007743]	auto[1]	49	1			T38	1		T28	2		T218	1
auto[3087007744:3221225471]	auto[0]	42	1			T17	1		T65	1		T217	1
auto[3087007744:3221225471]	auto[1]	59	1			T28	1		T23	1		T113	1
auto[3221225472:3355443199]	auto[0]	56	1			T28	1		T65	1		T40	1
auto[3221225472:3355443199]	auto[1]	45	1			T26	1		T27	1		T56	1
auto[3355443200:3489660927]	auto[0]	55	1			T40	1		T106	1		T215	1
auto[3355443200:3489660927]	auto[1]	54	1			T16	1		T41	1		T26	1
auto[3489660928:3623878655]	auto[0]	44	1			T4	1		T27	1		T145	1
auto[3489660928:3623878655]	auto[1]	50	1			T39	2		T41	1		T147	1
auto[3623878656:3758096383]	auto[0]	50	1			T19	1		T151	1		T23	1
auto[3623878656:3758096383]	auto[1]	58	1			T28	1		T71	2		T101	1
auto[3758096384:3892314111]	auto[0]	50	1			T217	1		T66	1		T48	1
auto[3758096384:3892314111]	auto[1]	63	1			T39	1		T50	1		T70	1
auto[3892314112:4026531839]	auto[0]	52	1			T39	1		T65	1		T217	1
auto[3892314112:4026531839]	auto[1]	59	1			T3	1		T4	1		T65	1
auto[4026531840:4160749567]	auto[0]	58	1			T26	1		T147	1		T151	1
auto[4026531840:4160749567]	auto[1]	54	1			T41	1		T150	1		T66	1
auto[4160749568:4294967295]	auto[0]	37	1			T202	1		T80	2		T234	1
auto[4160749568:4294967295]	auto[1]	48	1			T51	1		T23	1		T25	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1572

1

T2

2

T4

1

T17

6

auto[1]

1603

1

T2

1

T3

2

T4

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T40	1		T51	2		T23	1
auto[134217728:268435455]	109	1			T26	2		T217	1		T66	1
auto[268435456:402653183]	90	1			T41	1		T27	1		T210	1
auto[402653184:536870911]	120	1			T4	1		T39	1		T27	1
auto[536870912:671088639]	101	1			T28	1		T50	1		T212	1
auto[671088640:805306367]	108	1			T39	1		T28	1		T65	2
auto[805306368:939524095]	93	1			T41	1		T26	1		T65	1
auto[939524096:1073741823]	106	1			T26	1		T28	2		T214	1
auto[1073741824:1207959551]	103	1			T39	1		T65	3		T218	1
auto[1207959552:1342177279]	105	1			T17	1		T38	1		T28	1
auto[1342177280:1476395007]	100	1			T3	1		T19	1		T65	1
auto[1476395008:1610612735]	95	1			T2	1		T38	1		T39	1
auto[1610612736:1744830463]	109	1			T16	2		T28	1		T65	1
auto[1744830464:1879048191]	104	1			T50	1		T65	2		T151	1
auto[1879048192:2013265919]	92	1			T4	1		T39	1		T50	1
auto[2013265920:2147483647]	96	1			T19	1		T150	1		T66	1
auto[2147483648:2281701375]	99	1			T2	1		T66	1		T24	1
auto[2281701376:2415919103]	104	1			T2	1		T41	1		T145	1
auto[2415919104:2550136831]	94	1			T39	1		T41	1		T203	1
auto[2550136832:2684354559]	99	1			T26	1		T65	1		T147	1
auto[2684354560:2818572287]	92	1			T4	1		T17	1		T27	1
auto[2818572288:2952790015]	119	1			T4	2		T17	1		T27	1
auto[2952790016:3087007743]	81	1			T38	1		T65	1		T66	1
auto[3087007744:3221225471]	100	1			T39	1		T151	1		T80	2
auto[3221225472:3355443199]	86	1			T3	1		T39	1		T23	1
auto[3355443200:3489660927]	102	1			T4	1		T17	1		T39	2
auto[3489660928:3623878655]	89	1			T17	1		T27	1		T28	1
auto[3623878656:3758096383]	90	1			T39	1		T65	1		T51	1
auto[3758096384:3892314111]	90	1			T23	2		T210	1		T113	1
auto[3892314112:4026531839]	93	1			T39	1		T40	1		T152	1
auto[4026531840:4160749567]	98	1			T17	1		T38	1		T66	1
auto[4160749568:4294967295]	100	1			T145	1		T65	1		T151	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T40	1		T51	1		T66	1
auto[0:134217727]	auto[1]	54	1			T51	1		T23	1		T71	1
auto[134217728:268435455]	auto[0]	53	1			T217	1		T56	1		T71	2
auto[134217728:268435455]	auto[1]	56	1			T26	2		T66	1		T215	1
auto[268435456:402653183]	auto[0]	48	1			T27	1		T210	1		T76	1
auto[268435456:402653183]	auto[1]	42	1			T41	1		T60	1		T80	1
auto[402653184:536870911]	auto[0]	68	1			T65	1		T217	1		T51	1
auto[402653184:536870911]	auto[1]	52	1			T4	1		T39	1		T27	1
auto[536870912:671088639]	auto[0]	47	1			T50	1		T217	1		T23	2
auto[536870912:671088639]	auto[1]	54	1			T28	1		T212	1		T215	1
auto[671088640:805306367]	auto[0]	54	1			T39	1		T65	1		T51	1
auto[671088640:805306367]	auto[1]	54	1			T28	1		T65	1		T25	1
auto[805306368:939524095]	auto[0]	55	1			T26	1		T48	1		T71	1
auto[805306368:939524095]	auto[1]	38	1			T41	1		T65	1		T71	1
auto[939524096:1073741823]	auto[0]	53	1			T28	1		T217	1		T76	1
auto[939524096:1073741823]	auto[1]	53	1			T26	1		T28	1		T214	1
auto[1073741824:1207959551]	auto[0]	40	1			T39	1		T65	2		T60	1
auto[1073741824:1207959551]	auto[1]	63	1			T65	1		T218	1		T66	3
auto[1207959552:1342177279]	auto[0]	52	1			T17	1		T147	1		T113	1
auto[1207959552:1342177279]	auto[1]	53	1			T38	1		T28	1		T70	1
auto[1342177280:1476395007]	auto[0]	58	1			T19	1		T113	1		T69	1
auto[1342177280:1476395007]	auto[1]	42	1			T3	1		T65	1		T66	1
auto[1476395008:1610612735]	auto[0]	50	1			T2	1		T65	2		T152	1
auto[1476395008:1610612735]	auto[1]	45	1			T38	1		T39	1		T28	1
auto[1610612736:1744830463]	auto[0]	58	1			T65	1		T214	1		T217	1
auto[1610612736:1744830463]	auto[1]	51	1			T16	2		T28	1		T66	1
auto[1744830464:1879048191]	auto[0]	52	1			T151	1		T66	1		T6	1
auto[1744830464:1879048191]	auto[1]	52	1			T50	1		T65	2		T51	1
auto[1879048192:2013265919]	auto[0]	46	1			T145	1		T215	1		T201	1
auto[1879048192:2013265919]	auto[1]	46	1			T4	1		T39	1		T50	1
auto[2013265920:2147483647]	auto[0]	46	1			T19	1		T150	1		T66	1
auto[2013265920:2147483647]	auto[1]	50	1			T113	1		T48	1		T203	1
auto[2147483648:2281701375]	auto[0]	48	1			T2	1		T66	1		T24	1
auto[2147483648:2281701375]	auto[1]	51	1			T71	1		T211	1		T7	2
auto[2281701376:2415919103]	auto[0]	46	1			T150	1		T71	1		T49	1
auto[2281701376:2415919103]	auto[1]	58	1			T2	1		T41	1		T145	1
auto[2415919104:2550136831]	auto[0]	38	1			T203	1		T252	1		T258	1
auto[2415919104:2550136831]	auto[1]	56	1			T39	1		T41	1		T71	1
auto[2550136832:2684354559]	auto[0]	51	1			T26	1		T65	1		T151	1
auto[2550136832:2684354559]	auto[1]	48	1			T147	1		T152	1		T101	1
auto[2684354560:2818572287]	auto[0]	46	1			T17	1		T27	1		T50	1
auto[2684354560:2818572287]	auto[1]	46	1			T4	1		T148	1		T113	1
auto[2818572288:2952790015]	auto[0]	64	1			T4	1		T17	1		T27	1
auto[2818572288:2952790015]	auto[1]	55	1			T4	1		T28	1		T150	1
auto[2952790016:3087007743]	auto[0]	37	1			T38	1		T65	1		T215	1
auto[2952790016:3087007743]	auto[1]	44	1			T66	1		T113	1		T201	1
auto[3087007744:3221225471]	auto[0]	49	1			T39	1		T151	1		T80	1
auto[3087007744:3221225471]	auto[1]	51	1			T80	1		T77	1		T64	1
auto[3221225472:3355443199]	auto[0]	43	1			T39	1		T23	1		T210	1
auto[3221225472:3355443199]	auto[1]	43	1			T3	1		T6	1		T410	1
auto[3355443200:3489660927]	auto[0]	48	1			T17	1		T39	1		T19	1
auto[3355443200:3489660927]	auto[1]	54	1			T4	1		T39	1		T50	1
auto[3489660928:3623878655]	auto[0]	41	1			T17	1		T66	1		T411	1
auto[3489660928:3623878655]	auto[1]	48	1			T27	1		T28	1		T218	1
auto[3623878656:3758096383]	auto[0]	44	1			T39	1		T65	1		T51	1
auto[3623878656:3758096383]	auto[1]	46	1			T66	2		T245	1		T411	1
auto[3758096384:3892314111]	auto[0]	47	1			T23	1		T113	1		T69	1
auto[3758096384:3892314111]	auto[1]	43	1			T23	1		T210	1		T80	1
auto[3892314112:4026531839]	auto[0]	44	1			T25	1		T80	1		T64	1
auto[3892314112:4026531839]	auto[1]	49	1			T39	1		T40	1		T152	1
auto[4026531840:4160749567]	auto[0]	42	1			T17	1		T152	2		T226	1
auto[4026531840:4160749567]	auto[1]	56	1			T38	1		T66	1		T113	1
auto[4160749568:4294967295]	auto[0]	50	1			T145	1		T65	1		T151	1
auto[4160749568:4294967295]	auto[1]	50	1			T106	1		T66	1		T115	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1562

1

T2

1

T4

1

T17

6

auto[1]

1613

1

T2

2

T3

2

T4

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T17	1		T41	1		T65	2
auto[134217728:268435455]	116	1			T17	1		T65	2		T148	1
auto[268435456:402653183]	103	1			T17	1		T38	1		T28	1
auto[402653184:536870911]	87	1			T3	1		T39	1		T66	1
auto[536870912:671088639]	115	1			T39	2		T28	1		T147	1
auto[671088640:805306367]	96	1			T2	1		T38	1		T27	1
auto[805306368:939524095]	100	1			T39	1		T151	1		T51	1
auto[939524096:1073741823]	101	1			T2	1		T26	1		T150	1
auto[1073741824:1207959551]	107	1			T39	1		T26	1		T69	1
auto[1207959552:1342177279]	100	1			T38	1		T50	1		T65	3
auto[1342177280:1476395007]	86	1			T3	1		T38	1		T27	1
auto[1476395008:1610612735]	105	1			T26	1		T145	1		T65	1
auto[1610612736:1744830463]	114	1			T26	1		T28	1		T51	1
auto[1744830464:1879048191]	92	1			T16	1		T39	1		T66	1
auto[1879048192:2013265919]	110	1			T50	1		T70	1		T214	1
auto[2013265920:2147483647]	104	1			T17	1		T65	1		T51	1
auto[2147483648:2281701375]	103	1			T4	1		T28	1		T19	1
auto[2281701376:2415919103]	111	1			T41	1		T65	2		T150	1
auto[2415919104:2550136831]	111	1			T28	1		T19	1		T65	1
auto[2550136832:2684354559]	92	1			T50	1		T51	1		T23	1
auto[2684354560:2818572287]	98	1			T16	1		T39	2		T50	1
auto[2818572288:2952790015]	83	1			T4	1		T27	1		T152	1
auto[2952790016:3087007743]	108	1			T41	1		T28	2		T65	1
auto[3087007744:3221225471]	89	1			T39	1		T65	1		T212	1
auto[3221225472:3355443199]	115	1			T2	1		T17	1		T39	1
auto[3355443200:3489660927]	116	1			T4	1		T17	1		T39	1
auto[3489660928:3623878655]	79	1			T4	1		T41	1		T65	1
auto[3623878656:3758096383]	93	1			T4	1		T39	1		T28	1
auto[3758096384:3892314111]	68	1			T27	2		T28	1		T23	1
auto[3892314112:4026531839]	84	1			T4	1		T19	1		T70	1
auto[4026531840:4160749567]	80	1			T40	1		T51	1		T66	1
auto[4160749568:4294967295]	105	1			T65	1		T150	1		T51	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T17	1		T65	2		T151	1
auto[0:134217727]	auto[1]	52	1			T41	1		T147	1		T66	1
auto[134217728:268435455]	auto[0]	57	1			T17	1		T65	1		T215	1
auto[134217728:268435455]	auto[1]	59	1			T65	1		T148	1		T66	1
auto[268435456:402653183]	auto[0]	47	1			T17	1		T65	1		T66	1
auto[268435456:402653183]	auto[1]	56	1			T38	1		T28	1		T50	1
auto[402653184:536870911]	auto[0]	44	1			T39	1		T66	1		T115	1
auto[402653184:536870911]	auto[1]	43	1			T3	1		T80	1		T308	1
auto[536870912:671088639]	auto[0]	63	1			T39	1		T151	1		T217	1
auto[536870912:671088639]	auto[1]	52	1			T39	1		T28	1		T147	1
auto[671088640:805306367]	auto[0]	46	1			T27	1		T66	1		T80	3
auto[671088640:805306367]	auto[1]	50	1			T2	1		T38	1		T28	1
auto[805306368:939524095]	auto[0]	47	1			T151	1		T51	1		T203	1
auto[805306368:939524095]	auto[1]	53	1			T39	1		T71	1		T261	1
auto[939524096:1073741823]	auto[0]	49	1			T150	1		T217	2		T23	1
auto[939524096:1073741823]	auto[1]	52	1			T2	1		T26	1		T48	1
auto[1073741824:1207959551]	auto[0]	59	1			T39	1		T26	1		T69	1
auto[1073741824:1207959551]	auto[1]	48	1			T7	1		T63	1		T136	3
auto[1207959552:1342177279]	auto[0]	51	1			T38	1		T50	1		T65	2
auto[1207959552:1342177279]	auto[1]	49	1			T65	1		T115	1		T25	1
auto[1342177280:1476395007]	auto[0]	39	1			T51	1		T152	1		T202	1
auto[1342177280:1476395007]	auto[1]	47	1			T3	1		T38	1		T27	1
auto[1476395008:1610612735]	auto[0]	52	1			T145	1		T23	1		T24	1
auto[1476395008:1610612735]	auto[1]	53	1			T26	1		T65	1		T67	1
auto[1610612736:1744830463]	auto[0]	58	1			T26	1		T28	1		T66	1
auto[1610612736:1744830463]	auto[1]	56	1			T51	1		T215	1		T152	1
auto[1744830464:1879048191]	auto[0]	47	1			T66	1		T71	1		T7	1
auto[1744830464:1879048191]	auto[1]	45	1			T16	1		T39	1		T203	1
auto[1879048192:2013265919]	auto[0]	58	1			T214	1		T398	1		T66	1
auto[1879048192:2013265919]	auto[1]	52	1			T50	1		T70	1		T71	1
auto[2013265920:2147483647]	auto[0]	46	1			T17	1		T51	1		T210	1
auto[2013265920:2147483647]	auto[1]	58	1			T65	1		T23	1		T66	1
auto[2147483648:2281701375]	auto[0]	59	1			T28	1		T19	1		T217	1
auto[2147483648:2281701375]	auto[1]	44	1			T4	1		T60	1		T71	1
auto[2281701376:2415919103]	auto[0]	54	1			T65	1		T150	1		T152	1
auto[2281701376:2415919103]	auto[1]	57	1			T41	1		T65	1		T113	2
auto[2415919104:2550136831]	auto[0]	51	1			T19	1		T23	1		T226	1
auto[2415919104:2550136831]	auto[1]	60	1			T28	1		T65	1		T148	1
auto[2550136832:2684354559]	auto[0]	48	1			T51	1		T23	1		T113	1
auto[2550136832:2684354559]	auto[1]	44	1			T50	1		T66	1		T67	1
auto[2684354560:2818572287]	auto[0]	50	1			T39	1		T145	1		T69	1
auto[2684354560:2818572287]	auto[1]	48	1			T16	1		T39	1		T50	1
auto[2818572288:2952790015]	auto[0]	38	1			T152	1		T6	1		T80	2
auto[2818572288:2952790015]	auto[1]	45	1			T4	1		T27	1		T203	1
auto[2952790016:3087007743]	auto[0]	49	1			T65	1		T217	1		T113	1
auto[2952790016:3087007743]	auto[1]	59	1			T41	1		T28	2		T217	1
auto[3087007744:3221225471]	auto[0]	53	1			T39	1		T65	1		T212	1
auto[3087007744:3221225471]	auto[1]	36	1			T106	1		T247	1		T25	1
auto[3221225472:3355443199]	auto[0]	54	1			T2	1		T17	1		T39	1
auto[3221225472:3355443199]	auto[1]	61	1			T214	1		T212	1		T66	1
auto[3355443200:3489660927]	auto[0]	55	1			T17	1		T65	2		T40	1
auto[3355443200:3489660927]	auto[1]	61	1			T4	1		T39	1		T80	1
auto[3489660928:3623878655]	auto[0]	28	1			T4	1		T66	1		T234	1
auto[3489660928:3623878655]	auto[1]	51	1			T41	1		T65	1		T210	1
auto[3623878656:3758096383]	auto[0]	50	1			T39	1		T215	1		T80	1
auto[3623878656:3758096383]	auto[1]	43	1			T4	1		T28	1		T65	1
auto[3758096384:3892314111]	auto[0]	30	1			T27	1		T28	1		T60	1
auto[3758096384:3892314111]	auto[1]	38	1			T27	1		T23	1		T66	1
auto[3892314112:4026531839]	auto[0]	47	1			T19	1		T147	1		T23	1
auto[3892314112:4026531839]	auto[1]	37	1			T4	1		T70	1		T151	1
auto[4026531840:4160749567]	auto[0]	36	1			T40	1		T51	1		T113	1
auto[4026531840:4160749567]	auto[1]	44	1			T66	1		T80	2		T63	1
auto[4160749568:4294967295]	auto[0]	45	1			T201	1		T76	1		T80	1
auto[4160749568:4294967295]	auto[1]	60	1			T65	1		T150	1		T51	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1546

1

T2

1

T4

1

T17

6

auto[1]

1629

1

T2

2

T3

2

T4

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	85	1			T39	1		T41	1		T28	1
auto[134217728:268435455]	100	1			T4	1		T39	1		T151	1
auto[268435456:402653183]	72	1			T65	2		T66	2		T113	1
auto[402653184:536870911]	97	1			T16	1		T65	1		T148	1
auto[536870912:671088639]	75	1			T65	1		T40	1		T66	1
auto[671088640:805306367]	85	1			T17	1		T41	1		T27	1
auto[805306368:939524095]	131	1			T17	1		T38	2		T39	1
auto[939524096:1073741823]	98	1			T28	1		T66	2		T226	1
auto[1073741824:1207959551]	78	1			T17	1		T39	1		T65	2
auto[1207959552:1342177279]	109	1			T26	1		T28	1		T19	1
auto[1342177280:1476395007]	100	1			T2	1		T41	2		T145	2
auto[1476395008:1610612735]	92	1			T17	1		T26	1		T65	2
auto[1610612736:1744830463]	98	1			T26	3		T19	1		T70	1
auto[1744830464:1879048191]	94	1			T4	1		T38	1		T28	1
auto[1879048192:2013265919]	111	1			T4	1		T16	1		T38	1
auto[2013265920:2147483647]	103	1			T39	1		T28	1		T70	1
auto[2147483648:2281701375]	98	1			T23	2		T152	1		T113	4
auto[2281701376:2415919103]	88	1			T65	1		T214	1		T212	1
auto[2415919104:2550136831]	100	1			T3	1		T4	1		T50	1
auto[2550136832:2684354559]	112	1			T65	1		T51	1		T66	1
auto[2684354560:2818572287]	99	1			T4	1		T39	1		T59	1
auto[2818572288:2952790015]	110	1			T28	1		T217	1		T23	1
auto[2952790016:3087007743]	94	1			T217	1		T218	1		T66	1
auto[3087007744:3221225471]	102	1			T65	1		T151	1		T51	1
auto[3221225472:3355443199]	94	1			T3	1		T4	1		T27	1
auto[3355443200:3489660927]	112	1			T50	1		T214	1		T67	1
auto[3489660928:3623878655]	90	1			T17	1		T66	1		T113	1
auto[3623878656:3758096383]	107	1			T2	1		T39	1		T27	1
auto[3758096384:3892314111]	126	1			T39	1		T28	1		T50	1
auto[3892314112:4026531839]	95	1			T17	1		T39	1		T28	1
auto[4026531840:4160749567]	104	1			T2	1		T19	1		T65	1
auto[4160749568:4294967295]	116	1			T39	1		T27	2		T66	2