Unified Coverage Report :: Group Instance : sealing_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1537

1

T2

1

T4

1

T17

6

auto[1]

1638

1

T2

2

T3

2

T4

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T17	2		T38	1		T27	1
auto[134217728:268435455]	95	1			T3	1		T39	1		T26	1
auto[268435456:402653183]	99	1			T39	2		T65	1		T151	1
auto[402653184:536870911]	108	1			T2	1		T4	1		T39	1
auto[536870912:671088639]	84	1			T4	1		T60	1		T203	1
auto[671088640:805306367]	114	1			T4	1		T28	1		T50	1
auto[805306368:939524095]	86	1			T65	1		T147	1		T59	1
auto[939524096:1073741823]	92	1			T17	2		T70	1		T51	1
auto[1073741824:1207959551]	93	1			T65	3		T40	1		T217	2
auto[1207959552:1342177279]	118	1			T39	1		T41	1		T398	1
auto[1342177280:1476395007]	87	1			T38	2		T27	3		T65	1
auto[1476395008:1610612735]	92	1			T39	1		T26	1		T28	1
auto[1610612736:1744830463]	104	1			T38	1		T39	1		T26	1
auto[1744830464:1879048191]	104	1			T65	1		T148	1		T214	1
auto[1879048192:2013265919]	85	1			T4	1		T39	1		T66	1
auto[2013265920:2147483647]	116	1			T41	1		T26	1		T60	1
auto[2147483648:2281701375]	79	1			T39	1		T145	1		T66	1
auto[2281701376:2415919103]	101	1			T19	1		T65	1		T76	1
auto[2415919104:2550136831]	101	1			T17	1		T28	1		T217	1
auto[2550136832:2684354559]	99	1			T16	1		T65	1		T71	1
auto[2684354560:2818572287]	97	1			T17	1		T65	1		T217	1
auto[2818572288:2952790015]	104	1			T39	1		T28	2		T19	1
auto[2952790016:3087007743]	104	1			T41	1		T28	1		T151	1
auto[3087007744:3221225471]	108	1			T2	1		T26	1		T147	1
auto[3221225472:3355443199]	98	1			T2	1		T28	1		T145	1
auto[3355443200:3489660927]	103	1			T16	1		T27	1		T28	1
auto[3489660928:3623878655]	110	1			T4	1		T39	1		T41	1
auto[3623878656:3758096383]	80	1			T4	1		T28	1		T145	1
auto[3758096384:3892314111]	105	1			T28	1		T50	1		T65	1
auto[3892314112:4026531839]	99	1			T3	1		T39	1		T70	1
auto[4026531840:4160749567]	105	1			T212	1		T215	1		T113	1
auto[4160749568:4294967295]	100	1			T65	1		T23	1		T66	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	62	1			T17	2		T210	1		T215	1
auto[0:134217727]	auto[1]	43	1			T38	1		T27	1		T106	1
auto[134217728:268435455]	auto[0]	44	1			T26	1		T65	1		T66	1
auto[134217728:268435455]	auto[1]	51	1			T3	1		T39	1		T66	1
auto[268435456:402653183]	auto[0]	46	1			T217	1		T66	1		T48	1
auto[268435456:402653183]	auto[1]	53	1			T39	2		T65	1		T151	1
auto[402653184:536870911]	auto[0]	50	1			T39	1		T150	1		T113	1
auto[402653184:536870911]	auto[1]	58	1			T2	1		T4	1		T214	1
auto[536870912:671088639]	auto[0]	36	1			T4	1		T203	1		T71	1
auto[536870912:671088639]	auto[1]	48	1			T60	1		T80	2		T64	3
auto[671088640:805306367]	auto[0]	48	1			T51	1		T66	1		T113	1
auto[671088640:805306367]	auto[1]	66	1			T4	1		T28	1		T50	1
auto[805306368:939524095]	auto[0]	42	1			T66	1		T60	1		T71	1
auto[805306368:939524095]	auto[1]	44	1			T65	1		T147	1		T59	1
auto[939524096:1073741823]	auto[0]	37	1			T17	2		T51	1		T80	3
auto[939524096:1073741823]	auto[1]	55	1			T70	1		T66	1		T76	1
auto[1073741824:1207959551]	auto[0]	48	1			T65	2		T217	2		T6	1
auto[1073741824:1207959551]	auto[1]	45	1			T65	1		T40	1		T67	1
auto[1207959552:1342177279]	auto[0]	59	1			T66	1		T58	1		T155	1
auto[1207959552:1342177279]	auto[1]	59	1			T39	1		T41	1		T398	1
auto[1342177280:1476395007]	auto[0]	43	1			T27	3		T65	1		T40	1
auto[1342177280:1476395007]	auto[1]	44	1			T38	2		T210	1		T66	1
auto[1476395008:1610612735]	auto[0]	48	1			T26	1		T65	1		T151	1
auto[1476395008:1610612735]	auto[1]	44	1			T39	1		T28	1		T50	1
auto[1610612736:1744830463]	auto[0]	50	1			T26	1		T23	1		T203	1
auto[1610612736:1744830463]	auto[1]	54	1			T38	1		T39	1		T65	1
auto[1744830464:1879048191]	auto[0]	49	1			T214	1		T66	1		T226	1
auto[1744830464:1879048191]	auto[1]	55	1			T65	1		T148	1		T25	1
auto[1879048192:2013265919]	auto[0]	34	1			T39	1		T152	1		T155	1
auto[1879048192:2013265919]	auto[1]	51	1			T4	1		T66	1		T113	1
auto[2013265920:2147483647]	auto[0]	61	1			T26	1		T201	1		T24	1
auto[2013265920:2147483647]	auto[1]	55	1			T41	1		T60	1		T203	1
auto[2147483648:2281701375]	auto[0]	35	1			T39	1		T71	2		T155	2
auto[2147483648:2281701375]	auto[1]	44	1			T145	1		T66	1		T113	1
auto[2281701376:2415919103]	auto[0]	49	1			T19	1		T65	1		T226	1
auto[2281701376:2415919103]	auto[1]	52	1			T76	1		T71	1		T80	1
auto[2415919104:2550136831]	auto[0]	49	1			T17	1		T217	1		T152	2
auto[2415919104:2550136831]	auto[1]	52	1			T28	1		T113	1		T25	1
auto[2550136832:2684354559]	auto[0]	43	1			T65	1		T71	1		T414	1
auto[2550136832:2684354559]	auto[1]	56	1			T16	1		T245	1		T7	1
auto[2684354560:2818572287]	auto[0]	53	1			T17	1		T65	1		T217	1
auto[2684354560:2818572287]	auto[1]	44	1			T23	1		T80	2		T231	1
auto[2818572288:2952790015]	auto[0]	55	1			T39	1		T28	1		T19	1
auto[2818572288:2952790015]	auto[1]	49	1			T28	1		T67	1		T80	2
auto[2952790016:3087007743]	auto[0]	48	1			T151	1		T60	1		T7	1
auto[2952790016:3087007743]	auto[1]	56	1			T41	1		T28	1		T66	2
auto[3087007744:3221225471]	auto[0]	52	1			T2	1		T51	1		T23	1
auto[3087007744:3221225471]	auto[1]	56	1			T26	1		T147	1		T150	1
auto[3221225472:3355443199]	auto[0]	48	1			T145	1		T65	2		T23	1
auto[3221225472:3355443199]	auto[1]	50	1			T2	1		T28	1		T151	1
auto[3355443200:3489660927]	auto[0]	59	1			T27	1		T19	1		T113	2
auto[3355443200:3489660927]	auto[1]	44	1			T16	1		T28	1		T50	1
auto[3489660928:3623878655]	auto[0]	54	1			T39	1		T50	1		T65	1
auto[3489660928:3623878655]	auto[1]	56	1			T4	1		T41	1		T65	1
auto[3623878656:3758096383]	auto[0]	40	1			T145	1		T66	1		T6	1
auto[3623878656:3758096383]	auto[1]	40	1			T4	1		T28	1		T66	1
auto[3758096384:3892314111]	auto[0]	43	1			T28	1		T113	1		T76	1
auto[3758096384:3892314111]	auto[1]	62	1			T50	1		T65	1		T51	1
auto[3892314112:4026531839]	auto[0]	54	1			T39	1		T23	1		T71	1
auto[3892314112:4026531839]	auto[1]	45	1			T3	1		T70	1		T148	1
auto[4026531840:4160749567]	auto[0]	47	1			T215	1		T113	1		T69	1
auto[4026531840:4160749567]	auto[1]	58	1			T212	1		T56	1		T52	1
auto[4160749568:4294967295]	auto[0]	51	1			T65	1		T113	1		T71	1
auto[4160749568:4294967295]	auto[1]	49	1			T23	1		T66	2		T203	1