Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.15 98.34 100.00 99.02 98.41 91.14


Total test records in report: 1079
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T1005 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2119185449 Aug 15 04:41:08 PM PDT 24 Aug 15 04:41:10 PM PDT 24 26691761 ps
T1006 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.4022965665 Aug 15 04:41:09 PM PDT 24 Aug 15 04:41:17 PM PDT 24 133351877 ps
T1007 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1599788007 Aug 15 04:41:50 PM PDT 24 Aug 15 04:41:51 PM PDT 24 13207473 ps
T1008 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3257724322 Aug 15 04:41:24 PM PDT 24 Aug 15 04:41:30 PM PDT 24 654584856 ps
T1009 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.345779923 Aug 15 04:41:16 PM PDT 24 Aug 15 04:41:17 PM PDT 24 32175424 ps
T1010 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1342525352 Aug 15 04:41:33 PM PDT 24 Aug 15 04:41:38 PM PDT 24 870386832 ps
T1011 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.775621467 Aug 15 04:41:00 PM PDT 24 Aug 15 04:41:04 PM PDT 24 157444345 ps
T1012 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2599640645 Aug 15 04:41:02 PM PDT 24 Aug 15 04:41:03 PM PDT 24 203425160 ps
T1013 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2523490245 Aug 15 04:41:24 PM PDT 24 Aug 15 04:41:27 PM PDT 24 480274247 ps
T1014 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2435338292 Aug 15 04:41:09 PM PDT 24 Aug 15 04:41:25 PM PDT 24 1314869690 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1703400927 Aug 15 04:40:58 PM PDT 24 Aug 15 04:40:59 PM PDT 24 28130280 ps
T1016 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1308470329 Aug 15 04:41:50 PM PDT 24 Aug 15 04:41:51 PM PDT 24 10439338 ps
T1017 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1775444708 Aug 15 04:41:24 PM PDT 24 Aug 15 04:41:26 PM PDT 24 342367051 ps
T1018 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2722772406 Aug 15 04:41:41 PM PDT 24 Aug 15 04:41:42 PM PDT 24 11478354 ps
T1019 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3356736752 Aug 15 04:41:18 PM PDT 24 Aug 15 04:41:21 PM PDT 24 150564680 ps
T1020 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4244453057 Aug 15 04:41:31 PM PDT 24 Aug 15 04:41:34 PM PDT 24 145028770 ps
T170 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3003661810 Aug 15 04:41:18 PM PDT 24 Aug 15 04:41:21 PM PDT 24 81713718 ps
T1021 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2429573362 Aug 15 04:41:16 PM PDT 24 Aug 15 04:41:20 PM PDT 24 47662601 ps
T1022 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3706352795 Aug 15 04:41:28 PM PDT 24 Aug 15 04:41:36 PM PDT 24 838681186 ps
T1023 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3124646569 Aug 15 04:41:29 PM PDT 24 Aug 15 04:41:32 PM PDT 24 146753678 ps
T1024 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.567870588 Aug 15 04:41:39 PM PDT 24 Aug 15 04:41:42 PM PDT 24 61787072 ps
T1025 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1259990758 Aug 15 04:41:51 PM PDT 24 Aug 15 04:41:52 PM PDT 24 19706189 ps
T1026 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2197477091 Aug 15 04:41:27 PM PDT 24 Aug 15 04:41:31 PM PDT 24 120379704 ps
T1027 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4144187203 Aug 15 04:41:43 PM PDT 24 Aug 15 04:41:44 PM PDT 24 13770791 ps
T1028 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4250648427 Aug 15 04:41:24 PM PDT 24 Aug 15 04:41:26 PM PDT 24 76692221 ps
T1029 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.914939174 Aug 15 04:41:39 PM PDT 24 Aug 15 04:41:44 PM PDT 24 156509464 ps
T1030 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3418265425 Aug 15 04:41:16 PM PDT 24 Aug 15 04:41:19 PM PDT 24 176958832 ps
T1031 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2744716869 Aug 15 04:41:09 PM PDT 24 Aug 15 04:41:12 PM PDT 24 91735377 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1132453021 Aug 15 04:41:09 PM PDT 24 Aug 15 04:41:11 PM PDT 24 347135551 ps
T1033 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2905560429 Aug 15 04:41:42 PM PDT 24 Aug 15 04:41:43 PM PDT 24 12053699 ps
T1034 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3690442595 Aug 15 04:41:24 PM PDT 24 Aug 15 04:41:25 PM PDT 24 43132307 ps
T1035 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.238432291 Aug 15 04:41:19 PM PDT 24 Aug 15 04:41:20 PM PDT 24 37829221 ps
T1036 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2253331242 Aug 15 04:41:32 PM PDT 24 Aug 15 04:41:35 PM PDT 24 51991366 ps
T1037 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.232336293 Aug 15 04:41:08 PM PDT 24 Aug 15 04:41:17 PM PDT 24 986284888 ps
T1038 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3445008070 Aug 15 04:41:45 PM PDT 24 Aug 15 04:41:47 PM PDT 24 216435094 ps
T1039 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1331949078 Aug 15 04:41:45 PM PDT 24 Aug 15 04:41:46 PM PDT 24 28712486 ps
T1040 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1401587615 Aug 15 04:41:29 PM PDT 24 Aug 15 04:41:32 PM PDT 24 241964885 ps
T1041 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.56130306 Aug 15 04:41:22 PM PDT 24 Aug 15 04:41:24 PM PDT 24 58875944 ps
T1042 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.686289142 Aug 15 04:41:23 PM PDT 24 Aug 15 04:41:25 PM PDT 24 81582913 ps
T1043 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1027513269 Aug 15 04:41:25 PM PDT 24 Aug 15 04:41:26 PM PDT 24 12914025 ps
T1044 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3451855977 Aug 15 04:41:23 PM PDT 24 Aug 15 04:41:27 PM PDT 24 106481146 ps
T1045 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3980346311 Aug 15 04:41:08 PM PDT 24 Aug 15 04:41:09 PM PDT 24 9539022 ps
T1046 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3072659047 Aug 15 04:41:31 PM PDT 24 Aug 15 04:41:33 PM PDT 24 55594538 ps
T1047 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1337861761 Aug 15 04:41:16 PM PDT 24 Aug 15 04:41:21 PM PDT 24 590627770 ps
T1048 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3976963292 Aug 15 04:41:52 PM PDT 24 Aug 15 04:41:53 PM PDT 24 29902224 ps
T1049 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1401229305 Aug 15 04:41:00 PM PDT 24 Aug 15 04:41:03 PM PDT 24 57677100 ps
T1050 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3611932982 Aug 15 04:41:44 PM PDT 24 Aug 15 04:41:45 PM PDT 24 166806441 ps
T1051 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1430257984 Aug 15 04:41:09 PM PDT 24 Aug 15 04:41:12 PM PDT 24 121906765 ps
T1052 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2385191397 Aug 15 04:41:09 PM PDT 24 Aug 15 04:41:11 PM PDT 24 53390370 ps
T1053 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.625114337 Aug 15 04:41:16 PM PDT 24 Aug 15 04:41:18 PM PDT 24 198210189 ps
T1054 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1116256264 Aug 15 04:41:30 PM PDT 24 Aug 15 04:41:32 PM PDT 24 53565537 ps
T1055 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3194152757 Aug 15 04:41:30 PM PDT 24 Aug 15 04:41:31 PM PDT 24 43995318 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.4278736931 Aug 15 04:41:06 PM PDT 24 Aug 15 04:41:18 PM PDT 24 1041801074 ps
T1057 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3097603936 Aug 15 04:41:16 PM PDT 24 Aug 15 04:41:19 PM PDT 24 112957743 ps
T1058 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4093680066 Aug 15 04:41:17 PM PDT 24 Aug 15 04:41:19 PM PDT 24 292651348 ps
T1059 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2189940464 Aug 15 04:41:31 PM PDT 24 Aug 15 04:41:35 PM PDT 24 548045600 ps
T1060 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3785800116 Aug 15 04:41:16 PM PDT 24 Aug 15 04:41:20 PM PDT 24 379542841 ps
T187 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4182203728 Aug 15 04:41:10 PM PDT 24 Aug 15 04:41:13 PM PDT 24 138960618 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3627103152 Aug 15 04:41:17 PM PDT 24 Aug 15 04:41:26 PM PDT 24 472511403 ps
T1062 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3688526583 Aug 15 04:41:06 PM PDT 24 Aug 15 04:41:10 PM PDT 24 66986076 ps
T1063 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1998630775 Aug 15 04:41:02 PM PDT 24 Aug 15 04:41:04 PM PDT 24 187869471 ps
T1064 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2163614354 Aug 15 04:41:10 PM PDT 24 Aug 15 04:41:11 PM PDT 24 38255859 ps
T1065 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2999075527 Aug 15 04:41:27 PM PDT 24 Aug 15 04:41:28 PM PDT 24 43144227 ps
T1066 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2179950435 Aug 15 04:41:25 PM PDT 24 Aug 15 04:41:32 PM PDT 24 480052747 ps
T1067 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2729824814 Aug 15 04:41:24 PM PDT 24 Aug 15 04:41:25 PM PDT 24 17419427 ps
T1068 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1533370768 Aug 15 04:41:09 PM PDT 24 Aug 15 04:41:11 PM PDT 24 64208244 ps
T1069 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.287878314 Aug 15 04:41:31 PM PDT 24 Aug 15 04:41:33 PM PDT 24 48826816 ps
T1070 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1719286085 Aug 15 04:41:33 PM PDT 24 Aug 15 04:41:35 PM PDT 24 28180762 ps
T1071 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.402025600 Aug 15 04:41:15 PM PDT 24 Aug 15 04:41:16 PM PDT 24 29138152 ps
T1072 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.624153946 Aug 15 04:41:26 PM PDT 24 Aug 15 04:41:28 PM PDT 24 40238431 ps
T1073 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4131026527 Aug 15 04:41:32 PM PDT 24 Aug 15 04:41:39 PM PDT 24 357868482 ps
T1074 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3817086316 Aug 15 04:41:33 PM PDT 24 Aug 15 04:41:37 PM PDT 24 91560142 ps
T177 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2968726569 Aug 15 04:40:54 PM PDT 24 Aug 15 04:40:58 PM PDT 24 136436506 ps
T1075 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2019709806 Aug 15 04:41:25 PM PDT 24 Aug 15 04:41:27 PM PDT 24 151757058 ps
T1076 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2622626688 Aug 15 04:41:18 PM PDT 24 Aug 15 04:41:19 PM PDT 24 101505222 ps
T1077 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2680960072 Aug 15 04:41:24 PM PDT 24 Aug 15 04:41:26 PM PDT 24 256235974 ps
T1078 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1174812804 Aug 15 04:41:08 PM PDT 24 Aug 15 04:41:10 PM PDT 24 41256030 ps
T188 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.326496118 Aug 15 04:41:08 PM PDT 24 Aug 15 04:41:14 PM PDT 24 824482165 ps
T1079 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.895703854 Aug 15 04:41:52 PM PDT 24 Aug 15 04:41:53 PM PDT 24 9771440 ps

Test location /workspace/coverage/default/16.keymgr_lc_disable.2096059844
Short name T4
Test name
Test status
Simulation time 286557263 ps
CPU time 3.93 seconds
Started Aug 15 05:51:03 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 210036 kb
Host smart-f1984ebc-9625-4ab9-bf03-e0b50ed20a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096059844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2096059844
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.967151388
Short name T113
Test name
Test status
Simulation time 3342302287 ps
CPU time 26.7 seconds
Started Aug 15 05:50:36 PM PDT 24
Finished Aug 15 05:51:03 PM PDT 24
Peak memory 223064 kb
Host smart-2c582560-52cd-44f8-b7cf-72957bd3bb2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967151388 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.967151388
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2177038219
Short name T80
Test name
Test status
Simulation time 4064836776 ps
CPU time 39.4 seconds
Started Aug 15 05:50:27 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 215736 kb
Host smart-81d6f6f3-9103-443a-9966-571b73dffb9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177038219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2177038219
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2348905335
Short name T39
Test name
Test status
Simulation time 384178930 ps
CPU time 23.44 seconds
Started Aug 15 05:52:24 PM PDT 24
Finished Aug 15 05:52:47 PM PDT 24
Peak memory 223068 kb
Host smart-df87e9cb-be2f-4a73-9cec-fec52b1ce65b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348905335 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2348905335
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1879853137
Short name T11
Test name
Test status
Simulation time 325341134 ps
CPU time 7.34 seconds
Started Aug 15 05:50:28 PM PDT 24
Finished Aug 15 05:50:35 PM PDT 24
Peak memory 230188 kb
Host smart-7780ce0a-5480-44e7-a7e5-a0354cc4ee57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879853137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1879853137
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1980751378
Short name T64
Test name
Test status
Simulation time 5332819314 ps
CPU time 60.47 seconds
Started Aug 15 05:52:19 PM PDT 24
Finished Aug 15 05:53:20 PM PDT 24
Peak memory 216656 kb
Host smart-ffc34b1a-45d8-41b9-a405-6efc13eee507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980751378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1980751378
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2562318611
Short name T28
Test name
Test status
Simulation time 725662355 ps
CPU time 6.21 seconds
Started Aug 15 05:51:22 PM PDT 24
Finished Aug 15 05:51:28 PM PDT 24
Peak memory 222812 kb
Host smart-0e059ad1-a0bf-447f-8daf-ed56b865f7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562318611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2562318611
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1857374756
Short name T6
Test name
Test status
Simulation time 79096914 ps
CPU time 2.84 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 210100 kb
Host smart-d034364b-5316-417e-9018-f561154ed01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857374756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1857374756
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3002048069
Short name T38
Test name
Test status
Simulation time 2011237817 ps
CPU time 107.39 seconds
Started Aug 15 05:50:46 PM PDT 24
Finished Aug 15 05:52:34 PM PDT 24
Peak memory 216372 kb
Host smart-6cf73b6a-dec6-4ee0-bb2d-9b279a59960e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3002048069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3002048069
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2365942503
Short name T252
Test name
Test status
Simulation time 505652604 ps
CPU time 5.82 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:59 PM PDT 24
Peak memory 214716 kb
Host smart-08d8dab3-2ad4-416a-93d7-68aa7b7019d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365942503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2365942503
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1233307215
Short name T155
Test name
Test status
Simulation time 2227202204 ps
CPU time 25.77 seconds
Started Aug 15 05:50:39 PM PDT 24
Finished Aug 15 05:51:05 PM PDT 24
Peak memory 217132 kb
Host smart-8561a434-d579-42a5-ac3d-98fe02ffba81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233307215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1233307215
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2397999186
Short name T9
Test name
Test status
Simulation time 205353712 ps
CPU time 4.03 seconds
Started Aug 15 05:51:07 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 222548 kb
Host smart-0f8efb7f-9c73-435d-ae79-7e86307729a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397999186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2397999186
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.41537312
Short name T124
Test name
Test status
Simulation time 125851759 ps
CPU time 3.73 seconds
Started Aug 15 04:41:18 PM PDT 24
Finished Aug 15 04:41:22 PM PDT 24
Peak memory 214848 kb
Host smart-b42cee6f-476f-4fef-ab4f-28fd4d92c080
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41537312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.41537312
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3443420108
Short name T156
Test name
Test status
Simulation time 543509160 ps
CPU time 28.11 seconds
Started Aug 15 05:52:26 PM PDT 24
Finished Aug 15 05:52:55 PM PDT 24
Peak memory 215884 kb
Host smart-a74a1148-a023-4123-a260-c67e6e86649c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443420108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3443420108
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1270118458
Short name T71
Test name
Test status
Simulation time 2650669011 ps
CPU time 61.4 seconds
Started Aug 15 05:50:53 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 222996 kb
Host smart-39d5f8ce-f887-478d-a4b1-85daf371b31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270118458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1270118458
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.165227154
Short name T23
Test name
Test status
Simulation time 1450428441 ps
CPU time 10.63 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:57 PM PDT 24
Peak memory 214828 kb
Host smart-3df24b60-13c9-4cc3-a081-f88317dbf1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165227154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.165227154
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3382508062
Short name T408
Test name
Test status
Simulation time 1044790461 ps
CPU time 14.67 seconds
Started Aug 15 05:52:33 PM PDT 24
Finished Aug 15 05:52:49 PM PDT 24
Peak memory 214988 kb
Host smart-82b23b3e-7c08-474e-a105-c3ac0fbeefdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382508062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3382508062
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2966553132
Short name T311
Test name
Test status
Simulation time 531893032 ps
CPU time 14.9 seconds
Started Aug 15 05:51:24 PM PDT 24
Finished Aug 15 05:51:39 PM PDT 24
Peak memory 216112 kb
Host smart-00bac7b9-189b-4377-8946-39c40ef59e08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966553132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2966553132
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.921500589
Short name T40
Test name
Test status
Simulation time 102698614 ps
CPU time 3 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:50:57 PM PDT 24
Peak memory 218212 kb
Host smart-ac0abd94-2691-4bf8-a9b9-4830cd0fa879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921500589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.921500589
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2908771745
Short name T131
Test name
Test status
Simulation time 75019736 ps
CPU time 1.89 seconds
Started Aug 15 04:41:00 PM PDT 24
Finished Aug 15 04:41:02 PM PDT 24
Peak memory 214724 kb
Host smart-93726e61-b4f1-40f9-ba22-ebca44f0f34e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908771745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2908771745
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2575217004
Short name T21
Test name
Test status
Simulation time 497487443 ps
CPU time 1.97 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 209628 kb
Host smart-046dd2a1-4a5a-4624-8ed2-0f71f3f61374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575217004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2575217004
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3385502086
Short name T25
Test name
Test status
Simulation time 117113292 ps
CPU time 2.75 seconds
Started Aug 15 05:50:26 PM PDT 24
Finished Aug 15 05:50:29 PM PDT 24
Peak memory 222792 kb
Host smart-1478d9cd-f855-4b63-94a0-d53e0c276477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385502086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3385502086
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.850354962
Short name T268
Test name
Test status
Simulation time 638813446 ps
CPU time 11.17 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:33 PM PDT 24
Peak memory 216208 kb
Host smart-78c2a847-6234-474d-b76e-8ab724f77613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850354962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.850354962
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.768349760
Short name T65
Test name
Test status
Simulation time 601614427 ps
CPU time 8.96 seconds
Started Aug 15 05:51:52 PM PDT 24
Finished Aug 15 05:52:01 PM PDT 24
Peak memory 217008 kb
Host smart-e88f6aa9-54df-40ed-9fe3-89abbfea091a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768349760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.768349760
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1695859004
Short name T285
Test name
Test status
Simulation time 521611588 ps
CPU time 15.43 seconds
Started Aug 15 05:50:36 PM PDT 24
Finished Aug 15 05:50:51 PM PDT 24
Peak memory 214792 kb
Host smart-9fc7dadb-36c4-44f3-8e79-2a09069b8301
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695859004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1695859004
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1252277542
Short name T75
Test name
Test status
Simulation time 528192244 ps
CPU time 28.02 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:52:16 PM PDT 24
Peak memory 222164 kb
Host smart-ca66dfe9-7624-4ae1-98b9-6c3094eca492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252277542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1252277542
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2267205066
Short name T628
Test name
Test status
Simulation time 244691522 ps
CPU time 4.76 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 210012 kb
Host smart-890c3292-5dfa-4e6b-9518-fa78180efcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267205066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2267205066
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.342874747
Short name T29
Test name
Test status
Simulation time 44325025 ps
CPU time 2.76 seconds
Started Aug 15 05:51:11 PM PDT 24
Finished Aug 15 05:51:14 PM PDT 24
Peak memory 220412 kb
Host smart-24daf582-f888-422a-a44d-577aade8ffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342874747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.342874747
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1355549413
Short name T181
Test name
Test status
Simulation time 875935117 ps
CPU time 9.27 seconds
Started Aug 15 04:41:20 PM PDT 24
Finished Aug 15 04:41:30 PM PDT 24
Peak memory 214424 kb
Host smart-4671ee74-3e53-422f-a75a-f2d36ce3b92d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355549413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1355549413
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.4081830898
Short name T53
Test name
Test status
Simulation time 895190405 ps
CPU time 37.21 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:52:25 PM PDT 24
Peak memory 216020 kb
Host smart-538b0d14-995e-4cff-b1ad-45eb54a891e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081830898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.4081830898
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3889937146
Short name T1
Test name
Test status
Simulation time 31945221 ps
CPU time 0.81 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:50:55 PM PDT 24
Peak memory 206368 kb
Host smart-3994b0a4-57a4-42d6-bc6e-8c75b696b9f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889937146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3889937146
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3437248235
Short name T365
Test name
Test status
Simulation time 143733354 ps
CPU time 7.66 seconds
Started Aug 15 05:51:17 PM PDT 24
Finished Aug 15 05:51:25 PM PDT 24
Peak memory 214800 kb
Host smart-622b77b8-5f32-4581-ac50-a67ec2b110ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437248235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3437248235
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1110254562
Short name T110
Test name
Test status
Simulation time 290248699 ps
CPU time 7.44 seconds
Started Aug 15 05:50:38 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 209816 kb
Host smart-4c8134f7-34c0-430a-b5f7-d2ded264e02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110254562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1110254562
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2642623323
Short name T394
Test name
Test status
Simulation time 168753726 ps
CPU time 2.05 seconds
Started Aug 15 05:50:51 PM PDT 24
Finished Aug 15 05:50:53 PM PDT 24
Peak memory 210632 kb
Host smart-27a835b9-98de-446c-a942-560338fba0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642623323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2642623323
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.412261195
Short name T241
Test name
Test status
Simulation time 2371596716 ps
CPU time 28.99 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:26 PM PDT 24
Peak memory 222988 kb
Host smart-4de6c9e8-6bd1-41b6-bad6-3a56d2128910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412261195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.412261195
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3511085901
Short name T185
Test name
Test status
Simulation time 976901892 ps
CPU time 9.26 seconds
Started Aug 15 04:41:27 PM PDT 24
Finished Aug 15 04:41:36 PM PDT 24
Peak memory 214488 kb
Host smart-92f477b6-3da2-40af-b897-ff30838cf613
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511085901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3511085901
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2481123898
Short name T153
Test name
Test status
Simulation time 224424064 ps
CPU time 6.54 seconds
Started Aug 15 05:51:59 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 215548 kb
Host smart-ca3bd102-e203-421f-a7c0-6619fc9981fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481123898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2481123898
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3528270894
Short name T66
Test name
Test status
Simulation time 1252490199 ps
CPU time 40.05 seconds
Started Aug 15 05:50:46 PM PDT 24
Finished Aug 15 05:51:26 PM PDT 24
Peak memory 222956 kb
Host smart-013bab54-7b18-41e7-af53-ebd5ca697343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528270894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3528270894
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3395248106
Short name T368
Test name
Test status
Simulation time 762134931 ps
CPU time 5.36 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:14 PM PDT 24
Peak memory 214848 kb
Host smart-e3ade472-19c5-4f37-b99f-dd8a74baa87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395248106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3395248106
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1362213297
Short name T304
Test name
Test status
Simulation time 12047155168 ps
CPU time 331.92 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 218264 kb
Host smart-0919c618-de10-4530-a392-b66c7494f1d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362213297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1362213297
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2689850063
Short name T22
Test name
Test status
Simulation time 122960174 ps
CPU time 1.7 seconds
Started Aug 15 05:52:14 PM PDT 24
Finished Aug 15 05:52:16 PM PDT 24
Peak memory 210708 kb
Host smart-15ce4123-5030-403e-9180-4334370af8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689850063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2689850063
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.709267307
Short name T331
Test name
Test status
Simulation time 35470029 ps
CPU time 2.23 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:01 PM PDT 24
Peak memory 214616 kb
Host smart-4721c004-7d95-41b0-9423-07a8f975083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709267307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.709267307
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1537788581
Short name T276
Test name
Test status
Simulation time 88762222 ps
CPU time 1.92 seconds
Started Aug 15 05:51:16 PM PDT 24
Finished Aug 15 05:51:18 PM PDT 24
Peak memory 214644 kb
Host smart-f5d5b1b5-9d4e-4c8e-abe3-1ee12624dd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537788581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1537788581
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2954931127
Short name T334
Test name
Test status
Simulation time 25635847747 ps
CPU time 316.27 seconds
Started Aug 15 05:51:12 PM PDT 24
Finished Aug 15 05:56:28 PM PDT 24
Peak memory 222260 kb
Host smart-d80526e8-8dd7-46d1-bde0-f162f9ce0398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954931127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2954931127
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3706642780
Short name T152
Test name
Test status
Simulation time 974817838 ps
CPU time 10.98 seconds
Started Aug 15 05:51:54 PM PDT 24
Finished Aug 15 05:52:05 PM PDT 24
Peak memory 216480 kb
Host smart-f7ed2d9c-cd9f-444d-ad19-f4a68fd6566f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706642780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3706642780
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3316389250
Short name T142
Test name
Test status
Simulation time 418555725 ps
CPU time 10.68 seconds
Started Aug 15 05:51:59 PM PDT 24
Finished Aug 15 05:52:10 PM PDT 24
Peak memory 208900 kb
Host smart-3a43309c-85ba-4a60-916c-f0605388707e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316389250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3316389250
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1490634922
Short name T211
Test name
Test status
Simulation time 160989455 ps
CPU time 7.28 seconds
Started Aug 15 05:50:49 PM PDT 24
Finished Aug 15 05:50:56 PM PDT 24
Peak memory 215124 kb
Host smart-ee86bbca-c314-4824-88b0-2970d4077945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490634922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1490634922
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4184852007
Short name T183
Test name
Test status
Simulation time 394088591 ps
CPU time 11.41 seconds
Started Aug 15 04:41:25 PM PDT 24
Finished Aug 15 04:41:37 PM PDT 24
Peak memory 214468 kb
Host smart-becb22c3-9e85-484d-bd52-4ed4b4b12e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184852007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4184852007
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4208628559
Short name T173
Test name
Test status
Simulation time 383516454 ps
CPU time 8.48 seconds
Started Aug 15 04:41:31 PM PDT 24
Finished Aug 15 04:41:39 PM PDT 24
Peak memory 214444 kb
Host smart-29e3a6f8-768f-40b7-972c-18ce101b1988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208628559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4208628559
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2492695542
Short name T133
Test name
Test status
Simulation time 906968527 ps
CPU time 5.2 seconds
Started Aug 15 04:41:00 PM PDT 24
Finished Aug 15 04:41:06 PM PDT 24
Peak memory 214900 kb
Host smart-a1cd1035-4089-4090-83bd-761027233557
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492695542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2492695542
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1735230839
Short name T138
Test name
Test status
Simulation time 1472166242 ps
CPU time 13.96 seconds
Started Aug 15 05:51:03 PM PDT 24
Finished Aug 15 05:51:17 PM PDT 24
Peak memory 223060 kb
Host smart-4e2e7a41-3776-443c-872a-9f71957287ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735230839 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1735230839
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2365013
Short name T232
Test name
Test status
Simulation time 9164388854 ps
CPU time 251.52 seconds
Started Aug 15 05:51:20 PM PDT 24
Finished Aug 15 05:55:32 PM PDT 24
Peak memory 223168 kb
Host smart-a1b3156c-cebe-4d23-9e3b-1c79ad2d384a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2365013
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3414877430
Short name T245
Test name
Test status
Simulation time 83026699 ps
CPU time 4.57 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 214748 kb
Host smart-a57233ea-8952-4e74-a142-80e79f82475a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414877430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3414877430
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3496679626
Short name T535
Test name
Test status
Simulation time 434041539 ps
CPU time 3.24 seconds
Started Aug 15 05:52:03 PM PDT 24
Finished Aug 15 05:52:06 PM PDT 24
Peak memory 210556 kb
Host smart-f60c6ba7-365f-46b0-933e-7df2742b0b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496679626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3496679626
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2968726569
Short name T177
Test name
Test status
Simulation time 136436506 ps
CPU time 4.67 seconds
Started Aug 15 04:40:54 PM PDT 24
Finished Aug 15 04:40:58 PM PDT 24
Peak memory 206316 kb
Host smart-1e15b67a-8429-4795-ab0c-5be3f742b9ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968726569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2968726569
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2262088346
Short name T168
Test name
Test status
Simulation time 173332160 ps
CPU time 2.87 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:03 PM PDT 24
Peak memory 223124 kb
Host smart-04f98c42-48ee-45c3-91f1-d3227911ef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262088346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2262088346
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.784504432
Short name T52
Test name
Test status
Simulation time 1933293648 ps
CPU time 4.58 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:04 PM PDT 24
Peak memory 214700 kb
Host smart-0ff719ba-f0a8-4542-b2c5-34ed0efd4336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784504432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.784504432
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2970845481
Short name T907
Test name
Test status
Simulation time 265353328 ps
CPU time 3.56 seconds
Started Aug 15 05:51:14 PM PDT 24
Finished Aug 15 05:51:18 PM PDT 24
Peak memory 209336 kb
Host smart-05e725c8-f5d8-4bb8-8a4d-10e95aae8ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970845481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2970845481
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1091665088
Short name T423
Test name
Test status
Simulation time 513081553 ps
CPU time 13.53 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:52:04 PM PDT 24
Peak memory 222876 kb
Host smart-089b1fb9-5312-4da6-b622-c5e4004db359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091665088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1091665088
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3046054512
Short name T280
Test name
Test status
Simulation time 106253904 ps
CPU time 4.04 seconds
Started Aug 15 05:52:05 PM PDT 24
Finished Aug 15 05:52:09 PM PDT 24
Peak memory 215692 kb
Host smart-3fdd958f-79f0-4a41-91ad-e2de0d635120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046054512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3046054512
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3753985713
Short name T230
Test name
Test status
Simulation time 816160114 ps
CPU time 29.04 seconds
Started Aug 15 05:50:50 PM PDT 24
Finished Aug 15 05:51:20 PM PDT 24
Peak memory 222920 kb
Host smart-d9f2fef0-dcd7-4921-aec5-0d3534416d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753985713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3753985713
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.784714993
Short name T190
Test name
Test status
Simulation time 621197155 ps
CPU time 9.21 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:10 PM PDT 24
Peak memory 211380 kb
Host smart-02cefc5d-6561-454d-a03b-b4cd1c9690f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784714993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.784714993
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2628332321
Short name T165
Test name
Test status
Simulation time 2109535359 ps
CPU time 6.55 seconds
Started Aug 15 05:51:32 PM PDT 24
Finished Aug 15 05:51:39 PM PDT 24
Peak memory 218928 kb
Host smart-ed9ffa5c-6888-412f-b851-686942f6fb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628332321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2628332321
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2573604009
Short name T58
Test name
Test status
Simulation time 171146806 ps
CPU time 4.46 seconds
Started Aug 15 05:52:31 PM PDT 24
Finished Aug 15 05:52:36 PM PDT 24
Peak memory 218152 kb
Host smart-a605ac88-dc0f-4056-a65c-c4fabcf21161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573604009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2573604009
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2665364841
Short name T166
Test name
Test status
Simulation time 217923256 ps
CPU time 2.69 seconds
Started Aug 15 05:52:13 PM PDT 24
Finished Aug 15 05:52:16 PM PDT 24
Peak memory 216168 kb
Host smart-ca864ac2-9ba6-49ed-a1db-f5a43cbfd2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665364841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2665364841
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.302349706
Short name T164
Test name
Test status
Simulation time 546246018 ps
CPU time 4.63 seconds
Started Aug 15 05:52:28 PM PDT 24
Finished Aug 15 05:52:33 PM PDT 24
Peak memory 223060 kb
Host smart-56d47607-00e1-4643-8963-e28e3f6b931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302349706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.302349706
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1727129791
Short name T882
Test name
Test status
Simulation time 67938397 ps
CPU time 2.71 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 214828 kb
Host smart-a4188de4-d421-420b-9360-c801dfda516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727129791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1727129791
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1168617053
Short name T351
Test name
Test status
Simulation time 36855412 ps
CPU time 2.18 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:50:57 PM PDT 24
Peak memory 222928 kb
Host smart-364396f4-c3ce-474b-8c87-92373d72d798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168617053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1168617053
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3615199733
Short name T16
Test name
Test status
Simulation time 215097802 ps
CPU time 13.21 seconds
Started Aug 15 05:50:33 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 214784 kb
Host smart-f3bda72e-c0f5-430c-b50f-566f888a1981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615199733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3615199733
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1920904194
Short name T54
Test name
Test status
Simulation time 311491643 ps
CPU time 14 seconds
Started Aug 15 05:52:12 PM PDT 24
Finished Aug 15 05:52:26 PM PDT 24
Peak memory 216792 kb
Host smart-d472be0c-8029-4664-9540-155b519f0ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920904194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1920904194
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_random.1664640863
Short name T320
Test name
Test status
Simulation time 119942898 ps
CPU time 5.04 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:48 PM PDT 24
Peak memory 214740 kb
Host smart-3fc650ed-ec9b-4413-a25d-ebe6b0355b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664640863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1664640863
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3997291806
Short name T374
Test name
Test status
Simulation time 163251703 ps
CPU time 3.72 seconds
Started Aug 15 05:50:45 PM PDT 24
Finished Aug 15 05:50:49 PM PDT 24
Peak memory 210576 kb
Host smart-f4167552-b64d-4615-bf90-77440ba1fa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997291806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3997291806
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2289309225
Short name T180
Test name
Test status
Simulation time 55189675 ps
CPU time 3.02 seconds
Started Aug 15 04:41:00 PM PDT 24
Finished Aug 15 04:41:03 PM PDT 24
Peak memory 214324 kb
Host smart-d2238c77-c628-400d-bafb-eb89599eb911
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289309225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2289309225
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.635998091
Short name T182
Test name
Test status
Simulation time 534558416 ps
CPU time 5.97 seconds
Started Aug 15 04:41:25 PM PDT 24
Finished Aug 15 04:41:31 PM PDT 24
Peak memory 214696 kb
Host smart-8a100e27-aaef-4eb7-a040-66f85e183bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635998091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.635998091
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3003661810
Short name T170
Test name
Test status
Simulation time 81713718 ps
CPU time 2.92 seconds
Started Aug 15 04:41:18 PM PDT 24
Finished Aug 15 04:41:21 PM PDT 24
Peak memory 214380 kb
Host smart-0a2224f5-1830-4744-a7f3-11a7f83c1e99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003661810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3003661810
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3459789421
Short name T175
Test name
Test status
Simulation time 130720595 ps
CPU time 4.88 seconds
Started Aug 15 04:41:19 PM PDT 24
Finished Aug 15 04:41:24 PM PDT 24
Peak memory 206292 kb
Host smart-a77bb26b-6b8e-48b9-80af-26f7133d318d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459789421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3459789421
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3763791408
Short name T171
Test name
Test status
Simulation time 439542780 ps
CPU time 4.8 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 214412 kb
Host smart-63a7263c-6fbd-4124-bd21-a0a2c0edaa36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763791408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3763791408
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2498184550
Short name T47
Test name
Test status
Simulation time 913873597 ps
CPU time 19.66 seconds
Started Aug 15 05:50:42 PM PDT 24
Finished Aug 15 05:51:02 PM PDT 24
Peak memory 232708 kb
Host smart-40061b5a-6ce7-49b2-8e61-b690238694ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498184550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2498184550
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.912327193
Short name T167
Test name
Test status
Simulation time 76454819 ps
CPU time 3.95 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:51 PM PDT 24
Peak memory 218656 kb
Host smart-66a9bb83-fb99-4dcd-bc82-d76971a2cad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912327193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.912327193
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2572339022
Short name T796
Test name
Test status
Simulation time 599332501 ps
CPU time 11.82 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:34 PM PDT 24
Peak memory 207848 kb
Host smart-e56bc6d0-d452-4bc0-8bb6-60ded200822f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572339022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2572339022
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3800993169
Short name T43
Test name
Test status
Simulation time 39086871 ps
CPU time 2.12 seconds
Started Aug 15 05:50:28 PM PDT 24
Finished Aug 15 05:50:30 PM PDT 24
Peak memory 210596 kb
Host smart-6a8f78c6-e0ae-48c6-ad35-9366ec87c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800993169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3800993169
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1376084043
Short name T369
Test name
Test status
Simulation time 27854186 ps
CPU time 2.05 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:50:57 PM PDT 24
Peak memory 214800 kb
Host smart-256e2676-09c4-4493-a31e-16708a03c75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376084043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1376084043
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.399729353
Short name T67
Test name
Test status
Simulation time 80463221 ps
CPU time 2.31 seconds
Started Aug 15 05:50:58 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 207744 kb
Host smart-e9dd3eda-e196-4643-a638-33dba8938049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399729353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.399729353
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3037573379
Short name T123
Test name
Test status
Simulation time 110858505 ps
CPU time 3.29 seconds
Started Aug 15 05:50:53 PM PDT 24
Finished Aug 15 05:50:56 PM PDT 24
Peak memory 209148 kb
Host smart-f3bfcea3-22b7-4f4b-814a-4510833bda68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037573379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3037573379
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1682606550
Short name T7
Test name
Test status
Simulation time 8590276199 ps
CPU time 237.66 seconds
Started Aug 15 05:51:11 PM PDT 24
Finished Aug 15 05:55:08 PM PDT 24
Peak memory 222500 kb
Host smart-b6444c25-55ec-46a4-a338-8094e78ec0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682606550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1682606550
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1266050175
Short name T229
Test name
Test status
Simulation time 113431673 ps
CPU time 5.63 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:05 PM PDT 24
Peak memory 218052 kb
Host smart-068086b9-4e4b-4fdc-b111-f80a8103f2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266050175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1266050175
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2745995533
Short name T115
Test name
Test status
Simulation time 397352716 ps
CPU time 4.42 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 206484 kb
Host smart-1a63a459-1ab9-42b0-a089-0777be8a1b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745995533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2745995533
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3481652988
Short name T60
Test name
Test status
Simulation time 141671047 ps
CPU time 4.62 seconds
Started Aug 15 05:51:02 PM PDT 24
Finished Aug 15 05:51:06 PM PDT 24
Peak memory 214704 kb
Host smart-6e7116d3-5a99-4346-9a91-7e62f78c4b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481652988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3481652988
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2174841594
Short name T317
Test name
Test status
Simulation time 139336240 ps
CPU time 3.1 seconds
Started Aug 15 05:51:00 PM PDT 24
Finished Aug 15 05:51:04 PM PDT 24
Peak memory 215640 kb
Host smart-7b48969b-cc66-43a5-88fb-a517b137d8dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174841594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2174841594
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1374282062
Short name T35
Test name
Test status
Simulation time 55280113 ps
CPU time 3.05 seconds
Started Aug 15 05:51:11 PM PDT 24
Finished Aug 15 05:51:14 PM PDT 24
Peak memory 218872 kb
Host smart-490cc7bd-22f8-4684-a616-e3f797f3992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374282062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1374282062
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.302818044
Short name T349
Test name
Test status
Simulation time 67003042 ps
CPU time 2.77 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:12 PM PDT 24
Peak memory 214768 kb
Host smart-d2af62c8-c2f6-41aa-95f4-8ce206ed7f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302818044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.302818044
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4600730
Short name T237
Test name
Test status
Simulation time 197234999 ps
CPU time 4.84 seconds
Started Aug 15 05:51:21 PM PDT 24
Finished Aug 15 05:51:26 PM PDT 24
Peak memory 210384 kb
Host smart-c06bbcfe-a26b-47bf-8c00-403087662e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4600730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4600730
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2466995857
Short name T92
Test name
Test status
Simulation time 737494734 ps
CPU time 5.3 seconds
Started Aug 15 05:51:07 PM PDT 24
Finished Aug 15 05:51:13 PM PDT 24
Peak memory 209096 kb
Host smart-8bbdcedb-505f-4f71-bbef-a2a4bab33ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466995857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2466995857
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2825111956
Short name T344
Test name
Test status
Simulation time 579358636 ps
CPU time 11.58 seconds
Started Aug 15 05:51:22 PM PDT 24
Finished Aug 15 05:51:34 PM PDT 24
Peak memory 223008 kb
Host smart-dcc2d396-54c2-4a67-82ee-ff9b25f175df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825111956 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2825111956
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2842270691
Short name T366
Test name
Test status
Simulation time 31673566 ps
CPU time 1.54 seconds
Started Aug 15 05:51:17 PM PDT 24
Finished Aug 15 05:51:19 PM PDT 24
Peak memory 207756 kb
Host smart-acb4b080-d061-4979-9420-91d32dfa41ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842270691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2842270691
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1749729150
Short name T372
Test name
Test status
Simulation time 77002913 ps
CPU time 3.49 seconds
Started Aug 15 05:51:28 PM PDT 24
Finished Aug 15 05:51:31 PM PDT 24
Peak memory 209256 kb
Host smart-21f7bf61-69a4-4962-976f-322ca129b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749729150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1749729150
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2890075741
Short name T255
Test name
Test status
Simulation time 247000108 ps
CPU time 4.08 seconds
Started Aug 15 05:51:28 PM PDT 24
Finished Aug 15 05:51:33 PM PDT 24
Peak memory 222740 kb
Host smart-17450509-af2b-415c-aed7-5f0dc0a3157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890075741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2890075741
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3805114082
Short name T327
Test name
Test status
Simulation time 67785143 ps
CPU time 3.04 seconds
Started Aug 15 05:51:23 PM PDT 24
Finished Aug 15 05:51:31 PM PDT 24
Peak memory 219812 kb
Host smart-505a0ccb-1812-4082-9e83-b4f3d1dcaa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805114082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3805114082
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3707294561
Short name T312
Test name
Test status
Simulation time 49876843 ps
CPU time 2.86 seconds
Started Aug 15 05:51:32 PM PDT 24
Finished Aug 15 05:51:35 PM PDT 24
Peak memory 210784 kb
Host smart-48859e67-692c-4b71-a103-e8cad8a011aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707294561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3707294561
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2811183538
Short name T240
Test name
Test status
Simulation time 316942214 ps
CPU time 8.37 seconds
Started Aug 15 05:51:41 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 217632 kb
Host smart-a7c81ee2-bb59-4bb7-aa5d-9e35c248327d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811183538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2811183538
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2513072582
Short name T257
Test name
Test status
Simulation time 40250053 ps
CPU time 3.53 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:52 PM PDT 24
Peak memory 215908 kb
Host smart-9f1293f6-5cff-4734-91c6-87a70a1108c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513072582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2513072582
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3023423917
Short name T295
Test name
Test status
Simulation time 280002177 ps
CPU time 2.84 seconds
Started Aug 15 05:52:14 PM PDT 24
Finished Aug 15 05:52:17 PM PDT 24
Peak memory 214716 kb
Host smart-fdd30421-4c3a-48a0-ad44-6d4c0978aee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023423917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3023423917
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2638700477
Short name T90
Test name
Test status
Simulation time 1020485313 ps
CPU time 6.68 seconds
Started Aug 15 05:52:02 PM PDT 24
Finished Aug 15 05:52:08 PM PDT 24
Peak memory 210004 kb
Host smart-e14420ea-57f8-4325-aa38-7ad119f7d9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638700477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2638700477
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2678233071
Short name T861
Test name
Test status
Simulation time 71908307 ps
CPU time 3.49 seconds
Started Aug 15 05:52:24 PM PDT 24
Finished Aug 15 05:52:28 PM PDT 24
Peak memory 218972 kb
Host smart-35793eb8-a262-46dd-bdfc-3795299d44c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678233071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2678233071
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2817190926
Short name T223
Test name
Test status
Simulation time 2802162086 ps
CPU time 45.28 seconds
Started Aug 15 05:52:32 PM PDT 24
Finished Aug 15 05:53:17 PM PDT 24
Peak memory 214716 kb
Host smart-edcf0099-9b5e-4ddf-a00e-997524324232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817190926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2817190926
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3817395754
Short name T967
Test name
Test status
Simulation time 340777332 ps
CPU time 5.03 seconds
Started Aug 15 04:40:57 PM PDT 24
Finished Aug 15 04:41:02 PM PDT 24
Peak memory 206280 kb
Host smart-a35b6c29-ad16-4db1-b458-7c6746abf755
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817395754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
817395754
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3090743311
Short name T396
Test name
Test status
Simulation time 266030784 ps
CPU time 11.65 seconds
Started Aug 15 04:40:53 PM PDT 24
Finished Aug 15 04:41:04 PM PDT 24
Peak memory 206240 kb
Host smart-bae91041-46f0-4ba2-8d4c-e4d6e8a41ea9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090743311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
090743311
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.281202662
Short name T169
Test name
Test status
Simulation time 70208000 ps
CPU time 1.07 seconds
Started Aug 15 04:40:54 PM PDT 24
Finished Aug 15 04:40:55 PM PDT 24
Peak memory 206116 kb
Host smart-ae2e7784-a95d-4138-a7e9-7f946389ddb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281202662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.281202662
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2599640645
Short name T1012
Test name
Test status
Simulation time 203425160 ps
CPU time 1.58 seconds
Started Aug 15 04:41:02 PM PDT 24
Finished Aug 15 04:41:03 PM PDT 24
Peak memory 214612 kb
Host smart-9d92812a-6895-4601-b7f5-d15c4206b841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599640645 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2599640645
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1703400927
Short name T1015
Test name
Test status
Simulation time 28130280 ps
CPU time 1.52 seconds
Started Aug 15 04:40:58 PM PDT 24
Finished Aug 15 04:40:59 PM PDT 24
Peak memory 206240 kb
Host smart-5147fd55-2920-4a9c-8412-5555ccc38c52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703400927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1703400927
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2990877367
Short name T986
Test name
Test status
Simulation time 17764611 ps
CPU time 0.73 seconds
Started Aug 15 04:40:57 PM PDT 24
Finished Aug 15 04:40:58 PM PDT 24
Peak memory 206016 kb
Host smart-db1bfc7e-da7c-451f-8a51-55ff54afcca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990877367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2990877367
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2772556834
Short name T157
Test name
Test status
Simulation time 102230849 ps
CPU time 2.49 seconds
Started Aug 15 04:41:02 PM PDT 24
Finished Aug 15 04:41:04 PM PDT 24
Peak memory 206252 kb
Host smart-74ff33c4-600c-4ea7-a8f6-f982015d5168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772556834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2772556834
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3784969002
Short name T127
Test name
Test status
Simulation time 170620061 ps
CPU time 2.1 seconds
Started Aug 15 04:40:55 PM PDT 24
Finished Aug 15 04:40:58 PM PDT 24
Peak memory 214904 kb
Host smart-e9b327df-e881-4cec-9771-dfceebb66261
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784969002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3784969002
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1873827843
Short name T964
Test name
Test status
Simulation time 75348272 ps
CPU time 4.32 seconds
Started Aug 15 04:40:57 PM PDT 24
Finished Aug 15 04:41:02 PM PDT 24
Peak memory 214716 kb
Host smart-f44e98cc-5a6e-4897-9183-1d94264b3e89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873827843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1873827843
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2279720192
Short name T977
Test name
Test status
Simulation time 152988398 ps
CPU time 5.12 seconds
Started Aug 15 04:40:54 PM PDT 24
Finished Aug 15 04:40:59 PM PDT 24
Peak memory 214400 kb
Host smart-70fd2756-e4e5-48f0-accd-05351a38536d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279720192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2279720192
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3688526583
Short name T1062
Test name
Test status
Simulation time 66986076 ps
CPU time 4.54 seconds
Started Aug 15 04:41:06 PM PDT 24
Finished Aug 15 04:41:10 PM PDT 24
Peak memory 206332 kb
Host smart-55af29e6-fa3c-4ad0-8da3-827f56c2679b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688526583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
688526583
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1703387734
Short name T917
Test name
Test status
Simulation time 255588692 ps
CPU time 11.5 seconds
Started Aug 15 04:41:00 PM PDT 24
Finished Aug 15 04:41:12 PM PDT 24
Peak memory 206332 kb
Host smart-6f49f95e-6cf9-467d-bc5d-c1396b0f88d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703387734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
703387734
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1440767916
Short name T941
Test name
Test status
Simulation time 17281673 ps
CPU time 1.16 seconds
Started Aug 15 04:41:01 PM PDT 24
Finished Aug 15 04:41:02 PM PDT 24
Peak memory 206232 kb
Host smart-44a82f27-56fb-4d69-8b04-b717defdd059
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440767916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
440767916
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.520254364
Short name T932
Test name
Test status
Simulation time 96594099 ps
CPU time 1.51 seconds
Started Aug 15 04:41:01 PM PDT 24
Finished Aug 15 04:41:03 PM PDT 24
Peak memory 206412 kb
Host smart-d9d780d0-d641-4b5a-b8c4-465c073a908f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520254364 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.520254364
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2300026103
Short name T158
Test name
Test status
Simulation time 37199689 ps
CPU time 0.96 seconds
Started Aug 15 04:41:03 PM PDT 24
Finished Aug 15 04:41:04 PM PDT 24
Peak memory 206092 kb
Host smart-fa960de7-5ef2-48e4-acfd-d29d68d5ca3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300026103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2300026103
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3161768583
Short name T995
Test name
Test status
Simulation time 15718847 ps
CPU time 0.82 seconds
Started Aug 15 04:41:02 PM PDT 24
Finished Aug 15 04:41:03 PM PDT 24
Peak memory 205948 kb
Host smart-c499644b-e169-4805-82f6-671966443b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161768583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3161768583
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.218610807
Short name T933
Test name
Test status
Simulation time 59464355 ps
CPU time 2.61 seconds
Started Aug 15 04:41:03 PM PDT 24
Finished Aug 15 04:41:06 PM PDT 24
Peak memory 206336 kb
Host smart-221311eb-b261-45e6-8da5-6ecf8c721873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218610807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.218610807
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2253286575
Short name T998
Test name
Test status
Simulation time 64637825 ps
CPU time 2.11 seconds
Started Aug 15 04:41:06 PM PDT 24
Finished Aug 15 04:41:08 PM PDT 24
Peak memory 214764 kb
Host smart-185757b5-7694-446e-9f4a-cc98f40be7be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253286575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2253286575
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2373916585
Short name T993
Test name
Test status
Simulation time 97090218 ps
CPU time 1.99 seconds
Started Aug 15 04:41:00 PM PDT 24
Finished Aug 15 04:41:02 PM PDT 24
Peak memory 214444 kb
Host smart-c1f8fb70-95dc-496c-b1da-2700909723d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373916585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2373916585
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4250648427
Short name T1028
Test name
Test status
Simulation time 76692221 ps
CPU time 1.63 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 214568 kb
Host smart-4c169171-483b-4bbc-9c56-e7fb9c5cd839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250648427 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.4250648427
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2284547945
Short name T972
Test name
Test status
Simulation time 33217627 ps
CPU time 1.22 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 206188 kb
Host smart-39400802-cc43-43ce-80fe-2310303a62a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284547945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2284547945
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2729824814
Short name T1067
Test name
Test status
Simulation time 17419427 ps
CPU time 0.77 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:25 PM PDT 24
Peak memory 206044 kb
Host smart-7a2ea9f8-75c3-407e-9fa2-74d758fcd512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729824814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2729824814
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1355227086
Short name T161
Test name
Test status
Simulation time 446576240 ps
CPU time 1.66 seconds
Started Aug 15 04:41:22 PM PDT 24
Finished Aug 15 04:41:24 PM PDT 24
Peak memory 206132 kb
Host smart-7dcf7e73-a114-42fb-859c-29d409e90471
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355227086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1355227086
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.642312605
Short name T957
Test name
Test status
Simulation time 241326800 ps
CPU time 2.39 seconds
Started Aug 15 04:41:23 PM PDT 24
Finished Aug 15 04:41:25 PM PDT 24
Peak memory 214656 kb
Host smart-9fef62a1-4106-41f8-a386-3bacc6d03845
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642312605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.642312605
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2179950435
Short name T1066
Test name
Test status
Simulation time 480052747 ps
CPU time 7.3 seconds
Started Aug 15 04:41:25 PM PDT 24
Finished Aug 15 04:41:32 PM PDT 24
Peak memory 214740 kb
Host smart-431d1fcc-ca66-4c7e-bcae-044c7a8f09bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179950435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2179950435
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2019709806
Short name T1075
Test name
Test status
Simulation time 151757058 ps
CPU time 2.49 seconds
Started Aug 15 04:41:25 PM PDT 24
Finished Aug 15 04:41:27 PM PDT 24
Peak memory 214524 kb
Host smart-c71bd9f1-7413-4cd0-8636-e26971ab4b75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019709806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2019709806
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.4035400192
Short name T184
Test name
Test status
Simulation time 188192125 ps
CPU time 4.03 seconds
Started Aug 15 04:41:26 PM PDT 24
Finished Aug 15 04:41:30 PM PDT 24
Peak memory 214476 kb
Host smart-798421cc-8f9c-4683-9c7c-c8ff512c5344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035400192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.4035400192
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.44239406
Short name T979
Test name
Test status
Simulation time 101790791 ps
CPU time 2.38 seconds
Started Aug 15 04:41:23 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 214488 kb
Host smart-e7f96fb8-bbc0-4b33-95e3-937d2432271d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44239406 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.44239406
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1027513269
Short name T1043
Test name
Test status
Simulation time 12914025 ps
CPU time 1.05 seconds
Started Aug 15 04:41:25 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 206032 kb
Host smart-0b726460-5cf5-453b-a6c7-8b13ce2c8ef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027513269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1027513269
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3973983815
Short name T958
Test name
Test status
Simulation time 20134179 ps
CPU time 0.77 seconds
Started Aug 15 04:41:25 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 206276 kb
Host smart-1d3f38b1-b1c6-48bc-8b2e-353928841ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973983815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3973983815
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.56130306
Short name T1041
Test name
Test status
Simulation time 58875944 ps
CPU time 1.68 seconds
Started Aug 15 04:41:22 PM PDT 24
Finished Aug 15 04:41:24 PM PDT 24
Peak memory 206252 kb
Host smart-f3ff7bfc-2965-49f9-8b00-475cf84d9fae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56130306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sam
e_csr_outstanding.56130306
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3032559143
Short name T132
Test name
Test status
Simulation time 179618232 ps
CPU time 1.69 seconds
Started Aug 15 04:41:25 PM PDT 24
Finished Aug 15 04:41:27 PM PDT 24
Peak memory 214860 kb
Host smart-a0777b20-7d8c-4af1-8f5e-feb6f7673d0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032559143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3032559143
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3023397240
Short name T970
Test name
Test status
Simulation time 235824506 ps
CPU time 8.33 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:32 PM PDT 24
Peak memory 214712 kb
Host smart-86bbe24a-1f12-4105-9bea-227c2fcf8cac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023397240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3023397240
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3257724322
Short name T1008
Test name
Test status
Simulation time 654584856 ps
CPU time 5.81 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:30 PM PDT 24
Peak memory 214540 kb
Host smart-eb6df84b-0f83-4115-ac60-2b06b8c42b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257724322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3257724322
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2198251687
Short name T186
Test name
Test status
Simulation time 169909422 ps
CPU time 5.21 seconds
Started Aug 15 04:41:26 PM PDT 24
Finished Aug 15 04:41:32 PM PDT 24
Peak memory 214456 kb
Host smart-eb892ad6-f84e-4d75-874e-822476f4a14f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198251687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2198251687
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.624153946
Short name T1072
Test name
Test status
Simulation time 40238431 ps
CPU time 1.53 seconds
Started Aug 15 04:41:26 PM PDT 24
Finished Aug 15 04:41:28 PM PDT 24
Peak memory 214612 kb
Host smart-c919d3d0-d1ba-48db-ad5f-4c2c1435883b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624153946 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.624153946
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2918926890
Short name T919
Test name
Test status
Simulation time 188576893 ps
CPU time 1.29 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 206092 kb
Host smart-40b6c7d6-85d4-4a6c-a1cf-cc46f142d0f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918926890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2918926890
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2534625221
Short name T923
Test name
Test status
Simulation time 34270182 ps
CPU time 0.71 seconds
Started Aug 15 04:41:23 PM PDT 24
Finished Aug 15 04:41:24 PM PDT 24
Peak memory 205964 kb
Host smart-c8c06a2d-1afb-4d8d-8993-5a91fb71d5cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534625221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2534625221
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3812632105
Short name T937
Test name
Test status
Simulation time 118751018 ps
CPU time 2.26 seconds
Started Aug 15 04:41:23 PM PDT 24
Finished Aug 15 04:41:25 PM PDT 24
Peak memory 206216 kb
Host smart-c34e4e90-90a0-4f03-948e-84a5c2159158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812632105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3812632105
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4231698405
Short name T935
Test name
Test status
Simulation time 477694655 ps
CPU time 2.62 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:27 PM PDT 24
Peak memory 214860 kb
Host smart-06d6dca6-2ad2-413a-8d9b-8f27e669b201
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231698405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.4231698405
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3872931593
Short name T160
Test name
Test status
Simulation time 288998566 ps
CPU time 3.58 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:28 PM PDT 24
Peak memory 214808 kb
Host smart-1c805472-8af8-4ec3-9c15-17e94e30e2c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872931593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3872931593
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3451855977
Short name T1044
Test name
Test status
Simulation time 106481146 ps
CPU time 3.79 seconds
Started Aug 15 04:41:23 PM PDT 24
Finished Aug 15 04:41:27 PM PDT 24
Peak memory 214548 kb
Host smart-b915c01c-54cd-4437-89ec-da1913b4b287
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451855977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3451855977
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3906110638
Short name T959
Test name
Test status
Simulation time 128707579 ps
CPU time 1.56 seconds
Started Aug 15 04:41:23 PM PDT 24
Finished Aug 15 04:41:24 PM PDT 24
Peak memory 214512 kb
Host smart-f5f2fa44-2e69-4c3e-91aa-cbbf376d818a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906110638 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3906110638
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3690442595
Short name T1034
Test name
Test status
Simulation time 43132307 ps
CPU time 0.9 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:25 PM PDT 24
Peak memory 206028 kb
Host smart-dd2eaf06-47b7-4728-9956-e0a7c048678d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690442595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3690442595
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2999075527
Short name T1065
Test name
Test status
Simulation time 43144227 ps
CPU time 0.83 seconds
Started Aug 15 04:41:27 PM PDT 24
Finished Aug 15 04:41:28 PM PDT 24
Peak memory 206064 kb
Host smart-cb18ecb3-6492-4fc7-8018-a563250ce311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999075527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2999075527
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2680960072
Short name T1077
Test name
Test status
Simulation time 256235974 ps
CPU time 2.21 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 206292 kb
Host smart-a5079773-f849-4590-b255-e2b397a6ac01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680960072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2680960072
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3338741758
Short name T1001
Test name
Test status
Simulation time 134156983 ps
CPU time 1.71 seconds
Started Aug 15 04:41:23 PM PDT 24
Finished Aug 15 04:41:25 PM PDT 24
Peak memory 214784 kb
Host smart-eafaea04-85d6-435b-a1fb-b9d0474422b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338741758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3338741758
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3706352795
Short name T1022
Test name
Test status
Simulation time 838681186 ps
CPU time 8.59 seconds
Started Aug 15 04:41:28 PM PDT 24
Finished Aug 15 04:41:36 PM PDT 24
Peak memory 223024 kb
Host smart-adad984b-bf9f-4643-8594-26c41d077b5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706352795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3706352795
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2197477091
Short name T1026
Test name
Test status
Simulation time 120379704 ps
CPU time 4.37 seconds
Started Aug 15 04:41:27 PM PDT 24
Finished Aug 15 04:41:31 PM PDT 24
Peak memory 214468 kb
Host smart-fe7861fa-d69c-41ac-9ff4-5194cfbb2aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197477091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2197477091
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.635500085
Short name T978
Test name
Test status
Simulation time 26272597 ps
CPU time 1.42 seconds
Started Aug 15 04:41:27 PM PDT 24
Finished Aug 15 04:41:28 PM PDT 24
Peak memory 206460 kb
Host smart-c217579a-2791-407a-8cdf-fe018866c45a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635500085 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.635500085
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1471982496
Short name T990
Test name
Test status
Simulation time 56193396 ps
CPU time 1.03 seconds
Started Aug 15 04:41:28 PM PDT 24
Finished Aug 15 04:41:29 PM PDT 24
Peak memory 206312 kb
Host smart-aed7c22e-128d-4615-bf14-f3701674aac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471982496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1471982496
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.896342481
Short name T962
Test name
Test status
Simulation time 35912053 ps
CPU time 0.76 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:25 PM PDT 24
Peak memory 205852 kb
Host smart-24da7dde-7e8b-4ada-b4e2-f91c24d90fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896342481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.896342481
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1775444708
Short name T1017
Test name
Test status
Simulation time 342367051 ps
CPU time 2.38 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 206388 kb
Host smart-5dc5aa3c-7609-4153-9b80-6a3681ac26cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775444708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1775444708
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.686289142
Short name T1042
Test name
Test status
Simulation time 81582913 ps
CPU time 1.72 seconds
Started Aug 15 04:41:23 PM PDT 24
Finished Aug 15 04:41:25 PM PDT 24
Peak memory 214788 kb
Host smart-48f78c62-42f0-422c-aa20-196db479bf87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686289142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.686289142
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3775103896
Short name T951
Test name
Test status
Simulation time 521150353 ps
CPU time 11.19 seconds
Started Aug 15 04:41:22 PM PDT 24
Finished Aug 15 04:41:34 PM PDT 24
Peak memory 214848 kb
Host smart-6b4e5168-6f19-4a05-98f6-b5104f65fc68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775103896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3775103896
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.190350295
Short name T929
Test name
Test status
Simulation time 69435290 ps
CPU time 1.84 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 214580 kb
Host smart-7550d033-f7de-40d9-8ffb-77a9b19b446f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190350295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.190350295
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2987956802
Short name T1000
Test name
Test status
Simulation time 99193213 ps
CPU time 5.13 seconds
Started Aug 15 04:41:26 PM PDT 24
Finished Aug 15 04:41:31 PM PDT 24
Peak memory 214412 kb
Host smart-323818b7-ff74-4999-9348-8ba89b611fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987956802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2987956802
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3168998882
Short name T950
Test name
Test status
Simulation time 17473816 ps
CPU time 1.35 seconds
Started Aug 15 04:41:33 PM PDT 24
Finished Aug 15 04:41:35 PM PDT 24
Peak memory 214576 kb
Host smart-0bde8105-4c4a-4699-8e3d-3f69bfd5cee0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168998882 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3168998882
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1116256264
Short name T1054
Test name
Test status
Simulation time 53565537 ps
CPU time 1.13 seconds
Started Aug 15 04:41:30 PM PDT 24
Finished Aug 15 04:41:32 PM PDT 24
Peak memory 206300 kb
Host smart-1b169f69-cc6c-409d-a0fd-ffb53a5441c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116256264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1116256264
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.568638063
Short name T969
Test name
Test status
Simulation time 25341595 ps
CPU time 0.78 seconds
Started Aug 15 04:41:30 PM PDT 24
Finished Aug 15 04:41:31 PM PDT 24
Peak memory 205952 kb
Host smart-7952b6cb-6bae-4a2d-9c4d-9a2f0d2fdaa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568638063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.568638063
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.370196868
Short name T163
Test name
Test status
Simulation time 33288657 ps
CPU time 2 seconds
Started Aug 15 04:41:30 PM PDT 24
Finished Aug 15 04:41:32 PM PDT 24
Peak memory 206340 kb
Host smart-f47cf878-129c-46df-b913-413cba77000d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370196868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.370196868
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1252812147
Short name T128
Test name
Test status
Simulation time 221647807 ps
CPU time 1.67 seconds
Started Aug 15 04:41:27 PM PDT 24
Finished Aug 15 04:41:29 PM PDT 24
Peak memory 214756 kb
Host smart-a2d336e5-7c80-42a3-9f58-e387e97c432c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252812147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1252812147
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2523490245
Short name T1013
Test name
Test status
Simulation time 480274247 ps
CPU time 3.34 seconds
Started Aug 15 04:41:24 PM PDT 24
Finished Aug 15 04:41:27 PM PDT 24
Peak memory 214752 kb
Host smart-3e97797f-fac7-426d-868a-c5a612682006
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523490245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2523490245
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3295748379
Short name T947
Test name
Test status
Simulation time 49330628 ps
CPU time 1.61 seconds
Started Aug 15 04:41:25 PM PDT 24
Finished Aug 15 04:41:27 PM PDT 24
Peak memory 214484 kb
Host smart-6e7d8ea0-53a0-4b4a-a48b-04e5c4be538f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295748379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3295748379
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1719286085
Short name T1070
Test name
Test status
Simulation time 28180762 ps
CPU time 1.57 seconds
Started Aug 15 04:41:33 PM PDT 24
Finished Aug 15 04:41:35 PM PDT 24
Peak memory 214480 kb
Host smart-a869e464-3cc0-41a5-a8e4-2a865d1efc16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719286085 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1719286085
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3709148316
Short name T943
Test name
Test status
Simulation time 21938687 ps
CPU time 0.94 seconds
Started Aug 15 04:41:30 PM PDT 24
Finished Aug 15 04:41:31 PM PDT 24
Peak memory 205972 kb
Host smart-790e3f29-e923-4192-936c-5d39e1ef52fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709148316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3709148316
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3194152757
Short name T1055
Test name
Test status
Simulation time 43995318 ps
CPU time 0.87 seconds
Started Aug 15 04:41:30 PM PDT 24
Finished Aug 15 04:41:31 PM PDT 24
Peak memory 205976 kb
Host smart-ab731795-999e-42c6-b878-ab817635bd76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194152757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3194152757
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1401587615
Short name T1040
Test name
Test status
Simulation time 241964885 ps
CPU time 2.24 seconds
Started Aug 15 04:41:29 PM PDT 24
Finished Aug 15 04:41:32 PM PDT 24
Peak memory 206232 kb
Host smart-08489910-fe21-493e-8d8e-fcb1823ce032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401587615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1401587615
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3124646569
Short name T1023
Test name
Test status
Simulation time 146753678 ps
CPU time 2.46 seconds
Started Aug 15 04:41:29 PM PDT 24
Finished Aug 15 04:41:32 PM PDT 24
Peak memory 214740 kb
Host smart-ceb2ba11-2133-4885-8d2e-1ef4db0bcfa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124646569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3124646569
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1342525352
Short name T1010
Test name
Test status
Simulation time 870386832 ps
CPU time 4.84 seconds
Started Aug 15 04:41:33 PM PDT 24
Finished Aug 15 04:41:38 PM PDT 24
Peak memory 214908 kb
Host smart-70dbabf2-c66e-44a3-b060-9217f34d35c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342525352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1342525352
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2253331242
Short name T1036
Test name
Test status
Simulation time 51991366 ps
CPU time 2.33 seconds
Started Aug 15 04:41:32 PM PDT 24
Finished Aug 15 04:41:35 PM PDT 24
Peak memory 214356 kb
Host smart-32840587-66ff-49cf-a41a-d861ea635ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253331242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2253331242
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2568046916
Short name T176
Test name
Test status
Simulation time 202029375 ps
CPU time 5.41 seconds
Started Aug 15 04:41:31 PM PDT 24
Finished Aug 15 04:41:37 PM PDT 24
Peak memory 214464 kb
Host smart-7f2eba40-1f4d-422f-9b31-fd7a53ea1e02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568046916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2568046916
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3072659047
Short name T1046
Test name
Test status
Simulation time 55594538 ps
CPU time 2.16 seconds
Started Aug 15 04:41:31 PM PDT 24
Finished Aug 15 04:41:33 PM PDT 24
Peak memory 217428 kb
Host smart-bc41ca8b-2d3b-4cde-9842-5ad03922b85d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072659047 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3072659047
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4114202278
Short name T989
Test name
Test status
Simulation time 95770724 ps
CPU time 1.54 seconds
Started Aug 15 04:41:31 PM PDT 24
Finished Aug 15 04:41:32 PM PDT 24
Peak memory 206220 kb
Host smart-5fca23bd-4a1b-4a36-854e-6f3fd656172d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114202278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4114202278
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.810400484
Short name T954
Test name
Test status
Simulation time 19013658 ps
CPU time 0.71 seconds
Started Aug 15 04:41:30 PM PDT 24
Finished Aug 15 04:41:31 PM PDT 24
Peak memory 206076 kb
Host smart-19e741c7-1707-43cf-aeb0-d76561511a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810400484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.810400484
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.287878314
Short name T1069
Test name
Test status
Simulation time 48826816 ps
CPU time 1.53 seconds
Started Aug 15 04:41:31 PM PDT 24
Finished Aug 15 04:41:33 PM PDT 24
Peak memory 206248 kb
Host smart-963559a2-c091-48b8-a879-3990a383eeb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287878314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.287878314
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2189940464
Short name T1059
Test name
Test status
Simulation time 548045600 ps
CPU time 4.13 seconds
Started Aug 15 04:41:31 PM PDT 24
Finished Aug 15 04:41:35 PM PDT 24
Peak memory 214860 kb
Host smart-1569d63a-9bdc-4172-bb00-0189aab0b304
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189940464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2189940464
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4131026527
Short name T1073
Test name
Test status
Simulation time 357868482 ps
CPU time 7.69 seconds
Started Aug 15 04:41:32 PM PDT 24
Finished Aug 15 04:41:39 PM PDT 24
Peak memory 215052 kb
Host smart-b6eccfb0-a849-4c4c-8e5b-738c7bf0f75b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131026527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.4131026527
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4244453057
Short name T1020
Test name
Test status
Simulation time 145028770 ps
CPU time 3.14 seconds
Started Aug 15 04:41:31 PM PDT 24
Finished Aug 15 04:41:34 PM PDT 24
Peak memory 214544 kb
Host smart-309419d0-4f8d-40ef-8b8a-4f92f75217dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244453057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4244453057
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2524026613
Short name T1002
Test name
Test status
Simulation time 59886158 ps
CPU time 1.51 seconds
Started Aug 15 04:41:43 PM PDT 24
Finished Aug 15 04:41:44 PM PDT 24
Peak memory 214436 kb
Host smart-8b544338-eff9-4364-a6a9-debf6a8f5199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524026613 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2524026613
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1996991644
Short name T162
Test name
Test status
Simulation time 8754159 ps
CPU time 1.01 seconds
Started Aug 15 04:41:42 PM PDT 24
Finished Aug 15 04:41:44 PM PDT 24
Peak memory 206048 kb
Host smart-2bfbd3ac-c90c-4aba-bd17-9ddddc6ab325
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996991644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1996991644
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.419555330
Short name T966
Test name
Test status
Simulation time 13973195 ps
CPU time 0.86 seconds
Started Aug 15 04:41:40 PM PDT 24
Finished Aug 15 04:41:41 PM PDT 24
Peak memory 206088 kb
Host smart-caab0961-53d8-4a0c-b4be-6819c91c9300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419555330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.419555330
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.914939174
Short name T1029
Test name
Test status
Simulation time 156509464 ps
CPU time 4.4 seconds
Started Aug 15 04:41:39 PM PDT 24
Finished Aug 15 04:41:44 PM PDT 24
Peak memory 206192 kb
Host smart-fac680a5-07d5-4403-8622-304a8ee818d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914939174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.914939174
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3817086316
Short name T1074
Test name
Test status
Simulation time 91560142 ps
CPU time 3.62 seconds
Started Aug 15 04:41:33 PM PDT 24
Finished Aug 15 04:41:37 PM PDT 24
Peak memory 214760 kb
Host smart-2003dea6-3320-4a7a-9566-3e51fedbf778
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817086316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3817086316
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3027290272
Short name T992
Test name
Test status
Simulation time 317140107 ps
CPU time 4.76 seconds
Started Aug 15 04:41:45 PM PDT 24
Finished Aug 15 04:41:50 PM PDT 24
Peak memory 220888 kb
Host smart-a61eee45-f298-4cbd-894e-69159a6bbd47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027290272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3027290272
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.567870588
Short name T1024
Test name
Test status
Simulation time 61787072 ps
CPU time 2.12 seconds
Started Aug 15 04:41:39 PM PDT 24
Finished Aug 15 04:41:42 PM PDT 24
Peak memory 214576 kb
Host smart-ea0ce96e-69a1-45b1-9edc-a66a48eb512d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567870588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.567870588
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3868268868
Short name T189
Test name
Test status
Simulation time 563741396 ps
CPU time 6.3 seconds
Started Aug 15 04:41:42 PM PDT 24
Finished Aug 15 04:41:48 PM PDT 24
Peak memory 214384 kb
Host smart-03737188-2490-4f1a-93af-07b91797b149
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868268868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3868268868
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3445008070
Short name T1038
Test name
Test status
Simulation time 216435094 ps
CPU time 1.66 seconds
Started Aug 15 04:41:45 PM PDT 24
Finished Aug 15 04:41:47 PM PDT 24
Peak memory 214524 kb
Host smart-62a1c650-3de0-446a-8cca-b95602de58e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445008070 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3445008070
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3611932982
Short name T1050
Test name
Test status
Simulation time 166806441 ps
CPU time 1.11 seconds
Started Aug 15 04:41:44 PM PDT 24
Finished Aug 15 04:41:45 PM PDT 24
Peak memory 206248 kb
Host smart-ea8ab97f-c526-42ed-a419-8b512a5e352f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611932982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3611932982
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1700829288
Short name T945
Test name
Test status
Simulation time 14386508 ps
CPU time 0.87 seconds
Started Aug 15 04:41:41 PM PDT 24
Finished Aug 15 04:41:42 PM PDT 24
Peak memory 206148 kb
Host smart-63d22db0-c45a-4de4-8443-d5937ab874c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700829288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1700829288
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.657200447
Short name T994
Test name
Test status
Simulation time 94718236 ps
CPU time 1.7 seconds
Started Aug 15 04:41:38 PM PDT 24
Finished Aug 15 04:41:40 PM PDT 24
Peak memory 206192 kb
Host smart-690e7d1a-8846-472f-96b6-0d25bf9c8b26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657200447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.657200447
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.690576204
Short name T129
Test name
Test status
Simulation time 131752935 ps
CPU time 1.81 seconds
Started Aug 15 04:41:38 PM PDT 24
Finished Aug 15 04:41:40 PM PDT 24
Peak memory 214780 kb
Host smart-cc7869a0-ed05-4fb4-a1e1-41741d21cd1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690576204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.690576204
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.14821072
Short name T125
Test name
Test status
Simulation time 91576586 ps
CPU time 4.65 seconds
Started Aug 15 04:41:38 PM PDT 24
Finished Aug 15 04:41:43 PM PDT 24
Peak memory 214856 kb
Host smart-5ab41a34-06b8-45ec-928d-0492f27a04dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14821072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k
eymgr_shadow_reg_errors_with_csr_rw.14821072
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3908791299
Short name T930
Test name
Test status
Simulation time 96633320 ps
CPU time 1.55 seconds
Started Aug 15 04:41:43 PM PDT 24
Finished Aug 15 04:41:44 PM PDT 24
Peak memory 214544 kb
Host smart-421b2170-9a38-48fb-94a6-8120aa37fbac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908791299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3908791299
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4101077880
Short name T973
Test name
Test status
Simulation time 522126613 ps
CPU time 7.59 seconds
Started Aug 15 04:41:44 PM PDT 24
Finished Aug 15 04:41:52 PM PDT 24
Peak memory 217008 kb
Host smart-ea8f64c8-636e-4b27-a358-bda9aa505d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101077880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.4101077880
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1104021052
Short name T924
Test name
Test status
Simulation time 504079307 ps
CPU time 7.48 seconds
Started Aug 15 04:41:08 PM PDT 24
Finished Aug 15 04:41:16 PM PDT 24
Peak memory 206204 kb
Host smart-05bdcd5f-b86b-4726-b345-04a213968736
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104021052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
104021052
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.4278736931
Short name T1056
Test name
Test status
Simulation time 1041801074 ps
CPU time 12.15 seconds
Started Aug 15 04:41:06 PM PDT 24
Finished Aug 15 04:41:18 PM PDT 24
Peak memory 206140 kb
Host smart-56835dae-c864-4a62-bf3d-c796afe11295
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278736931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.4
278736931
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.317587248
Short name T914
Test name
Test status
Simulation time 105695029 ps
CPU time 1.41 seconds
Started Aug 15 04:41:00 PM PDT 24
Finished Aug 15 04:41:01 PM PDT 24
Peak memory 206368 kb
Host smart-63891a54-12c2-4803-8364-cb808ab7ff8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317587248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.317587248
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3900975064
Short name T981
Test name
Test status
Simulation time 92977080 ps
CPU time 1.31 seconds
Started Aug 15 04:41:08 PM PDT 24
Finished Aug 15 04:41:09 PM PDT 24
Peak memory 214476 kb
Host smart-30701121-e189-4a03-ab28-8826ee1fffb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900975064 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3900975064
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1147500439
Short name T159
Test name
Test status
Simulation time 27189405 ps
CPU time 1.33 seconds
Started Aug 15 04:41:03 PM PDT 24
Finished Aug 15 04:41:04 PM PDT 24
Peak memory 206248 kb
Host smart-a84ba5eb-e886-47ec-8246-6106d7919026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147500439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1147500439
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2566794987
Short name T916
Test name
Test status
Simulation time 30715826 ps
CPU time 0.74 seconds
Started Aug 15 04:41:06 PM PDT 24
Finished Aug 15 04:41:06 PM PDT 24
Peak memory 206044 kb
Host smart-1401d953-cdb4-44f7-8b9b-a504358cdd5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566794987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2566794987
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3088238705
Short name T934
Test name
Test status
Simulation time 208740053 ps
CPU time 2.13 seconds
Started Aug 15 04:41:07 PM PDT 24
Finished Aug 15 04:41:09 PM PDT 24
Peak memory 206216 kb
Host smart-524cd9dc-b47f-4b48-a599-7270f0566bac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088238705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3088238705
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.775621467
Short name T1011
Test name
Test status
Simulation time 157444345 ps
CPU time 3.95 seconds
Started Aug 15 04:41:00 PM PDT 24
Finished Aug 15 04:41:04 PM PDT 24
Peak memory 214808 kb
Host smart-852bc24d-8ac3-4235-a8b5-f75c25c59833
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775621467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.775621467
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1998630775
Short name T1063
Test name
Test status
Simulation time 187869471 ps
CPU time 1.92 seconds
Started Aug 15 04:41:02 PM PDT 24
Finished Aug 15 04:41:04 PM PDT 24
Peak memory 214576 kb
Host smart-f0df071d-36de-47bc-b2c1-9814d3d11d88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998630775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1998630775
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1401229305
Short name T1049
Test name
Test status
Simulation time 57677100 ps
CPU time 2.81 seconds
Started Aug 15 04:41:00 PM PDT 24
Finished Aug 15 04:41:03 PM PDT 24
Peak memory 214356 kb
Host smart-e280d0d0-f521-41a0-b1e5-af757860027b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401229305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1401229305
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2555524989
Short name T939
Test name
Test status
Simulation time 35333049 ps
CPU time 0.85 seconds
Started Aug 15 04:41:44 PM PDT 24
Finished Aug 15 04:41:45 PM PDT 24
Peak memory 206056 kb
Host smart-9f953e80-8162-46d3-bb75-e18c1f731496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555524989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2555524989
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1126640974
Short name T982
Test name
Test status
Simulation time 24345833 ps
CPU time 0.71 seconds
Started Aug 15 04:41:40 PM PDT 24
Finished Aug 15 04:41:41 PM PDT 24
Peak memory 205968 kb
Host smart-4aca94fc-8897-428f-a7aa-9e59d7e99925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126640974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1126640974
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2722772406
Short name T1018
Test name
Test status
Simulation time 11478354 ps
CPU time 0.84 seconds
Started Aug 15 04:41:41 PM PDT 24
Finished Aug 15 04:41:42 PM PDT 24
Peak memory 205988 kb
Host smart-d9feb833-16fd-4dec-b2f1-9ff17fd1e249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722772406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2722772406
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2992633553
Short name T928
Test name
Test status
Simulation time 16279915 ps
CPU time 0.84 seconds
Started Aug 15 04:41:38 PM PDT 24
Finished Aug 15 04:41:39 PM PDT 24
Peak memory 205972 kb
Host smart-601c11e9-d280-4960-af2f-30c76c7dddbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992633553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2992633553
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4144187203
Short name T1027
Test name
Test status
Simulation time 13770791 ps
CPU time 0.74 seconds
Started Aug 15 04:41:43 PM PDT 24
Finished Aug 15 04:41:44 PM PDT 24
Peak memory 205912 kb
Host smart-23a3f8de-44d5-42a4-8868-e5847fc11e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144187203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.4144187203
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2127196849
Short name T936
Test name
Test status
Simulation time 40576956 ps
CPU time 0.8 seconds
Started Aug 15 04:41:38 PM PDT 24
Finished Aug 15 04:41:39 PM PDT 24
Peak memory 205992 kb
Host smart-2a9cd0f5-06f7-47bb-9f8c-21b008700c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127196849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2127196849
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1331949078
Short name T1039
Test name
Test status
Simulation time 28712486 ps
CPU time 0.71 seconds
Started Aug 15 04:41:45 PM PDT 24
Finished Aug 15 04:41:46 PM PDT 24
Peak memory 205980 kb
Host smart-d379958c-e5ad-4982-b2a3-d0e8b81af057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331949078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1331949078
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1412746693
Short name T915
Test name
Test status
Simulation time 11013672 ps
CPU time 0.82 seconds
Started Aug 15 04:41:49 PM PDT 24
Finished Aug 15 04:41:50 PM PDT 24
Peak memory 206000 kb
Host smart-66b52913-835b-4e66-855a-1f1f827c1489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412746693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1412746693
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3892048773
Short name T955
Test name
Test status
Simulation time 36421090 ps
CPU time 0.81 seconds
Started Aug 15 04:41:38 PM PDT 24
Finished Aug 15 04:41:39 PM PDT 24
Peak memory 205960 kb
Host smart-d8f42a6c-62fd-4a41-8d7b-ddcedf1e5da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892048773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3892048773
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1670927884
Short name T913
Test name
Test status
Simulation time 9040305 ps
CPU time 0.73 seconds
Started Aug 15 04:41:39 PM PDT 24
Finished Aug 15 04:41:39 PM PDT 24
Peak memory 205964 kb
Host smart-1f79b638-0c2a-4632-a343-23a6f68e7c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670927884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1670927884
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.232336293
Short name T1037
Test name
Test status
Simulation time 986284888 ps
CPU time 9.06 seconds
Started Aug 15 04:41:08 PM PDT 24
Finished Aug 15 04:41:17 PM PDT 24
Peak memory 206284 kb
Host smart-91b474e3-343b-44b4-86c5-4b3cc84a7af6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232336293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.232336293
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.4022965665
Short name T1006
Test name
Test status
Simulation time 133351877 ps
CPU time 7.83 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:17 PM PDT 24
Peak memory 206192 kb
Host smart-d75a19b1-58b0-41d3-b914-60b5b5540eae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022965665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.4
022965665
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2385191397
Short name T1052
Test name
Test status
Simulation time 53390370 ps
CPU time 1.07 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:11 PM PDT 24
Peak memory 206296 kb
Host smart-520229dd-d796-4f5a-997c-0896d155fdfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385191397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
385191397
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2119185449
Short name T1005
Test name
Test status
Simulation time 26691761 ps
CPU time 1.79 seconds
Started Aug 15 04:41:08 PM PDT 24
Finished Aug 15 04:41:10 PM PDT 24
Peak memory 214572 kb
Host smart-acc4466a-b27e-4ccc-a30f-922ff8e13488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119185449 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2119185449
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1180292260
Short name T983
Test name
Test status
Simulation time 34782617 ps
CPU time 1.21 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:11 PM PDT 24
Peak memory 206116 kb
Host smart-7c841e5b-2724-47c8-a1ee-b6cb3d99ae0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180292260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1180292260
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1172475734
Short name T946
Test name
Test status
Simulation time 9796608 ps
CPU time 0.72 seconds
Started Aug 15 04:41:08 PM PDT 24
Finished Aug 15 04:41:09 PM PDT 24
Peak memory 206068 kb
Host smart-5da87866-24a0-47f2-b0dd-d872826cebf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172475734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1172475734
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1430257984
Short name T1051
Test name
Test status
Simulation time 121906765 ps
CPU time 2.34 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:12 PM PDT 24
Peak memory 206240 kb
Host smart-54d4c3a9-4d78-4b94-a1a7-0db3b332c15c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430257984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1430257984
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2139942582
Short name T976
Test name
Test status
Simulation time 99635070 ps
CPU time 1.81 seconds
Started Aug 15 04:41:07 PM PDT 24
Finished Aug 15 04:41:09 PM PDT 24
Peak memory 214728 kb
Host smart-6c2148d4-2b40-40d0-816d-122a34f9b9dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139942582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2139942582
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2744716869
Short name T1031
Test name
Test status
Simulation time 91735377 ps
CPU time 3.5 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:12 PM PDT 24
Peak memory 214856 kb
Host smart-67ee7f1f-3c53-4953-96b4-324d3d1e26af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744716869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2744716869
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.40834803
Short name T1003
Test name
Test status
Simulation time 19358599 ps
CPU time 1.52 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:11 PM PDT 24
Peak memory 214568 kb
Host smart-a6e5a16d-e532-4e16-bcc1-0ecdde0e0d28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40834803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.40834803
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4182203728
Short name T187
Test name
Test status
Simulation time 138960618 ps
CPU time 3.05 seconds
Started Aug 15 04:41:10 PM PDT 24
Finished Aug 15 04:41:13 PM PDT 24
Peak memory 214512 kb
Host smart-efe5a28c-5e3e-4b25-a889-ca5880adf3ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182203728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4182203728
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3074623743
Short name T944
Test name
Test status
Simulation time 23653083 ps
CPU time 0.76 seconds
Started Aug 15 04:41:39 PM PDT 24
Finished Aug 15 04:41:40 PM PDT 24
Peak memory 205928 kb
Host smart-3a1f5b69-6a12-49b4-8dc2-36666f25dd07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074623743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3074623743
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.387329402
Short name T952
Test name
Test status
Simulation time 41396347 ps
CPU time 0.84 seconds
Started Aug 15 04:41:39 PM PDT 24
Finished Aug 15 04:41:40 PM PDT 24
Peak memory 206004 kb
Host smart-836cbf8c-c782-4c24-9cdf-b9b60974567c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387329402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.387329402
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1378708220
Short name T963
Test name
Test status
Simulation time 23671584 ps
CPU time 0.91 seconds
Started Aug 15 04:41:45 PM PDT 24
Finished Aug 15 04:41:46 PM PDT 24
Peak memory 206004 kb
Host smart-456615d1-a0c6-4d59-b96b-7d565addf95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378708220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1378708220
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1183402218
Short name T922
Test name
Test status
Simulation time 24803255 ps
CPU time 0.83 seconds
Started Aug 15 04:41:42 PM PDT 24
Finished Aug 15 04:41:43 PM PDT 24
Peak memory 206088 kb
Host smart-b8f63744-a8a7-4a90-93c0-629120e4a6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183402218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1183402218
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.564932793
Short name T938
Test name
Test status
Simulation time 11875326 ps
CPU time 0.81 seconds
Started Aug 15 04:41:44 PM PDT 24
Finished Aug 15 04:41:44 PM PDT 24
Peak memory 205916 kb
Host smart-7106851b-e018-4546-b801-03a3f5ab3c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564932793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.564932793
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1860266454
Short name T987
Test name
Test status
Simulation time 12956129 ps
CPU time 0.85 seconds
Started Aug 15 04:41:39 PM PDT 24
Finished Aug 15 04:41:40 PM PDT 24
Peak memory 205992 kb
Host smart-e3fcbff3-bb18-44ce-8465-e804f71c1233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860266454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1860266454
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2905560429
Short name T1033
Test name
Test status
Simulation time 12053699 ps
CPU time 0.71 seconds
Started Aug 15 04:41:42 PM PDT 24
Finished Aug 15 04:41:43 PM PDT 24
Peak memory 206028 kb
Host smart-ed20c261-76c6-4cd6-9f37-6b26daf50298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905560429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2905560429
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3753115613
Short name T942
Test name
Test status
Simulation time 43149618 ps
CPU time 0.71 seconds
Started Aug 15 04:41:42 PM PDT 24
Finished Aug 15 04:41:43 PM PDT 24
Peak memory 205988 kb
Host smart-c1a27660-c1ac-4a89-9744-2ba9d7c0e46e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753115613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3753115613
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4283771426
Short name T971
Test name
Test status
Simulation time 20197892 ps
CPU time 0.85 seconds
Started Aug 15 04:41:39 PM PDT 24
Finished Aug 15 04:41:40 PM PDT 24
Peak memory 206076 kb
Host smart-dddf6748-8199-459e-af34-3e3de9cb97b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283771426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4283771426
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.779454996
Short name T920
Test name
Test status
Simulation time 12726950 ps
CPU time 0.79 seconds
Started Aug 15 04:41:40 PM PDT 24
Finished Aug 15 04:41:41 PM PDT 24
Peak memory 205964 kb
Host smart-3c18a8c9-234f-4a4d-bbd8-bdfc53d83c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779454996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.779454996
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2435780509
Short name T1004
Test name
Test status
Simulation time 143539000 ps
CPU time 4.59 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:13 PM PDT 24
Peak memory 206316 kb
Host smart-7a767b0a-092e-4e8b-a3ed-3e975568061c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435780509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
435780509
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2435338292
Short name T1014
Test name
Test status
Simulation time 1314869690 ps
CPU time 15.39 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:25 PM PDT 24
Peak memory 206260 kb
Host smart-1d532181-b636-4769-af35-381940251f1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435338292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
435338292
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1184930751
Short name T988
Test name
Test status
Simulation time 107437324 ps
CPU time 1.41 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:10 PM PDT 24
Peak memory 206156 kb
Host smart-7a132982-cb77-48de-a776-d5bf125d3340
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184930751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
184930751
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1132453021
Short name T1032
Test name
Test status
Simulation time 347135551 ps
CPU time 1.61 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:11 PM PDT 24
Peak memory 214540 kb
Host smart-12a839c3-097c-486f-b1e3-e81938a042ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132453021 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1132453021
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1533370768
Short name T1068
Test name
Test status
Simulation time 64208244 ps
CPU time 0.95 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:11 PM PDT 24
Peak memory 206028 kb
Host smart-b7a9d983-d1bf-4d28-abf1-72728e10535a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533370768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1533370768
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3980346311
Short name T1045
Test name
Test status
Simulation time 9539022 ps
CPU time 0.68 seconds
Started Aug 15 04:41:08 PM PDT 24
Finished Aug 15 04:41:09 PM PDT 24
Peak memory 205960 kb
Host smart-a1d751c9-c14b-446c-99ea-f0a294415c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980346311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3980346311
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1174812804
Short name T1078
Test name
Test status
Simulation time 41256030 ps
CPU time 2.31 seconds
Started Aug 15 04:41:08 PM PDT 24
Finished Aug 15 04:41:10 PM PDT 24
Peak memory 206380 kb
Host smart-5037bf48-a477-4468-8c9f-e7a69775e18a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174812804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1174812804
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1518893
Short name T130
Test name
Test status
Simulation time 1796953750 ps
CPU time 2.78 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:12 PM PDT 24
Peak memory 214776 kb
Host smart-7fea1958-3418-47b2-84a7-7a5b7c2d0be4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_r
eg_errors.1518893
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2734768550
Short name T134
Test name
Test status
Simulation time 161773784 ps
CPU time 3.76 seconds
Started Aug 15 04:41:10 PM PDT 24
Finished Aug 15 04:41:14 PM PDT 24
Peak memory 220612 kb
Host smart-ec602b0b-1c3c-4f37-8735-9bafdf9722fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734768550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2734768550
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2163614354
Short name T1064
Test name
Test status
Simulation time 38255859 ps
CPU time 1.61 seconds
Started Aug 15 04:41:10 PM PDT 24
Finished Aug 15 04:41:11 PM PDT 24
Peak memory 214448 kb
Host smart-4ec70d58-1d9a-44e5-830c-f8ad264d2cd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163614354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2163614354
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.326496118
Short name T188
Test name
Test status
Simulation time 824482165 ps
CPU time 5.36 seconds
Started Aug 15 04:41:08 PM PDT 24
Finished Aug 15 04:41:14 PM PDT 24
Peak memory 214328 kb
Host smart-cbf6e058-bbeb-400b-a762-36ed8eb066a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326496118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
326496118
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1042945880
Short name T980
Test name
Test status
Simulation time 23552941 ps
CPU time 0.9 seconds
Started Aug 15 04:41:43 PM PDT 24
Finished Aug 15 04:41:44 PM PDT 24
Peak memory 206012 kb
Host smart-1aec4c41-28b8-423b-91c7-f9a4453e34f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042945880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1042945880
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1136658780
Short name T975
Test name
Test status
Simulation time 33192509 ps
CPU time 0.72 seconds
Started Aug 15 04:41:45 PM PDT 24
Finished Aug 15 04:41:46 PM PDT 24
Peak memory 206056 kb
Host smart-a0f5f87e-717e-4ead-8dd8-6eb5f444325d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136658780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1136658780
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1308470329
Short name T1016
Test name
Test status
Simulation time 10439338 ps
CPU time 0.75 seconds
Started Aug 15 04:41:50 PM PDT 24
Finished Aug 15 04:41:51 PM PDT 24
Peak memory 206064 kb
Host smart-62b31a0a-b02c-4c38-acbb-b070fb37d9cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308470329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1308470329
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.895703854
Short name T1079
Test name
Test status
Simulation time 9771440 ps
CPU time 0.76 seconds
Started Aug 15 04:41:52 PM PDT 24
Finished Aug 15 04:41:53 PM PDT 24
Peak memory 205992 kb
Host smart-262fc73b-2e29-400e-a2f2-969f2f91f645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895703854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.895703854
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1153026571
Short name T968
Test name
Test status
Simulation time 11535253 ps
CPU time 0.87 seconds
Started Aug 15 04:41:51 PM PDT 24
Finished Aug 15 04:41:52 PM PDT 24
Peak memory 206024 kb
Host smart-b4de4b56-e790-4832-af5b-607ad78212cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153026571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1153026571
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2958965216
Short name T953
Test name
Test status
Simulation time 9167891 ps
CPU time 0.85 seconds
Started Aug 15 04:41:49 PM PDT 24
Finished Aug 15 04:41:50 PM PDT 24
Peak memory 205872 kb
Host smart-66bb6072-51b4-47c7-a70a-8291101620ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958965216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2958965216
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4222077706
Short name T940
Test name
Test status
Simulation time 39116606 ps
CPU time 0.73 seconds
Started Aug 15 04:41:51 PM PDT 24
Finished Aug 15 04:41:51 PM PDT 24
Peak memory 205888 kb
Host smart-9632dfca-3671-4407-83ea-ac323c5ae7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222077706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4222077706
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1259990758
Short name T1025
Test name
Test status
Simulation time 19706189 ps
CPU time 0.86 seconds
Started Aug 15 04:41:51 PM PDT 24
Finished Aug 15 04:41:52 PM PDT 24
Peak memory 205928 kb
Host smart-6f7b31bd-e9e4-4443-baab-73797de2811a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259990758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1259990758
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1599788007
Short name T1007
Test name
Test status
Simulation time 13207473 ps
CPU time 0.88 seconds
Started Aug 15 04:41:50 PM PDT 24
Finished Aug 15 04:41:51 PM PDT 24
Peak memory 205928 kb
Host smart-57277768-73b2-431b-ba81-db2d65842941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599788007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1599788007
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3976963292
Short name T1048
Test name
Test status
Simulation time 29902224 ps
CPU time 0.8 seconds
Started Aug 15 04:41:52 PM PDT 24
Finished Aug 15 04:41:53 PM PDT 24
Peak memory 205928 kb
Host smart-51dbcfe5-23c3-42ac-93c6-f24bb0d8c46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976963292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3976963292
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2622626688
Short name T1076
Test name
Test status
Simulation time 101505222 ps
CPU time 1.34 seconds
Started Aug 15 04:41:18 PM PDT 24
Finished Aug 15 04:41:19 PM PDT 24
Peak memory 214460 kb
Host smart-2d18b57a-fafa-4968-96f8-b49b0119dbfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622626688 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2622626688
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3543180171
Short name T200
Test name
Test status
Simulation time 110047014 ps
CPU time 1.24 seconds
Started Aug 15 04:41:14 PM PDT 24
Finished Aug 15 04:41:16 PM PDT 24
Peak memory 206204 kb
Host smart-1c840445-ef23-4e52-93ea-dd719daac762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543180171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3543180171
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3926651410
Short name T918
Test name
Test status
Simulation time 79397633 ps
CPU time 0.79 seconds
Started Aug 15 04:41:19 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 206076 kb
Host smart-613bba40-d67a-4065-ab73-bc2117c6dec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926651410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3926651410
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3356736752
Short name T1019
Test name
Test status
Simulation time 150564680 ps
CPU time 2.07 seconds
Started Aug 15 04:41:18 PM PDT 24
Finished Aug 15 04:41:21 PM PDT 24
Peak memory 206352 kb
Host smart-5e44fdb8-6ef9-47dd-923a-8e067cd585c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356736752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3356736752
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2630914401
Short name T991
Test name
Test status
Simulation time 358066414 ps
CPU time 2.78 seconds
Started Aug 15 04:41:10 PM PDT 24
Finished Aug 15 04:41:13 PM PDT 24
Peak memory 214748 kb
Host smart-9265625a-f304-4010-9ec2-0f0909607ba9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630914401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2630914401
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1024029550
Short name T949
Test name
Test status
Simulation time 195522458 ps
CPU time 7.14 seconds
Started Aug 15 04:41:09 PM PDT 24
Finished Aug 15 04:41:17 PM PDT 24
Peak memory 222984 kb
Host smart-3ae07171-884b-49c3-974a-f959b477be49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024029550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1024029550
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2429573362
Short name T1021
Test name
Test status
Simulation time 47662601 ps
CPU time 3.38 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 217616 kb
Host smart-9cbaee00-aa49-478c-8cc0-1566443e19d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429573362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2429573362
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.315265327
Short name T193
Test name
Test status
Simulation time 194376821 ps
CPU time 2.54 seconds
Started Aug 15 04:41:17 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 206252 kb
Host smart-dddb27b6-54fb-4726-be94-5ed55783b208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315265327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
315265327
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.91175661
Short name T925
Test name
Test status
Simulation time 39464854 ps
CPU time 1.5 seconds
Started Aug 15 04:41:18 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 206356 kb
Host smart-b0fc803e-eada-42b4-97cc-dd9dcf061fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91175661 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.91175661
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1119725349
Short name T984
Test name
Test status
Simulation time 21418336 ps
CPU time 1 seconds
Started Aug 15 04:41:17 PM PDT 24
Finished Aug 15 04:41:18 PM PDT 24
Peak memory 206164 kb
Host smart-3d13109d-0af2-4362-b979-90dd976e4a10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119725349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1119725349
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1606180351
Short name T985
Test name
Test status
Simulation time 33047209 ps
CPU time 0.86 seconds
Started Aug 15 04:41:19 PM PDT 24
Finished Aug 15 04:41:21 PM PDT 24
Peak memory 205928 kb
Host smart-f4d2b64d-2cdd-4f01-95e8-9145ef0374c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606180351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1606180351
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.129011277
Short name T956
Test name
Test status
Simulation time 115926261 ps
CPU time 1.59 seconds
Started Aug 15 04:41:18 PM PDT 24
Finished Aug 15 04:41:19 PM PDT 24
Peak memory 206200 kb
Host smart-29f6ea47-1289-474f-bef7-94b00ce4f9dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129011277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.129011277
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2595232597
Short name T948
Test name
Test status
Simulation time 82704178 ps
CPU time 2.63 seconds
Started Aug 15 04:41:17 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 214720 kb
Host smart-1f1520db-693a-4c09-b4b6-f65ddbe5bf2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595232597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2595232597
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3785800116
Short name T1060
Test name
Test status
Simulation time 379542841 ps
CPU time 4.35 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 214780 kb
Host smart-97e8b685-4bd0-47c4-a508-6c1a374e9aea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785800116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3785800116
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4093680066
Short name T1058
Test name
Test status
Simulation time 292651348 ps
CPU time 2.1 seconds
Started Aug 15 04:41:17 PM PDT 24
Finished Aug 15 04:41:19 PM PDT 24
Peak memory 214576 kb
Host smart-4fd7e329-2489-4f70-910f-61965d124717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093680066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4093680066
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1060833029
Short name T997
Test name
Test status
Simulation time 39806474 ps
CPU time 1.76 seconds
Started Aug 15 04:41:17 PM PDT 24
Finished Aug 15 04:41:19 PM PDT 24
Peak memory 214548 kb
Host smart-f9743148-9ddc-4cef-a43f-bbd8f2abda28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060833029 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1060833029
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2830209574
Short name T927
Test name
Test status
Simulation time 56147530 ps
CPU time 1.21 seconds
Started Aug 15 04:41:18 PM PDT 24
Finished Aug 15 04:41:19 PM PDT 24
Peak memory 206220 kb
Host smart-a2159095-c259-4d95-ab12-f59de2ea9786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830209574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2830209574
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.402025600
Short name T1071
Test name
Test status
Simulation time 29138152 ps
CPU time 0.84 seconds
Started Aug 15 04:41:15 PM PDT 24
Finished Aug 15 04:41:16 PM PDT 24
Peak memory 205988 kb
Host smart-ce4888c1-cd51-4b4a-b993-7dfa5f08f762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402025600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.402025600
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3262756745
Short name T921
Test name
Test status
Simulation time 42141721 ps
CPU time 1.34 seconds
Started Aug 15 04:41:18 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 206172 kb
Host smart-8ce4494f-39ea-4749-a67e-d7d7bbeb9dbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262756745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3262756745
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3418265425
Short name T1030
Test name
Test status
Simulation time 176958832 ps
CPU time 2.25 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:19 PM PDT 24
Peak memory 214836 kb
Host smart-fc6705a1-e542-4b91-9bc7-9cb13ca46b4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418265425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3418265425
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2258140440
Short name T126
Test name
Test status
Simulation time 773427968 ps
CPU time 6.23 seconds
Started Aug 15 04:41:15 PM PDT 24
Finished Aug 15 04:41:21 PM PDT 24
Peak memory 214704 kb
Host smart-e84cd59a-10cd-40fe-b3c5-2d5378e9a164
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258140440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2258140440
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.921552675
Short name T965
Test name
Test status
Simulation time 38273472 ps
CPU time 1.85 seconds
Started Aug 15 04:41:14 PM PDT 24
Finished Aug 15 04:41:16 PM PDT 24
Peak memory 213580 kb
Host smart-b84b6827-506c-4c25-8fce-1247d55611b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921552675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.921552675
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1593034211
Short name T926
Test name
Test status
Simulation time 32697299 ps
CPU time 1.22 seconds
Started Aug 15 04:41:18 PM PDT 24
Finished Aug 15 04:41:19 PM PDT 24
Peak memory 214496 kb
Host smart-e3d670e9-4d36-480d-8bf0-2ad9b74f9261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593034211 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1593034211
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3394686952
Short name T996
Test name
Test status
Simulation time 12190573 ps
CPU time 1 seconds
Started Aug 15 04:41:17 PM PDT 24
Finished Aug 15 04:41:18 PM PDT 24
Peak memory 206120 kb
Host smart-dfb990a1-7224-4a99-8ea5-7a3b21e1d225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394686952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3394686952
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.238432291
Short name T1035
Test name
Test status
Simulation time 37829221 ps
CPU time 0.74 seconds
Started Aug 15 04:41:19 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 205996 kb
Host smart-88621c83-0d68-4caa-b7f0-e72beddd8c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238432291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.238432291
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.625114337
Short name T1053
Test name
Test status
Simulation time 198210189 ps
CPU time 1.79 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:18 PM PDT 24
Peak memory 206384 kb
Host smart-03feb11a-0fbd-47ca-8000-de93f2c75675
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625114337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.625114337
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3097603936
Short name T1057
Test name
Test status
Simulation time 112957743 ps
CPU time 2.5 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:19 PM PDT 24
Peak memory 214648 kb
Host smart-ce244372-065c-49c4-b8f1-b94ed3794d65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097603936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3097603936
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1259861869
Short name T999
Test name
Test status
Simulation time 152883286 ps
CPU time 4.61 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:20 PM PDT 24
Peak memory 217780 kb
Host smart-0e47e3b5-0331-4e6f-9cc8-e71a26149cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259861869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1259861869
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.345779923
Short name T1009
Test name
Test status
Simulation time 32175424 ps
CPU time 1.13 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:17 PM PDT 24
Peak memory 214408 kb
Host smart-d8389968-2fde-4815-9a9a-11a40589d9e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345779923 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.345779923
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3525228511
Short name T931
Test name
Test status
Simulation time 18729351 ps
CPU time 1.07 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:17 PM PDT 24
Peak memory 205988 kb
Host smart-2e4b9071-8e9e-4557-86e2-0ab59430244b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525228511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3525228511
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2614062284
Short name T960
Test name
Test status
Simulation time 37851546 ps
CPU time 0.76 seconds
Started Aug 15 04:41:17 PM PDT 24
Finished Aug 15 04:41:18 PM PDT 24
Peak memory 205916 kb
Host smart-7f97b9bf-9183-444c-bf30-451eabf133da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614062284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2614062284
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3446659171
Short name T961
Test name
Test status
Simulation time 121042747 ps
CPU time 1.41 seconds
Started Aug 15 04:41:19 PM PDT 24
Finished Aug 15 04:41:21 PM PDT 24
Peak memory 206264 kb
Host smart-edbb81bc-97c7-4507-a7d7-353b5fa76b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446659171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3446659171
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1337861761
Short name T1047
Test name
Test status
Simulation time 590627770 ps
CPU time 4.49 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:21 PM PDT 24
Peak memory 214824 kb
Host smart-3a95652a-c00e-489a-819c-02828b4edd2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337861761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1337861761
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3627103152
Short name T1061
Test name
Test status
Simulation time 472511403 ps
CPU time 9.27 seconds
Started Aug 15 04:41:17 PM PDT 24
Finished Aug 15 04:41:26 PM PDT 24
Peak memory 214828 kb
Host smart-2f572914-55aa-41da-9627-7fa4197a020f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627103152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3627103152
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3596741292
Short name T974
Test name
Test status
Simulation time 130249850 ps
CPU time 2.52 seconds
Started Aug 15 04:41:16 PM PDT 24
Finished Aug 15 04:41:19 PM PDT 24
Peak memory 216652 kb
Host smart-7538b5dd-7f52-4b61-b060-56f28f34c09e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596741292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3596741292
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2854427459
Short name T846
Test name
Test status
Simulation time 34002069 ps
CPU time 0.83 seconds
Started Aug 15 05:50:23 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 206404 kb
Host smart-b07aa6a9-a0f2-4fdd-a609-41b675824134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854427459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2854427459
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.250930155
Short name T416
Test name
Test status
Simulation time 119896197 ps
CPU time 2.84 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 214648 kb
Host smart-0e2d7bf7-b41d-4057-bc47-9730d75102a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250930155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.250930155
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2666397246
Short name T78
Test name
Test status
Simulation time 311720681 ps
CPU time 4.48 seconds
Started Aug 15 05:50:29 PM PDT 24
Finished Aug 15 05:50:33 PM PDT 24
Peak memory 223104 kb
Host smart-b930b579-a731-4a02-a871-efe9dbbf3633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666397246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2666397246
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1289021091
Short name T697
Test name
Test status
Simulation time 5314732938 ps
CPU time 18.39 seconds
Started Aug 15 05:50:27 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 209284 kb
Host smart-4a41a74d-fe0c-4248-ba22-8bebe0ece197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289021091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1289021091
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2729989551
Short name T884
Test name
Test status
Simulation time 422937528 ps
CPU time 3.22 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:25 PM PDT 24
Peak memory 214704 kb
Host smart-cd5956bf-d4d7-49fa-91a0-60a2575bc0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729989551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2729989551
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.3032744688
Short name T863
Test name
Test status
Simulation time 532871639 ps
CPU time 6.78 seconds
Started Aug 15 05:50:17 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 208388 kb
Host smart-340014cc-4074-44fb-b96e-b45b408eee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032744688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3032744688
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3154742346
Short name T12
Test name
Test status
Simulation time 980541679 ps
CPU time 12.53 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:34 PM PDT 24
Peak memory 231572 kb
Host smart-410af19a-5b4d-430c-b9d5-41808bd77459
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154742346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3154742346
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2803579241
Short name T480
Test name
Test status
Simulation time 341636923 ps
CPU time 7.65 seconds
Started Aug 15 05:50:36 PM PDT 24
Finished Aug 15 05:50:43 PM PDT 24
Peak memory 209320 kb
Host smart-06344321-9c76-410c-901f-ac201d3e7d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803579241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2803579241
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2481093709
Short name T478
Test name
Test status
Simulation time 293642748 ps
CPU time 4.89 seconds
Started Aug 15 05:50:27 PM PDT 24
Finished Aug 15 05:50:32 PM PDT 24
Peak memory 207408 kb
Host smart-8e00755f-fa38-4c43-b8f5-1f5a7527c7d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481093709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2481093709
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3599162673
Short name T403
Test name
Test status
Simulation time 2843351743 ps
CPU time 19.05 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:41 PM PDT 24
Peak memory 208704 kb
Host smart-b67585ff-adab-434c-9f82-74e49b5e329d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599162673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3599162673
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1669445906
Short name T613
Test name
Test status
Simulation time 119114213 ps
CPU time 4.36 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:20 PM PDT 24
Peak memory 207388 kb
Host smart-9d1980e8-a2e7-497f-8676-dd0642f2c7cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669445906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1669445906
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.786092730
Short name T464
Test name
Test status
Simulation time 136811776 ps
CPU time 3.35 seconds
Started Aug 15 05:50:35 PM PDT 24
Finished Aug 15 05:50:38 PM PDT 24
Peak memory 209136 kb
Host smart-0eec4eca-4928-4819-ac25-05d9186064f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786092730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.786092730
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2830714185
Short name T784
Test name
Test status
Simulation time 621762085 ps
CPU time 14.22 seconds
Started Aug 15 05:50:17 PM PDT 24
Finished Aug 15 05:50:31 PM PDT 24
Peak memory 209052 kb
Host smart-dbd2fac2-fec7-47b6-88aa-a62a2bbf6e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830714185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2830714185
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.394565595
Short name T303
Test name
Test status
Simulation time 999060632 ps
CPU time 26.49 seconds
Started Aug 15 05:50:20 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 209684 kb
Host smart-bb1535a5-09af-4b9e-80da-648726ca8ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394565595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.394565595
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3800400548
Short name T395
Test name
Test status
Simulation time 231198566 ps
CPU time 4.92 seconds
Started Aug 15 05:50:30 PM PDT 24
Finished Aug 15 05:50:35 PM PDT 24
Peak memory 211100 kb
Host smart-f0281c1c-8c80-478a-9207-56f9fa694c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800400548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3800400548
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2165941004
Short name T638
Test name
Test status
Simulation time 16905507 ps
CPU time 0.95 seconds
Started Aug 15 05:50:24 PM PDT 24
Finished Aug 15 05:50:25 PM PDT 24
Peak memory 206536 kb
Host smart-60de86b5-7ed3-480a-806b-cb71e942b0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165941004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2165941004
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.549947760
Short name T246
Test name
Test status
Simulation time 204870276 ps
CPU time 11.33 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:32 PM PDT 24
Peak memory 215348 kb
Host smart-1afedb92-cc23-4ace-bd58-c1f990466266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549947760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.549947760
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2099198331
Short name T885
Test name
Test status
Simulation time 185956766 ps
CPU time 7.11 seconds
Started Aug 15 05:50:24 PM PDT 24
Finished Aug 15 05:50:31 PM PDT 24
Peak memory 215060 kb
Host smart-a55055bc-b72f-4b9f-8add-bac9bc1704ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099198331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2099198331
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1716882854
Short name T248
Test name
Test status
Simulation time 366380455 ps
CPU time 3.03 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 209528 kb
Host smart-7c91f77e-d62c-418b-81c3-75f93c28ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716882854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1716882854
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.635818122
Short name T309
Test name
Test status
Simulation time 144137306 ps
CPU time 3.07 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:25 PM PDT 24
Peak memory 222128 kb
Host smart-7f7b085a-5b83-4d5d-85ef-b070818eaeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635818122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.635818122
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1991638714
Short name T719
Test name
Test status
Simulation time 88760451 ps
CPU time 2.14 seconds
Started Aug 15 05:50:35 PM PDT 24
Finished Aug 15 05:50:37 PM PDT 24
Peak memory 217256 kb
Host smart-1d889557-72ee-422e-bac3-2234fde0da69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991638714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1991638714
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1425277831
Short name T812
Test name
Test status
Simulation time 151450913 ps
CPU time 3.44 seconds
Started Aug 15 05:50:32 PM PDT 24
Finished Aug 15 05:50:36 PM PDT 24
Peak memory 220844 kb
Host smart-311853e2-f753-4549-bffb-015be916cb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425277831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1425277831
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2178091807
Short name T289
Test name
Test status
Simulation time 80701808 ps
CPU time 4.38 seconds
Started Aug 15 05:50:28 PM PDT 24
Finished Aug 15 05:50:33 PM PDT 24
Peak memory 214776 kb
Host smart-19f59aff-61b5-46c1-b0a9-ec0f2d12e350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178091807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2178091807
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.313210357
Short name T116
Test name
Test status
Simulation time 1469103714 ps
CPU time 6.89 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:38 PM PDT 24
Peak memory 229372 kb
Host smart-7a095ec0-e586-408b-ada7-e856ebbe7404
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313210357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.313210357
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1663342105
Short name T562
Test name
Test status
Simulation time 165379002 ps
CPU time 3.54 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:25 PM PDT 24
Peak memory 209184 kb
Host smart-15efc6ba-5c98-4175-a604-28ae729d91dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663342105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1663342105
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1300898503
Short name T648
Test name
Test status
Simulation time 215728216 ps
CPU time 4.86 seconds
Started Aug 15 05:50:23 PM PDT 24
Finished Aug 15 05:50:28 PM PDT 24
Peak memory 209120 kb
Host smart-f90761e7-23c6-4b25-95bd-15f045028745
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300898503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1300898503
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1710490069
Short name T541
Test name
Test status
Simulation time 633605614 ps
CPU time 5.04 seconds
Started Aug 15 05:50:24 PM PDT 24
Finished Aug 15 05:50:30 PM PDT 24
Peak memory 209256 kb
Host smart-70f8ffce-91bf-4dfa-aa60-990f9bfefe40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710490069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1710490069
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3091791936
Short name T566
Test name
Test status
Simulation time 698424216 ps
CPU time 5.28 seconds
Started Aug 15 05:50:33 PM PDT 24
Finished Aug 15 05:50:39 PM PDT 24
Peak memory 208604 kb
Host smart-09f6a72a-10a6-493b-8a27-be9f9bf6894c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091791936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3091791936
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3360398398
Short name T410
Test name
Test status
Simulation time 60041007 ps
CPU time 1.78 seconds
Started Aug 15 05:50:36 PM PDT 24
Finished Aug 15 05:50:38 PM PDT 24
Peak memory 214736 kb
Host smart-939ed19c-114f-4368-bd79-112d1803c194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360398398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3360398398
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2259614057
Short name T146
Test name
Test status
Simulation time 343210289 ps
CPU time 1.75 seconds
Started Aug 15 05:50:36 PM PDT 24
Finished Aug 15 05:50:38 PM PDT 24
Peak memory 207560 kb
Host smart-24ee2370-8af1-4932-b124-11b9dd0e2f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259614057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2259614057
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.692084361
Short name T197
Test name
Test status
Simulation time 283441930 ps
CPU time 10.68 seconds
Started Aug 15 05:50:23 PM PDT 24
Finished Aug 15 05:50:34 PM PDT 24
Peak memory 223056 kb
Host smart-365ea216-c065-4b56-84b3-3a2090c64894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692084361 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.692084361
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2651743770
Short name T874
Test name
Test status
Simulation time 236750904 ps
CPU time 3.38 seconds
Started Aug 15 05:50:32 PM PDT 24
Finished Aug 15 05:50:35 PM PDT 24
Peak memory 214832 kb
Host smart-631260e6-4d01-446f-bfdb-75c1d29122cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651743770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2651743770
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1459276921
Short name T595
Test name
Test status
Simulation time 38079623 ps
CPU time 0.81 seconds
Started Aug 15 05:50:53 PM PDT 24
Finished Aug 15 05:50:54 PM PDT 24
Peak memory 206408 kb
Host smart-233c0491-e2e7-4376-b317-46276266f36d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459276921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1459276921
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1401872229
Short name T260
Test name
Test status
Simulation time 505605653 ps
CPU time 12.05 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:51:06 PM PDT 24
Peak memory 222904 kb
Host smart-edc1c538-dee8-457a-af51-13c138482e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401872229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1401872229
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3485828491
Short name T833
Test name
Test status
Simulation time 189236425 ps
CPU time 2.87 seconds
Started Aug 15 05:51:10 PM PDT 24
Finished Aug 15 05:51:13 PM PDT 24
Peak memory 223164 kb
Host smart-7261c542-47ab-4d0b-98ad-2c21131d2408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485828491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3485828491
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1195295214
Short name T70
Test name
Test status
Simulation time 89278415 ps
CPU time 3.25 seconds
Started Aug 15 05:51:07 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 209612 kb
Host smart-3983d195-a7d6-4fbd-99f1-60ea4ebde52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195295214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1195295214
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1990257904
Short name T854
Test name
Test status
Simulation time 79002591 ps
CPU time 3.39 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:50:57 PM PDT 24
Peak memory 212364 kb
Host smart-632c7bcf-00c7-4589-bb60-65fa419d450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990257904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1990257904
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2312775363
Short name T739
Test name
Test status
Simulation time 68010806 ps
CPU time 2.27 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:50:57 PM PDT 24
Peak memory 220228 kb
Host smart-f664bcb6-9adc-44ac-b862-98803c5315cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312775363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2312775363
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2056197986
Short name T273
Test name
Test status
Simulation time 287393181 ps
CPU time 3.06 seconds
Started Aug 15 05:50:53 PM PDT 24
Finished Aug 15 05:50:56 PM PDT 24
Peak memory 207932 kb
Host smart-d482e615-1979-4e86-80b4-f8195e9e4590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056197986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2056197986
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1612382672
Short name T869
Test name
Test status
Simulation time 664290038 ps
CPU time 5.41 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 208488 kb
Host smart-6a9821fb-9006-49d3-a393-73e4f1c7eadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612382672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1612382672
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2034673181
Short name T343
Test name
Test status
Simulation time 214896275 ps
CPU time 3.91 seconds
Started Aug 15 05:50:56 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 207796 kb
Host smart-71627afc-2f8c-4b1c-a0e8-62257d43c09d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034673181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2034673181
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1729144612
Short name T338
Test name
Test status
Simulation time 132697484 ps
CPU time 3.22 seconds
Started Aug 15 05:51:03 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 209060 kb
Host smart-93b602bc-4655-41d2-abeb-05de40dc7611
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729144612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1729144612
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1368794308
Short name T500
Test name
Test status
Simulation time 106977802 ps
CPU time 4.31 seconds
Started Aug 15 05:50:51 PM PDT 24
Finished Aug 15 05:50:56 PM PDT 24
Peak memory 207372 kb
Host smart-c1f7751e-0e9a-4726-849d-cef452848b83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368794308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1368794308
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2927304775
Short name T699
Test name
Test status
Simulation time 209081691 ps
CPU time 4.35 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:50:59 PM PDT 24
Peak memory 209744 kb
Host smart-ecd73f68-207f-4c8c-8649-e84089e46974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927304775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2927304775
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3837403854
Short name T427
Test name
Test status
Simulation time 44089813 ps
CPU time 2.27 seconds
Started Aug 15 05:50:47 PM PDT 24
Finished Aug 15 05:50:50 PM PDT 24
Peak memory 207372 kb
Host smart-56e46aba-1251-4479-af6e-c5a911a856d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837403854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3837403854
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3213124525
Short name T576
Test name
Test status
Simulation time 10383405894 ps
CPU time 29.51 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:51:24 PM PDT 24
Peak memory 209620 kb
Host smart-57c6b433-1d0e-4967-8fdb-68525e178a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213124525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3213124525
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1374025084
Short name T409
Test name
Test status
Simulation time 230442339 ps
CPU time 4.89 seconds
Started Aug 15 05:50:58 PM PDT 24
Finished Aug 15 05:51:03 PM PDT 24
Peak memory 215580 kb
Host smart-e19319a7-6975-4924-bc6e-d3158957810d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374025084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1374025084
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1367826680
Short name T225
Test name
Test status
Simulation time 290130948 ps
CPU time 6.05 seconds
Started Aug 15 05:50:58 PM PDT 24
Finished Aug 15 05:51:04 PM PDT 24
Peak memory 216476 kb
Host smart-6fd44a3c-9a96-412b-8d30-37c2518ce124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367826680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1367826680
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2694998506
Short name T717
Test name
Test status
Simulation time 137074028 ps
CPU time 1.94 seconds
Started Aug 15 05:50:56 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 209300 kb
Host smart-434727e5-5978-44e0-93d8-710c5e34e0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694998506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2694998506
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1664696117
Short name T102
Test name
Test status
Simulation time 208290431 ps
CPU time 4.59 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:50:59 PM PDT 24
Peak memory 221256 kb
Host smart-f9297b97-2e26-4998-b439-90649b5762f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664696117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1664696117
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3106419971
Short name T859
Test name
Test status
Simulation time 372927360 ps
CPU time 3.12 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:05 PM PDT 24
Peak memory 222860 kb
Host smart-33d7b45a-082a-4a63-b9e1-0f31f8d355d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106419971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3106419971
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_random.3159981036
Short name T345
Test name
Test status
Simulation time 4542504173 ps
CPU time 45.97 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:47 PM PDT 24
Peak memory 209072 kb
Host smart-f698a836-91e0-4b96-b692-9a1e64c019ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159981036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3159981036
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1425512660
Short name T801
Test name
Test status
Simulation time 560133960 ps
CPU time 4.17 seconds
Started Aug 15 05:51:00 PM PDT 24
Finished Aug 15 05:51:04 PM PDT 24
Peak memory 207232 kb
Host smart-81c20f0d-271f-4bfd-8af9-5d32bc6707e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425512660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1425512660
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1952042081
Short name T860
Test name
Test status
Simulation time 926564413 ps
CPU time 3.07 seconds
Started Aug 15 05:51:04 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 209260 kb
Host smart-19e00514-23fb-4ad1-8aee-52c5009126d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952042081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1952042081
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1131055257
Short name T816
Test name
Test status
Simulation time 3117491258 ps
CPU time 34.24 seconds
Started Aug 15 05:51:03 PM PDT 24
Finished Aug 15 05:51:38 PM PDT 24
Peak memory 208472 kb
Host smart-0c4191d9-3900-4342-9d5e-881d5dba5338
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131055257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1131055257
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2116134278
Short name T685
Test name
Test status
Simulation time 119529218 ps
CPU time 4.23 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:05 PM PDT 24
Peak memory 209044 kb
Host smart-6604318d-272f-4010-a97d-8ae8aef4beb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116134278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2116134278
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3691772829
Short name T644
Test name
Test status
Simulation time 86129088 ps
CPU time 3.04 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:03 PM PDT 24
Peak memory 209660 kb
Host smart-df005d2a-1166-42e5-81bf-5b06a36bcefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691772829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3691772829
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3915533058
Short name T479
Test name
Test status
Simulation time 100686797 ps
CPU time 2.37 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:04 PM PDT 24
Peak memory 208372 kb
Host smart-db77d3e6-7e41-4156-894e-094b7afece51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915533058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3915533058
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2960774791
Short name T335
Test name
Test status
Simulation time 4748343765 ps
CPU time 32.34 seconds
Started Aug 15 05:50:52 PM PDT 24
Finished Aug 15 05:51:24 PM PDT 24
Peak memory 217012 kb
Host smart-3253f356-6756-4c02-aee7-5e20d3657877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960774791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2960774791
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3567107461
Short name T522
Test name
Test status
Simulation time 79448272 ps
CPU time 4.42 seconds
Started Aug 15 05:50:52 PM PDT 24
Finished Aug 15 05:50:57 PM PDT 24
Peak memory 214752 kb
Host smart-66246ef8-e59c-46d7-b199-80951868023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567107461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3567107461
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3767886742
Short name T843
Test name
Test status
Simulation time 433718157 ps
CPU time 5.46 seconds
Started Aug 15 05:50:52 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 211400 kb
Host smart-b71c7456-3775-4556-ae49-85bfb2bc5ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767886742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3767886742
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1271529881
Short name T119
Test name
Test status
Simulation time 15284268 ps
CPU time 0.89 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 206560 kb
Host smart-7fc0feb4-9cc9-4c3d-9374-11f38e3affb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271529881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1271529881
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.732902912
Short name T383
Test name
Test status
Simulation time 78606809 ps
CPU time 3.36 seconds
Started Aug 15 05:50:52 PM PDT 24
Finished Aug 15 05:50:55 PM PDT 24
Peak memory 214764 kb
Host smart-97038268-7edb-407f-91d1-ddbd5de70c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=732902912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.732902912
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.762530172
Short name T357
Test name
Test status
Simulation time 95400041 ps
CPU time 4.23 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 210692 kb
Host smart-90d52c72-6229-4e68-b66d-3005ffed1d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762530172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.762530172
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1308131773
Short name T520
Test name
Test status
Simulation time 89018391 ps
CPU time 2.72 seconds
Started Aug 15 05:50:57 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 214668 kb
Host smart-16ecee44-69f3-4623-b110-c8ef33354a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308131773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1308131773
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1554687186
Short name T702
Test name
Test status
Simulation time 261063951 ps
CPU time 3.69 seconds
Started Aug 15 05:50:53 PM PDT 24
Finished Aug 15 05:50:57 PM PDT 24
Peak memory 221428 kb
Host smart-4a39b9ca-318e-4f58-b87c-5ac7a569b435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554687186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1554687186
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.420474960
Short name T716
Test name
Test status
Simulation time 296150410 ps
CPU time 4.3 seconds
Started Aug 15 05:51:04 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 207592 kb
Host smart-591ef1d8-ec35-498c-b088-754176745a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420474960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.420474960
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.4262924406
Short name T775
Test name
Test status
Simulation time 1535438181 ps
CPU time 31.73 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:51:27 PM PDT 24
Peak memory 208928 kb
Host smart-e1effe27-5a8c-4640-b1b7-d1a82b5902eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262924406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.4262924406
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2244114106
Short name T118
Test name
Test status
Simulation time 299151798 ps
CPU time 2.66 seconds
Started Aug 15 05:50:57 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 207440 kb
Host smart-d8c2d48c-947e-4ca5-b9d9-e3148cb0755e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244114106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2244114106
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3338370286
Short name T592
Test name
Test status
Simulation time 106351661 ps
CPU time 4.23 seconds
Started Aug 15 05:50:57 PM PDT 24
Finished Aug 15 05:51:02 PM PDT 24
Peak memory 209072 kb
Host smart-3833b3bc-91b2-46a5-a08c-268fcdf57cd6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338370286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3338370286
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3541486115
Short name T663
Test name
Test status
Simulation time 63271264 ps
CPU time 1.59 seconds
Started Aug 15 05:50:57 PM PDT 24
Finished Aug 15 05:50:59 PM PDT 24
Peak memory 208384 kb
Host smart-d96a48b6-3ec5-4628-b540-1ea82936aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541486115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3541486115
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2452406191
Short name T439
Test name
Test status
Simulation time 71567113 ps
CPU time 2.93 seconds
Started Aug 15 05:50:52 PM PDT 24
Finished Aug 15 05:50:55 PM PDT 24
Peak memory 208892 kb
Host smart-074abbf5-5777-4509-8e78-1a3d65946bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452406191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2452406191
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1828984302
Short name T206
Test name
Test status
Simulation time 527754928 ps
CPU time 9.61 seconds
Started Aug 15 05:51:00 PM PDT 24
Finished Aug 15 05:51:09 PM PDT 24
Peak memory 220728 kb
Host smart-b1bd665f-86b0-4e8b-95b0-eb513793d8cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828984302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1828984302
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1701642178
Short name T26
Test name
Test status
Simulation time 659033660 ps
CPU time 5.76 seconds
Started Aug 15 05:50:56 PM PDT 24
Finished Aug 15 05:51:02 PM PDT 24
Peak memory 214768 kb
Host smart-4e5a826e-1528-4784-8d90-3b23e906445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701642178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1701642178
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3063645164
Short name T524
Test name
Test status
Simulation time 700042493 ps
CPU time 3.02 seconds
Started Aug 15 05:51:04 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 210684 kb
Host smart-6887502e-cf99-4770-b2bc-c7ef81ddb8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063645164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3063645164
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3740203839
Short name T818
Test name
Test status
Simulation time 69960674 ps
CPU time 0.79 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 206320 kb
Host smart-1009fd30-20ad-412a-b99f-75522367e95c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740203839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3740203839
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.940146431
Short name T306
Test name
Test status
Simulation time 68840784 ps
CPU time 4.83 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 214936 kb
Host smart-b9947add-8a2d-4539-9b15-144a68ff75ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940146431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.940146431
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2292832236
Short name T33
Test name
Test status
Simulation time 235532175 ps
CPU time 3.81 seconds
Started Aug 15 05:51:12 PM PDT 24
Finished Aug 15 05:51:16 PM PDT 24
Peak memory 210092 kb
Host smart-3f38bfc2-e8e2-4a28-93c8-589b312bd29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292832236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2292832236
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1910825591
Short name T59
Test name
Test status
Simulation time 340630939 ps
CPU time 3.65 seconds
Started Aug 15 05:50:57 PM PDT 24
Finished Aug 15 05:51:01 PM PDT 24
Peak memory 208172 kb
Host smart-7cdd2ff9-d3fc-4ece-9bad-c5eaffa055d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910825591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1910825591
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2195439948
Short name T234
Test name
Test status
Simulation time 181175484 ps
CPU time 3.13 seconds
Started Aug 15 05:50:56 PM PDT 24
Finished Aug 15 05:50:59 PM PDT 24
Peak memory 222868 kb
Host smart-2ffacd3b-7838-4c71-8c46-902223ce8df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195439948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2195439948
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2186503760
Short name T446
Test name
Test status
Simulation time 121457106 ps
CPU time 3.77 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:50:59 PM PDT 24
Peak memory 214780 kb
Host smart-9cbe32ba-7fd8-4010-95f2-e22f520bb13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186503760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2186503760
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3911677128
Short name T768
Test name
Test status
Simulation time 564412783 ps
CPU time 3.3 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:50:57 PM PDT 24
Peak memory 207360 kb
Host smart-a44d2403-429e-4d45-bc38-67208b89410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911677128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3911677128
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2443681173
Short name T361
Test name
Test status
Simulation time 210499540 ps
CPU time 2.99 seconds
Started Aug 15 05:50:58 PM PDT 24
Finished Aug 15 05:51:01 PM PDT 24
Peak memory 207452 kb
Host smart-45803537-240f-4104-8b2b-a76ebff7fcbb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443681173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2443681173
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3628127879
Short name T910
Test name
Test status
Simulation time 311144353 ps
CPU time 3.52 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:04 PM PDT 24
Peak memory 207352 kb
Host smart-f7b4751f-6666-4514-80d9-ff2b0408b3e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628127879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3628127879
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2606347244
Short name T337
Test name
Test status
Simulation time 150458142 ps
CPU time 3.85 seconds
Started Aug 15 05:50:56 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 209248 kb
Host smart-be11b0bd-8305-4a03-9277-1062e1031340
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606347244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2606347244
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3081035004
Short name T559
Test name
Test status
Simulation time 17613207 ps
CPU time 1.61 seconds
Started Aug 15 05:50:56 PM PDT 24
Finished Aug 15 05:50:57 PM PDT 24
Peak memory 208104 kb
Host smart-db34457c-d0e8-42ed-9192-b1098c4c58b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081035004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3081035004
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1452545145
Short name T778
Test name
Test status
Simulation time 44020279 ps
CPU time 1.63 seconds
Started Aug 15 05:50:52 PM PDT 24
Finished Aug 15 05:50:54 PM PDT 24
Peak memory 207324 kb
Host smart-7d97c98a-88e2-43c2-83fe-e3314694040d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452545145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1452545145
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.78295862
Short name T896
Test name
Test status
Simulation time 202499320 ps
CPU time 7.85 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:17 PM PDT 24
Peak memory 219188 kb
Host smart-ab10a399-4861-4bd8-bcf4-349a819f5674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78295862 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.78295862
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2654586918
Short name T261
Test name
Test status
Simulation time 7112424371 ps
CPU time 53.6 seconds
Started Aug 15 05:50:58 PM PDT 24
Finished Aug 15 05:51:52 PM PDT 24
Peak memory 223000 kb
Host smart-aed58eff-796d-4402-97ce-c59c2ad05f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654586918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2654586918
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2235786535
Short name T543
Test name
Test status
Simulation time 199595345 ps
CPU time 2.39 seconds
Started Aug 15 05:50:57 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 210624 kb
Host smart-756cb554-c910-4918-bd6b-33f3ecd640f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235786535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2235786535
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.667664651
Short name T880
Test name
Test status
Simulation time 15999504 ps
CPU time 0.95 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 206504 kb
Host smart-7887bfb7-3661-4f8e-91c5-09e9d05652a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667664651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.667664651
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3128348995
Short name T250
Test name
Test status
Simulation time 4225300906 ps
CPU time 45.85 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:46 PM PDT 24
Peak memory 214720 kb
Host smart-feb47fff-10b6-448a-a0b1-2f11de5bcd50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128348995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3128348995
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3533469437
Short name T552
Test name
Test status
Simulation time 449605507 ps
CPU time 2.26 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:03 PM PDT 24
Peak memory 218604 kb
Host smart-e433c7a9-9477-4642-bd56-cd4f55576237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533469437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3533469437
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1639430811
Short name T879
Test name
Test status
Simulation time 94637019 ps
CPU time 4.67 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:06 PM PDT 24
Peak memory 214816 kb
Host smart-e49c239c-a4d8-44a8-b51f-3c2922046909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639430811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1639430811
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_random.2540310356
Short name T771
Test name
Test status
Simulation time 140536840 ps
CPU time 3.51 seconds
Started Aug 15 05:51:03 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 209776 kb
Host smart-09aba869-7c08-410a-b04b-8e0e8e803994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540310356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2540310356
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4037397838
Short name T382
Test name
Test status
Simulation time 3543779751 ps
CPU time 16.33 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:22 PM PDT 24
Peak memory 209068 kb
Host smart-a8b11cbd-d851-4127-879e-fc5a4d619795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037397838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4037397838
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2228580001
Short name T582
Test name
Test status
Simulation time 1186222725 ps
CPU time 14.41 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:20 PM PDT 24
Peak memory 208516 kb
Host smart-d25780c6-43f7-42f9-943e-25cc1a333e0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228580001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2228580001
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.491132630
Short name T99
Test name
Test status
Simulation time 54362234 ps
CPU time 3.1 seconds
Started Aug 15 05:50:58 PM PDT 24
Finished Aug 15 05:51:01 PM PDT 24
Peak memory 207600 kb
Host smart-d591440c-d281-46da-b389-976003cb8448
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491132630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.491132630
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2736302527
Short name T688
Test name
Test status
Simulation time 246998895 ps
CPU time 4.5 seconds
Started Aug 15 05:51:07 PM PDT 24
Finished Aug 15 05:51:12 PM PDT 24
Peak memory 209144 kb
Host smart-5fdb38db-1aa1-4c7b-a2dd-8951a236cbc6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736302527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2736302527
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3298451806
Short name T747
Test name
Test status
Simulation time 139803981 ps
CPU time 2.13 seconds
Started Aug 15 05:51:12 PM PDT 24
Finished Aug 15 05:51:14 PM PDT 24
Peak memory 207328 kb
Host smart-6f261876-6f3d-4f4e-819c-e3e5905ab8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298451806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3298451806
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2980484667
Short name T835
Test name
Test status
Simulation time 83906690 ps
CPU time 3.09 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:02 PM PDT 24
Peak memory 208788 kb
Host smart-cdf2dc77-df2f-4838-a7e1-0cb55513b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980484667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2980484667
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.609530948
Short name T89
Test name
Test status
Simulation time 13712439655 ps
CPU time 169.86 seconds
Started Aug 15 05:50:57 PM PDT 24
Finished Aug 15 05:53:47 PM PDT 24
Peak memory 218168 kb
Host smart-d7601c00-182f-468f-9c7b-fb562eb5f0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609530948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.609530948
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.967002250
Short name T212
Test name
Test status
Simulation time 1664410107 ps
CPU time 53.98 seconds
Started Aug 15 05:51:10 PM PDT 24
Finished Aug 15 05:52:04 PM PDT 24
Peak memory 214752 kb
Host smart-8422eab8-ecd2-4e7c-852f-4d40d6c5da78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967002250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.967002250
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1203920091
Short name T209
Test name
Test status
Simulation time 88882776 ps
CPU time 2.59 seconds
Started Aug 15 05:51:00 PM PDT 24
Finished Aug 15 05:51:03 PM PDT 24
Peak memory 210208 kb
Host smart-6066c4bc-4820-4feb-a390-40cbfd7f7f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203920091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1203920091
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1235201905
Short name T425
Test name
Test status
Simulation time 137214608 ps
CPU time 0.82 seconds
Started Aug 15 05:51:03 PM PDT 24
Finished Aug 15 05:51:05 PM PDT 24
Peak memory 206368 kb
Host smart-f0a832ed-2bfb-412e-bcc5-d8cdc9b97309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235201905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1235201905
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.168740981
Short name T36
Test name
Test status
Simulation time 172477133 ps
CPU time 2.66 seconds
Started Aug 15 05:51:04 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 223160 kb
Host smart-17f57282-a1f6-4cc4-821a-703b0758f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168740981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.168740981
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2709122495
Short name T362
Test name
Test status
Simulation time 2935855214 ps
CPU time 18.36 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:25 PM PDT 24
Peak memory 209260 kb
Host smart-a4c6e243-ae50-430d-a0fd-fc54bcfee377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709122495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2709122495
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3072600620
Short name T101
Test name
Test status
Simulation time 54620966 ps
CPU time 2.96 seconds
Started Aug 15 05:50:57 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 214772 kb
Host smart-6992f031-a694-4d84-8422-28b52ed430c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072600620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3072600620
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3557051376
Short name T618
Test name
Test status
Simulation time 215358175 ps
CPU time 9.57 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:16 PM PDT 24
Peak memory 220528 kb
Host smart-e1e797b7-f5ae-454f-958c-445b51a2a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557051376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3557051376
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.212860132
Short name T733
Test name
Test status
Simulation time 947512752 ps
CPU time 5.96 seconds
Started Aug 15 05:51:10 PM PDT 24
Finished Aug 15 05:51:16 PM PDT 24
Peak memory 208776 kb
Host smart-b9fae870-0e83-47b5-b739-d8546e2745a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212860132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.212860132
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2648029262
Short name T681
Test name
Test status
Simulation time 357338020 ps
CPU time 4.9 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 208844 kb
Host smart-6555fcce-73fe-4710-b805-ce9ed3e62cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648029262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2648029262
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1758292677
Short name T438
Test name
Test status
Simulation time 131351462 ps
CPU time 5.65 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:05 PM PDT 24
Peak memory 207408 kb
Host smart-c1617d89-207f-4043-a8d3-6b149eb296fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758292677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1758292677
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3863283300
Short name T790
Test name
Test status
Simulation time 1771772956 ps
CPU time 40.23 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:45 PM PDT 24
Peak memory 208956 kb
Host smart-ea35534f-b9da-412b-97ad-6f7f615238c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863283300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3863283300
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.598220400
Short name T431
Test name
Test status
Simulation time 151917241 ps
CPU time 2.43 seconds
Started Aug 15 05:50:58 PM PDT 24
Finished Aug 15 05:51:01 PM PDT 24
Peak memory 207228 kb
Host smart-898c3e50-3b5b-44db-a248-9a216b85b185
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598220400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.598220400
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2302085607
Short name T269
Test name
Test status
Simulation time 2564412880 ps
CPU time 50.91 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:51:45 PM PDT 24
Peak memory 218932 kb
Host smart-5867626f-0775-4ddb-8cee-664df01d6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302085607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2302085607
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3145625219
Short name T637
Test name
Test status
Simulation time 531333958 ps
CPU time 5.35 seconds
Started Aug 15 05:51:04 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 207292 kb
Host smart-2bfdea9e-d12d-4a47-9d60-82446c347630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145625219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3145625219
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3905768631
Short name T691
Test name
Test status
Simulation time 380289282 ps
CPU time 8.45 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 221040 kb
Host smart-32bb8c97-6e21-4591-ac6a-c246cf22b82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905768631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3905768631
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3654692049
Short name T210
Test name
Test status
Simulation time 146220004 ps
CPU time 5.64 seconds
Started Aug 15 05:50:59 PM PDT 24
Finished Aug 15 05:51:05 PM PDT 24
Peak memory 208304 kb
Host smart-78b66ef4-7da0-40c3-b0e8-f54e0170aaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654692049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3654692049
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.299795256
Short name T803
Test name
Test status
Simulation time 223452907 ps
CPU time 2.64 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 210828 kb
Host smart-7bcd5150-314a-4346-be85-65dfc39f885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299795256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.299795256
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2653631269
Short name T462
Test name
Test status
Simulation time 86317736 ps
CPU time 0.95 seconds
Started Aug 15 05:50:56 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 206524 kb
Host smart-578bc533-ca26-4003-8877-7eb05068341f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653631269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2653631269
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3162278189
Short name T316
Test name
Test status
Simulation time 32372336 ps
CPU time 2.68 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 214328 kb
Host smart-f4763467-7fa1-493e-aafd-72b2e83a79b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162278189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3162278189
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3592327863
Short name T664
Test name
Test status
Simulation time 287077242 ps
CPU time 3.53 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:04 PM PDT 24
Peak memory 210300 kb
Host smart-96e26fb8-eb4c-4148-9820-0abe5ef1a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592327863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3592327863
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.800893636
Short name T671
Test name
Test status
Simulation time 89990898 ps
CPU time 4.46 seconds
Started Aug 15 05:50:57 PM PDT 24
Finished Aug 15 05:51:02 PM PDT 24
Peak memory 222960 kb
Host smart-c4c5cd29-459d-4992-aeb5-f0e39457688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800893636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.800893636
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_random.275907440
Short name T287
Test name
Test status
Simulation time 513574308 ps
CPU time 5.48 seconds
Started Aug 15 05:51:00 PM PDT 24
Finished Aug 15 05:51:05 PM PDT 24
Peak memory 208808 kb
Host smart-8617aa58-cacb-4500-91dd-ed183f9fd055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275907440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.275907440
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1311699054
Short name T609
Test name
Test status
Simulation time 101527062 ps
CPU time 4.31 seconds
Started Aug 15 05:51:00 PM PDT 24
Finished Aug 15 05:51:04 PM PDT 24
Peak memory 207392 kb
Host smart-984866f4-3ad1-40a3-802d-e1052236e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311699054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1311699054
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.674810720
Short name T807
Test name
Test status
Simulation time 165113319 ps
CPU time 4.82 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:50:59 PM PDT 24
Peak memory 208620 kb
Host smart-32f45ec1-4440-487f-b27a-f7d7e5cd1c16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674810720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.674810720
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3600991760
Short name T727
Test name
Test status
Simulation time 86368988 ps
CPU time 3.27 seconds
Started Aug 15 05:51:00 PM PDT 24
Finished Aug 15 05:51:03 PM PDT 24
Peak memory 209004 kb
Host smart-af9be9f2-8329-44dd-b8c7-2d3aad0ebf9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600991760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3600991760
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2226790398
Short name T324
Test name
Test status
Simulation time 115328156 ps
CPU time 3.67 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 209224 kb
Host smart-52d0752d-d997-446d-98aa-3c93d3fb7ba3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226790398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2226790398
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3574804403
Short name T673
Test name
Test status
Simulation time 68770971 ps
CPU time 2.73 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 210476 kb
Host smart-0e427855-c4ee-4bef-a79f-3410659941c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574804403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3574804403
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1737900169
Short name T641
Test name
Test status
Simulation time 2467679482 ps
CPU time 15.33 seconds
Started Aug 15 05:50:52 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 208884 kb
Host smart-69ecf55a-98b2-41f5-b89d-d8fff76a1ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737900169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1737900169
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2588546388
Short name T895
Test name
Test status
Simulation time 265314729 ps
CPU time 4.95 seconds
Started Aug 15 05:50:56 PM PDT 24
Finished Aug 15 05:51:01 PM PDT 24
Peak memory 207344 kb
Host smart-440e667d-7a94-475d-8426-eb9dd4ae0a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588546388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2588546388
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2540021184
Short name T760
Test name
Test status
Simulation time 376284359 ps
CPU time 6.99 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:51:02 PM PDT 24
Peak memory 214764 kb
Host smart-17a890c5-dab4-46bc-ac32-2e89f0b0b47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540021184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2540021184
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2135272013
Short name T774
Test name
Test status
Simulation time 183580560 ps
CPU time 2.16 seconds
Started Aug 15 05:50:53 PM PDT 24
Finished Aug 15 05:50:56 PM PDT 24
Peak memory 210244 kb
Host smart-dc4de0b7-0434-4cd5-bf39-c7ce05efa638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135272013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2135272013
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2940708664
Short name T449
Test name
Test status
Simulation time 45704540 ps
CPU time 0.75 seconds
Started Aug 15 05:51:10 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 206316 kb
Host smart-2d929c25-162f-41c9-8b9c-4e5dcce541f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940708664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2940708664
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3784205379
Short name T151
Test name
Test status
Simulation time 31555703 ps
CPU time 2.24 seconds
Started Aug 15 05:51:00 PM PDT 24
Finished Aug 15 05:51:03 PM PDT 24
Peak memory 214748 kb
Host smart-50b1cceb-815b-4429-a7a1-b92c83b03fec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784205379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3784205379
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.607511918
Short name T855
Test name
Test status
Simulation time 649217892 ps
CPU time 5.38 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 209296 kb
Host smart-5505e123-d837-4f33-a872-22254965ad04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607511918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.607511918
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2022057433
Short name T841
Test name
Test status
Simulation time 2134792981 ps
CPU time 4.9 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 214696 kb
Host smart-df442292-03a8-40aa-9568-2dcdbcecdd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022057433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2022057433
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1110658593
Short name T844
Test name
Test status
Simulation time 478227263 ps
CPU time 5.33 seconds
Started Aug 15 05:51:10 PM PDT 24
Finished Aug 15 05:51:15 PM PDT 24
Peak memory 208472 kb
Host smart-162f05e7-2c79-44cd-bb64-163daab561a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110658593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1110658593
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1035168214
Short name T483
Test name
Test status
Simulation time 274798746 ps
CPU time 3.34 seconds
Started Aug 15 05:51:03 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 207572 kb
Host smart-7b194a3a-5d80-4ec4-ab02-56ce386c930e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035168214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1035168214
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.4215018727
Short name T120
Test name
Test status
Simulation time 201171367 ps
CPU time 3.64 seconds
Started Aug 15 05:51:18 PM PDT 24
Finished Aug 15 05:51:22 PM PDT 24
Peak memory 208880 kb
Host smart-7ddae279-6869-41dd-8b0c-3e2a55904890
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215018727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4215018727
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3334320007
Short name T405
Test name
Test status
Simulation time 197262170 ps
CPU time 3.27 seconds
Started Aug 15 05:51:10 PM PDT 24
Finished Aug 15 05:51:14 PM PDT 24
Peak memory 207364 kb
Host smart-4a26aa66-4901-4b1d-94ac-8ce12ee22daa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334320007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3334320007
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2305815311
Short name T757
Test name
Test status
Simulation time 925273021 ps
CPU time 12.41 seconds
Started Aug 15 05:51:04 PM PDT 24
Finished Aug 15 05:51:16 PM PDT 24
Peak memory 208464 kb
Host smart-15fb484f-fbd4-4e18-ab57-f6af5f50bd7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305815311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2305815311
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.929179052
Short name T145
Test name
Test status
Simulation time 45812040 ps
CPU time 1.88 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 208936 kb
Host smart-8275cc0c-db1f-4afe-ac8c-09769dc3b313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929179052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.929179052
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3012359930
Short name T700
Test name
Test status
Simulation time 426517189 ps
CPU time 2.6 seconds
Started Aug 15 05:50:58 PM PDT 24
Finished Aug 15 05:51:01 PM PDT 24
Peak memory 207772 kb
Host smart-e6bf75c1-6fe9-4e32-939a-657d58e110bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012359930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3012359930
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3800091104
Short name T655
Test name
Test status
Simulation time 1150795770 ps
CPU time 14.79 seconds
Started Aug 15 05:51:07 PM PDT 24
Finished Aug 15 05:51:22 PM PDT 24
Peak memory 217076 kb
Host smart-c2343930-057b-4a67-96d8-0ad4ff214732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800091104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3800091104
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1392206520
Short name T659
Test name
Test status
Simulation time 7370845004 ps
CPU time 60.59 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:52:09 PM PDT 24
Peak memory 209172 kb
Host smart-7a842b87-f2f6-456c-9717-bc507aea70db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392206520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1392206520
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2541447426
Short name T191
Test name
Test status
Simulation time 103770089 ps
CPU time 2.89 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:09 PM PDT 24
Peak memory 210272 kb
Host smart-e9ba642d-5db7-4be7-904c-94fb65f18cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541447426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2541447426
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1184579325
Short name T658
Test name
Test status
Simulation time 14872460 ps
CPU time 0.77 seconds
Started Aug 15 05:51:13 PM PDT 24
Finished Aug 15 05:51:14 PM PDT 24
Peak memory 206412 kb
Host smart-6f2b2346-ac0c-49bd-8e40-39315d35f6d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184579325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1184579325
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.4290572023
Short name T95
Test name
Test status
Simulation time 140805615 ps
CPU time 5.22 seconds
Started Aug 15 05:51:07 PM PDT 24
Finished Aug 15 05:51:13 PM PDT 24
Peak memory 215864 kb
Host smart-bbc8af19-38f4-46fe-88e5-c8c12aaa2faf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290572023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4290572023
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3091118601
Short name T897
Test name
Test status
Simulation time 183893803 ps
CPU time 2.82 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 222948 kb
Host smart-a3be9de1-257c-478d-9301-5e81fe92df86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091118601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3091118601
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2186154236
Short name T434
Test name
Test status
Simulation time 160451196 ps
CPU time 2.48 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 208660 kb
Host smart-1781f253-986d-44b4-b2b4-38e803e98484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186154236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2186154236
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1638455157
Short name T389
Test name
Test status
Simulation time 270557569 ps
CPU time 7.36 seconds
Started Aug 15 05:51:19 PM PDT 24
Finished Aug 15 05:51:26 PM PDT 24
Peak memory 221692 kb
Host smart-69597ea6-8eec-45ad-8f0e-102e462c9de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638455157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1638455157
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2655801349
Short name T569
Test name
Test status
Simulation time 106708831 ps
CPU time 5.18 seconds
Started Aug 15 05:51:10 PM PDT 24
Finished Aug 15 05:51:15 PM PDT 24
Peak memory 214680 kb
Host smart-06d787bc-9082-45b2-a012-26c91e24ca46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655801349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2655801349
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.847302285
Short name T226
Test name
Test status
Simulation time 61877621 ps
CPU time 2.02 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 215504 kb
Host smart-318ece2e-c616-4ac6-9ec2-0127a17b2d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847302285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.847302285
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.394612648
Short name T679
Test name
Test status
Simulation time 1363351048 ps
CPU time 20.88 seconds
Started Aug 15 05:51:14 PM PDT 24
Finished Aug 15 05:51:35 PM PDT 24
Peak memory 208856 kb
Host smart-1298e95d-0495-4358-b393-a9abf0a626d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394612648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.394612648
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2234832175
Short name T18
Test name
Test status
Simulation time 2455814779 ps
CPU time 28.15 seconds
Started Aug 15 05:51:12 PM PDT 24
Finished Aug 15 05:51:41 PM PDT 24
Peak memory 208500 kb
Host smart-60cde949-e1d1-4271-9f48-32c68b2f9b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234832175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2234832175
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2097666128
Short name T355
Test name
Test status
Simulation time 71700913 ps
CPU time 2.65 seconds
Started Aug 15 05:51:15 PM PDT 24
Finished Aug 15 05:51:18 PM PDT 24
Peak memory 209080 kb
Host smart-9da00892-9efa-4172-a3ba-dd9078a3de64
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097666128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2097666128
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1091172528
Short name T5
Test name
Test status
Simulation time 204312607 ps
CPU time 6.41 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:12 PM PDT 24
Peak memory 209304 kb
Host smart-240dded3-58f9-4404-9baf-9906cb832a3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091172528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1091172528
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.127028535
Short name T695
Test name
Test status
Simulation time 486453206 ps
CPU time 5.57 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 209008 kb
Host smart-625dfb0f-3f1b-4ac2-adc8-0202c16c308e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127028535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.127028535
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2637661409
Short name T532
Test name
Test status
Simulation time 30268490 ps
CPU time 2.25 seconds
Started Aug 15 05:51:01 PM PDT 24
Finished Aug 15 05:51:04 PM PDT 24
Peak memory 208216 kb
Host smart-28145d29-5dc0-4b1f-b817-b1a5d9298aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637661409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2637661409
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1229293010
Short name T404
Test name
Test status
Simulation time 168690437 ps
CPU time 4.08 seconds
Started Aug 15 05:51:07 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 208308 kb
Host smart-6b598c86-c8e2-4578-a423-03c3a12e5c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229293010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1229293010
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2839050266
Short name T205
Test name
Test status
Simulation time 1418780876 ps
CPU time 27.26 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:36 PM PDT 24
Peak memory 222944 kb
Host smart-635a009a-b9ac-4239-bf11-7fc3ab83e235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839050266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2839050266
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2514237727
Short name T86
Test name
Test status
Simulation time 254180174 ps
CPU time 16.33 seconds
Started Aug 15 05:51:03 PM PDT 24
Finished Aug 15 05:51:20 PM PDT 24
Peak memory 223036 kb
Host smart-f8d34074-c9ca-428e-9a39-64d36ae38c74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514237727 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2514237727
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3671896143
Short name T201
Test name
Test status
Simulation time 124447286 ps
CPU time 3.27 seconds
Started Aug 15 05:51:25 PM PDT 24
Finished Aug 15 05:51:28 PM PDT 24
Peak memory 210276 kb
Host smart-056b73c4-2ae1-407c-9103-dc1e45d72e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671896143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3671896143
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2367980827
Short name T622
Test name
Test status
Simulation time 134164622 ps
CPU time 2.12 seconds
Started Aug 15 05:51:05 PM PDT 24
Finished Aug 15 05:51:07 PM PDT 24
Peak memory 210036 kb
Host smart-62791785-c06d-466a-8c87-ddbc7df4cca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367980827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2367980827
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1513388402
Short name T430
Test name
Test status
Simulation time 57029560 ps
CPU time 1.04 seconds
Started Aug 15 05:51:24 PM PDT 24
Finished Aug 15 05:51:25 PM PDT 24
Peak memory 206488 kb
Host smart-c52f9f82-6bbe-4306-9712-f905bd850e82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513388402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1513388402
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2979553678
Short name T413
Test name
Test status
Simulation time 165611419 ps
CPU time 9.28 seconds
Started Aug 15 05:51:07 PM PDT 24
Finished Aug 15 05:51:16 PM PDT 24
Peak memory 215528 kb
Host smart-6330f40a-675f-46d5-9fbc-8df1963650b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979553678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2979553678
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.451981048
Short name T523
Test name
Test status
Simulation time 126660284 ps
CPU time 1.99 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 209420 kb
Host smart-30cf9859-6a5c-4435-9755-eeaa9527abdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451981048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.451981048
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2562638956
Short name T386
Test name
Test status
Simulation time 226134586 ps
CPU time 2.72 seconds
Started Aug 15 05:51:19 PM PDT 24
Finished Aug 15 05:51:22 PM PDT 24
Peak memory 208644 kb
Host smart-1e11bfc1-bd29-484f-b444-09bb84a8f3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562638956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2562638956
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3069551521
Short name T109
Test name
Test status
Simulation time 159241930 ps
CPU time 3.85 seconds
Started Aug 15 05:51:06 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 209232 kb
Host smart-408add90-7f47-4f0f-89e6-592851dc9db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069551521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3069551521
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sideload.87338718
Short name T828
Test name
Test status
Simulation time 367762402 ps
CPU time 7.25 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:16 PM PDT 24
Peak memory 209248 kb
Host smart-b15fbfc0-6566-4f78-9059-eb0832f99714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87338718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.87338718
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.368925846
Short name T220
Test name
Test status
Simulation time 450246526 ps
CPU time 3.67 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:12 PM PDT 24
Peak memory 209040 kb
Host smart-8bfaafd9-6486-4aa7-834c-db03916b2fee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368925846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.368925846
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3407040411
Short name T737
Test name
Test status
Simulation time 3745898551 ps
CPU time 38.82 seconds
Started Aug 15 05:51:24 PM PDT 24
Finished Aug 15 05:52:03 PM PDT 24
Peak memory 209652 kb
Host smart-228ceddb-9180-41a0-8032-af7a3c98d9e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407040411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3407040411
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1408856689
Short name T475
Test name
Test status
Simulation time 44015089 ps
CPU time 2.62 seconds
Started Aug 15 05:51:29 PM PDT 24
Finished Aug 15 05:51:32 PM PDT 24
Peak memory 207584 kb
Host smart-4a873ce9-1f9f-4aa2-bd56-2c4d0ac8284c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408856689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1408856689
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2514086680
Short name T453
Test name
Test status
Simulation time 55249752 ps
CPU time 3.05 seconds
Started Aug 15 05:51:07 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 218860 kb
Host smart-470778a6-398e-4c78-a480-674e298c9a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514086680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2514086680
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2207593684
Short name T779
Test name
Test status
Simulation time 191020232 ps
CPU time 2.9 seconds
Started Aug 15 05:51:11 PM PDT 24
Finished Aug 15 05:51:14 PM PDT 24
Peak memory 208716 kb
Host smart-299d948b-d53b-48d3-a254-2760b97c0f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207593684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2207593684
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.4002162613
Short name T318
Test name
Test status
Simulation time 546875866 ps
CPU time 24.5 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:33 PM PDT 24
Peak memory 216412 kb
Host smart-df46db58-cbbe-43e7-8f2a-9d3adb77f16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002162613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4002162613
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3856543866
Short name T650
Test name
Test status
Simulation time 188532163 ps
CPU time 2.84 seconds
Started Aug 15 05:51:12 PM PDT 24
Finished Aug 15 05:51:15 PM PDT 24
Peak memory 208640 kb
Host smart-fc12d964-1531-49ab-8a3c-df31811c131c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856543866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3856543866
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2147847514
Short name T42
Test name
Test status
Simulation time 114615889 ps
CPU time 1.82 seconds
Started Aug 15 05:51:13 PM PDT 24
Finished Aug 15 05:51:15 PM PDT 24
Peak memory 210848 kb
Host smart-93f6a2b8-54ea-47e0-8eca-a76efa497016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147847514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2147847514
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2782638840
Short name T738
Test name
Test status
Simulation time 12329163 ps
CPU time 0.72 seconds
Started Aug 15 05:50:39 PM PDT 24
Finished Aug 15 05:50:40 PM PDT 24
Peak memory 206388 kb
Host smart-0007b4f5-4a1f-4c54-b130-bfc0a6b41a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782638840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2782638840
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3885819077
Short name T639
Test name
Test status
Simulation time 56834108 ps
CPU time 1.48 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 214880 kb
Host smart-668aa0cd-0689-4408-bce1-6b0e3212f7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885819077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3885819077
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2298801409
Short name T765
Test name
Test status
Simulation time 105750141 ps
CPU time 2.83 seconds
Started Aug 15 05:50:28 PM PDT 24
Finished Aug 15 05:50:31 PM PDT 24
Peak memory 208552 kb
Host smart-151590a0-cb13-4e47-867f-7bdd66d77a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298801409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2298801409
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2465229494
Short name T254
Test name
Test status
Simulation time 29238097 ps
CPU time 2.02 seconds
Started Aug 15 05:50:28 PM PDT 24
Finished Aug 15 05:50:31 PM PDT 24
Peak memory 214780 kb
Host smart-5a25d1fd-638e-444c-927a-843b4a8e80e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465229494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2465229494
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1187367705
Short name T886
Test name
Test status
Simulation time 113052954 ps
CPU time 2.39 seconds
Started Aug 15 05:50:23 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 214664 kb
Host smart-d96554f4-2595-4648-bb8d-f0739c99e335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187367705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1187367705
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3809035574
Short name T783
Test name
Test status
Simulation time 261493738 ps
CPU time 2.98 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:25 PM PDT 24
Peak memory 209044 kb
Host smart-7ce3be86-b6e2-45b5-89bb-faf93d18bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809035574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3809035574
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1234595005
Short name T299
Test name
Test status
Simulation time 106049228 ps
CPU time 5.31 seconds
Started Aug 15 05:50:34 PM PDT 24
Finished Aug 15 05:50:40 PM PDT 24
Peak memory 214780 kb
Host smart-03471b60-eef2-4119-9f47-07e5a91089d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234595005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1234595005
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2407999255
Short name T649
Test name
Test status
Simulation time 79945944 ps
CPU time 2.42 seconds
Started Aug 15 05:50:24 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 207328 kb
Host smart-ba337daa-eda0-4d63-97f3-c91d8d1682f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407999255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2407999255
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1053785555
Short name T528
Test name
Test status
Simulation time 199735302 ps
CPU time 2.82 seconds
Started Aug 15 05:50:41 PM PDT 24
Finished Aug 15 05:50:44 PM PDT 24
Peak memory 207296 kb
Host smart-9b4ecd0f-5eb0-44b4-abb1-2b6744cf1de7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053785555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1053785555
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3685361781
Short name T290
Test name
Test status
Simulation time 826930747 ps
CPU time 19.42 seconds
Started Aug 15 05:50:24 PM PDT 24
Finished Aug 15 05:50:43 PM PDT 24
Peak memory 208616 kb
Host smart-8ebee5ac-20f3-4b27-9ba5-08defc72c15f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685361781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3685361781
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1577396651
Short name T282
Test name
Test status
Simulation time 289778934 ps
CPU time 4.34 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 209060 kb
Host smart-5f31bf04-0811-464c-b294-0aa3c47781d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577396651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1577396651
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1174743374
Short name T302
Test name
Test status
Simulation time 28508695 ps
CPU time 2.33 seconds
Started Aug 15 05:50:24 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 210696 kb
Host smart-8463d05c-c023-46e8-bb85-c04d10b41092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174743374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1174743374
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.566000689
Short name T117
Test name
Test status
Simulation time 209689241 ps
CPU time 2.82 seconds
Started Aug 15 05:50:25 PM PDT 24
Finished Aug 15 05:50:28 PM PDT 24
Peak memory 208968 kb
Host smart-bda01ebd-6b04-4064-8b6e-ab6e6f2a5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566000689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.566000689
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2452192065
Short name T235
Test name
Test status
Simulation time 521279181 ps
CPU time 17.66 seconds
Started Aug 15 05:50:36 PM PDT 24
Finished Aug 15 05:50:54 PM PDT 24
Peak memory 217376 kb
Host smart-54b58401-8679-41b8-b380-70df8c5650ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452192065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2452192065
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3606734088
Short name T218
Test name
Test status
Simulation time 159583058 ps
CPU time 4.05 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:25 PM PDT 24
Peak memory 209096 kb
Host smart-56f82037-5319-4887-8579-83159608d145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606734088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3606734088
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2481282493
Short name T192
Test name
Test status
Simulation time 72946993 ps
CPU time 2.1 seconds
Started Aug 15 05:50:33 PM PDT 24
Finished Aug 15 05:50:35 PM PDT 24
Peak memory 210400 kb
Host smart-cb3496ee-b881-4cfd-bf3a-c38fca3f7572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481282493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2481282493
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3673216361
Short name T905
Test name
Test status
Simulation time 30652034 ps
CPU time 0.8 seconds
Started Aug 15 05:51:18 PM PDT 24
Finished Aug 15 05:51:19 PM PDT 24
Peak memory 206376 kb
Host smart-a0be6978-b189-4fbc-b59f-dfb8862c2652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673216361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3673216361
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.4175488532
Short name T722
Test name
Test status
Simulation time 531907582 ps
CPU time 3.78 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:13 PM PDT 24
Peak memory 222136 kb
Host smart-6ebb59ff-acc9-4667-a1eb-0cc3f2d5e1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175488532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.4175488532
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.428897164
Short name T360
Test name
Test status
Simulation time 37869554 ps
CPU time 2.46 seconds
Started Aug 15 05:51:24 PM PDT 24
Finished Aug 15 05:51:26 PM PDT 24
Peak memory 208260 kb
Host smart-048164a7-f20d-4f1b-8450-d350af277e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428897164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.428897164
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2853232540
Short name T111
Test name
Test status
Simulation time 461996539 ps
CPU time 13.78 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:22 PM PDT 24
Peak memory 222840 kb
Host smart-e61f7de1-c861-435d-8a74-6d48df2cb36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853232540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2853232540
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2806468396
Short name T62
Test name
Test status
Simulation time 141695410 ps
CPU time 4.49 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:12 PM PDT 24
Peak memory 215036 kb
Host smart-a967235b-f635-4e62-bffb-f35db6e07de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806468396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2806468396
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1508914083
Short name T674
Test name
Test status
Simulation time 64279962 ps
CPU time 1.83 seconds
Started Aug 15 05:51:11 PM PDT 24
Finished Aug 15 05:51:13 PM PDT 24
Peak memory 214768 kb
Host smart-cc37b5e3-b3ce-4170-b820-f812bf54c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508914083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1508914083
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2048448004
Short name T267
Test name
Test status
Simulation time 123152933 ps
CPU time 2.58 seconds
Started Aug 15 05:51:15 PM PDT 24
Finished Aug 15 05:51:18 PM PDT 24
Peak memory 209628 kb
Host smart-33d02df5-5d5d-4e44-8d83-db23e2de4726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048448004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2048448004
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2264199950
Short name T707
Test name
Test status
Simulation time 134450078 ps
CPU time 3.29 seconds
Started Aug 15 05:51:15 PM PDT 24
Finished Aug 15 05:51:19 PM PDT 24
Peak memory 208856 kb
Host smart-9f18b8cf-4a12-43ec-8199-a8a5d6bf9437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264199950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2264199950
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.486340686
Short name T553
Test name
Test status
Simulation time 1251133392 ps
CPU time 3.39 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:12 PM PDT 24
Peak memory 209304 kb
Host smart-7f80b5a0-ef2c-4536-8277-80cb4cb8a6fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486340686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.486340686
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.689816156
Short name T877
Test name
Test status
Simulation time 99936534 ps
CPU time 3.28 seconds
Started Aug 15 05:51:21 PM PDT 24
Finished Aug 15 05:51:24 PM PDT 24
Peak memory 209552 kb
Host smart-adacaa99-5099-4d4a-a7cb-aa2fd370509f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689816156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.689816156
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3075080876
Short name T497
Test name
Test status
Simulation time 194313665 ps
CPU time 3.42 seconds
Started Aug 15 05:51:37 PM PDT 24
Finished Aug 15 05:51:41 PM PDT 24
Peak memory 207368 kb
Host smart-77e2d840-b10c-45a5-a5be-0801cf54fabe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075080876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3075080876
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4190094710
Short name T513
Test name
Test status
Simulation time 377854386 ps
CPU time 5.65 seconds
Started Aug 15 05:51:24 PM PDT 24
Finished Aug 15 05:51:30 PM PDT 24
Peak memory 208612 kb
Host smart-d1b0a8fe-05b3-46a2-8c72-5332702d21cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190094710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4190094710
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3620564618
Short name T603
Test name
Test status
Simulation time 156536416 ps
CPU time 2.01 seconds
Started Aug 15 05:51:27 PM PDT 24
Finished Aug 15 05:51:29 PM PDT 24
Peak memory 207296 kb
Host smart-41fac12b-dd11-43a3-ae43-2aac22093113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620564618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3620564618
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3154701381
Short name T579
Test name
Test status
Simulation time 8200931991 ps
CPU time 94.61 seconds
Started Aug 15 05:51:12 PM PDT 24
Finished Aug 15 05:52:47 PM PDT 24
Peak memory 208908 kb
Host smart-53171120-0d7e-4e59-8537-cedd7824b26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154701381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3154701381
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2460956412
Short name T736
Test name
Test status
Simulation time 988388308 ps
CPU time 9.3 seconds
Started Aug 15 05:51:23 PM PDT 24
Finished Aug 15 05:51:33 PM PDT 24
Peak memory 211520 kb
Host smart-8b6ec9b0-78e6-43f2-b1e6-6bbb9f8169bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460956412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2460956412
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.795582111
Short name T594
Test name
Test status
Simulation time 11661537 ps
CPU time 0.85 seconds
Started Aug 15 05:51:18 PM PDT 24
Finished Aug 15 05:51:19 PM PDT 24
Peak memory 206380 kb
Host smart-78f1d227-d1c7-4e53-9392-d8bb1d317c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795582111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.795582111
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2420787902
Short name T348
Test name
Test status
Simulation time 185853569 ps
CPU time 3.72 seconds
Started Aug 15 05:51:10 PM PDT 24
Finished Aug 15 05:51:14 PM PDT 24
Peak memory 214760 kb
Host smart-bab49112-27b2-4562-829c-e8d7cfa1e489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420787902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2420787902
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2955827120
Short name T50
Test name
Test status
Simulation time 97532763 ps
CPU time 4.39 seconds
Started Aug 15 05:51:22 PM PDT 24
Finished Aug 15 05:51:26 PM PDT 24
Peak memory 210452 kb
Host smart-2c461902-14b1-493a-9d5e-e835424d3094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955827120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2955827120
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2692346234
Short name T730
Test name
Test status
Simulation time 58575792 ps
CPU time 1.78 seconds
Started Aug 15 05:51:20 PM PDT 24
Finished Aug 15 05:51:22 PM PDT 24
Peak memory 214820 kb
Host smart-bb40fcda-7eba-4b40-8d9c-183d5d234519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692346234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2692346234
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3232880304
Short name T69
Test name
Test status
Simulation time 85661982 ps
CPU time 2.36 seconds
Started Aug 15 05:51:20 PM PDT 24
Finished Aug 15 05:51:23 PM PDT 24
Peak memory 208264 kb
Host smart-91d51ae4-d694-4deb-9153-07ea0936df64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232880304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3232880304
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1758823301
Short name T808
Test name
Test status
Simulation time 915217936 ps
CPU time 7.52 seconds
Started Aug 15 05:51:29 PM PDT 24
Finished Aug 15 05:51:36 PM PDT 24
Peak memory 208620 kb
Host smart-296efdfc-3f30-4ea3-9bef-d539a9b4b133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758823301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1758823301
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.581458556
Short name T660
Test name
Test status
Simulation time 49123438 ps
CPU time 2.83 seconds
Started Aug 15 05:51:28 PM PDT 24
Finished Aug 15 05:51:31 PM PDT 24
Peak memory 207360 kb
Host smart-d559cd81-3355-4954-96ef-bc7feba4d62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581458556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.581458556
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2106719715
Short name T530
Test name
Test status
Simulation time 49440787 ps
CPU time 2.69 seconds
Started Aug 15 05:51:28 PM PDT 24
Finished Aug 15 05:51:31 PM PDT 24
Peak memory 207336 kb
Host smart-a4b254a7-f5e1-4c8b-bbe8-500e9ded6c2e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106719715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2106719715
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3766056811
Short name T632
Test name
Test status
Simulation time 702524425 ps
CPU time 8.04 seconds
Started Aug 15 05:51:27 PM PDT 24
Finished Aug 15 05:51:35 PM PDT 24
Peak memory 209304 kb
Host smart-cc4c7636-846d-44f0-b0ca-e5f328754e6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766056811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3766056811
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3252992806
Short name T715
Test name
Test status
Simulation time 70788502 ps
CPU time 3.15 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 209204 kb
Host smart-a132bfbb-0dd5-4da3-b9a8-9ff53f2e29c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252992806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3252992806
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2272588225
Short name T665
Test name
Test status
Simulation time 1406874218 ps
CPU time 20.23 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:29 PM PDT 24
Peak memory 210156 kb
Host smart-9d3a864d-9f46-4a70-be87-98db34e07efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272588225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2272588225
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3163160710
Short name T766
Test name
Test status
Simulation time 77903771 ps
CPU time 3.17 seconds
Started Aug 15 05:51:22 PM PDT 24
Finished Aug 15 05:51:25 PM PDT 24
Peak memory 209128 kb
Host smart-77fcda83-c1a1-42fa-b26a-c561acf5ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163160710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3163160710
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2601768773
Short name T574
Test name
Test status
Simulation time 221171620 ps
CPU time 5.78 seconds
Started Aug 15 05:51:24 PM PDT 24
Finished Aug 15 05:51:30 PM PDT 24
Peak memory 208912 kb
Host smart-3b7f9fb6-d75c-4268-87b6-a7f0119add2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601768773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2601768773
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.832150271
Short name T823
Test name
Test status
Simulation time 1028310047 ps
CPU time 6.56 seconds
Started Aug 15 05:51:23 PM PDT 24
Finished Aug 15 05:51:30 PM PDT 24
Peak memory 214684 kb
Host smart-45ec1c63-f678-41d2-9c74-74bf5eed3ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832150271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.832150271
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3044863815
Short name T555
Test name
Test status
Simulation time 119869461 ps
CPU time 2.3 seconds
Started Aug 15 05:51:31 PM PDT 24
Finished Aug 15 05:51:34 PM PDT 24
Peak memory 210760 kb
Host smart-b6b53383-b9c8-4612-9bca-b995d2d382ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044863815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3044863815
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1743012337
Short name T424
Test name
Test status
Simulation time 15189242 ps
CPU time 0.78 seconds
Started Aug 15 05:51:16 PM PDT 24
Finished Aug 15 05:51:22 PM PDT 24
Peak memory 206372 kb
Host smart-9b0561df-1ec2-4d8f-beb6-44a967155184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743012337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1743012337
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1176547340
Short name T407
Test name
Test status
Simulation time 35393914 ps
CPU time 2.47 seconds
Started Aug 15 05:51:14 PM PDT 24
Finished Aug 15 05:51:16 PM PDT 24
Peak memory 214692 kb
Host smart-b37378f3-4ed2-46fd-94c8-6f79758e5989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176547340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1176547340
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2856777030
Short name T19
Test name
Test status
Simulation time 258501667 ps
CPU time 6.24 seconds
Started Aug 15 05:51:20 PM PDT 24
Finished Aug 15 05:51:26 PM PDT 24
Peak memory 223244 kb
Host smart-480696df-bb0b-4f29-bcf5-ec35d9ddd8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856777030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2856777030
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1140600881
Short name T293
Test name
Test status
Simulation time 32628198 ps
CPU time 2.21 seconds
Started Aug 15 05:51:32 PM PDT 24
Finished Aug 15 05:51:34 PM PDT 24
Peak memory 207932 kb
Host smart-335fffb5-9445-4c86-820a-24e1364f3152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140600881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1140600881
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.4096335120
Short name T107
Test name
Test status
Simulation time 33619501 ps
CPU time 2.59 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:12 PM PDT 24
Peak memory 214740 kb
Host smart-d3c1b8ea-d13f-45ed-be50-950518e11c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096335120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.4096335120
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3256551072
Short name T310
Test name
Test status
Simulation time 111005206 ps
CPU time 1.86 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 206520 kb
Host smart-1b9e1c5a-235a-4aad-bf05-ad313597c3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256551072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3256551072
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3536437058
Short name T525
Test name
Test status
Simulation time 86531774 ps
CPU time 4.16 seconds
Started Aug 15 05:51:32 PM PDT 24
Finished Aug 15 05:51:36 PM PDT 24
Peak memory 215732 kb
Host smart-5f54ad1b-886b-4cae-8547-2e1c9ffb709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536437058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3536437058
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1030226113
Short name T865
Test name
Test status
Simulation time 203471327 ps
CPU time 4.02 seconds
Started Aug 15 05:51:32 PM PDT 24
Finished Aug 15 05:51:36 PM PDT 24
Peak memory 208656 kb
Host smart-0561f6a2-557d-47b6-aed5-39b1c667e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030226113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1030226113
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1524388624
Short name T503
Test name
Test status
Simulation time 94000396 ps
CPU time 2.35 seconds
Started Aug 15 05:51:26 PM PDT 24
Finished Aug 15 05:51:28 PM PDT 24
Peak memory 207176 kb
Host smart-2d8d30da-bee8-487d-83cc-907b81f37e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524388624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1524388624
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2338804170
Short name T651
Test name
Test status
Simulation time 38081833 ps
CPU time 2.62 seconds
Started Aug 15 05:51:18 PM PDT 24
Finished Aug 15 05:51:20 PM PDT 24
Peak memory 209060 kb
Host smart-87204f7f-a3da-4749-a9dd-2601bdf828d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338804170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2338804170
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.856829878
Short name T272
Test name
Test status
Simulation time 62384981 ps
CPU time 3.09 seconds
Started Aug 15 05:51:18 PM PDT 24
Finished Aug 15 05:51:21 PM PDT 24
Peak memory 209184 kb
Host smart-4a8c7925-3936-4287-a286-6910bce5f533
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856829878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.856829878
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2598477556
Short name T221
Test name
Test status
Simulation time 865718826 ps
CPU time 6.79 seconds
Started Aug 15 05:51:17 PM PDT 24
Finished Aug 15 05:51:24 PM PDT 24
Peak memory 208408 kb
Host smart-8eac12ae-6cb7-4dfb-92fa-a05ca81db77e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598477556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2598477556
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3706281041
Short name T219
Test name
Test status
Simulation time 225692544 ps
CPU time 3.11 seconds
Started Aug 15 05:51:08 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 216368 kb
Host smart-4900c7ca-3b89-49a4-be7f-47c835ca336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706281041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3706281041
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3230810034
Short name T531
Test name
Test status
Simulation time 86359229 ps
CPU time 3.33 seconds
Started Aug 15 05:51:16 PM PDT 24
Finished Aug 15 05:51:19 PM PDT 24
Peak memory 209100 kb
Host smart-4d0e3626-7d9c-4413-a4ad-faed809660bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230810034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3230810034
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.245667621
Short name T857
Test name
Test status
Simulation time 340188934 ps
CPU time 11.65 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:21 PM PDT 24
Peak memory 216276 kb
Host smart-edf62507-00cb-4310-b030-fc04e33e4ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245667621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.245667621
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3384430742
Short name T507
Test name
Test status
Simulation time 478652392 ps
CPU time 7.18 seconds
Started Aug 15 05:51:10 PM PDT 24
Finished Aug 15 05:51:18 PM PDT 24
Peak memory 208164 kb
Host smart-934e813e-c39e-4f87-a71b-b31738626c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384430742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3384430742
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1488502069
Short name T845
Test name
Test status
Simulation time 32710346 ps
CPU time 1.82 seconds
Started Aug 15 05:51:23 PM PDT 24
Finished Aug 15 05:51:25 PM PDT 24
Peak memory 210552 kb
Host smart-83e6d0eb-048c-4b69-aaa8-e86b66ae25a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488502069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1488502069
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3338561803
Short name T849
Test name
Test status
Simulation time 25378365 ps
CPU time 0.77 seconds
Started Aug 15 05:51:18 PM PDT 24
Finished Aug 15 05:51:19 PM PDT 24
Peak memory 206396 kb
Host smart-ccbabec6-30fe-44c9-95b9-d37eae666b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338561803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3338561803
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3310472791
Short name T412
Test name
Test status
Simulation time 11433455809 ps
CPU time 72.19 seconds
Started Aug 15 05:51:23 PM PDT 24
Finished Aug 15 05:52:35 PM PDT 24
Peak memory 215056 kb
Host smart-0b286f00-076a-40d4-b2d5-f871f0f9ce46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310472791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3310472791
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2461727110
Short name T46
Test name
Test status
Simulation time 147429201 ps
CPU time 1.31 seconds
Started Aug 15 05:51:35 PM PDT 24
Finished Aug 15 05:51:37 PM PDT 24
Peak memory 218760 kb
Host smart-8d93ca7b-06f8-4016-baa9-63587e6ddace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461727110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2461727110
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1401237176
Short name T643
Test name
Test status
Simulation time 35835515 ps
CPU time 2.15 seconds
Started Aug 15 05:51:17 PM PDT 24
Finished Aug 15 05:51:19 PM PDT 24
Peak memory 214848 kb
Host smart-2a1ff52f-7e8b-49fa-bb08-8c45631f0edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401237176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1401237176
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3935855093
Short name T798
Test name
Test status
Simulation time 717283655 ps
CPU time 8.15 seconds
Started Aug 15 05:51:37 PM PDT 24
Finished Aug 15 05:51:45 PM PDT 24
Peak memory 222860 kb
Host smart-ff96213a-b800-4758-8131-16d9d3a93e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935855093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3935855093
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3753886164
Short name T601
Test name
Test status
Simulation time 44063251 ps
CPU time 3.02 seconds
Started Aug 15 05:51:18 PM PDT 24
Finished Aug 15 05:51:26 PM PDT 24
Peak memory 214840 kb
Host smart-f982c80d-5017-4cab-a429-6ed33d80945e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753886164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3753886164
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.275033472
Short name T773
Test name
Test status
Simulation time 101549283 ps
CPU time 4.31 seconds
Started Aug 15 05:51:34 PM PDT 24
Finished Aug 15 05:51:39 PM PDT 24
Peak memory 208536 kb
Host smart-289a3399-c5b6-4374-9b03-5c75a355f939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275033472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.275033472
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2603368899
Short name T460
Test name
Test status
Simulation time 132774765 ps
CPU time 2.48 seconds
Started Aug 15 05:51:38 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 207452 kb
Host smart-906251e0-49c4-47f6-af98-a745e6375eb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603368899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2603368899
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2768407399
Short name T758
Test name
Test status
Simulation time 992283392 ps
CPU time 6.31 seconds
Started Aug 15 05:51:23 PM PDT 24
Finished Aug 15 05:51:29 PM PDT 24
Peak memory 209408 kb
Host smart-c75a0566-030a-479b-b8f0-3664221859a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768407399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2768407399
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3787887840
Short name T608
Test name
Test status
Simulation time 48567457 ps
CPU time 2.8 seconds
Started Aug 15 05:51:37 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 207468 kb
Host smart-e1293e81-ff8f-4511-8b7c-56c8005147cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787887840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3787887840
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1381900459
Short name T247
Test name
Test status
Simulation time 259012291 ps
CPU time 2.26 seconds
Started Aug 15 05:51:16 PM PDT 24
Finished Aug 15 05:51:18 PM PDT 24
Peak memory 210084 kb
Host smart-2aa01f60-b076-45bd-b8f1-53c9ffaf138c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381900459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1381900459
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.4080492405
Short name T836
Test name
Test status
Simulation time 116457164 ps
CPU time 2.39 seconds
Started Aug 15 05:51:21 PM PDT 24
Finished Aug 15 05:51:24 PM PDT 24
Peak memory 207316 kb
Host smart-daa9245b-aa2a-4cd3-aff9-73b9307a7019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080492405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.4080492405
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2723587842
Short name T883
Test name
Test status
Simulation time 425591553 ps
CPU time 7.64 seconds
Started Aug 15 05:51:34 PM PDT 24
Finished Aug 15 05:51:42 PM PDT 24
Peak memory 209732 kb
Host smart-0c339980-8801-4758-a74a-676c3b0e926f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723587842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2723587842
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1964322400
Short name T215
Test name
Test status
Simulation time 656667444 ps
CPU time 5.79 seconds
Started Aug 15 05:51:42 PM PDT 24
Finished Aug 15 05:51:48 PM PDT 24
Peak memory 210804 kb
Host smart-e7a8bd39-7f2e-466a-a82e-9f22b2153cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964322400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1964322400
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3368093553
Short name T596
Test name
Test status
Simulation time 79342833 ps
CPU time 2.3 seconds
Started Aug 15 05:51:20 PM PDT 24
Finished Aug 15 05:51:22 PM PDT 24
Peak memory 210584 kb
Host smart-daff605b-2d48-44a1-a0af-228eeb0e5f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368093553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3368093553
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3078649012
Short name T487
Test name
Test status
Simulation time 22013483 ps
CPU time 0.71 seconds
Started Aug 15 05:51:20 PM PDT 24
Finished Aug 15 05:51:21 PM PDT 24
Peak memory 206372 kb
Host smart-d48c0428-858f-4270-8345-6fe77ef31293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078649012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3078649012
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.596997282
Short name T31
Test name
Test status
Simulation time 193793957 ps
CPU time 2.29 seconds
Started Aug 15 05:51:21 PM PDT 24
Finished Aug 15 05:51:23 PM PDT 24
Peak memory 218644 kb
Host smart-bacb4933-2542-433b-b0b3-e4e6e75dbb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596997282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.596997282
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1818792836
Short name T560
Test name
Test status
Simulation time 84777032 ps
CPU time 1.39 seconds
Started Aug 15 05:51:22 PM PDT 24
Finished Aug 15 05:51:23 PM PDT 24
Peak memory 208148 kb
Host smart-edda77c8-4ea6-47c6-9e7e-8acbbf6a65e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818792836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1818792836
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.382023611
Short name T387
Test name
Test status
Simulation time 4973786526 ps
CPU time 26.71 seconds
Started Aug 15 05:51:28 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 220028 kb
Host smart-bc9fe317-78e8-47b1-86fe-48e7eaffa577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382023611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.382023611
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2752077779
Short name T231
Test name
Test status
Simulation time 85358605 ps
CPU time 3.99 seconds
Started Aug 15 05:51:39 PM PDT 24
Finished Aug 15 05:51:43 PM PDT 24
Peak memory 209608 kb
Host smart-2eed6702-07a6-45ee-891e-d660b74d9e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752077779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2752077779
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.502841170
Short name T755
Test name
Test status
Simulation time 40039250 ps
CPU time 2.46 seconds
Started Aug 15 05:51:27 PM PDT 24
Finished Aug 15 05:51:30 PM PDT 24
Peak memory 207976 kb
Host smart-445eb7cf-d596-4ac3-8b2d-b2d3e3662a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502841170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.502841170
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3086971994
Short name T630
Test name
Test status
Simulation time 898124963 ps
CPU time 10.36 seconds
Started Aug 15 05:51:22 PM PDT 24
Finished Aug 15 05:51:32 PM PDT 24
Peak memory 208928 kb
Host smart-fae1ecd2-a6b4-4662-9535-17fd5784ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086971994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3086971994
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1917888057
Short name T820
Test name
Test status
Simulation time 76414865 ps
CPU time 2.99 seconds
Started Aug 15 05:51:36 PM PDT 24
Finished Aug 15 05:51:39 PM PDT 24
Peak memory 209024 kb
Host smart-42657e40-4698-4fef-b7b3-f63a13effb48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917888057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1917888057
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1617140258
Short name T441
Test name
Test status
Simulation time 20128553 ps
CPU time 1.84 seconds
Started Aug 15 05:51:18 PM PDT 24
Finished Aug 15 05:51:20 PM PDT 24
Peak memory 207252 kb
Host smart-1e6714f0-a940-495c-96f9-572a4655f3f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617140258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1617140258
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2944840910
Short name T785
Test name
Test status
Simulation time 2813186692 ps
CPU time 28.08 seconds
Started Aug 15 05:51:40 PM PDT 24
Finished Aug 15 05:52:08 PM PDT 24
Peak memory 209656 kb
Host smart-b38dd6f1-884c-497d-acb4-ec14bbd3e981
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944840910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2944840910
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3363466640
Short name T677
Test name
Test status
Simulation time 109779564 ps
CPU time 2.74 seconds
Started Aug 15 05:51:21 PM PDT 24
Finished Aug 15 05:51:24 PM PDT 24
Peak memory 209588 kb
Host smart-0e985223-3ce6-4cf4-8166-a852a756adb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363466640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3363466640
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3395040365
Short name T838
Test name
Test status
Simulation time 56585162 ps
CPU time 2.34 seconds
Started Aug 15 05:51:37 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 207292 kb
Host smart-15e399fd-e01e-4cfc-a7e3-6d30fe363a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395040365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3395040365
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2882834204
Short name T266
Test name
Test status
Simulation time 1124126819 ps
CPU time 11.62 seconds
Started Aug 15 05:51:33 PM PDT 24
Finished Aug 15 05:51:44 PM PDT 24
Peak memory 223088 kb
Host smart-d66e1794-bd8f-435c-8404-bf8705de1564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882834204 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2882834204
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1671341618
Short name T300
Test name
Test status
Simulation time 225339008 ps
CPU time 6.64 seconds
Started Aug 15 05:51:34 PM PDT 24
Finished Aug 15 05:51:41 PM PDT 24
Peak memory 214836 kb
Host smart-313d00e1-6eae-4b1a-807b-6210f2b707fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671341618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1671341618
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2316133795
Short name T393
Test name
Test status
Simulation time 36041849 ps
CPU time 2 seconds
Started Aug 15 05:51:27 PM PDT 24
Finished Aug 15 05:51:29 PM PDT 24
Peak memory 210384 kb
Host smart-72c5e5cd-aa0c-4aba-8585-40ad5f92ab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316133795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2316133795
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3466568531
Short name T911
Test name
Test status
Simulation time 106307082 ps
CPU time 0.74 seconds
Started Aug 15 05:51:29 PM PDT 24
Finished Aug 15 05:51:30 PM PDT 24
Peak memory 206404 kb
Host smart-10bab285-554c-4e75-8efd-ea8cd7680d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466568531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3466568531
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1215008531
Short name T891
Test name
Test status
Simulation time 83257848 ps
CPU time 4.37 seconds
Started Aug 15 05:51:35 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 214840 kb
Host smart-150306c6-7bc1-461d-b737-5ea2cad44ec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215008531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1215008531
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.792755965
Short name T474
Test name
Test status
Simulation time 70949226 ps
CPU time 3.19 seconds
Started Aug 15 05:51:42 PM PDT 24
Finished Aug 15 05:51:45 PM PDT 24
Peak memory 210808 kb
Host smart-147852b1-d0c5-480a-87e3-e68d9e158039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792755965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.792755965
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2065055055
Short name T485
Test name
Test status
Simulation time 1165055862 ps
CPU time 9.77 seconds
Started Aug 15 05:51:35 PM PDT 24
Finished Aug 15 05:51:45 PM PDT 24
Peak memory 222852 kb
Host smart-ea258757-e90e-4ee7-8868-f501beff6329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065055055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2065055055
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1769157195
Short name T539
Test name
Test status
Simulation time 151927481 ps
CPU time 3.64 seconds
Started Aug 15 05:51:27 PM PDT 24
Finished Aug 15 05:51:30 PM PDT 24
Peak memory 215212 kb
Host smart-9daf2e37-2929-4149-a3e4-618bcce26173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769157195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1769157195
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2609104471
Short name T657
Test name
Test status
Simulation time 53927718 ps
CPU time 3.28 seconds
Started Aug 15 05:51:37 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 208976 kb
Host smart-be60e8e0-34f4-4397-b0f9-bcdff16af116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609104471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2609104471
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1434291640
Short name T842
Test name
Test status
Simulation time 1583190764 ps
CPU time 9.36 seconds
Started Aug 15 05:51:31 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 208880 kb
Host smart-c630b36f-bbf8-4d2b-b505-5173f0f99100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434291640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1434291640
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3070989001
Short name T698
Test name
Test status
Simulation time 346057722 ps
CPU time 3.72 seconds
Started Aug 15 05:51:32 PM PDT 24
Finished Aug 15 05:51:36 PM PDT 24
Peak memory 209488 kb
Host smart-ac01bb1c-c723-450b-a550-a1e887ecfa7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070989001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3070989001
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.962952139
Short name T526
Test name
Test status
Simulation time 48966910 ps
CPU time 2.79 seconds
Started Aug 15 05:51:31 PM PDT 24
Finished Aug 15 05:51:33 PM PDT 24
Peak memory 207408 kb
Host smart-89526bc7-7be1-4804-8e24-038bdc097f51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962952139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.962952139
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.634936073
Short name T222
Test name
Test status
Simulation time 111603878 ps
CPU time 2.99 seconds
Started Aug 15 05:51:36 PM PDT 24
Finished Aug 15 05:51:39 PM PDT 24
Peak memory 208564 kb
Host smart-406c12d4-3313-47c7-b423-56dff3ab3c75
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634936073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.634936073
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.4230423251
Short name T748
Test name
Test status
Simulation time 30925873 ps
CPU time 1.48 seconds
Started Aug 15 05:51:20 PM PDT 24
Finished Aug 15 05:51:21 PM PDT 24
Peak memory 208544 kb
Host smart-05666e2d-d6e3-420d-8459-2f08604b7a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230423251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.4230423251
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1150389129
Short name T696
Test name
Test status
Simulation time 54840526 ps
CPU time 2.58 seconds
Started Aug 15 05:51:28 PM PDT 24
Finished Aug 15 05:51:30 PM PDT 24
Peak memory 208708 kb
Host smart-8db43af1-8a68-4299-9999-6b0613e91dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150389129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1150389129
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.355995107
Short name T264
Test name
Test status
Simulation time 1950266232 ps
CPU time 37.63 seconds
Started Aug 15 05:51:29 PM PDT 24
Finished Aug 15 05:52:07 PM PDT 24
Peak memory 215588 kb
Host smart-c1e5b0b6-179f-4a4e-b9c6-682a125d45ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355995107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.355995107
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2586372799
Short name T826
Test name
Test status
Simulation time 51669442 ps
CPU time 2.4 seconds
Started Aug 15 05:51:40 PM PDT 24
Finished Aug 15 05:51:43 PM PDT 24
Peak memory 210572 kb
Host smart-3efa2c1c-fcb1-4b28-858b-83f16a740117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586372799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2586372799
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1018113469
Short name T631
Test name
Test status
Simulation time 59694023 ps
CPU time 0.83 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:45 PM PDT 24
Peak memory 206396 kb
Host smart-23a94b5b-02da-47b9-93a4-aa6cf9b8d87d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018113469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1018113469
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2120300822
Short name T420
Test name
Test status
Simulation time 805935383 ps
CPU time 12.09 seconds
Started Aug 15 05:51:39 PM PDT 24
Finished Aug 15 05:51:51 PM PDT 24
Peak memory 214940 kb
Host smart-d36c3491-6dca-4256-b5a0-bd5736633c2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120300822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2120300822
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.4197351966
Short name T759
Test name
Test status
Simulation time 189201853 ps
CPU time 3.35 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:52 PM PDT 24
Peak memory 220496 kb
Host smart-a73fe154-03a0-422a-bf03-d045d484d11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197351966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4197351966
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2343353119
Short name T319
Test name
Test status
Simulation time 552163070 ps
CPU time 7.4 seconds
Started Aug 15 05:51:35 PM PDT 24
Finished Aug 15 05:51:42 PM PDT 24
Peak memory 220144 kb
Host smart-322dea1b-712a-4858-90df-a08ebf6b8f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343353119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2343353119
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2222122874
Short name T734
Test name
Test status
Simulation time 126291562 ps
CPU time 2.35 seconds
Started Aug 15 05:51:41 PM PDT 24
Finished Aug 15 05:51:43 PM PDT 24
Peak memory 215084 kb
Host smart-55957e71-f6cb-4edb-a221-5c703019810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222122874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2222122874
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.4191899794
Short name T728
Test name
Test status
Simulation time 936208816 ps
CPU time 3.58 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 214636 kb
Host smart-9dc56500-0138-47eb-a2aa-1d855a195c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191899794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.4191899794
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3118073549
Short name T244
Test name
Test status
Simulation time 179196455 ps
CPU time 4.25 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:48 PM PDT 24
Peak memory 220740 kb
Host smart-5b5d545f-941e-4775-8a95-0f77faea95b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118073549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3118073549
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3464481242
Short name T490
Test name
Test status
Simulation time 41773223 ps
CPU time 3.03 seconds
Started Aug 15 05:51:40 PM PDT 24
Finished Aug 15 05:51:44 PM PDT 24
Peak memory 210340 kb
Host smart-dea7bb9e-7df0-496f-8e89-233e59602136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464481242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3464481242
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.909907881
Short name T326
Test name
Test status
Simulation time 1348010713 ps
CPU time 9.38 seconds
Started Aug 15 05:51:27 PM PDT 24
Finished Aug 15 05:51:37 PM PDT 24
Peak memory 208524 kb
Host smart-8d1e8d3d-b99b-481e-ac75-b7d98fa5aa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909907881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.909907881
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2126279268
Short name T672
Test name
Test status
Simulation time 183884921 ps
CPU time 5.27 seconds
Started Aug 15 05:51:35 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 208440 kb
Host smart-8f6e47bc-0720-4d95-bbe6-fe4223f8a531
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126279268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2126279268
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2125442837
Short name T623
Test name
Test status
Simulation time 494060725 ps
CPU time 3.32 seconds
Started Aug 15 05:51:32 PM PDT 24
Finished Aug 15 05:51:36 PM PDT 24
Peak memory 208968 kb
Host smart-bf612e62-80ad-44d8-b1ae-3db7d8d133b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125442837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2125442837
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3847853118
Short name T315
Test name
Test status
Simulation time 2540058621 ps
CPU time 8.38 seconds
Started Aug 15 05:51:33 PM PDT 24
Finished Aug 15 05:51:42 PM PDT 24
Peak memory 209344 kb
Host smart-6dcc05c4-6e09-498e-9a4e-e7f7cc6574fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847853118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3847853118
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2962131960
Short name T581
Test name
Test status
Simulation time 332926118 ps
CPU time 2.12 seconds
Started Aug 15 05:51:36 PM PDT 24
Finished Aug 15 05:51:38 PM PDT 24
Peak memory 208548 kb
Host smart-09bc4196-6724-460b-97fb-92fc760dbcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962131960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2962131960
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.4115824962
Short name T600
Test name
Test status
Simulation time 130577076 ps
CPU time 2.24 seconds
Started Aug 15 05:51:37 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 207252 kb
Host smart-81c81e3f-cb01-492c-906e-631e52c4a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115824962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4115824962
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3193191234
Short name T141
Test name
Test status
Simulation time 614694657 ps
CPU time 17.19 seconds
Started Aug 15 05:51:38 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 223072 kb
Host smart-fe3c734a-2ce6-49c2-83b5-b75f23b61804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193191234 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3193191234
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4112189101
Short name T602
Test name
Test status
Simulation time 86990037 ps
CPU time 3.28 seconds
Started Aug 15 05:51:42 PM PDT 24
Finished Aug 15 05:51:46 PM PDT 24
Peak memory 207744 kb
Host smart-2cf71887-15c4-42db-ab03-60425581322b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112189101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4112189101
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1069542769
Short name T731
Test name
Test status
Simulation time 419791112 ps
CPU time 7.4 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 211180 kb
Host smart-b8daaf9b-fbe3-4201-bf0e-b4562096facb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069542769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1069542769
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.368688510
Short name T463
Test name
Test status
Simulation time 11623883 ps
CPU time 0.84 seconds
Started Aug 15 05:51:33 PM PDT 24
Finished Aug 15 05:51:34 PM PDT 24
Peak memory 206428 kb
Host smart-7c810583-49d5-4205-9d9c-112af6d7cec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368688510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.368688510
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1583742686
Short name T150
Test name
Test status
Simulation time 136043012 ps
CPU time 3.63 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:48 PM PDT 24
Peak memory 214756 kb
Host smart-608e0080-52e5-4360-adab-cc28ba42bf17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583742686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1583742686
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1518752943
Short name T45
Test name
Test status
Simulation time 76921867 ps
CPU time 3.36 seconds
Started Aug 15 05:51:40 PM PDT 24
Finished Aug 15 05:51:43 PM PDT 24
Peak memory 209520 kb
Host smart-f0d74131-bba1-4403-8f07-a1befda5798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518752943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1518752943
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1503359616
Short name T88
Test name
Test status
Simulation time 1366036707 ps
CPU time 33.78 seconds
Started Aug 15 05:51:41 PM PDT 24
Finished Aug 15 05:52:15 PM PDT 24
Peak memory 214772 kb
Host smart-83b1580d-2798-4fcc-98f1-48f8e0ace2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503359616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1503359616
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3626520974
Short name T105
Test name
Test status
Simulation time 66376106 ps
CPU time 2.49 seconds
Started Aug 15 05:51:41 PM PDT 24
Finished Aug 15 05:51:43 PM PDT 24
Peak memory 214744 kb
Host smart-fe3e23d4-468e-487b-a9d8-994676bd8b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626520974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3626520974
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1795432249
Short name T604
Test name
Test status
Simulation time 59177273 ps
CPU time 3.53 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:52 PM PDT 24
Peak memory 214648 kb
Host smart-e01b140c-e396-440c-b034-1341ff79d5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795432249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1795432249
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_random.3347601029
Short name T871
Test name
Test status
Simulation time 27548865 ps
CPU time 2.26 seconds
Started Aug 15 05:51:37 PM PDT 24
Finished Aug 15 05:51:39 PM PDT 24
Peak memory 207988 kb
Host smart-729272cd-5932-4f3d-8de3-0d34c2d199e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347601029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3347601029
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4017889002
Short name T787
Test name
Test status
Simulation time 516659392 ps
CPU time 4.42 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 209340 kb
Host smart-f942a4ba-9441-40aa-a748-6d3ce641cc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017889002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4017889002
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1466922560
Short name T899
Test name
Test status
Simulation time 52335492 ps
CPU time 2.82 seconds
Started Aug 15 05:51:42 PM PDT 24
Finished Aug 15 05:51:45 PM PDT 24
Peak memory 207328 kb
Host smart-59e8658c-f389-40f0-8bd6-589d8cde3240
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466922560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1466922560
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4093477057
Short name T538
Test name
Test status
Simulation time 863978965 ps
CPU time 20.7 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:52:07 PM PDT 24
Peak memory 208900 kb
Host smart-81f57607-52b5-421c-a262-cb13953fb927
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093477057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4093477057
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.251234491
Short name T432
Test name
Test status
Simulation time 253788108 ps
CPU time 3 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:52 PM PDT 24
Peak memory 207716 kb
Host smart-56e42fc4-6fbe-4cc7-a7d0-772dc833d0fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251234491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.251234491
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1774929934
Short name T751
Test name
Test status
Simulation time 442178886 ps
CPU time 4.47 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:48 PM PDT 24
Peak memory 209708 kb
Host smart-7681b7c5-4ffd-470d-bd8c-505ed0d9aa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774929934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1774929934
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3792453827
Short name T544
Test name
Test status
Simulation time 191951225 ps
CPU time 5.04 seconds
Started Aug 15 05:51:36 PM PDT 24
Finished Aug 15 05:51:41 PM PDT 24
Peak memory 208832 kb
Host smart-36caf10a-5882-4514-b3b4-792a47dda19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792453827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3792453827
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.4097588482
Short name T195
Test name
Test status
Simulation time 171655775 ps
CPU time 9.85 seconds
Started Aug 15 05:51:43 PM PDT 24
Finished Aug 15 05:51:53 PM PDT 24
Peak memory 215732 kb
Host smart-df25fe14-b37f-4025-bd73-562443911a91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097588482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.4097588482
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.457745365
Short name T817
Test name
Test status
Simulation time 500692997 ps
CPU time 4.59 seconds
Started Aug 15 05:51:42 PM PDT 24
Finished Aug 15 05:51:46 PM PDT 24
Peak memory 207732 kb
Host smart-5ad0a168-d70a-4a21-9492-134118439345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457745365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.457745365
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2344641561
Short name T858
Test name
Test status
Simulation time 445499952 ps
CPU time 11.63 seconds
Started Aug 15 05:51:38 PM PDT 24
Finished Aug 15 05:51:50 PM PDT 24
Peak memory 210892 kb
Host smart-d580d823-634c-48ce-8899-9477c76fd45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344641561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2344641561
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2483391143
Short name T452
Test name
Test status
Simulation time 57038938 ps
CPU time 0.81 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:50 PM PDT 24
Peak memory 206344 kb
Host smart-d1adf195-131c-4877-92e9-c8d9de816518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483391143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2483391143
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3294171013
Short name T340
Test name
Test status
Simulation time 66869315 ps
CPU time 3.16 seconds
Started Aug 15 05:51:39 PM PDT 24
Finished Aug 15 05:51:42 PM PDT 24
Peak memory 214780 kb
Host smart-28d3f178-a4db-4070-b330-ae3280804afa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3294171013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3294171013
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.523268792
Short name T32
Test name
Test status
Simulation time 107719910 ps
CPU time 4.33 seconds
Started Aug 15 05:51:34 PM PDT 24
Finished Aug 15 05:51:39 PM PDT 24
Peak memory 212460 kb
Host smart-7997bfb8-cd04-4500-88a5-cb4cc6d293db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523268792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.523268792
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4130476510
Short name T723
Test name
Test status
Simulation time 515494877 ps
CPU time 2.61 seconds
Started Aug 15 05:51:40 PM PDT 24
Finished Aug 15 05:51:43 PM PDT 24
Peak memory 208568 kb
Host smart-7001dcd9-3e66-44fa-afda-6097cbf6ff08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130476510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4130476510
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1131842675
Short name T852
Test name
Test status
Simulation time 34428684 ps
CPU time 2.28 seconds
Started Aug 15 05:51:43 PM PDT 24
Finished Aug 15 05:51:46 PM PDT 24
Peak memory 214700 kb
Host smart-b2a2ab91-5957-4bbb-98b2-5193df8470c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131842675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1131842675
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1652768049
Short name T617
Test name
Test status
Simulation time 90987634 ps
CPU time 4.3 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 214828 kb
Host smart-9bbea221-f4cc-490a-b0e9-1808ea09aa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652768049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1652768049
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3128651137
Short name T515
Test name
Test status
Simulation time 327071948 ps
CPU time 2.84 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 218144 kb
Host smart-1ea7f21e-9752-4567-bdbd-15a3af0d31ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128651137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3128651137
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3618734148
Short name T831
Test name
Test status
Simulation time 44952540 ps
CPU time 3.18 seconds
Started Aug 15 05:51:38 PM PDT 24
Finished Aug 15 05:51:42 PM PDT 24
Peak memory 207808 kb
Host smart-783fb4c9-24d3-4c05-b6eb-9131b33301eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618734148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3618734148
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1845394664
Short name T678
Test name
Test status
Simulation time 78886914 ps
CPU time 3.26 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 209156 kb
Host smart-419cc4c3-cff8-4125-8bb5-48130ae51b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845394664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1845394664
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3810985710
Short name T735
Test name
Test status
Simulation time 584700523 ps
CPU time 3.65 seconds
Started Aug 15 05:51:34 PM PDT 24
Finished Aug 15 05:51:37 PM PDT 24
Peak memory 207364 kb
Host smart-641746ba-9320-49ea-a173-f9865d29506f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810985710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3810985710
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1561865686
Short name T472
Test name
Test status
Simulation time 85788068 ps
CPU time 3.56 seconds
Started Aug 15 05:51:46 PM PDT 24
Finished Aug 15 05:51:50 PM PDT 24
Peak memory 208472 kb
Host smart-d8c0c267-4081-4296-a2bb-f949fc3f9652
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561865686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1561865686
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2711710305
Short name T216
Test name
Test status
Simulation time 768846225 ps
CPU time 4.17 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:51 PM PDT 24
Peak memory 207408 kb
Host smart-564c8123-a759-4dc9-9620-321e5626c20b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711710305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2711710305
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3970991284
Short name T202
Test name
Test status
Simulation time 301446155 ps
CPU time 2.97 seconds
Started Aug 15 05:51:38 PM PDT 24
Finished Aug 15 05:51:41 PM PDT 24
Peak memory 208980 kb
Host smart-dbae46aa-3172-4e06-9860-3241403f3ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970991284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3970991284
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3944275141
Short name T426
Test name
Test status
Simulation time 37200679 ps
CPU time 2.1 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:50 PM PDT 24
Peak memory 207352 kb
Host smart-7436368d-bc28-4522-ac5e-ef26b252d5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944275141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3944275141
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1404037057
Short name T693
Test name
Test status
Simulation time 647794466 ps
CPU time 17.9 seconds
Started Aug 15 05:51:40 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 216428 kb
Host smart-d52f7b1e-24eb-4769-af71-9577a4ba35f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404037057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1404037057
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3030596007
Short name T364
Test name
Test status
Simulation time 127104696 ps
CPU time 4.32 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 214768 kb
Host smart-7d3758a3-4966-4518-8017-95cbd8faa5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030596007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3030596007
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2888235128
Short name T178
Test name
Test status
Simulation time 342370149 ps
CPU time 6.89 seconds
Started Aug 15 05:51:40 PM PDT 24
Finished Aug 15 05:51:47 PM PDT 24
Peak memory 210852 kb
Host smart-658fac39-2ba7-4999-912c-aa741725f5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888235128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2888235128
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.361884036
Short name T551
Test name
Test status
Simulation time 77844950 ps
CPU time 0.76 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:45 PM PDT 24
Peak memory 206324 kb
Host smart-74c40dae-0627-4abe-b67e-f9f0eaeef6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361884036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.361884036
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1202596991
Short name T321
Test name
Test status
Simulation time 52945920 ps
CPU time 2.28 seconds
Started Aug 15 05:51:45 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 214756 kb
Host smart-152301e2-4b8f-4b4a-b304-3fa220853aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202596991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1202596991
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2692796835
Short name T802
Test name
Test status
Simulation time 314023569 ps
CPU time 2.58 seconds
Started Aug 15 05:51:43 PM PDT 24
Finished Aug 15 05:51:45 PM PDT 24
Peak memory 209504 kb
Host smart-5ff3b44b-33a1-41f6-8f72-e5827213aa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692796835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2692796835
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.4159465848
Short name T85
Test name
Test status
Simulation time 25031217 ps
CPU time 1.93 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:50 PM PDT 24
Peak memory 208104 kb
Host smart-f36e30a5-ceec-497b-8ea1-c9d13d582f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159465848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.4159465848
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.375312153
Short name T599
Test name
Test status
Simulation time 29936711 ps
CPU time 2.34 seconds
Started Aug 15 05:51:43 PM PDT 24
Finished Aug 15 05:51:46 PM PDT 24
Peak memory 214788 kb
Host smart-6b7633c1-5dc2-44c3-9adc-0ff8d12e23bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375312153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.375312153
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2699703639
Short name T296
Test name
Test status
Simulation time 116983899 ps
CPU time 3.7 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:48 PM PDT 24
Peak memory 214700 kb
Host smart-52788a35-7e3c-420b-842e-e13f003e6747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699703639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2699703639
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2724882387
Short name T400
Test name
Test status
Simulation time 509968304 ps
CPU time 4.36 seconds
Started Aug 15 05:51:42 PM PDT 24
Finished Aug 15 05:51:46 PM PDT 24
Peak memory 209968 kb
Host smart-85fa74cb-6b59-4106-93e2-64d4f98430d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724882387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2724882387
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1926837000
Short name T635
Test name
Test status
Simulation time 367884512 ps
CPU time 4.38 seconds
Started Aug 15 05:51:45 PM PDT 24
Finished Aug 15 05:51:59 PM PDT 24
Peak memory 208452 kb
Host smart-8bc672e2-1cc1-43fc-9a13-8fc1e9192289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926837000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1926837000
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.778191107
Short name T401
Test name
Test status
Simulation time 646510516 ps
CPU time 5.13 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 207232 kb
Host smart-f956f829-fba8-48d1-9daf-3958fc46da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778191107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.778191107
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.657571065
Short name T442
Test name
Test status
Simulation time 176024155 ps
CPU time 2.64 seconds
Started Aug 15 05:51:46 PM PDT 24
Finished Aug 15 05:51:48 PM PDT 24
Peak memory 207268 kb
Host smart-5d037794-9fed-419f-ade0-2259f8d63c15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657571065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.657571065
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3279939043
Short name T509
Test name
Test status
Simulation time 332658508 ps
CPU time 3.87 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 209008 kb
Host smart-223ae1f9-7efe-40a6-a1a0-2ba9379c53ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279939043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3279939043
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.784387956
Short name T612
Test name
Test status
Simulation time 478421226 ps
CPU time 2.81 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:57 PM PDT 24
Peak memory 207216 kb
Host smart-3bc6d4bf-5e20-473a-97e3-cad11156dea6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784387956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.784387956
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2912619122
Short name T498
Test name
Test status
Simulation time 9177652391 ps
CPU time 23.26 seconds
Started Aug 15 05:51:46 PM PDT 24
Finished Aug 15 05:52:09 PM PDT 24
Peak memory 209668 kb
Host smart-c1c9cca3-a91b-4059-b0e9-e773a21462d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912619122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2912619122
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2513606571
Short name T512
Test name
Test status
Simulation time 56287529 ps
CPU time 2.76 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:53 PM PDT 24
Peak memory 208412 kb
Host smart-fd6667c0-737f-4831-8c3a-8fe3d1e40413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513606571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2513606571
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1569062075
Short name T136
Test name
Test status
Simulation time 438419193 ps
CPU time 18.1 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:52:09 PM PDT 24
Peak memory 222960 kb
Host smart-2f50e22b-a542-4ea1-a447-2d7675e7ce7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569062075 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1569062075
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1253566425
Short name T203
Test name
Test status
Simulation time 387181199 ps
CPU time 11.24 seconds
Started Aug 15 05:51:46 PM PDT 24
Finished Aug 15 05:51:57 PM PDT 24
Peak memory 207924 kb
Host smart-3e881a4e-011a-4361-a2d9-c5452000ad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253566425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1253566425
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3730510560
Short name T777
Test name
Test status
Simulation time 194639816 ps
CPU time 2.41 seconds
Started Aug 15 05:51:52 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 210324 kb
Host smart-ad4e53d5-966e-428d-a258-769330a8a206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730510560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3730510560
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1314757659
Short name T614
Test name
Test status
Simulation time 40193370 ps
CPU time 0.76 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:32 PM PDT 24
Peak memory 206340 kb
Host smart-a95f0930-fee5-4ed6-bf5e-84d9ca239ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314757659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1314757659
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3324339329
Short name T379
Test name
Test status
Simulation time 138584604 ps
CPU time 7.59 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:39 PM PDT 24
Peak memory 215796 kb
Host smart-08916303-2cd4-4e91-a481-baf2979a5df9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324339329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3324339329
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1122438335
Short name T30
Test name
Test status
Simulation time 103907232 ps
CPU time 3.28 seconds
Started Aug 15 05:50:24 PM PDT 24
Finished Aug 15 05:50:28 PM PDT 24
Peak memory 220424 kb
Host smart-42168814-ba20-4d8c-9058-22a863ce41df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122438335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1122438335
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.922436294
Short name T591
Test name
Test status
Simulation time 37161604 ps
CPU time 1.88 seconds
Started Aug 15 05:50:24 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 207984 kb
Host smart-e4380b67-ee06-496e-9e2f-ab8e9dbd6704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922436294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.922436294
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3264311547
Short name T667
Test name
Test status
Simulation time 85030918 ps
CPU time 3.59 seconds
Started Aug 15 05:50:26 PM PDT 24
Finished Aug 15 05:50:29 PM PDT 24
Peak memory 209396 kb
Host smart-58b1ebaf-1cdd-491a-8e01-7efa1e03ab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264311547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3264311547
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2340915968
Short name T333
Test name
Test status
Simulation time 46410764 ps
CPU time 2.51 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 214584 kb
Host smart-0dcd57b1-7bb6-4a8c-8ae4-743d1c969dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340915968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2340915968
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.451068947
Short name T154
Test name
Test status
Simulation time 180450591 ps
CPU time 3.78 seconds
Started Aug 15 05:50:25 PM PDT 24
Finished Aug 15 05:50:29 PM PDT 24
Peak memory 222860 kb
Host smart-ce45ef69-49f7-4192-abe3-a928804b5c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451068947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.451068947
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3775681756
Short name T571
Test name
Test status
Simulation time 1146391684 ps
CPU time 3.72 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 209136 kb
Host smart-07c54c6d-c3a7-478d-a8eb-2da26a7e1ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775681756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3775681756
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1898861518
Short name T13
Test name
Test status
Simulation time 600598217 ps
CPU time 11.77 seconds
Started Aug 15 05:50:43 PM PDT 24
Finished Aug 15 05:50:55 PM PDT 24
Peak memory 232168 kb
Host smart-cd7e2055-4207-4790-a0d3-c10a7fa2b450
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898861518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1898861518
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3800066850
Short name T862
Test name
Test status
Simulation time 3870993524 ps
CPU time 23.35 seconds
Started Aug 15 05:50:36 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 208448 kb
Host smart-6a49f92d-6ea2-44e9-9cf1-a4cfc23f699e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800066850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3800066850
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2922100622
Short name T469
Test name
Test status
Simulation time 198175234 ps
CPU time 3.27 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 207440 kb
Host smart-a871d3c4-0d9f-421f-a3c8-61c224549565
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922100622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2922100622
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1773034821
Short name T519
Test name
Test status
Simulation time 1431063946 ps
CPU time 5.45 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:28 PM PDT 24
Peak memory 208800 kb
Host smart-20d95dda-5125-47d3-9738-dbafe4f4ffaa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773034821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1773034821
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.699984975
Short name T794
Test name
Test status
Simulation time 227922259 ps
CPU time 7.92 seconds
Started Aug 15 05:50:28 PM PDT 24
Finished Aug 15 05:50:37 PM PDT 24
Peak memory 209192 kb
Host smart-2c2110eb-985a-450e-812e-fd3cba7664d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699984975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.699984975
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3613673233
Short name T358
Test name
Test status
Simulation time 257477570 ps
CPU time 3.97 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:36 PM PDT 24
Peak memory 218792 kb
Host smart-d59ab777-88fa-4ac5-ae7b-3e58942b444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613673233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3613673233
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3621850789
Short name T570
Test name
Test status
Simulation time 1222404581 ps
CPU time 24.8 seconds
Started Aug 15 05:50:25 PM PDT 24
Finished Aug 15 05:50:50 PM PDT 24
Peak memory 208476 kb
Host smart-69db60ed-dbd3-4cc8-8ae4-a4ca2f548ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621850789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3621850789
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3963959715
Short name T139
Test name
Test status
Simulation time 701993840 ps
CPU time 12.06 seconds
Started Aug 15 05:50:39 PM PDT 24
Finished Aug 15 05:50:51 PM PDT 24
Peak memory 223096 kb
Host smart-4f8ebaa2-e14a-4bf3-903e-d59f18252669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963959715 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3963959715
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.227262560
Short name T359
Test name
Test status
Simulation time 249425635 ps
CPU time 8.01 seconds
Started Aug 15 05:50:27 PM PDT 24
Finished Aug 15 05:50:35 PM PDT 24
Peak memory 210304 kb
Host smart-88a96994-16f5-403c-9b15-dfd026e9156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227262560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.227262560
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2912833553
Short name T502
Test name
Test status
Simulation time 238644860 ps
CPU time 2.71 seconds
Started Aug 15 05:50:45 PM PDT 24
Finished Aug 15 05:50:48 PM PDT 24
Peak memory 210360 kb
Host smart-7824fcc6-c364-4127-ada1-ddcb2d7fd99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912833553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2912833553
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.4204767021
Short name T494
Test name
Test status
Simulation time 32709513 ps
CPU time 0.76 seconds
Started Aug 15 05:51:39 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 206396 kb
Host smart-d5e78581-4c8f-43ce-aca8-c9b4ab79d572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204767021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4204767021
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1474161425
Short name T414
Test name
Test status
Simulation time 205935637 ps
CPU time 2.67 seconds
Started Aug 15 05:51:46 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 208160 kb
Host smart-1333fdc5-1536-4cf5-9ba7-1dae3e4aec6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474161425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1474161425
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3791740034
Short name T804
Test name
Test status
Simulation time 1112554569 ps
CPU time 7.78 seconds
Started Aug 15 05:51:52 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 214760 kb
Host smart-8c7784a0-aa24-4231-bca1-474b3f2dcd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791740034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3791740034
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3340978877
Short name T56
Test name
Test status
Simulation time 147328505 ps
CPU time 4.06 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:53 PM PDT 24
Peak memory 215292 kb
Host smart-3f1900fb-a546-43cd-b277-3048bb579832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340978877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3340978877
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.649481704
Short name T866
Test name
Test status
Simulation time 122435718 ps
CPU time 3.21 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:48 PM PDT 24
Peak memory 220200 kb
Host smart-e75384df-34c9-4128-99ce-3e98373a02ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649481704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.649481704
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3084318900
Short name T342
Test name
Test status
Simulation time 513867047 ps
CPU time 4.15 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:57 PM PDT 24
Peak memory 208684 kb
Host smart-9d0560ae-1723-48bd-834e-f8165b75277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084318900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3084318900
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2973734150
Short name T764
Test name
Test status
Simulation time 630296046 ps
CPU time 7.9 seconds
Started Aug 15 05:51:45 PM PDT 24
Finished Aug 15 05:51:53 PM PDT 24
Peak memory 209252 kb
Host smart-90f517e9-3c33-48f3-a27a-12f0c086df7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973734150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2973734150
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.90378581
Short name T577
Test name
Test status
Simulation time 115737257 ps
CPU time 4 seconds
Started Aug 15 05:51:35 PM PDT 24
Finished Aug 15 05:51:39 PM PDT 24
Peak memory 207320 kb
Host smart-5ecd5c62-1e86-40d0-95bf-fed00c1400e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90378581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.90378581
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2247356555
Short name T454
Test name
Test status
Simulation time 347667913 ps
CPU time 4.64 seconds
Started Aug 15 05:51:56 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 209316 kb
Host smart-c86c2947-c0a0-445e-83a5-0f8a230a441e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247356555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2247356555
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2139874244
Short name T458
Test name
Test status
Simulation time 234014469 ps
CPU time 3.19 seconds
Started Aug 15 05:51:46 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 207264 kb
Host smart-6bd3b3fa-45f9-4cbe-a5db-cd0c53d96b0d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139874244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2139874244
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.693068930
Short name T380
Test name
Test status
Simulation time 465668604 ps
CPU time 11.91 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 218696 kb
Host smart-e87b4bc7-ebf3-4139-b311-881a69504a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693068930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.693068930
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4237758990
Short name T590
Test name
Test status
Simulation time 172309246 ps
CPU time 4.87 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 207956 kb
Host smart-ccc38953-07bf-4ff7-9572-824f4ece2c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237758990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4237758990
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2141678716
Short name T411
Test name
Test status
Simulation time 320404618 ps
CPU time 8.82 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:59 PM PDT 24
Peak memory 214788 kb
Host smart-a1c9097f-c065-4f2c-b379-e658c6f44077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141678716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2141678716
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.144491308
Short name T557
Test name
Test status
Simulation time 175096186 ps
CPU time 2.18 seconds
Started Aug 15 05:51:54 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 210416 kb
Host smart-9edc47bb-6606-4f62-9e19-17411ec1fd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144491308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.144491308
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3433455232
Short name T647
Test name
Test status
Simulation time 50635370 ps
CPU time 0.76 seconds
Started Aug 15 05:52:03 PM PDT 24
Finished Aug 15 05:52:04 PM PDT 24
Peak memory 206328 kb
Host smart-230a2a65-aa9c-400c-9adb-c3a5975d2650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433455232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3433455232
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2811613183
Short name T370
Test name
Test status
Simulation time 497818878 ps
CPU time 7.31 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 214780 kb
Host smart-a42bd688-6a93-4816-a10f-03a4c7b8a95a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811613183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2811613183
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1222606445
Short name T789
Test name
Test status
Simulation time 861790126 ps
CPU time 4.4 seconds
Started Aug 15 05:51:41 PM PDT 24
Finished Aug 15 05:51:46 PM PDT 24
Peak memory 208572 kb
Host smart-f61fc69f-9e56-4879-b031-bc4514d90b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222606445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1222606445
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2870910973
Short name T388
Test name
Test status
Simulation time 65784730 ps
CPU time 4.17 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:48 PM PDT 24
Peak memory 222820 kb
Host smart-acfb94ed-21f1-45f7-adbd-40564d37c2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870910973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2870910973
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.4137438353
Short name T645
Test name
Test status
Simulation time 345527027 ps
CPU time 3.18 seconds
Started Aug 15 05:51:42 PM PDT 24
Finished Aug 15 05:51:46 PM PDT 24
Peak memory 214716 kb
Host smart-8cabf1ee-e30d-487c-9995-efe71522ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137438353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.4137438353
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3641683173
Short name T48
Test name
Test status
Simulation time 1367440207 ps
CPU time 4.56 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 222952 kb
Host smart-92331db2-98ad-44c8-9925-1b118df2c64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641683173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3641683173
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2582271860
Short name T682
Test name
Test status
Simulation time 128811284 ps
CPU time 4.63 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 209388 kb
Host smart-23e44932-083f-4ab8-a7e2-c1f568ea975f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582271860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2582271860
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3929026341
Short name T840
Test name
Test status
Simulation time 182525352 ps
CPU time 2.62 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 208992 kb
Host smart-8ee9830c-333b-4ccc-960e-314136f5498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929026341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3929026341
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3550809759
Short name T720
Test name
Test status
Simulation time 148283295 ps
CPU time 2.17 seconds
Started Aug 15 05:51:46 PM PDT 24
Finished Aug 15 05:51:48 PM PDT 24
Peak memory 209356 kb
Host smart-69c9d497-d088-4017-8c4d-ab3ccece67c0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550809759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3550809759
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1249437882
Short name T732
Test name
Test status
Simulation time 1292459692 ps
CPU time 7.44 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 209204 kb
Host smart-d51fe851-9e1c-4cbb-b2a9-8d814ac9e125
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249437882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1249437882
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.721184272
Short name T752
Test name
Test status
Simulation time 91480544 ps
CPU time 2.07 seconds
Started Aug 15 05:51:52 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 207348 kb
Host smart-023571c9-1f8f-49f6-918c-62df46831ae1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721184272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.721184272
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1829999000
Short name T322
Test name
Test status
Simulation time 1971051299 ps
CPU time 33.59 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:52:18 PM PDT 24
Peak memory 218172 kb
Host smart-aa503f54-4043-4cfb-a0d1-32e505d4ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829999000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1829999000
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3136466754
Short name T406
Test name
Test status
Simulation time 135477402 ps
CPU time 2.41 seconds
Started Aug 15 05:51:35 PM PDT 24
Finished Aug 15 05:51:38 PM PDT 24
Peak memory 208908 kb
Host smart-782b5b72-5488-45f8-90b2-1f2779d319f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136466754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3136466754
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.901711593
Short name T27
Test name
Test status
Simulation time 113512528 ps
CPU time 4.12 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:52 PM PDT 24
Peak memory 218700 kb
Host smart-cc610245-9774-425d-91bf-0b3c7240ee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901711593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.901711593
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.180105539
Short name T144
Test name
Test status
Simulation time 256985248 ps
CPU time 3 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:50 PM PDT 24
Peak memory 211056 kb
Host smart-dcfbb306-8ad6-4d80-b58f-c5139118104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180105539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.180105539
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1474669524
Short name T112
Test name
Test status
Simulation time 19179606 ps
CPU time 0.71 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 206348 kb
Host smart-3b14c28f-2bc0-4743-b568-8daecf9ff341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474669524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1474669524
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1663916980
Short name T912
Test name
Test status
Simulation time 443576508 ps
CPU time 3.18 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:08 PM PDT 24
Peak memory 221960 kb
Host smart-332c798f-50dc-4132-b9da-c85bc8e8c853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663916980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1663916980
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1946207712
Short name T813
Test name
Test status
Simulation time 130049758 ps
CPU time 1.87 seconds
Started Aug 15 05:51:44 PM PDT 24
Finished Aug 15 05:51:46 PM PDT 24
Peak memory 207940 kb
Host smart-9ff54f1d-e6d9-4725-94e1-0fa990ab1b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946207712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1946207712
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3941032520
Short name T822
Test name
Test status
Simulation time 150319512 ps
CPU time 6.21 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 214696 kb
Host smart-1f24d38d-a76e-4f0c-9d24-b0a52c1e3a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941032520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3941032520
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1445479023
Short name T3
Test name
Test status
Simulation time 75987378 ps
CPU time 2.26 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 214756 kb
Host smart-ebba6d04-6f4f-49f3-9384-02d019ddc387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445479023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1445479023
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1786506315
Short name T456
Test name
Test status
Simulation time 4704710726 ps
CPU time 27.96 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:52:19 PM PDT 24
Peak memory 209376 kb
Host smart-e2a3d035-3a2f-4a73-90cf-23f2ce2a5cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786506315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1786506315
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3944816445
Short name T263
Test name
Test status
Simulation time 2167043345 ps
CPU time 14.37 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:52:04 PM PDT 24
Peak memory 209148 kb
Host smart-d48ff3ca-32f0-4095-aeff-a8d790a400a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944816445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3944816445
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2871673063
Short name T701
Test name
Test status
Simulation time 427545257 ps
CPU time 4.02 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:02 PM PDT 24
Peak memory 207396 kb
Host smart-aaa2d815-cc69-46f9-b94b-6af52ad29d2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871673063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2871673063
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.4210427476
Short name T305
Test name
Test status
Simulation time 164662726 ps
CPU time 2.5 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 209188 kb
Host smart-7bafb170-c19a-4885-a9b0-91f76b622452
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210427476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.4210427476
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2981554663
Short name T96
Test name
Test status
Simulation time 30157044 ps
CPU time 2.17 seconds
Started Aug 15 05:51:46 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 207344 kb
Host smart-a2384dfe-ddba-4674-a0e5-b8170dd3f6f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981554663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2981554663
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.607333024
Short name T491
Test name
Test status
Simulation time 136824660 ps
CPU time 4.23 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:52 PM PDT 24
Peak memory 209184 kb
Host smart-c6459ce6-c1c9-4f3e-85f2-008862392267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607333024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.607333024
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3450522060
Short name T620
Test name
Test status
Simulation time 103690081 ps
CPU time 2.67 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:51 PM PDT 24
Peak memory 209020 kb
Host smart-00e7abbb-d458-4a72-8228-95b622c3609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450522060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3450522060
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3449419819
Short name T373
Test name
Test status
Simulation time 76172429 ps
CPU time 2.57 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 210656 kb
Host smart-0938dbab-2d4c-4288-ae82-3e9028b384dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449419819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3449419819
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2232588968
Short name T341
Test name
Test status
Simulation time 361641961 ps
CPU time 4.51 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:52:02 PM PDT 24
Peak memory 207956 kb
Host smart-881e3548-c6e5-413d-94cb-aaf52f69200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232588968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2232588968
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.517492602
Short name T741
Test name
Test status
Simulation time 140996909 ps
CPU time 2.77 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 211276 kb
Host smart-5ea2b1e9-c3a1-4776-bc05-74a478bf7765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517492602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.517492602
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2711126961
Short name T825
Test name
Test status
Simulation time 47459573 ps
CPU time 0.91 seconds
Started Aug 15 05:52:01 PM PDT 24
Finished Aug 15 05:52:02 PM PDT 24
Peak memory 206524 kb
Host smart-3ebdaa81-b49b-46b3-bf04-100a692ec176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711126961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2711126961
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.417837867
Short name T34
Test name
Test status
Simulation time 405629271 ps
CPU time 3.15 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 218220 kb
Host smart-f40df136-e007-4eb0-960d-a4707aab873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417837867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.417837867
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1577092592
Short name T901
Test name
Test status
Simulation time 31108870 ps
CPU time 2.18 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 218800 kb
Host smart-e0baa197-a23a-4b2d-89b9-c1685a191da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577092592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1577092592
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1079568025
Short name T277
Test name
Test status
Simulation time 123692897 ps
CPU time 5.21 seconds
Started Aug 15 05:51:52 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 214876 kb
Host smart-5a3bec9a-6d54-4fdc-8314-cb0c643d7713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079568025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1079568025
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.4228931525
Short name T279
Test name
Test status
Simulation time 67864640 ps
CPU time 2.68 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 214688 kb
Host smart-0b41d0de-da7d-4cec-9a78-c1b930edd36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228931525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4228931525
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2309964145
Short name T233
Test name
Test status
Simulation time 1185372427 ps
CPU time 2.56 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:51 PM PDT 24
Peak memory 215920 kb
Host smart-de39d2cd-25bd-491d-b2df-1b9737622265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309964145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2309964145
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.521915134
Short name T746
Test name
Test status
Simulation time 1326522673 ps
CPU time 7.27 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 208968 kb
Host smart-7187d659-8725-4ef8-bcfa-55eb17cf01ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521915134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.521915134
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2279187240
Short name T506
Test name
Test status
Simulation time 358797758 ps
CPU time 1.68 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:49 PM PDT 24
Peak memory 207316 kb
Host smart-b90daf44-24de-4ef1-8b4f-4eb2c2237e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279187240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2279187240
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3550657530
Short name T568
Test name
Test status
Simulation time 322612314 ps
CPU time 4 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:02 PM PDT 24
Peak memory 209052 kb
Host smart-8f3cc3f4-41b7-4538-8d79-246e53550e4f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550657530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3550657530
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3685864041
Short name T437
Test name
Test status
Simulation time 215394153 ps
CPU time 3.07 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 207248 kb
Host smart-43e7fcad-d74c-4035-afa0-543c8d63189e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685864041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3685864041
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.854328874
Short name T573
Test name
Test status
Simulation time 1264602313 ps
CPU time 5.64 seconds
Started Aug 15 05:52:06 PM PDT 24
Finished Aug 15 05:52:12 PM PDT 24
Peak memory 207420 kb
Host smart-4e5adeab-d439-42db-9603-18ed2d35330a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854328874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.854328874
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1737165554
Short name T607
Test name
Test status
Simulation time 38803579 ps
CPU time 2.5 seconds
Started Aug 15 05:51:56 PM PDT 24
Finished Aug 15 05:51:59 PM PDT 24
Peak memory 208628 kb
Host smart-cc509f74-de14-4393-8efa-b362d029d68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737165554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1737165554
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3371200111
Short name T589
Test name
Test status
Simulation time 514103729 ps
CPU time 3.08 seconds
Started Aug 15 05:51:36 PM PDT 24
Finished Aug 15 05:51:40 PM PDT 24
Peak memory 208940 kb
Host smart-d34a4e97-7954-414d-bdbf-0a1f5d77ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371200111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3371200111
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1916934454
Short name T705
Test name
Test status
Simulation time 774449504 ps
CPU time 8.77 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 209036 kb
Host smart-8bb5d740-6767-460e-9f40-80008cd0af96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916934454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1916934454
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3597279593
Short name T72
Test name
Test status
Simulation time 348895279 ps
CPU time 2.71 seconds
Started Aug 15 05:51:55 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 210204 kb
Host smart-df1ee465-d112-4d0f-a8de-29351da69389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597279593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3597279593
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3085803515
Short name T624
Test name
Test status
Simulation time 9458097 ps
CPU time 0.72 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 206324 kb
Host smart-9222ab1e-5c21-4145-a030-43598779cc17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085803515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3085803515
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1503032687
Short name T892
Test name
Test status
Simulation time 71885862 ps
CPU time 3.19 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 215592 kb
Host smart-f30bf189-0d91-48e5-a55d-70bd2057ea1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503032687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1503032687
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.946327765
Short name T37
Test name
Test status
Simulation time 96320413 ps
CPU time 3.05 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 220440 kb
Host smart-4a4cdea6-f9a3-4dba-8059-42b24bf1f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946327765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.946327765
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1333420699
Short name T492
Test name
Test status
Simulation time 150270753 ps
CPU time 2.66 seconds
Started Aug 15 05:51:58 PM PDT 24
Finished Aug 15 05:52:01 PM PDT 24
Peak memory 208060 kb
Host smart-38707fc1-71fc-4807-9d29-9c0e2ff68338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333420699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1333420699
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2891166204
Short name T729
Test name
Test status
Simulation time 119518105 ps
CPU time 2.54 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 214756 kb
Host smart-83e1e831-423c-40ab-a841-462dd9450643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891166204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2891166204
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3132595570
Short name T329
Test name
Test status
Simulation time 237957235 ps
CPU time 2.68 seconds
Started Aug 15 05:51:55 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 222332 kb
Host smart-efb50e1f-7600-40d7-bc67-540da2b151f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132595570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3132595570
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3840577907
Short name T242
Test name
Test status
Simulation time 258377349 ps
CPU time 3.58 seconds
Started Aug 15 05:51:54 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 214840 kb
Host smart-6d72f136-008e-4c35-9bfb-ee6e9bda7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840577907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3840577907
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2633845053
Short name T610
Test name
Test status
Simulation time 388938910 ps
CPU time 4.58 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 208316 kb
Host smart-0a7a56fb-a131-4bb0-9060-0cb2fdf00a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633845053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2633845053
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3784837074
Short name T578
Test name
Test status
Simulation time 216917588 ps
CPU time 3.1 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 207408 kb
Host smart-36a5d43f-36a3-4d69-8522-f3a151df2b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784837074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3784837074
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1599543999
Short name T323
Test name
Test status
Simulation time 452479558 ps
CPU time 3.25 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 207288 kb
Host smart-7c246246-f5f4-45aa-8c88-4b956f7067ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599543999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1599543999
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4058977832
Short name T402
Test name
Test status
Simulation time 584051259 ps
CPU time 17.61 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 208656 kb
Host smart-15873879-6f65-4305-a50d-3e230d9a4d7a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058977832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4058977832
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2850408700
Short name T710
Test name
Test status
Simulation time 1238705075 ps
CPU time 27.55 seconds
Started Aug 15 05:51:58 PM PDT 24
Finished Aug 15 05:52:26 PM PDT 24
Peak memory 209184 kb
Host smart-d836af68-ab53-4e2f-a543-ec5c6292522a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850408700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2850408700
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3224124278
Short name T666
Test name
Test status
Simulation time 74562375 ps
CPU time 3.15 seconds
Started Aug 15 05:51:47 PM PDT 24
Finished Aug 15 05:51:50 PM PDT 24
Peak memory 218632 kb
Host smart-ad9f3d61-53e9-48f2-9d34-a32117eca157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224124278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3224124278
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3334473413
Short name T399
Test name
Test status
Simulation time 249446495 ps
CPU time 3.2 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:51:51 PM PDT 24
Peak memory 209220 kb
Host smart-48aa1f4b-0f31-438b-b5d4-ca7612fd0178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334473413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3334473413
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3385162117
Short name T196
Test name
Test status
Simulation time 282547105 ps
CPU time 11.1 seconds
Started Aug 15 05:52:01 PM PDT 24
Finished Aug 15 05:52:12 PM PDT 24
Peak memory 222992 kb
Host smart-5e43ef74-5c54-430b-ba44-1f8bce58fcd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385162117 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3385162117
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1453262457
Short name T675
Test name
Test status
Simulation time 198262290 ps
CPU time 6.08 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:51:57 PM PDT 24
Peak memory 208232 kb
Host smart-e53089e1-4b8e-4173-897f-6c6710e999e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453262457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1453262457
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1203901033
Short name T708
Test name
Test status
Simulation time 810362236 ps
CPU time 4.07 seconds
Started Aug 15 05:52:09 PM PDT 24
Finished Aug 15 05:52:13 PM PDT 24
Peak memory 211492 kb
Host smart-9b03675b-9be4-4c8d-a686-26e02575866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203901033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1203901033
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.730043826
Short name T762
Test name
Test status
Simulation time 26698852 ps
CPU time 0.76 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 206440 kb
Host smart-d629c866-2322-42eb-aa48-622239bab7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730043826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.730043826
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1455226386
Short name T259
Test name
Test status
Simulation time 73850731 ps
CPU time 4.62 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 215700 kb
Host smart-7669e744-d8cf-44af-b94a-5d3aefa0a5ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455226386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1455226386
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3242863324
Short name T625
Test name
Test status
Simulation time 115337987 ps
CPU time 2.32 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 222228 kb
Host smart-fa87991c-a2af-467d-a0b7-47592c9955a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242863324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3242863324
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3302663611
Short name T275
Test name
Test status
Simulation time 27664967 ps
CPU time 1.64 seconds
Started Aug 15 05:51:56 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 209088 kb
Host smart-f6a76b93-5858-4241-9f71-d123626ffa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302663611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3302663611
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1446338014
Short name T106
Test name
Test status
Simulation time 268795026 ps
CPU time 4.3 seconds
Started Aug 15 05:51:55 PM PDT 24
Finished Aug 15 05:51:59 PM PDT 24
Peak memory 209676 kb
Host smart-fc7e7e6e-4ed0-4025-98c3-8c23e29e5568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446338014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1446338014
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3148610908
Short name T74
Test name
Test status
Simulation time 143010497 ps
CPU time 6.36 seconds
Started Aug 15 05:51:59 PM PDT 24
Finished Aug 15 05:52:06 PM PDT 24
Peak memory 210616 kb
Host smart-2ecadc1a-03b1-451b-a82a-8798bb52ab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148610908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3148610908
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1103033804
Short name T537
Test name
Test status
Simulation time 3029465210 ps
CPU time 34.14 seconds
Started Aug 15 05:51:48 PM PDT 24
Finished Aug 15 05:52:22 PM PDT 24
Peak memory 208776 kb
Host smart-1d28d576-46d1-45ed-8068-b005f4040910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103033804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1103033804
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1591202267
Short name T872
Test name
Test status
Simulation time 398439292 ps
CPU time 6.2 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:04 PM PDT 24
Peak memory 209020 kb
Host smart-2a3732e7-2897-4a9f-9c23-cbf65f15c64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591202267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1591202267
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1395414848
Short name T501
Test name
Test status
Simulation time 101634401 ps
CPU time 4.14 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 208420 kb
Host smart-2f81c14b-491e-4520-9371-d26bda85e98f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395414848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1395414848
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1419318797
Short name T376
Test name
Test status
Simulation time 36107220 ps
CPU time 2.86 seconds
Started Aug 15 05:51:56 PM PDT 24
Finished Aug 15 05:51:59 PM PDT 24
Peak memory 209396 kb
Host smart-60ca236e-46c2-45f7-b5fb-0cc6f95ae4ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419318797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1419318797
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2082337154
Short name T850
Test name
Test status
Simulation time 92337537 ps
CPU time 4.5 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 209280 kb
Host smart-6974fe9d-f99f-4fc3-818b-1d36b9ca5598
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082337154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2082337154
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2537314526
Short name T754
Test name
Test status
Simulation time 86686163 ps
CPU time 2.9 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:52 PM PDT 24
Peak memory 209836 kb
Host smart-91bf1a76-0e60-4e86-a4c3-6b6b197309aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537314526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2537314526
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3708712706
Short name T149
Test name
Test status
Simulation time 199260640 ps
CPU time 3.08 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 207396 kb
Host smart-3ee02c41-6fa4-47e2-8783-1a52440f99ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708712706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3708712706
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.824289630
Short name T207
Test name
Test status
Simulation time 1486597104 ps
CPU time 24.6 seconds
Started Aug 15 05:52:02 PM PDT 24
Finished Aug 15 05:52:26 PM PDT 24
Peak memory 216560 kb
Host smart-32d2fcde-f5d2-46c4-915b-a5e10e268af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824289630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.824289630
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2022082206
Short name T198
Test name
Test status
Simulation time 653101936 ps
CPU time 12.97 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:52:04 PM PDT 24
Peak memory 223052 kb
Host smart-25ddf9b7-6862-413b-80b9-78ed24286161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022082206 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2022082206
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3846918072
Short name T761
Test name
Test status
Simulation time 82070373 ps
CPU time 3.9 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:57 PM PDT 24
Peak memory 209476 kb
Host smart-187dd5b5-1bdd-470b-afe9-987b2b084e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846918072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3846918072
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2220902283
Short name T174
Test name
Test status
Simulation time 1287065541 ps
CPU time 4.95 seconds
Started Aug 15 05:52:03 PM PDT 24
Finished Aug 15 05:52:14 PM PDT 24
Peak memory 210124 kb
Host smart-e107f87d-2da3-4fb7-a59a-61b75850b811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220902283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2220902283
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.657392452
Short name T436
Test name
Test status
Simulation time 9712271 ps
CPU time 0.84 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 206396 kb
Host smart-764418ed-c23d-4f54-82ee-eca4b4fd73f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657392452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.657392452
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3962807999
Short name T20
Test name
Test status
Simulation time 146815368 ps
CPU time 3.32 seconds
Started Aug 15 05:51:52 PM PDT 24
Finished Aug 15 05:51:56 PM PDT 24
Peak memory 215008 kb
Host smart-e8393869-6364-43c2-945d-bdd143304d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962807999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3962807999
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2771534059
Short name T17
Test name
Test status
Simulation time 320528932 ps
CPU time 2.77 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:52 PM PDT 24
Peak memory 214748 kb
Host smart-98cb584a-2584-4f43-874f-276fbd1a9622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771534059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2771534059
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4134414019
Short name T367
Test name
Test status
Simulation time 122089484 ps
CPU time 4.29 seconds
Started Aug 15 05:52:06 PM PDT 24
Finished Aug 15 05:52:10 PM PDT 24
Peak memory 214756 kb
Host smart-87725eea-9f25-41a9-ad2f-778cac15ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134414019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4134414019
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1850882195
Short name T606
Test name
Test status
Simulation time 478118639 ps
CPU time 3.36 seconds
Started Aug 15 05:51:49 PM PDT 24
Finished Aug 15 05:51:53 PM PDT 24
Peak memory 214688 kb
Host smart-a6c6af5d-2d0d-4114-82a2-a4f91041dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850882195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1850882195
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.682254122
Short name T724
Test name
Test status
Simulation time 615773004 ps
CPU time 5.82 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:55 PM PDT 24
Peak memory 221032 kb
Host smart-f1c04be5-d27a-47b5-ab5e-4c953bd67bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682254122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.682254122
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3400293059
Short name T819
Test name
Test status
Simulation time 348401671 ps
CPU time 3.75 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:57 PM PDT 24
Peak memory 208256 kb
Host smart-58de36b5-1934-4526-875d-520970d7b911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400293059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3400293059
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.822005285
Short name T556
Test name
Test status
Simulation time 200619171 ps
CPU time 2.87 seconds
Started Aug 15 05:51:55 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 207328 kb
Host smart-c038136c-cb90-4c3a-b777-3607e52baff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822005285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.822005285
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2295240738
Short name T781
Test name
Test status
Simulation time 2615966072 ps
CPU time 7.12 seconds
Started Aug 15 05:51:56 PM PDT 24
Finished Aug 15 05:52:03 PM PDT 24
Peak memory 208872 kb
Host smart-2c5ae7ed-0be5-413f-894f-78c526b4d7f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295240738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2295240738
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.322515199
Short name T616
Test name
Test status
Simulation time 642481683 ps
CPU time 15.43 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:52:09 PM PDT 24
Peak memory 209112 kb
Host smart-20df6052-1fc7-4981-bf3d-f427e4c6165f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322515199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.322515199
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1003893657
Short name T465
Test name
Test status
Simulation time 110389493 ps
CPU time 2.93 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 207472 kb
Host smart-0e4ac9ca-6412-4189-9033-3cb486ea751a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003893657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1003893657
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.754918893
Short name T792
Test name
Test status
Simulation time 670605369 ps
CPU time 7.88 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:05 PM PDT 24
Peak memory 220928 kb
Host smart-f50954dc-d421-4203-8485-db68f655b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754918893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.754918893
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3885630411
Short name T753
Test name
Test status
Simulation time 793933255 ps
CPU time 3.48 seconds
Started Aug 15 05:51:54 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 208976 kb
Host smart-52c5329b-95d0-48ee-a1af-44fbaee05095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885630411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3885630411
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1119724264
Short name T563
Test name
Test status
Simulation time 104295729 ps
CPU time 4.48 seconds
Started Aug 15 05:52:03 PM PDT 24
Finished Aug 15 05:52:08 PM PDT 24
Peak memory 209420 kb
Host smart-457ebe2f-9d9a-4c5a-9cf1-86dd58b1c78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119724264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1119724264
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.729830868
Short name T68
Test name
Test status
Simulation time 141833875 ps
CPU time 2.23 seconds
Started Aug 15 05:52:10 PM PDT 24
Finished Aug 15 05:52:12 PM PDT 24
Peak memory 210956 kb
Host smart-c5ed0788-a632-4f82-b781-7f7d2749ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729830868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.729830868
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.146323095
Short name T611
Test name
Test status
Simulation time 9903867 ps
CPU time 0.91 seconds
Started Aug 15 05:52:05 PM PDT 24
Finished Aug 15 05:52:06 PM PDT 24
Peak memory 206324 kb
Host smart-28c2a756-766b-4140-b3b6-776274eb1788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146323095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.146323095
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1220608352
Short name T239
Test name
Test status
Simulation time 906749103 ps
CPU time 4.84 seconds
Started Aug 15 05:52:02 PM PDT 24
Finished Aug 15 05:52:07 PM PDT 24
Peak memory 220544 kb
Host smart-a88eae64-6805-4d83-a9b1-2b8ccd2a94f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220608352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1220608352
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.701901554
Short name T83
Test name
Test status
Simulation time 67100324 ps
CPU time 3.25 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:01 PM PDT 24
Peak memory 209408 kb
Host smart-da11443a-aa11-4ba8-b669-bb00fff45c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701901554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.701901554
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3655318781
Short name T375
Test name
Test status
Simulation time 8112097165 ps
CPU time 21.77 seconds
Started Aug 15 05:52:07 PM PDT 24
Finished Aug 15 05:52:29 PM PDT 24
Peak memory 214772 kb
Host smart-ae8e6c13-afea-4c98-affa-8d5855615a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655318781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3655318781
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1706581011
Short name T827
Test name
Test status
Simulation time 132965462 ps
CPU time 2.71 seconds
Started Aug 15 05:52:05 PM PDT 24
Finished Aug 15 05:52:08 PM PDT 24
Peak memory 214680 kb
Host smart-fe6a3e39-d944-438c-abe5-bd21f0b33535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706581011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1706581011
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2620902659
Short name T325
Test name
Test status
Simulation time 53183299 ps
CPU time 3.35 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:03 PM PDT 24
Peak memory 214796 kb
Host smart-1d4f3ae9-ed8d-4a8d-9ec7-b6005b26336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620902659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2620902659
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2505906062
Short name T546
Test name
Test status
Simulation time 160602376 ps
CPU time 3.03 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:13 PM PDT 24
Peak memory 208692 kb
Host smart-e3e5658c-faa8-452f-b230-9a398c6fc36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505906062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2505906062
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2436477290
Short name T713
Test name
Test status
Simulation time 73048863 ps
CPU time 2.97 seconds
Started Aug 15 05:52:01 PM PDT 24
Finished Aug 15 05:52:04 PM PDT 24
Peak memory 207308 kb
Host smart-934fb9a9-38fe-412c-ac62-f1036ecf925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436477290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2436477290
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2497746391
Short name T878
Test name
Test status
Simulation time 263775005 ps
CPU time 3.48 seconds
Started Aug 15 05:51:58 PM PDT 24
Finished Aug 15 05:52:02 PM PDT 24
Peak memory 209356 kb
Host smart-52d53b10-b178-48ce-85ff-12fdba990cdf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497746391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2497746391
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.764596001
Short name T597
Test name
Test status
Simulation time 504429028 ps
CPU time 3.47 seconds
Started Aug 15 05:52:11 PM PDT 24
Finished Aug 15 05:52:14 PM PDT 24
Peak memory 207432 kb
Host smart-3aef9c7f-3eb4-4837-889c-ecc7395d8b2a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764596001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.764596001
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3315294534
Short name T824
Test name
Test status
Simulation time 268227053 ps
CPU time 4.1 seconds
Started Aug 15 05:51:54 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 208352 kb
Host smart-ecf0eaab-ba49-4da6-b32d-ace1a96e56a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315294534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3315294534
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.566805429
Short name T903
Test name
Test status
Simulation time 260538986 ps
CPU time 2.88 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 208744 kb
Host smart-6de3b808-8da4-4f87-9d4e-a0ad63757875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566805429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.566805429
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.709422742
Short name T811
Test name
Test status
Simulation time 447365618 ps
CPU time 5.98 seconds
Started Aug 15 05:52:07 PM PDT 24
Finished Aug 15 05:52:13 PM PDT 24
Peak memory 221352 kb
Host smart-9d1a1133-20cc-4fe5-8a8e-319aa0c1d484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709422742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.709422742
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3653574445
Short name T482
Test name
Test status
Simulation time 1241672302 ps
CPU time 10.51 seconds
Started Aug 15 05:52:04 PM PDT 24
Finished Aug 15 05:52:15 PM PDT 24
Peak memory 214764 kb
Host smart-ea1b0c27-094d-43ed-9515-e9f9a6fd326a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653574445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3653574445
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.32191886
Short name T57
Test name
Test status
Simulation time 33545319 ps
CPU time 1.32 seconds
Started Aug 15 05:52:03 PM PDT 24
Finished Aug 15 05:52:05 PM PDT 24
Peak memory 209976 kb
Host smart-106dfa37-13d6-4230-be1f-10eb9879971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32191886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.32191886
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1450880213
Short name T763
Test name
Test status
Simulation time 22593070 ps
CPU time 1 seconds
Started Aug 15 05:52:13 PM PDT 24
Finished Aug 15 05:52:14 PM PDT 24
Peak memory 206528 kb
Host smart-1212f867-c17c-44bd-85cd-bad435550552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450880213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1450880213
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2888442462
Short name T421
Test name
Test status
Simulation time 32478682 ps
CPU time 2.95 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:01 PM PDT 24
Peak memory 214660 kb
Host smart-1e4f4f1e-fc39-4979-a13d-3a185c947bbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888442462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2888442462
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2335775708
Short name T839
Test name
Test status
Simulation time 150666307 ps
CPU time 2.37 seconds
Started Aug 15 05:52:14 PM PDT 24
Finished Aug 15 05:52:17 PM PDT 24
Peak memory 219528 kb
Host smart-63ddd6e1-c0dd-4d7f-bb43-4da46abccdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335775708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2335775708
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1948973109
Short name T398
Test name
Test status
Simulation time 57418548 ps
CPU time 1.38 seconds
Started Aug 15 05:51:59 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 208636 kb
Host smart-c982e6ab-1de7-494c-bc9b-5a63540e8b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948973109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1948973109
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1284780478
Short name T392
Test name
Test status
Simulation time 1161883430 ps
CPU time 7.36 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 220284 kb
Host smart-60ffe78a-1847-413b-b10e-f3afcbf0481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284780478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1284780478
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.577837666
Short name T278
Test name
Test status
Simulation time 65187577 ps
CPU time 1.88 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:51:53 PM PDT 24
Peak memory 214632 kb
Host smart-63141b36-cee2-49a0-92f9-7e7385b7999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577837666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.577837666
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3466668837
Short name T554
Test name
Test status
Simulation time 105168484 ps
CPU time 1.84 seconds
Started Aug 15 05:51:53 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 206584 kb
Host smart-5c948ff0-8666-4146-9958-4ce6f7671a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466668837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3466668837
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2195727685
Short name T615
Test name
Test status
Simulation time 2477310095 ps
CPU time 9.24 seconds
Started Aug 15 05:52:02 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 210144 kb
Host smart-bbd73e7f-e7b9-41e1-88d5-14847c43ab82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195727685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2195727685
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.339625107
Short name T301
Test name
Test status
Simulation time 2052479613 ps
CPU time 9.19 seconds
Started Aug 15 05:52:02 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 207424 kb
Host smart-0d297d44-ab1d-4f97-956d-862eb9bbca81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339625107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.339625107
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2951862046
Short name T15
Test name
Test status
Simulation time 90456487 ps
CPU time 3.29 seconds
Started Aug 15 05:51:56 PM PDT 24
Finished Aug 15 05:51:59 PM PDT 24
Peak memory 209044 kb
Host smart-50a9cb0a-7713-4634-9240-2979cc8c7283
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951862046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2951862046
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3261333885
Short name T484
Test name
Test status
Simulation time 828565729 ps
CPU time 10.11 seconds
Started Aug 15 05:52:01 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 209428 kb
Host smart-9302b3e7-13c3-48e0-91d1-7abccbd4f906
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261333885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3261333885
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1653564492
Short name T493
Test name
Test status
Simulation time 219545310 ps
CPU time 2.85 seconds
Started Aug 15 05:52:10 PM PDT 24
Finished Aug 15 05:52:13 PM PDT 24
Peak memory 209184 kb
Host smart-416cb5c3-164f-4e45-8129-96692e2ccc41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653564492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1653564492
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1393555609
Short name T676
Test name
Test status
Simulation time 126790522 ps
CPU time 2.41 seconds
Started Aug 15 05:51:58 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 207828 kb
Host smart-4b67302d-bcdf-4ecd-affd-4d64d281b997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393555609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1393555609
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.354688073
Short name T740
Test name
Test status
Simulation time 172060897 ps
CPU time 4.62 seconds
Started Aug 15 05:52:05 PM PDT 24
Finished Aug 15 05:52:09 PM PDT 24
Peak memory 207224 kb
Host smart-e958a699-c1de-461e-ade3-f7f1077b86ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354688073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.354688073
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1147023598
Short name T669
Test name
Test status
Simulation time 590659832 ps
CPU time 29.55 seconds
Started Aug 15 05:51:51 PM PDT 24
Finished Aug 15 05:52:21 PM PDT 24
Peak memory 222884 kb
Host smart-5e3f779d-2384-40bf-8a39-ccdb582e9845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147023598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1147023598
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.874346072
Short name T881
Test name
Test status
Simulation time 735240760 ps
CPU time 7.82 seconds
Started Aug 15 05:52:02 PM PDT 24
Finished Aug 15 05:52:10 PM PDT 24
Peak memory 223040 kb
Host smart-b66ceda2-4409-4ca0-a231-c13984a5ca52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874346072 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.874346072
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1568190845
Short name T148
Test name
Test status
Simulation time 1538915272 ps
CPU time 9.84 seconds
Started Aug 15 05:51:50 PM PDT 24
Finished Aug 15 05:52:01 PM PDT 24
Peak memory 208096 kb
Host smart-536af307-a522-49b2-a9cc-900cacaf5487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568190845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1568190845
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.783709167
Short name T208
Test name
Test status
Simulation time 4453645029 ps
CPU time 17.39 seconds
Started Aug 15 05:51:56 PM PDT 24
Finished Aug 15 05:52:13 PM PDT 24
Peak memory 212136 kb
Host smart-e2bff0b1-6bcf-4065-8b00-63dfbe08cc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783709167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.783709167
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1045698747
Short name T888
Test name
Test status
Simulation time 27914515 ps
CPU time 0.74 seconds
Started Aug 15 05:52:08 PM PDT 24
Finished Aug 15 05:52:09 PM PDT 24
Peak memory 206340 kb
Host smart-2a73731b-897d-41a4-bbc7-e9a70efac819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045698747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1045698747
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.447844516
Short name T79
Test name
Test status
Simulation time 2507046630 ps
CPU time 29.76 seconds
Started Aug 15 05:51:58 PM PDT 24
Finished Aug 15 05:52:28 PM PDT 24
Peak memory 223284 kb
Host smart-5a1b0973-644d-4e18-8948-2dd253d0a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447844516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.447844516
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4143880466
Short name T633
Test name
Test status
Simulation time 576658196 ps
CPU time 2.03 seconds
Started Aug 15 05:52:05 PM PDT 24
Finished Aug 15 05:52:07 PM PDT 24
Peak memory 209820 kb
Host smart-d79c12cc-ad1c-427e-9e14-23a181ead9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143880466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4143880466
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.505847702
Short name T390
Test name
Test status
Simulation time 210147183 ps
CPU time 4.86 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:05 PM PDT 24
Peak memory 222916 kb
Host smart-6ae283e2-b1a8-4c54-8c71-775b135d962a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505847702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.505847702
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2500778647
Short name T786
Test name
Test status
Simulation time 197556636 ps
CPU time 2.15 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:00 PM PDT 24
Peak memory 214652 kb
Host smart-653745c9-1ca9-48be-bd2e-1bf24a31fbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500778647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2500778647
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2536811347
Short name T77
Test name
Test status
Simulation time 63727288 ps
CPU time 3.57 seconds
Started Aug 15 05:51:55 PM PDT 24
Finished Aug 15 05:51:58 PM PDT 24
Peak memory 214768 kb
Host smart-6d9ed47e-b465-4d41-9191-8f20bc414843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536811347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2536811347
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2083306454
Short name T476
Test name
Test status
Simulation time 5272149278 ps
CPU time 33.86 seconds
Started Aug 15 05:52:07 PM PDT 24
Finished Aug 15 05:52:41 PM PDT 24
Peak memory 209028 kb
Host smart-fb4fa032-55e3-45b6-be20-8eab5ef15889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083306454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2083306454
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.242431209
Short name T297
Test name
Test status
Simulation time 322104156 ps
CPU time 6.75 seconds
Started Aug 15 05:51:54 PM PDT 24
Finished Aug 15 05:52:01 PM PDT 24
Peak memory 209104 kb
Host smart-a37235b1-4fee-4246-bb84-85b5960dc0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242431209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.242431209
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2909093817
Short name T488
Test name
Test status
Simulation time 976534187 ps
CPU time 6.21 seconds
Started Aug 15 05:51:58 PM PDT 24
Finished Aug 15 05:52:04 PM PDT 24
Peak memory 208432 kb
Host smart-283d2ecc-d382-4ba7-b082-295d8a38eb00
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909093817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2909093817
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3853396916
Short name T514
Test name
Test status
Simulation time 105135951 ps
CPU time 2.36 seconds
Started Aug 15 05:52:09 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 207376 kb
Host smart-c9322a0a-65d6-4b47-8c3a-e2fa769256c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853396916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3853396916
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3792362175
Short name T670
Test name
Test status
Simulation time 1766158391 ps
CPU time 46.46 seconds
Started Aug 15 05:52:14 PM PDT 24
Finished Aug 15 05:53:01 PM PDT 24
Peak memory 208988 kb
Host smart-da3c27b4-fb04-42ab-a5b4-cab579dab43b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792362175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3792362175
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1780679263
Short name T356
Test name
Test status
Simulation time 682718295 ps
CPU time 6.83 seconds
Started Aug 15 05:52:02 PM PDT 24
Finished Aug 15 05:52:09 PM PDT 24
Peak memory 209452 kb
Host smart-772359c6-f7bb-4b85-92d6-20559542cc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780679263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1780679263
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.531726674
Short name T547
Test name
Test status
Simulation time 418175781 ps
CPU time 4.08 seconds
Started Aug 15 05:52:08 PM PDT 24
Finished Aug 15 05:52:12 PM PDT 24
Peak memory 207456 kb
Host smart-2842ce62-7213-40d1-b292-94eb0b305ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531726674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.531726674
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2388782627
Short name T381
Test name
Test status
Simulation time 1415888848 ps
CPU time 19.97 seconds
Started Aug 15 05:52:19 PM PDT 24
Finished Aug 15 05:52:39 PM PDT 24
Peak memory 215536 kb
Host smart-2f8b8848-575a-45f6-9644-9d9a79c6094b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388782627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2388782627
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1489428465
Short name T890
Test name
Test status
Simulation time 178165073 ps
CPU time 6.72 seconds
Started Aug 15 05:51:52 PM PDT 24
Finished Aug 15 05:51:59 PM PDT 24
Peak memory 218756 kb
Host smart-6c8a93d0-b982-4dd3-a375-667c8f9b1391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489428465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1489428465
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2826466970
Short name T14
Test name
Test status
Simulation time 14691320 ps
CPU time 1 seconds
Started Aug 15 05:50:35 PM PDT 24
Finished Aug 15 05:50:36 PM PDT 24
Peak memory 206464 kb
Host smart-9bf881b4-2ca4-458b-b433-8eac65a2ed88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826466970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2826466970
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.231038323
Short name T793
Test name
Test status
Simulation time 46878721 ps
CPU time 2.31 seconds
Started Aug 15 05:50:39 PM PDT 24
Finished Aug 15 05:50:41 PM PDT 24
Peak memory 208400 kb
Host smart-53ad8737-e004-44ef-b57c-b25c9cd87061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231038323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.231038323
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2422340762
Short name T583
Test name
Test status
Simulation time 203007192 ps
CPU time 2.01 seconds
Started Aug 15 05:50:44 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 214732 kb
Host smart-3ee00f83-39f7-4dac-9b27-d9502ecf65c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422340762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2422340762
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3715157486
Short name T51
Test name
Test status
Simulation time 53812248 ps
CPU time 3.38 seconds
Started Aug 15 05:50:36 PM PDT 24
Finished Aug 15 05:50:39 PM PDT 24
Peak memory 221472 kb
Host smart-7766177f-19dc-47d0-8e04-f50396073b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715157486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3715157486
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.4054131125
Short name T76
Test name
Test status
Simulation time 427745618 ps
CPU time 4.27 seconds
Started Aug 15 05:50:32 PM PDT 24
Finished Aug 15 05:50:37 PM PDT 24
Peak memory 210816 kb
Host smart-dacb093a-d17a-4e7d-8002-872922f96cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054131125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.4054131125
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1080694965
Short name T147
Test name
Test status
Simulation time 280711020 ps
CPU time 5.64 seconds
Started Aug 15 05:50:35 PM PDT 24
Finished Aug 15 05:50:41 PM PDT 24
Peak memory 214756 kb
Host smart-c27a324b-33be-4044-8a27-b9c8c530b4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080694965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1080694965
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1580333810
Short name T459
Test name
Test status
Simulation time 544945358 ps
CPU time 4.64 seconds
Started Aug 15 05:50:29 PM PDT 24
Finished Aug 15 05:50:33 PM PDT 24
Peak memory 207408 kb
Host smart-35c63e5a-5a68-4854-9c56-0e793e351515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580333810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1580333810
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.162163553
Short name T815
Test name
Test status
Simulation time 127125351 ps
CPU time 2.47 seconds
Started Aug 15 05:50:34 PM PDT 24
Finished Aug 15 05:50:37 PM PDT 24
Peak memory 209084 kb
Host smart-42398688-f5ad-402b-ab94-6da601190070
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162163553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.162163553
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3683305647
Short name T447
Test name
Test status
Simulation time 129581398 ps
CPU time 2.44 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:34 PM PDT 24
Peak memory 207244 kb
Host smart-c4fe1c72-b34f-4af9-9235-d0c85740f68c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683305647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3683305647
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2531018317
Short name T703
Test name
Test status
Simulation time 36253056 ps
CPU time 2.45 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:34 PM PDT 24
Peak memory 207484 kb
Host smart-5e52bab8-79df-4b85-a30c-e6da8483921d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531018317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2531018317
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3116933722
Short name T363
Test name
Test status
Simulation time 88712094 ps
CPU time 4.06 seconds
Started Aug 15 05:50:29 PM PDT 24
Finished Aug 15 05:50:33 PM PDT 24
Peak memory 218800 kb
Host smart-06d540f3-bbdd-40d7-8d8d-34fe81c357f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116933722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3116933722
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.562643022
Short name T549
Test name
Test status
Simulation time 1132503154 ps
CPU time 27.64 seconds
Started Aug 15 05:50:29 PM PDT 24
Finished Aug 15 05:50:56 PM PDT 24
Peak memory 208348 kb
Host smart-32728c73-c790-4b28-8362-683daa5b0fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562643022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.562643022
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1203081703
Short name T902
Test name
Test status
Simulation time 17831846960 ps
CPU time 303.31 seconds
Started Aug 15 05:50:44 PM PDT 24
Finished Aug 15 05:55:48 PM PDT 24
Peak memory 222996 kb
Host smart-65320c71-d493-4421-b721-3d8432b14667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203081703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1203081703
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.313714013
Short name T228
Test name
Test status
Simulation time 492763735 ps
CPU time 7.81 seconds
Started Aug 15 05:50:38 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 223032 kb
Host smart-af404b28-7077-448b-887e-4c9d1b43ce0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313714013 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.313714013
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.753241283
Short name T314
Test name
Test status
Simulation time 453132543 ps
CPU time 5.76 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:37 PM PDT 24
Peak memory 210856 kb
Host smart-ffcea5d6-d715-44ae-9c7f-2e1bb8e667e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753241283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.753241283
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.31728887
Short name T744
Test name
Test status
Simulation time 962840373 ps
CPU time 16.31 seconds
Started Aug 15 05:50:29 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 211432 kb
Host smart-a4e34c54-3ae6-4772-876e-8df867ce8604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31728887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.31728887
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2696222175
Short name T440
Test name
Test status
Simulation time 34156496 ps
CPU time 0.82 seconds
Started Aug 15 05:52:10 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 206572 kb
Host smart-274d4a4d-d9cc-48ee-8018-df40ce856e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696222175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2696222175
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2836499152
Short name T769
Test name
Test status
Simulation time 141320265 ps
CPU time 3.86 seconds
Started Aug 15 05:52:03 PM PDT 24
Finished Aug 15 05:52:07 PM PDT 24
Peak memory 210432 kb
Host smart-7acb2abf-b502-4918-98fb-3d167d2416c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836499152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2836499152
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.826169640
Short name T782
Test name
Test status
Simulation time 781056785 ps
CPU time 5.36 seconds
Started Aug 15 05:51:52 PM PDT 24
Finished Aug 15 05:51:57 PM PDT 24
Peak memory 208560 kb
Host smart-08987440-e1e1-41d1-bab4-af7f9f32d9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826169640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.826169640
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3378554310
Short name T384
Test name
Test status
Simulation time 1280802195 ps
CPU time 3.21 seconds
Started Aug 15 05:52:23 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 214756 kb
Host smart-32b86533-927d-4ba8-a669-e3f63436a52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378554310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3378554310
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_random.1752543390
Short name T726
Test name
Test status
Simulation time 372278182 ps
CPU time 7.59 seconds
Started Aug 15 05:51:55 PM PDT 24
Finished Aug 15 05:52:02 PM PDT 24
Peak memory 213616 kb
Host smart-1b765f68-66e5-4e12-8f39-53d8e0214638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752543390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1752543390
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.183310532
Short name T904
Test name
Test status
Simulation time 843685288 ps
CPU time 7.45 seconds
Started Aug 15 05:52:04 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 208892 kb
Host smart-49386b48-c8ed-4ff8-b7ee-6a198b471ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183310532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.183310532
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.581249604
Short name T834
Test name
Test status
Simulation time 153073903 ps
CPU time 2.71 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:03 PM PDT 24
Peak memory 206292 kb
Host smart-75bdf023-90b6-4843-9e93-9365af01b5cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581249604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.581249604
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3764780345
Short name T689
Test name
Test status
Simulation time 768531393 ps
CPU time 6.48 seconds
Started Aug 15 05:52:20 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 209372 kb
Host smart-0ecd7f27-8595-4f43-a1ed-bc741912e15f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764780345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3764780345
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3379779991
Short name T461
Test name
Test status
Simulation time 683433882 ps
CPU time 5.81 seconds
Started Aug 15 05:52:09 PM PDT 24
Finished Aug 15 05:52:15 PM PDT 24
Peak memory 209324 kb
Host smart-8c788824-0b9c-481e-90eb-5687842fbb64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379779991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3379779991
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2951357574
Short name T262
Test name
Test status
Simulation time 135839936 ps
CPU time 3.57 seconds
Started Aug 15 05:51:58 PM PDT 24
Finished Aug 15 05:52:02 PM PDT 24
Peak memory 214788 kb
Host smart-7d754369-b72c-4834-933d-e60a6dde0542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951357574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2951357574
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1081981975
Short name T683
Test name
Test status
Simulation time 1504294213 ps
CPU time 9.51 seconds
Started Aug 15 05:51:55 PM PDT 24
Finished Aug 15 05:52:04 PM PDT 24
Peak memory 207588 kb
Host smart-6f1e47ba-adbd-4077-93d0-a114e1e2fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081981975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1081981975
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1025129463
Short name T55
Test name
Test status
Simulation time 63851786546 ps
CPU time 202.12 seconds
Started Aug 15 05:52:19 PM PDT 24
Finished Aug 15 05:55:41 PM PDT 24
Peak memory 222864 kb
Host smart-0399cdcb-6f58-42fb-aef7-1877dd63bb8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025129463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1025129463
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1012692636
Short name T140
Test name
Test status
Simulation time 557642057 ps
CPU time 10.13 seconds
Started Aug 15 05:51:59 PM PDT 24
Finished Aug 15 05:52:14 PM PDT 24
Peak memory 223096 kb
Host smart-020c48ba-814e-4af6-aad8-bf300a328906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012692636 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1012692636
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4155106086
Short name T270
Test name
Test status
Simulation time 2964737054 ps
CPU time 36.01 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:36 PM PDT 24
Peak memory 209756 kb
Host smart-af81f142-6484-4beb-8a33-fae1f5c57399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155106086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4155106086
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.13955800
Short name T143
Test name
Test status
Simulation time 100439224 ps
CPU time 2.33 seconds
Started Aug 15 05:52:10 PM PDT 24
Finished Aug 15 05:52:13 PM PDT 24
Peak memory 210356 kb
Host smart-b9504c4c-880e-4f67-9e23-a7369c398ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13955800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.13955800
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4201862595
Short name T468
Test name
Test status
Simulation time 12813160 ps
CPU time 0.89 seconds
Started Aug 15 05:52:30 PM PDT 24
Finished Aug 15 05:52:31 PM PDT 24
Peak memory 206348 kb
Host smart-27969145-3e81-4250-8371-15db3070e919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201862595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4201862595
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2555646480
Short name T307
Test name
Test status
Simulation time 1413890341 ps
CPU time 76.9 seconds
Started Aug 15 05:52:10 PM PDT 24
Finished Aug 15 05:53:27 PM PDT 24
Peak memory 216660 kb
Host smart-05b20fc4-06bc-4e3b-9c89-da072849932b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555646480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2555646480
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3783667173
Short name T292
Test name
Test status
Simulation time 343219016 ps
CPU time 2.88 seconds
Started Aug 15 05:52:03 PM PDT 24
Finished Aug 15 05:52:06 PM PDT 24
Peak memory 207924 kb
Host smart-fbd07a22-095c-4b99-a331-8c0c697e07b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783667173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3783667173
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1987320447
Short name T24
Test name
Test status
Simulation time 4828312873 ps
CPU time 8.09 seconds
Started Aug 15 05:52:13 PM PDT 24
Finished Aug 15 05:52:22 PM PDT 24
Peak memory 209924 kb
Host smart-3c2b8f54-a981-45ce-982d-18bc7faa38a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987320447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1987320447
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3807930522
Short name T350
Test name
Test status
Simulation time 397298860 ps
CPU time 2.86 seconds
Started Aug 15 05:52:14 PM PDT 24
Finished Aug 15 05:52:17 PM PDT 24
Peak memory 214696 kb
Host smart-a9c932c1-b0f1-4f17-9b69-db8c55c4f7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807930522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3807930522
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.480728398
Short name T227
Test name
Test status
Simulation time 127618103 ps
CPU time 5.76 seconds
Started Aug 15 05:52:20 PM PDT 24
Finished Aug 15 05:52:26 PM PDT 24
Peak memory 214696 kb
Host smart-a186b153-9800-4103-8669-a9028239760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480728398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.480728398
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3101239217
Short name T788
Test name
Test status
Simulation time 437023100 ps
CPU time 3.61 seconds
Started Aug 15 05:52:14 PM PDT 24
Finished Aug 15 05:52:18 PM PDT 24
Peak memory 207892 kb
Host smart-4dce1400-15f3-4243-add0-2dfc28b9077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101239217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3101239217
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1259691116
Short name T473
Test name
Test status
Simulation time 185101968 ps
CPU time 2.27 seconds
Started Aug 15 05:52:19 PM PDT 24
Finished Aug 15 05:52:21 PM PDT 24
Peak memory 207344 kb
Host smart-06df0e0c-2c16-44db-b6f1-a49de0eb9fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259691116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1259691116
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3754192065
Short name T517
Test name
Test status
Simulation time 207866125 ps
CPU time 6.56 seconds
Started Aug 15 05:52:17 PM PDT 24
Finished Aug 15 05:52:24 PM PDT 24
Peak memory 209220 kb
Host smart-6df0db3b-8967-4c77-96d3-d742f328071d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754192065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3754192065
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2880601341
Short name T98
Test name
Test status
Simulation time 357724186 ps
CPU time 12.52 seconds
Started Aug 15 05:52:22 PM PDT 24
Finished Aug 15 05:52:34 PM PDT 24
Peak memory 209172 kb
Host smart-98ae3166-482f-49dc-9625-0e7daea0c91d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880601341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2880601341
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1056092170
Short name T830
Test name
Test status
Simulation time 66741627 ps
CPU time 3.34 seconds
Started Aug 15 05:52:08 PM PDT 24
Finished Aug 15 05:52:12 PM PDT 24
Peak memory 209496 kb
Host smart-e18dd39a-978c-48c4-8819-1fa137f6678b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056092170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1056092170
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1397593838
Short name T217
Test name
Test status
Simulation time 466954646 ps
CPU time 4.66 seconds
Started Aug 15 05:52:04 PM PDT 24
Finished Aug 15 05:52:09 PM PDT 24
Peak memory 210148 kb
Host smart-90c15b4f-960b-460c-be0d-8907af268d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397593838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1397593838
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2673482727
Short name T536
Test name
Test status
Simulation time 652854802 ps
CPU time 11.89 seconds
Started Aug 15 05:52:09 PM PDT 24
Finished Aug 15 05:52:21 PM PDT 24
Peak memory 208872 kb
Host smart-66ca3aaf-b723-4f8c-855b-beea5e7016f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673482727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2673482727
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2770426843
Short name T451
Test name
Test status
Simulation time 103696130 ps
CPU time 3.56 seconds
Started Aug 15 05:51:57 PM PDT 24
Finished Aug 15 05:52:01 PM PDT 24
Peak memory 210640 kb
Host smart-142ff5e0-9604-4bee-b9eb-5073e5c87b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770426843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2770426843
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3987931149
Short name T499
Test name
Test status
Simulation time 51397236 ps
CPU time 1.91 seconds
Started Aug 15 05:52:06 PM PDT 24
Finished Aug 15 05:52:08 PM PDT 24
Peak memory 210776 kb
Host smart-4dbb0ab4-ddd3-4c36-a59f-f2e12569b7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987931149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3987931149
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3022184468
Short name T433
Test name
Test status
Simulation time 52822577 ps
CPU time 0.91 seconds
Started Aug 15 05:52:17 PM PDT 24
Finished Aug 15 05:52:18 PM PDT 24
Peak memory 206524 kb
Host smart-7ee5e485-6c62-446c-a885-adc719a8e840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022184468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3022184468
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2835036793
Short name T419
Test name
Test status
Simulation time 196581894 ps
CPU time 4.06 seconds
Started Aug 15 05:52:12 PM PDT 24
Finished Aug 15 05:52:16 PM PDT 24
Peak memory 214784 kb
Host smart-b6014850-f16e-4eeb-973a-fb2f185bb2c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835036793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2835036793
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3901096005
Short name T875
Test name
Test status
Simulation time 91506197 ps
CPU time 1.3 seconds
Started Aug 15 05:52:14 PM PDT 24
Finished Aug 15 05:52:15 PM PDT 24
Peak memory 208236 kb
Host smart-f8933995-0c36-423d-bd27-1aadd964cb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901096005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3901096005
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1991332541
Short name T84
Test name
Test status
Simulation time 38447714 ps
CPU time 2.63 seconds
Started Aug 15 05:52:11 PM PDT 24
Finished Aug 15 05:52:14 PM PDT 24
Peak memory 209532 kb
Host smart-feb07e4b-71d9-4c4c-a92c-18200879f622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991332541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1991332541
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.655905032
Short name T575
Test name
Test status
Simulation time 181012673 ps
CPU time 4.63 seconds
Started Aug 15 05:52:15 PM PDT 24
Finished Aug 15 05:52:20 PM PDT 24
Peak memory 215040 kb
Host smart-7fba87a1-569a-4368-8e93-b65bc7780ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655905032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.655905032
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1442721218
Short name T114
Test name
Test status
Simulation time 253027069 ps
CPU time 3.63 seconds
Started Aug 15 05:52:11 PM PDT 24
Finished Aug 15 05:52:14 PM PDT 24
Peak memory 222784 kb
Host smart-206c0abf-d73c-4fac-98d3-8fe6e5e673f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442721218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1442721218
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1497135126
Short name T281
Test name
Test status
Simulation time 453440298 ps
CPU time 3.56 seconds
Started Aug 15 05:52:23 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 215580 kb
Host smart-4af3d8b8-5df2-4111-ba63-d78a4d442d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497135126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1497135126
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.725169339
Short name T661
Test name
Test status
Simulation time 240684373 ps
CPU time 5.2 seconds
Started Aug 15 05:52:02 PM PDT 24
Finished Aug 15 05:52:07 PM PDT 24
Peak memory 209216 kb
Host smart-a8ddab86-b1b2-47a6-90ca-5f5d6a201a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725169339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.725169339
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2683062628
Short name T346
Test name
Test status
Simulation time 662523632 ps
CPU time 5.94 seconds
Started Aug 15 05:52:21 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 207320 kb
Host smart-7dfb70f1-8843-444b-9927-ecc7bb004dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683062628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2683062628
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.721842700
Short name T564
Test name
Test status
Simulation time 1994414222 ps
CPU time 7.95 seconds
Started Aug 15 05:52:19 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 208880 kb
Host smart-39c37c6f-5ad5-49d3-81ec-b51c78fb0443
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721842700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.721842700
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3601910436
Short name T567
Test name
Test status
Simulation time 60245799 ps
CPU time 3.11 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:03 PM PDT 24
Peak memory 209216 kb
Host smart-927ceb36-47ea-4b7a-a807-25d966c2d900
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601910436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3601910436
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1532663824
Short name T527
Test name
Test status
Simulation time 78263249 ps
CPU time 3.57 seconds
Started Aug 15 05:51:58 PM PDT 24
Finished Aug 15 05:52:02 PM PDT 24
Peak memory 209508 kb
Host smart-f0501fca-4a63-4354-b060-8c069df77de0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532663824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1532663824
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2878982298
Short name T856
Test name
Test status
Simulation time 397734255 ps
CPU time 2.76 seconds
Started Aug 15 05:52:09 PM PDT 24
Finished Aug 15 05:52:12 PM PDT 24
Peak memory 207272 kb
Host smart-2e34d20b-1b56-4ddd-a331-b04fbd468d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878982298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2878982298
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4028994919
Short name T291
Test name
Test status
Simulation time 529285455 ps
CPU time 8.45 seconds
Started Aug 15 05:52:02 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 220572 kb
Host smart-2486f2da-c212-4c58-9000-1738dcc6ac79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028994919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4028994919
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3899865427
Short name T135
Test name
Test status
Simulation time 1255242828 ps
CPU time 11.53 seconds
Started Aug 15 05:52:06 PM PDT 24
Finished Aug 15 05:52:18 PM PDT 24
Peak memory 222984 kb
Host smart-34ee2946-7e47-4295-b0b4-d6f69f876d60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899865427 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3899865427
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1944430546
Short name T91
Test name
Test status
Simulation time 2020813270 ps
CPU time 11.34 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 214740 kb
Host smart-e9e7328d-c191-4717-9061-cf93e6bab174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944430546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1944430546
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3573689679
Short name T194
Test name
Test status
Simulation time 167783490 ps
CPU time 2.39 seconds
Started Aug 15 05:52:22 PM PDT 24
Finished Aug 15 05:52:25 PM PDT 24
Peak memory 210784 kb
Host smart-373601a1-9392-4d35-8f24-a6be1af38394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573689679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3573689679
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.562519053
Short name T587
Test name
Test status
Simulation time 18613045 ps
CPU time 1.03 seconds
Started Aug 15 05:52:33 PM PDT 24
Finished Aug 15 05:52:35 PM PDT 24
Peak memory 206564 kb
Host smart-2eef5bf9-701e-4289-9fc7-d7dfa71c8e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562519053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.562519053
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.4259694930
Short name T417
Test name
Test status
Simulation time 65058899 ps
CPU time 2.88 seconds
Started Aug 15 05:52:00 PM PDT 24
Finished Aug 15 05:52:03 PM PDT 24
Peak memory 214736 kb
Host smart-30552d2f-4514-4d7c-b337-10f61a20705c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259694930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4259694930
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3494603789
Short name T686
Test name
Test status
Simulation time 2274112049 ps
CPU time 14.22 seconds
Started Aug 15 05:52:17 PM PDT 24
Finished Aug 15 05:52:31 PM PDT 24
Peak memory 218948 kb
Host smart-62130e44-fa36-4508-a87e-dd14c8f4a0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494603789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3494603789
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2822586738
Short name T328
Test name
Test status
Simulation time 190816035 ps
CPU time 3.17 seconds
Started Aug 15 05:52:18 PM PDT 24
Finished Aug 15 05:52:21 PM PDT 24
Peak memory 215024 kb
Host smart-f6d7ab9b-8607-448a-adab-e73e9507a09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822586738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2822586738
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2301488863
Short name T385
Test name
Test status
Simulation time 275733109 ps
CPU time 4 seconds
Started Aug 15 05:52:10 PM PDT 24
Finished Aug 15 05:52:14 PM PDT 24
Peak memory 222100 kb
Host smart-25a14427-6d5f-4fc8-a67e-531c63c30ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301488863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2301488863
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2816548469
Short name T652
Test name
Test status
Simulation time 96244766 ps
CPU time 1.47 seconds
Started Aug 15 05:52:14 PM PDT 24
Finished Aug 15 05:52:16 PM PDT 24
Peak memory 206564 kb
Host smart-9b75984a-44e9-4319-b170-6c068f36a10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816548469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2816548469
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4028278030
Short name T470
Test name
Test status
Simulation time 446203788 ps
CPU time 9 seconds
Started Aug 15 05:52:22 PM PDT 24
Finished Aug 15 05:52:31 PM PDT 24
Peak memory 208796 kb
Host smart-0b995419-0e50-4237-b6da-23d6917109fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028278030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4028278030
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1999163571
Short name T336
Test name
Test status
Simulation time 4079445787 ps
CPU time 24.99 seconds
Started Aug 15 05:52:07 PM PDT 24
Finished Aug 15 05:52:32 PM PDT 24
Peak memory 209224 kb
Host smart-f442e1f8-1b24-4bda-b05f-8fbc3fabee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999163571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1999163571
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.611416876
Short name T906
Test name
Test status
Simulation time 2943408772 ps
CPU time 24.58 seconds
Started Aug 15 05:52:21 PM PDT 24
Finished Aug 15 05:52:45 PM PDT 24
Peak memory 209608 kb
Host smart-77300439-6161-4656-ac03-5fdd7d99cc3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611416876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.611416876
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.846236105
Short name T797
Test name
Test status
Simulation time 1441115737 ps
CPU time 32.86 seconds
Started Aug 15 05:52:23 PM PDT 24
Finished Aug 15 05:52:56 PM PDT 24
Peak memory 208936 kb
Host smart-65832dba-5a5d-4adc-8479-5272695c31cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846236105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.846236105
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3437658746
Short name T870
Test name
Test status
Simulation time 85282698 ps
CPU time 3.5 seconds
Started Aug 15 05:52:23 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 207448 kb
Host smart-5dc647f5-5c9a-43d2-a08e-ebdc4df4d957
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437658746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3437658746
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.222912454
Short name T837
Test name
Test status
Simulation time 238484261 ps
CPU time 3.05 seconds
Started Aug 15 05:52:17 PM PDT 24
Finished Aug 15 05:52:20 PM PDT 24
Peak memory 209108 kb
Host smart-47a2bfd6-531e-42f0-a017-c070400066a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222912454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.222912454
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2765788934
Short name T586
Test name
Test status
Simulation time 117160749 ps
CPU time 4.44 seconds
Started Aug 15 05:52:09 PM PDT 24
Finished Aug 15 05:52:14 PM PDT 24
Peak memory 208952 kb
Host smart-7f9813d0-91b4-42f2-bbd4-351d48967534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765788934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2765788934
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4114908950
Short name T8
Test name
Test status
Simulation time 15494340808 ps
CPU time 245.31 seconds
Started Aug 15 05:52:01 PM PDT 24
Finished Aug 15 05:56:06 PM PDT 24
Peak memory 222968 kb
Host smart-fd4bd6e0-dca9-4350-9a0a-f5cba47f42df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114908950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4114908950
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1156510471
Short name T243
Test name
Test status
Simulation time 365019950 ps
CPU time 24.61 seconds
Started Aug 15 05:52:17 PM PDT 24
Finished Aug 15 05:52:42 PM PDT 24
Peak memory 223004 kb
Host smart-c6d8272b-14d5-44ad-93b2-2723f6bafa49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156510471 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1156510471
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1534390153
Short name T805
Test name
Test status
Simulation time 39327944 ps
CPU time 2.83 seconds
Started Aug 15 05:52:19 PM PDT 24
Finished Aug 15 05:52:22 PM PDT 24
Peak memory 214808 kb
Host smart-f3b6df7c-4882-4568-9020-5fe995e7d2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534390153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1534390153
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1480374607
Short name T887
Test name
Test status
Simulation time 10351034 ps
CPU time 0.77 seconds
Started Aug 15 05:52:24 PM PDT 24
Finished Aug 15 05:52:25 PM PDT 24
Peak memory 206420 kb
Host smart-017318b3-84c6-4825-8c66-3e50faec3d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480374607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1480374607
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3173429590
Short name T422
Test name
Test status
Simulation time 128743659 ps
CPU time 6.84 seconds
Started Aug 15 05:52:18 PM PDT 24
Finished Aug 15 05:52:25 PM PDT 24
Peak memory 215692 kb
Host smart-41c2c2e2-601c-424b-9267-94dff2c6e6b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3173429590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3173429590
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1987678223
Short name T908
Test name
Test status
Simulation time 83975839 ps
CPU time 3.03 seconds
Started Aug 15 05:52:17 PM PDT 24
Finished Aug 15 05:52:20 PM PDT 24
Peak memory 207900 kb
Host smart-e95dce3d-7cef-422c-8eeb-c07e4693d2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987678223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1987678223
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.947182242
Short name T332
Test name
Test status
Simulation time 432188903 ps
CPU time 3.8 seconds
Started Aug 15 05:52:07 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 214808 kb
Host smart-62211010-dd2e-4375-847b-91a01e6c7f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947182242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.947182242
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.31288293
Short name T41
Test name
Test status
Simulation time 80269263 ps
CPU time 1.77 seconds
Started Aug 15 05:52:27 PM PDT 24
Finished Aug 15 05:52:29 PM PDT 24
Peak memory 214672 kb
Host smart-7d8b0062-0a24-40d7-97d6-067a343b3b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31288293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.31288293
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.4107617255
Short name T550
Test name
Test status
Simulation time 101251525 ps
CPU time 4.04 seconds
Started Aug 15 05:52:26 PM PDT 24
Finished Aug 15 05:52:30 PM PDT 24
Peak memory 215764 kb
Host smart-f6a7ec93-b785-43b9-8821-615346aef2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107617255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.4107617255
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.767163501
Short name T900
Test name
Test status
Simulation time 454391317 ps
CPU time 4.1 seconds
Started Aug 15 05:52:18 PM PDT 24
Finished Aug 15 05:52:22 PM PDT 24
Peak memory 218808 kb
Host smart-79e03a06-b97d-4e40-8989-6b83e310bf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767163501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.767163501
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1848661457
Short name T868
Test name
Test status
Simulation time 81619572 ps
CPU time 1.72 seconds
Started Aug 15 05:52:09 PM PDT 24
Finished Aug 15 05:52:10 PM PDT 24
Peak memory 207900 kb
Host smart-19459fd8-a4de-46b0-a325-7614d4000828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848661457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1848661457
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2475916481
Short name T486
Test name
Test status
Simulation time 238154447 ps
CPU time 6.04 seconds
Started Aug 15 05:52:12 PM PDT 24
Finished Aug 15 05:52:18 PM PDT 24
Peak memory 208428 kb
Host smart-35515425-025f-4f63-9288-bac82c3460fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475916481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2475916481
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2040908452
Short name T572
Test name
Test status
Simulation time 36400526 ps
CPU time 2.38 seconds
Started Aug 15 05:52:25 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 207400 kb
Host smart-e1a5f722-f5c4-49a9-91f1-38fc29f3a13c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040908452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2040908452
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.459801903
Short name T853
Test name
Test status
Simulation time 106110532 ps
CPU time 1.92 seconds
Started Aug 15 05:52:16 PM PDT 24
Finished Aug 15 05:52:18 PM PDT 24
Peak memory 207460 kb
Host smart-96b42200-d2d8-4d97-ba8c-56ac2e71e4f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459801903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.459801903
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1701094721
Short name T867
Test name
Test status
Simulation time 78456288 ps
CPU time 1.97 seconds
Started Aug 15 05:52:20 PM PDT 24
Finished Aug 15 05:52:22 PM PDT 24
Peak memory 218740 kb
Host smart-ff66e266-a8b7-4182-9065-efe1b404747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701094721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1701094721
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2154107886
Short name T646
Test name
Test status
Simulation time 89273542 ps
CPU time 2.53 seconds
Started Aug 15 05:52:20 PM PDT 24
Finished Aug 15 05:52:23 PM PDT 24
Peak memory 207360 kb
Host smart-82eb9a06-dd08-435e-a410-f800a862818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154107886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2154107886
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1910299458
Short name T199
Test name
Test status
Simulation time 896362518 ps
CPU time 6.4 seconds
Started Aug 15 05:52:31 PM PDT 24
Finished Aug 15 05:52:38 PM PDT 24
Peak memory 222968 kb
Host smart-824d79aa-ef8d-4a8b-9fe8-a18c1af5d130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910299458 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1910299458
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2005633305
Short name T265
Test name
Test status
Simulation time 132577642 ps
CPU time 3.22 seconds
Started Aug 15 05:52:25 PM PDT 24
Finished Aug 15 05:52:28 PM PDT 24
Peak memory 208028 kb
Host smart-df5796a5-3682-4526-8576-0de71751c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005633305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2005633305
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2117989601
Short name T829
Test name
Test status
Simulation time 342796671 ps
CPU time 2.56 seconds
Started Aug 15 05:52:30 PM PDT 24
Finished Aug 15 05:52:33 PM PDT 24
Peak memory 210428 kb
Host smart-16cd92b8-e891-4e3f-955b-824d725750ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117989601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2117989601
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.873377618
Short name T876
Test name
Test status
Simulation time 56679293 ps
CPU time 0.88 seconds
Started Aug 15 05:52:18 PM PDT 24
Finished Aug 15 05:52:24 PM PDT 24
Peak memory 206388 kb
Host smart-330dae06-0620-42af-a2e0-8ef367aebc67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873377618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.873377618
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.829835548
Short name T418
Test name
Test status
Simulation time 74144677 ps
CPU time 3.49 seconds
Started Aug 15 05:52:17 PM PDT 24
Finished Aug 15 05:52:20 PM PDT 24
Peak memory 214744 kb
Host smart-9e083b5a-2993-4608-b5e7-7b7980a50f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829835548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.829835548
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1717944708
Short name T81
Test name
Test status
Simulation time 157373710 ps
CPU time 3.56 seconds
Started Aug 15 05:52:14 PM PDT 24
Finished Aug 15 05:52:17 PM PDT 24
Peak memory 218580 kb
Host smart-b6cfdc9c-a3fc-41b6-8a8a-2896c378e7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717944708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1717944708
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1792465728
Short name T832
Test name
Test status
Simulation time 278663337 ps
CPU time 2.79 seconds
Started Aug 15 05:52:23 PM PDT 24
Finished Aug 15 05:52:26 PM PDT 24
Peak memory 215012 kb
Host smart-65b82655-30e6-49f1-bba7-9810cc9b965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792465728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1792465728
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.462190313
Short name T330
Test name
Test status
Simulation time 310321843 ps
CPU time 3.85 seconds
Started Aug 15 05:52:18 PM PDT 24
Finished Aug 15 05:52:22 PM PDT 24
Peak memory 214672 kb
Host smart-8d7ff1ce-fc12-42c6-a9b6-60b05479ed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462190313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.462190313
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.750228060
Short name T749
Test name
Test status
Simulation time 337249766 ps
CPU time 3.62 seconds
Started Aug 15 05:52:24 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 220528 kb
Host smart-74ad12d5-da50-4486-937a-802600968533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750228060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.750228060
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.910859355
Short name T496
Test name
Test status
Simulation time 110244601 ps
CPU time 5.24 seconds
Started Aug 15 05:52:11 PM PDT 24
Finished Aug 15 05:52:16 PM PDT 24
Peak memory 208564 kb
Host smart-c453efa4-ea63-4b03-a99b-a3ce03056346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910859355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.910859355
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.609415900
Short name T791
Test name
Test status
Simulation time 339135580 ps
CPU time 5.36 seconds
Started Aug 15 05:52:10 PM PDT 24
Finished Aug 15 05:52:16 PM PDT 24
Peak memory 207444 kb
Host smart-e45b9844-7e78-41c3-b74f-e49abdf0883f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609415900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.609415900
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2474491467
Short name T100
Test name
Test status
Simulation time 698620321 ps
CPU time 5.78 seconds
Started Aug 15 05:52:30 PM PDT 24
Finished Aug 15 05:52:36 PM PDT 24
Peak memory 209080 kb
Host smart-e92e50e3-ab99-45d0-a21b-ca9f8f69749f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474491467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2474491467
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.30197793
Short name T455
Test name
Test status
Simulation time 284943556 ps
CPU time 4.55 seconds
Started Aug 15 05:52:19 PM PDT 24
Finished Aug 15 05:52:24 PM PDT 24
Peak memory 208544 kb
Host smart-0ccb74ce-08c8-4950-a953-28ac70327451
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30197793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.30197793
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2970483052
Short name T548
Test name
Test status
Simulation time 33703397 ps
CPU time 2.27 seconds
Started Aug 15 05:52:06 PM PDT 24
Finished Aug 15 05:52:08 PM PDT 24
Peak memory 207892 kb
Host smart-15f9d0df-ad54-4eb0-a95a-6ce8d49e394d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970483052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2970483052
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1625776904
Short name T718
Test name
Test status
Simulation time 91665697 ps
CPU time 3.73 seconds
Started Aug 15 05:52:04 PM PDT 24
Finished Aug 15 05:52:08 PM PDT 24
Peak memory 210868 kb
Host smart-3ee91295-89dd-4919-a017-65173cae6461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625776904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1625776904
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3443032945
Short name T545
Test name
Test status
Simulation time 615677055 ps
CPU time 12.14 seconds
Started Aug 15 05:52:08 PM PDT 24
Finished Aug 15 05:52:20 PM PDT 24
Peak memory 208400 kb
Host smart-d2480675-7146-4e57-8150-09d262241901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443032945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3443032945
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2638712334
Short name T87
Test name
Test status
Simulation time 737406552 ps
CPU time 16.6 seconds
Started Aug 15 05:52:23 PM PDT 24
Finished Aug 15 05:52:39 PM PDT 24
Peak memory 215424 kb
Host smart-c59c6f18-84d7-4ae5-aa51-63e21c006a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638712334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2638712334
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3262493651
Short name T627
Test name
Test status
Simulation time 34463970 ps
CPU time 2.27 seconds
Started Aug 15 05:52:15 PM PDT 24
Finished Aug 15 05:52:18 PM PDT 24
Peak memory 209960 kb
Host smart-cb8a9fba-eed9-48b3-9a7a-e4afff33a094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262493651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3262493651
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1414701305
Short name T799
Test name
Test status
Simulation time 1452208842 ps
CPU time 4.09 seconds
Started Aug 15 05:52:25 PM PDT 24
Finished Aug 15 05:52:29 PM PDT 24
Peak memory 210988 kb
Host smart-c84c1ec5-6ad8-449a-a80d-52e460663967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414701305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1414701305
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.696951244
Short name T598
Test name
Test status
Simulation time 42052931 ps
CPU time 0.79 seconds
Started Aug 15 05:52:20 PM PDT 24
Finished Aug 15 05:52:21 PM PDT 24
Peak memory 206352 kb
Host smart-2f541d49-0e8f-4154-b88b-7ea4d76b09bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696951244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.696951244
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2787006025
Short name T776
Test name
Test status
Simulation time 404135912 ps
CPU time 3.28 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:52:44 PM PDT 24
Peak memory 223128 kb
Host smart-e3fd417e-344b-4481-bb7d-f68c17051471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787006025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2787006025
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3555523757
Short name T684
Test name
Test status
Simulation time 140377176 ps
CPU time 4.2 seconds
Started Aug 15 05:52:33 PM PDT 24
Finished Aug 15 05:52:37 PM PDT 24
Peak memory 208368 kb
Host smart-4bd9a41c-1ed6-4dce-aa3e-063a0857cd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555523757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3555523757
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1678154353
Short name T256
Test name
Test status
Simulation time 93132266 ps
CPU time 4.19 seconds
Started Aug 15 05:52:30 PM PDT 24
Finished Aug 15 05:52:34 PM PDT 24
Peak memory 214760 kb
Host smart-e2f2225f-f05c-4c4c-812b-f0b79afa4c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678154353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1678154353
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2338197439
Short name T540
Test name
Test status
Simulation time 192546308 ps
CPU time 3.35 seconds
Started Aug 15 05:52:40 PM PDT 24
Finished Aug 15 05:52:44 PM PDT 24
Peak memory 214716 kb
Host smart-b39ab4f6-a40e-4c93-9f99-1610c1ffa86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338197439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2338197439
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.214252299
Short name T415
Test name
Test status
Simulation time 72429805 ps
CPU time 2.44 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:52:47 PM PDT 24
Peak memory 216860 kb
Host smart-63ef5c9c-174f-49c3-9536-1f340f20a479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214252299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.214252299
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3454913388
Short name T709
Test name
Test status
Simulation time 246456852 ps
CPU time 8.96 seconds
Started Aug 15 05:52:28 PM PDT 24
Finished Aug 15 05:52:37 PM PDT 24
Peak memory 209440 kb
Host smart-f0ae9a73-d8b1-47be-8f32-68905c84f8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454913388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3454913388
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4151945322
Short name T780
Test name
Test status
Simulation time 62367046 ps
CPU time 2.38 seconds
Started Aug 15 05:52:23 PM PDT 24
Finished Aug 15 05:52:25 PM PDT 24
Peak memory 207452 kb
Host smart-ffcc6eb3-8420-4dfd-b405-2e9249ab2b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151945322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4151945322
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3601890981
Short name T809
Test name
Test status
Simulation time 302015181 ps
CPU time 2.96 seconds
Started Aug 15 05:52:13 PM PDT 24
Finished Aug 15 05:52:16 PM PDT 24
Peak memory 207372 kb
Host smart-c36b1ea5-0b8c-4b27-88c6-464dc3cd1aca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601890981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3601890981
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2940891911
Short name T378
Test name
Test status
Simulation time 259484947 ps
CPU time 3.45 seconds
Started Aug 15 05:52:13 PM PDT 24
Finished Aug 15 05:52:17 PM PDT 24
Peak memory 207884 kb
Host smart-8b683155-f945-4073-8c81-229b3ca14a6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940891911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2940891911
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1098803277
Short name T687
Test name
Test status
Simulation time 59309242 ps
CPU time 2.95 seconds
Started Aug 15 05:52:08 PM PDT 24
Finished Aug 15 05:52:11 PM PDT 24
Peak memory 207296 kb
Host smart-c25765df-2377-47b0-859c-3bef4dc9553e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098803277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1098803277
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.798956095
Short name T308
Test name
Test status
Simulation time 172949808 ps
CPU time 2.75 seconds
Started Aug 15 05:52:24 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 214756 kb
Host smart-ee4308cb-93aa-4522-aea7-3065403f900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798956095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.798956095
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2765625862
Short name T444
Test name
Test status
Simulation time 1148849017 ps
CPU time 5.34 seconds
Started Aug 15 05:52:10 PM PDT 24
Finished Aug 15 05:52:15 PM PDT 24
Peak memory 208752 kb
Host smart-70d43cfd-8806-49fa-8f6e-ba8f8f852cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765625862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2765625862
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1371173097
Short name T73
Test name
Test status
Simulation time 4602822307 ps
CPU time 43.06 seconds
Started Aug 15 05:52:32 PM PDT 24
Finished Aug 15 05:53:15 PM PDT 24
Peak memory 222952 kb
Host smart-8b8159da-ca98-45ee-9fa1-5562a476215b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371173097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1371173097
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3950998419
Short name T258
Test name
Test status
Simulation time 30954653 ps
CPU time 2.3 seconds
Started Aug 15 05:52:38 PM PDT 24
Finished Aug 15 05:52:41 PM PDT 24
Peak memory 214776 kb
Host smart-444aba58-5629-48b0-83e8-fb1912bac888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950998419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3950998419
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2304638830
Short name T889
Test name
Test status
Simulation time 153310815 ps
CPU time 2.02 seconds
Started Aug 15 05:52:33 PM PDT 24
Finished Aug 15 05:52:35 PM PDT 24
Peak memory 210276 kb
Host smart-167536d6-1ea5-463f-8eda-d78c7c20a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304638830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2304638830
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3557871421
Short name T712
Test name
Test status
Simulation time 37890908 ps
CPU time 0.83 seconds
Started Aug 15 05:52:39 PM PDT 24
Finished Aug 15 05:52:40 PM PDT 24
Peak memory 206408 kb
Host smart-d571b9e7-8f32-45c5-bb22-fdeb7597d5e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557871421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3557871421
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2409944561
Short name T61
Test name
Test status
Simulation time 99772991 ps
CPU time 3.16 seconds
Started Aug 15 05:52:28 PM PDT 24
Finished Aug 15 05:52:31 PM PDT 24
Peak memory 207768 kb
Host smart-36d1cf8a-74e0-4f83-bb30-5ad810a5fca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409944561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2409944561
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.152393662
Short name T391
Test name
Test status
Simulation time 90782394 ps
CPU time 4.08 seconds
Started Aug 15 05:52:27 PM PDT 24
Finished Aug 15 05:52:31 PM PDT 24
Peak memory 214688 kb
Host smart-39afbaaf-4ecf-4cff-abb4-34534403dbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152393662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.152393662
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2785652523
Short name T294
Test name
Test status
Simulation time 287502585 ps
CPU time 3.85 seconds
Started Aug 15 05:52:21 PM PDT 24
Finished Aug 15 05:52:25 PM PDT 24
Peak memory 214664 kb
Host smart-ac05f3bc-5f3e-4be7-b254-afe821c201c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785652523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2785652523
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3014803823
Short name T508
Test name
Test status
Simulation time 102224184 ps
CPU time 2.02 seconds
Started Aug 15 05:52:26 PM PDT 24
Finished Aug 15 05:52:33 PM PDT 24
Peak memory 206548 kb
Host smart-e9125a85-82a4-4346-8889-24795c638c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014803823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3014803823
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3993099731
Short name T565
Test name
Test status
Simulation time 520104456 ps
CPU time 6.24 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:52:47 PM PDT 24
Peak memory 208636 kb
Host smart-f59216ff-b483-433f-ac85-0b5acc82565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993099731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3993099731
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.4019191552
Short name T213
Test name
Test status
Simulation time 1365313859 ps
CPU time 13.31 seconds
Started Aug 15 05:52:24 PM PDT 24
Finished Aug 15 05:52:37 PM PDT 24
Peak memory 208512 kb
Host smart-c92f6b6e-0f05-4562-9738-afa569a4bba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019191552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.4019191552
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1282172496
Short name T893
Test name
Test status
Simulation time 317082160 ps
CPU time 3.96 seconds
Started Aug 15 05:52:30 PM PDT 24
Finished Aug 15 05:52:34 PM PDT 24
Peak memory 209320 kb
Host smart-f1c42ceb-2bde-480b-a722-23037ed7f905
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282172496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1282172496
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1787113540
Short name T585
Test name
Test status
Simulation time 1462518885 ps
CPU time 32.06 seconds
Started Aug 15 05:52:32 PM PDT 24
Finished Aug 15 05:53:04 PM PDT 24
Peak memory 209404 kb
Host smart-495dd0df-34fa-4a66-a090-8a0ec3f33bfb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787113540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1787113540
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.884508070
Short name T848
Test name
Test status
Simulation time 162473721 ps
CPU time 2.46 seconds
Started Aug 15 05:52:32 PM PDT 24
Finished Aug 15 05:52:35 PM PDT 24
Peak memory 208916 kb
Host smart-158f2d3f-d0fa-44fa-9344-79712d587850
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884508070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.884508070
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4043423658
Short name T489
Test name
Test status
Simulation time 322388152 ps
CPU time 3.67 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:52:48 PM PDT 24
Peak memory 216332 kb
Host smart-2190f2f7-6db3-4a74-bdac-42740754db56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043423658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4043423658
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1017837368
Short name T743
Test name
Test status
Simulation time 386004952 ps
CPU time 6.51 seconds
Started Aug 15 05:52:36 PM PDT 24
Finished Aug 15 05:52:43 PM PDT 24
Peak memory 209296 kb
Host smart-4ea80221-0349-4d43-8840-f123e05d0fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017837368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1017837368
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.814474668
Short name T821
Test name
Test status
Simulation time 744270833 ps
CPU time 8.14 seconds
Started Aug 15 05:52:40 PM PDT 24
Finished Aug 15 05:52:49 PM PDT 24
Peak memory 216808 kb
Host smart-6fcf1b8e-f52b-4b7d-a4a9-d8cc44803575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814474668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.814474668
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2824192603
Short name T354
Test name
Test status
Simulation time 246529973 ps
CPU time 15.66 seconds
Started Aug 15 05:52:25 PM PDT 24
Finished Aug 15 05:52:41 PM PDT 24
Peak memory 222992 kb
Host smart-db7117f7-9f68-4668-b0b8-69377b3e28f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824192603 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2824192603
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2942374521
Short name T800
Test name
Test status
Simulation time 188277804 ps
CPU time 3.13 seconds
Started Aug 15 05:52:37 PM PDT 24
Finished Aug 15 05:52:40 PM PDT 24
Peak memory 208500 kb
Host smart-4d7661c7-7911-4991-a760-ac8ccec36c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942374521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2942374521
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2541762432
Short name T172
Test name
Test status
Simulation time 200637632 ps
CPU time 5.22 seconds
Started Aug 15 05:52:39 PM PDT 24
Finished Aug 15 05:52:44 PM PDT 24
Peak memory 210900 kb
Host smart-ea403e84-0731-4c34-881e-bfb23c57d5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541762432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2541762432
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.156529981
Short name T450
Test name
Test status
Simulation time 17077514 ps
CPU time 0.88 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:44 PM PDT 24
Peak memory 206400 kb
Host smart-a47bd02e-45c5-49e3-b095-12a2eac62b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156529981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.156529981
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1764767636
Short name T298
Test name
Test status
Simulation time 156498239 ps
CPU time 3.13 seconds
Started Aug 15 05:52:33 PM PDT 24
Finished Aug 15 05:52:37 PM PDT 24
Peak memory 215832 kb
Host smart-0b60ef2b-22ce-4e10-a3f3-1cb0b6b67a9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1764767636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1764767636
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3451913137
Short name T605
Test name
Test status
Simulation time 43840366 ps
CPU time 3.36 seconds
Started Aug 15 05:52:38 PM PDT 24
Finished Aug 15 05:52:41 PM PDT 24
Peak memory 214780 kb
Host smart-03024181-8349-4657-ac6e-7f6555c0f222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451913137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3451913137
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.910244743
Short name T510
Test name
Test status
Simulation time 176170443 ps
CPU time 1.74 seconds
Started Aug 15 05:52:26 PM PDT 24
Finished Aug 15 05:52:28 PM PDT 24
Peak memory 208760 kb
Host smart-94a86866-1d09-4885-bf25-b2618f135fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910244743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.910244743
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.462635888
Short name T251
Test name
Test status
Simulation time 131284031 ps
CPU time 4.43 seconds
Started Aug 15 05:52:37 PM PDT 24
Finished Aug 15 05:52:42 PM PDT 24
Peak memory 214760 kb
Host smart-a5081559-7cf1-4d6d-80e3-c7c2cf28c9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462635888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.462635888
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3766449898
Short name T580
Test name
Test status
Simulation time 158595373 ps
CPU time 5.75 seconds
Started Aug 15 05:52:38 PM PDT 24
Finished Aug 15 05:52:44 PM PDT 24
Peak memory 222776 kb
Host smart-2f753c73-a68a-4161-9141-5b969b032f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766449898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3766449898
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_random.208019540
Short name T634
Test name
Test status
Simulation time 4332290051 ps
CPU time 53.84 seconds
Started Aug 15 05:52:31 PM PDT 24
Finished Aug 15 05:53:25 PM PDT 24
Peak memory 218828 kb
Host smart-fc9b79d0-9933-42a5-a2b3-dc3921fdbde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208019540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.208019540
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2196078273
Short name T584
Test name
Test status
Simulation time 439026758 ps
CPU time 3.45 seconds
Started Aug 15 05:52:56 PM PDT 24
Finished Aug 15 05:52:59 PM PDT 24
Peak memory 207904 kb
Host smart-f75d8dfb-c94f-4e11-b75d-0b549a36718f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196078273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2196078273
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1683379517
Short name T521
Test name
Test status
Simulation time 60565379 ps
CPU time 3.06 seconds
Started Aug 15 05:52:30 PM PDT 24
Finished Aug 15 05:52:34 PM PDT 24
Peak memory 207356 kb
Host smart-4b50f2a6-0cc6-4960-93a6-0947223bb9e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683379517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1683379517
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3392959865
Short name T429
Test name
Test status
Simulation time 258417294 ps
CPU time 2.8 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:52:44 PM PDT 24
Peak memory 207448 kb
Host smart-81c9b52f-d543-40df-83cf-add6ecdd45ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392959865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3392959865
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3061937466
Short name T495
Test name
Test status
Simulation time 295867554 ps
CPU time 3.16 seconds
Started Aug 15 05:52:28 PM PDT 24
Finished Aug 15 05:52:31 PM PDT 24
Peak memory 207208 kb
Host smart-23be9054-f7ac-449d-9876-a50bde6d0d32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061937466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3061937466
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1448278549
Short name T214
Test name
Test status
Simulation time 3745661942 ps
CPU time 12.04 seconds
Started Aug 15 05:52:37 PM PDT 24
Finished Aug 15 05:52:49 PM PDT 24
Peak memory 216932 kb
Host smart-b3d045d0-5c5e-411c-8f46-2576b091807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448278549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1448278549
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.415375022
Short name T122
Test name
Test status
Simulation time 105545703 ps
CPU time 2.54 seconds
Started Aug 15 05:52:33 PM PDT 24
Finished Aug 15 05:52:37 PM PDT 24
Peak memory 207388 kb
Host smart-f849b0cb-1dee-4971-a305-469d50a74cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415375022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.415375022
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3618831308
Short name T377
Test name
Test status
Simulation time 1738621858 ps
CPU time 11.85 seconds
Started Aug 15 05:52:35 PM PDT 24
Finished Aug 15 05:52:47 PM PDT 24
Peak memory 216516 kb
Host smart-c6681f8f-44b4-4567-a1c8-c5e5174c314e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618831308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3618831308
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.280335025
Short name T63
Test name
Test status
Simulation time 361674911 ps
CPU time 8.36 seconds
Started Aug 15 05:52:23 PM PDT 24
Finished Aug 15 05:52:31 PM PDT 24
Peak memory 220192 kb
Host smart-bcfc8849-5552-436d-8fdc-00256c3c01c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280335025 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.280335025
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.294466297
Short name T443
Test name
Test status
Simulation time 469566346 ps
CPU time 5.7 seconds
Started Aug 15 05:52:35 PM PDT 24
Finished Aug 15 05:52:41 PM PDT 24
Peak memory 214676 kb
Host smart-7e583675-38db-4cfa-b213-acf70893abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294466297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.294466297
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.986827862
Short name T94
Test name
Test status
Simulation time 77178006 ps
CPU time 2.02 seconds
Started Aug 15 05:52:34 PM PDT 24
Finished Aug 15 05:52:37 PM PDT 24
Peak memory 210464 kb
Host smart-3cb7c9fe-230b-419c-9df7-7ea4b30a2944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986827862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.986827862
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3546737427
Short name T873
Test name
Test status
Simulation time 19808009 ps
CPU time 0.76 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:44 PM PDT 24
Peak memory 206328 kb
Host smart-7148a6ba-80a9-4b4c-b876-c6745d4baa82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546737427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3546737427
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2021552552
Short name T397
Test name
Test status
Simulation time 40819773 ps
CPU time 3.07 seconds
Started Aug 15 05:52:37 PM PDT 24
Finished Aug 15 05:52:41 PM PDT 24
Peak memory 214780 kb
Host smart-9f536471-28d8-42d6-ab3f-9bf842a195a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2021552552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2021552552
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1393325276
Short name T795
Test name
Test status
Simulation time 64881225 ps
CPU time 4.23 seconds
Started Aug 15 05:52:36 PM PDT 24
Finished Aug 15 05:52:41 PM PDT 24
Peak memory 209456 kb
Host smart-9e279c40-0802-4a93-9144-2f3def095a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393325276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1393325276
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.616033302
Short name T750
Test name
Test status
Simulation time 414866946 ps
CPU time 3.33 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:46 PM PDT 24
Peak memory 220108 kb
Host smart-7384a89c-0e11-4b0e-80f5-6883853b68ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616033302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.616033302
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2690230075
Short name T108
Test name
Test status
Simulation time 1852159082 ps
CPU time 21.8 seconds
Started Aug 15 05:52:39 PM PDT 24
Finished Aug 15 05:53:01 PM PDT 24
Peak memory 214676 kb
Host smart-4daaabef-80b2-4f45-86bb-581054749c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690230075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2690230075
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.39742968
Short name T542
Test name
Test status
Simulation time 356409304 ps
CPU time 2.69 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:45 PM PDT 24
Peak memory 214700 kb
Host smart-8d718278-3229-4e53-86af-802e07baf3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39742968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.39742968
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.507915386
Short name T662
Test name
Test status
Simulation time 441830606 ps
CPU time 3.79 seconds
Started Aug 15 05:52:28 PM PDT 24
Finished Aug 15 05:52:32 PM PDT 24
Peak memory 214788 kb
Host smart-fdb3ee0f-5cb1-4204-b32c-44c532a83050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507915386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.507915386
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2204773126
Short name T626
Test name
Test status
Simulation time 523931315 ps
CPU time 8.82 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:52:53 PM PDT 24
Peak memory 207324 kb
Host smart-ed4afb3a-a9d1-4f2d-aa1e-c1ee4d13385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204773126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2204773126
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1187614555
Short name T629
Test name
Test status
Simulation time 113119268 ps
CPU time 3.1 seconds
Started Aug 15 05:52:30 PM PDT 24
Finished Aug 15 05:52:33 PM PDT 24
Peak memory 209240 kb
Host smart-dbf806fc-d132-4a0d-96a8-b87ba1e6e388
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187614555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1187614555
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.190521741
Short name T680
Test name
Test status
Simulation time 40906831 ps
CPU time 2.37 seconds
Started Aug 15 05:52:25 PM PDT 24
Finished Aug 15 05:52:27 PM PDT 24
Peak memory 208752 kb
Host smart-f0176fdf-8f0e-425f-8c58-0282c6d916e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190521741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.190521741
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2831548573
Short name T477
Test name
Test status
Simulation time 165118858 ps
CPU time 4.09 seconds
Started Aug 15 05:52:35 PM PDT 24
Finished Aug 15 05:52:39 PM PDT 24
Peak memory 209392 kb
Host smart-db0a4c28-5369-4215-9b21-debc647d02c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831548573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2831548573
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.750546897
Short name T810
Test name
Test status
Simulation time 72171423 ps
CPU time 1.71 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:49 PM PDT 24
Peak memory 208756 kb
Host smart-6d9e02f4-90fc-4013-a964-b29dbd2df48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750546897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.750546897
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2378171298
Short name T97
Test name
Test status
Simulation time 4578383651 ps
CPU time 35.22 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:53:18 PM PDT 24
Peak memory 208908 kb
Host smart-e3f724d1-972d-4a0a-bfda-49db462f495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378171298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2378171298
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.4054688308
Short name T654
Test name
Test status
Simulation time 1238785259 ps
CPU time 28.15 seconds
Started Aug 15 05:52:38 PM PDT 24
Finished Aug 15 05:53:07 PM PDT 24
Peak memory 222788 kb
Host smart-9a882a45-6299-4170-8d0a-ce0d44d7ca26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054688308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4054688308
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2297875525
Short name T704
Test name
Test status
Simulation time 362022452 ps
CPU time 5.55 seconds
Started Aug 15 05:52:39 PM PDT 24
Finished Aug 15 05:52:45 PM PDT 24
Peak memory 208608 kb
Host smart-fe70b2ac-e9f9-45dd-b880-c6fa42735cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297875525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2297875525
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1531890343
Short name T668
Test name
Test status
Simulation time 182834022 ps
CPU time 1.76 seconds
Started Aug 15 05:52:39 PM PDT 24
Finished Aug 15 05:52:47 PM PDT 24
Peak memory 210568 kb
Host smart-9a7668c0-535a-41fb-8861-cfb26185b885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531890343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1531890343
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4215116916
Short name T466
Test name
Test status
Simulation time 17625981 ps
CPU time 1.03 seconds
Started Aug 15 05:50:43 PM PDT 24
Finished Aug 15 05:50:44 PM PDT 24
Peak memory 206624 kb
Host smart-80cbb3e4-723e-433c-9230-428ae3d7af7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215116916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4215116916
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3006261963
Short name T909
Test name
Test status
Simulation time 770392777 ps
CPU time 42.34 seconds
Started Aug 15 05:50:34 PM PDT 24
Finished Aug 15 05:51:16 PM PDT 24
Peak memory 215688 kb
Host smart-01bbc19a-7555-44a6-8a9b-2f4096f71f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3006261963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3006261963
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2011890506
Short name T224
Test name
Test status
Simulation time 284328736 ps
CPU time 4.43 seconds
Started Aug 15 05:50:29 PM PDT 24
Finished Aug 15 05:50:34 PM PDT 24
Peak memory 223008 kb
Host smart-10cd30cd-1cbf-4346-9785-d4374b7ab572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011890506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2011890506
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2051549242
Short name T274
Test name
Test status
Simulation time 70424195 ps
CPU time 3.42 seconds
Started Aug 15 05:50:29 PM PDT 24
Finished Aug 15 05:50:33 PM PDT 24
Peak memory 214760 kb
Host smart-7735c1ef-fb86-495e-a654-2474a2b2e3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051549242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2051549242
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2226930489
Short name T93
Test name
Test status
Simulation time 240643697 ps
CPU time 3.67 seconds
Started Aug 15 05:50:30 PM PDT 24
Finished Aug 15 05:50:34 PM PDT 24
Peak memory 209856 kb
Host smart-5ab30fb8-11e0-479d-b8c0-4f3adb4116ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226930489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2226930489
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.203045778
Short name T353
Test name
Test status
Simulation time 37293229 ps
CPU time 2.33 seconds
Started Aug 15 05:50:36 PM PDT 24
Finished Aug 15 05:50:39 PM PDT 24
Peak memory 214716 kb
Host smart-e1b76a87-af3b-4976-9a84-0f3bf9e27ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203045778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.203045778
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2339926343
Short name T313
Test name
Test status
Simulation time 204619390 ps
CPU time 3.62 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:35 PM PDT 24
Peak memory 220156 kb
Host smart-766887c6-eeaa-4b0d-81e0-942d7655d90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339926343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2339926343
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2210626428
Short name T694
Test name
Test status
Simulation time 603208841 ps
CPU time 6.32 seconds
Started Aug 15 05:50:43 PM PDT 24
Finished Aug 15 05:50:50 PM PDT 24
Peak memory 220132 kb
Host smart-069995d2-1074-4234-8152-cdd957d3d912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210626428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2210626428
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3007446057
Short name T847
Test name
Test status
Simulation time 1423460962 ps
CPU time 30.37 seconds
Started Aug 15 05:50:40 PM PDT 24
Finished Aug 15 05:51:11 PM PDT 24
Peak memory 208708 kb
Host smart-8803bf8d-3392-4025-bb2b-2d5baa979f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007446057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3007446057
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2353445055
Short name T814
Test name
Test status
Simulation time 90968617 ps
CPU time 3.21 seconds
Started Aug 15 05:50:28 PM PDT 24
Finished Aug 15 05:50:31 PM PDT 24
Peak memory 207360 kb
Host smart-f49d2f0a-b1a4-4382-bb87-eb8b5379821e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353445055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2353445055
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2327059487
Short name T533
Test name
Test status
Simulation time 65767373 ps
CPU time 3.34 seconds
Started Aug 15 05:50:33 PM PDT 24
Finished Aug 15 05:50:37 PM PDT 24
Peak memory 208604 kb
Host smart-09bec2ca-cb28-4169-ab2b-9b314525e979
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327059487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2327059487
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2800970516
Short name T511
Test name
Test status
Simulation time 57416817 ps
CPU time 2.4 seconds
Started Aug 15 05:50:38 PM PDT 24
Finished Aug 15 05:50:40 PM PDT 24
Peak memory 207316 kb
Host smart-5dce1313-f609-4929-a85b-9d885c937813
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800970516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2800970516
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3888756279
Short name T806
Test name
Test status
Simulation time 1210989349 ps
CPU time 15.43 seconds
Started Aug 15 05:50:29 PM PDT 24
Finished Aug 15 05:50:45 PM PDT 24
Peak memory 214736 kb
Host smart-6af254ab-034d-4175-8575-0414e73523b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888756279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3888756279
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1507410504
Short name T588
Test name
Test status
Simulation time 314974298 ps
CPU time 2.75 seconds
Started Aug 15 05:50:30 PM PDT 24
Finished Aug 15 05:50:33 PM PDT 24
Peak memory 207624 kb
Host smart-e3b4d3fc-3986-4c7d-85db-9c92f56edcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507410504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1507410504
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.4110987275
Short name T894
Test name
Test status
Simulation time 1052641169 ps
CPU time 31.31 seconds
Started Aug 15 05:50:28 PM PDT 24
Finished Aug 15 05:51:00 PM PDT 24
Peak memory 216648 kb
Host smart-7ef92ddb-3372-4f75-ab0b-272ee3539e06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110987275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.4110987275
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.797717711
Short name T286
Test name
Test status
Simulation time 873770031 ps
CPU time 4.97 seconds
Started Aug 15 05:50:37 PM PDT 24
Finished Aug 15 05:50:42 PM PDT 24
Peak memory 207732 kb
Host smart-ddecae3b-afac-4df2-973e-fb63acde8068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797717711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.797717711
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.334589366
Short name T621
Test name
Test status
Simulation time 5850391411 ps
CPU time 31.6 seconds
Started Aug 15 05:50:45 PM PDT 24
Finished Aug 15 05:51:17 PM PDT 24
Peak memory 211964 kb
Host smart-3178dd98-0b75-49ce-b30a-a165c6b0b020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334589366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.334589366
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.410617255
Short name T445
Test name
Test status
Simulation time 14702857 ps
CPU time 0.94 seconds
Started Aug 15 05:50:45 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 206544 kb
Host smart-611cee8c-54c9-44fc-a375-229c296f4c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410617255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.410617255
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.4278730144
Short name T44
Test name
Test status
Simulation time 313083922 ps
CPU time 4.09 seconds
Started Aug 15 05:50:44 PM PDT 24
Finished Aug 15 05:50:49 PM PDT 24
Peak memory 214768 kb
Host smart-4b1179e1-87b8-4b35-b522-5affa716dfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278730144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4278730144
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2350982007
Short name T82
Test name
Test status
Simulation time 362004684 ps
CPU time 2.49 seconds
Started Aug 15 05:50:32 PM PDT 24
Finished Aug 15 05:50:35 PM PDT 24
Peak memory 210112 kb
Host smart-a92ee211-a7b1-4301-9553-1be2280adc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350982007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2350982007
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2908846182
Short name T284
Test name
Test status
Simulation time 157041603 ps
CPU time 3.07 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:34 PM PDT 24
Peak memory 214848 kb
Host smart-5b804057-b94e-4b20-819b-020e879022ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908846182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2908846182
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1103575552
Short name T864
Test name
Test status
Simulation time 826960577 ps
CPU time 5.22 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:36 PM PDT 24
Peak memory 222052 kb
Host smart-b4621239-939c-407b-8435-bc4debd09704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103575552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1103575552
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1410108011
Short name T725
Test name
Test status
Simulation time 167633147 ps
CPU time 2.51 seconds
Started Aug 15 05:50:32 PM PDT 24
Finished Aug 15 05:50:35 PM PDT 24
Peak memory 220520 kb
Host smart-d2348051-20c8-4feb-9be8-8faae461c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410108011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1410108011
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.757331298
Short name T692
Test name
Test status
Simulation time 176357983 ps
CPU time 4.87 seconds
Started Aug 15 05:50:30 PM PDT 24
Finished Aug 15 05:50:40 PM PDT 24
Peak memory 209352 kb
Host smart-c958cfba-7223-48fc-ba92-a5e34b454ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757331298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.757331298
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1890923101
Short name T636
Test name
Test status
Simulation time 49827040 ps
CPU time 2.98 seconds
Started Aug 15 05:50:38 PM PDT 24
Finished Aug 15 05:50:42 PM PDT 24
Peak memory 207428 kb
Host smart-7fca259a-40ef-4fdf-a840-8087ef40b51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890923101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1890923101
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1209558524
Short name T767
Test name
Test status
Simulation time 3060652764 ps
CPU time 31.02 seconds
Started Aug 15 05:50:37 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 208460 kb
Host smart-d25b6e7b-b0ec-4f4c-b760-9e63c533428f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209558524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1209558524
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.59423933
Short name T534
Test name
Test status
Simulation time 217521904 ps
CPU time 5.85 seconds
Started Aug 15 05:50:35 PM PDT 24
Finished Aug 15 05:50:41 PM PDT 24
Peak memory 208388 kb
Host smart-a397163c-92e2-49a5-bd6e-47d2146ab710
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59423933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.59423933
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1365609138
Short name T558
Test name
Test status
Simulation time 106359518 ps
CPU time 2.61 seconds
Started Aug 15 05:50:30 PM PDT 24
Finished Aug 15 05:50:33 PM PDT 24
Peak memory 207364 kb
Host smart-c567dec8-d741-4df6-baee-7c5beea45d5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365609138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1365609138
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3176843314
Short name T518
Test name
Test status
Simulation time 346066138 ps
CPU time 3.79 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:35 PM PDT 24
Peak memory 208720 kb
Host smart-d661a825-db18-4e0d-acfe-770b06ed333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176843314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3176843314
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.937730862
Short name T448
Test name
Test status
Simulation time 19586991 ps
CPU time 1.73 seconds
Started Aug 15 05:50:48 PM PDT 24
Finished Aug 15 05:50:49 PM PDT 24
Peak memory 207324 kb
Host smart-72f18246-4d22-483d-9d3f-6dc8699265d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937730862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.937730862
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1005614629
Short name T238
Test name
Test status
Simulation time 1959405533 ps
CPU time 40.18 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:51:35 PM PDT 24
Peak memory 215496 kb
Host smart-d7fd5e92-ff48-4ffb-afca-c2c7f2750a73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005614629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1005614629
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3052534623
Short name T745
Test name
Test status
Simulation time 418288449 ps
CPU time 3.42 seconds
Started Aug 15 05:50:35 PM PDT 24
Finished Aug 15 05:50:38 PM PDT 24
Peak memory 214680 kb
Host smart-e86a4a7c-4e76-406e-adf3-4b65e7bfc06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052534623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3052534623
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3901236378
Short name T756
Test name
Test status
Simulation time 744684565 ps
CPU time 3.98 seconds
Started Aug 15 05:50:42 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 210732 kb
Host smart-d02bfd20-8b20-4b0a-910e-29e28ddedbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901236378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3901236378
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1679039427
Short name T428
Test name
Test status
Simulation time 17639311 ps
CPU time 0.87 seconds
Started Aug 15 05:50:48 PM PDT 24
Finished Aug 15 05:50:49 PM PDT 24
Peak memory 206596 kb
Host smart-8fb699e1-66c9-4c62-ad68-bde0ef960126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679039427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1679039427
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.863850341
Short name T236
Test name
Test status
Simulation time 294951913 ps
CPU time 6.9 seconds
Started Aug 15 05:50:40 PM PDT 24
Finished Aug 15 05:50:48 PM PDT 24
Peak memory 218700 kb
Host smart-7bd832c1-556a-45c8-bd8c-1749d6bf612c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863850341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.863850341
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4084361365
Short name T898
Test name
Test status
Simulation time 774967255 ps
CPU time 24.11 seconds
Started Aug 15 05:50:34 PM PDT 24
Finished Aug 15 05:50:59 PM PDT 24
Peak memory 213384 kb
Host smart-8c026788-34b6-44d5-af47-8ca99c08f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084361365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4084361365
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2444864057
Short name T104
Test name
Test status
Simulation time 83589500 ps
CPU time 3.16 seconds
Started Aug 15 05:50:43 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 214756 kb
Host smart-2abd4660-eb81-47af-a8bd-38e513d434d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444864057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2444864057
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1469641505
Short name T253
Test name
Test status
Simulation time 36341255 ps
CPU time 2.33 seconds
Started Aug 15 05:50:41 PM PDT 24
Finished Aug 15 05:50:44 PM PDT 24
Peak memory 214692 kb
Host smart-a0357c78-261e-49b0-894a-43df2453637c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469641505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1469641505
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1776712219
Short name T642
Test name
Test status
Simulation time 189129296 ps
CPU time 7.72 seconds
Started Aug 15 05:50:34 PM PDT 24
Finished Aug 15 05:50:42 PM PDT 24
Peak memory 210448 kb
Host smart-a377c98a-e643-49c5-93ed-2e66866a9c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776712219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1776712219
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2891847374
Short name T706
Test name
Test status
Simulation time 916867730 ps
CPU time 33.3 seconds
Started Aug 15 05:50:34 PM PDT 24
Finished Aug 15 05:51:08 PM PDT 24
Peak memory 207456 kb
Host smart-7818fa2e-2cf0-4bdc-a1a7-88f0a0468117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891847374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2891847374
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3021996508
Short name T371
Test name
Test status
Simulation time 1865187952 ps
CPU time 5.38 seconds
Started Aug 15 05:50:38 PM PDT 24
Finished Aug 15 05:50:43 PM PDT 24
Peak memory 207712 kb
Host smart-04441bbe-3a92-4b03-9b4e-3c6d29a646ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021996508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3021996508
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3226604665
Short name T347
Test name
Test status
Simulation time 106621332 ps
CPU time 3.29 seconds
Started Aug 15 05:50:46 PM PDT 24
Finished Aug 15 05:50:49 PM PDT 24
Peak memory 209084 kb
Host smart-7dad5a9a-173c-4622-bfc4-f1b85bea00df
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226604665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3226604665
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.382714813
Short name T656
Test name
Test status
Simulation time 134514221 ps
CPU time 3.22 seconds
Started Aug 15 05:50:48 PM PDT 24
Finished Aug 15 05:50:51 PM PDT 24
Peak memory 209064 kb
Host smart-a47bc13c-6732-49ee-a9c2-a529527c481f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382714813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.382714813
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3222881975
Short name T770
Test name
Test status
Simulation time 489185092 ps
CPU time 5.56 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:37 PM PDT 24
Peak memory 209036 kb
Host smart-deff7bb2-554d-4b6e-aca7-1c52b105fb25
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222881975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3222881975
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4220586245
Short name T288
Test name
Test status
Simulation time 49611928 ps
CPU time 2.66 seconds
Started Aug 15 05:50:41 PM PDT 24
Finished Aug 15 05:50:44 PM PDT 24
Peak memory 216092 kb
Host smart-69bdcfb8-790a-4ec3-a3c3-9df68ad0b8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220586245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4220586245
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3919916128
Short name T435
Test name
Test status
Simulation time 60812251 ps
CPU time 2.77 seconds
Started Aug 15 05:50:47 PM PDT 24
Finished Aug 15 05:50:50 PM PDT 24
Peak memory 209024 kb
Host smart-0ff25465-3d4d-4809-995d-3959fb75e5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919916128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3919916128
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3433005377
Short name T714
Test name
Test status
Simulation time 1146371695 ps
CPU time 11.65 seconds
Started Aug 15 05:50:40 PM PDT 24
Finished Aug 15 05:50:51 PM PDT 24
Peak memory 220344 kb
Host smart-7db3b57d-5c09-4b43-898a-6f83cdc1c0bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433005377 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3433005377
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2679528132
Short name T249
Test name
Test status
Simulation time 29811455 ps
CPU time 2.46 seconds
Started Aug 15 05:50:34 PM PDT 24
Finished Aug 15 05:50:37 PM PDT 24
Peak memory 207796 kb
Host smart-d2b56d6d-e070-4695-aab4-123e0831815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679528132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2679528132
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2881162512
Short name T179
Test name
Test status
Simulation time 325747994 ps
CPU time 1.46 seconds
Started Aug 15 05:50:46 PM PDT 24
Finished Aug 15 05:50:48 PM PDT 24
Peak memory 210516 kb
Host smart-df080490-7eb3-4f0f-b759-8d47657cadee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881162512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2881162512
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3295264737
Short name T721
Test name
Test status
Simulation time 25863401 ps
CPU time 0.96 seconds
Started Aug 15 05:50:47 PM PDT 24
Finished Aug 15 05:50:48 PM PDT 24
Peak memory 206460 kb
Host smart-c1635f3e-4a5b-4335-80cf-c57c47192cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295264737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3295264737
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2559413289
Short name T504
Test name
Test status
Simulation time 484945292 ps
CPU time 3.25 seconds
Started Aug 15 05:50:42 PM PDT 24
Finished Aug 15 05:50:45 PM PDT 24
Peak memory 214792 kb
Host smart-113ffcdc-9dba-492b-bf57-ef6c250ea8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559413289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2559413289
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3914293147
Short name T352
Test name
Test status
Simulation time 60818815 ps
CPU time 3.63 seconds
Started Aug 15 05:50:48 PM PDT 24
Finished Aug 15 05:50:52 PM PDT 24
Peak memory 222792 kb
Host smart-14971494-58ef-453b-a2f3-143e03c23a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914293147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3914293147
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1739804346
Short name T467
Test name
Test status
Simulation time 36489259 ps
CPU time 2.46 seconds
Started Aug 15 05:50:45 PM PDT 24
Finished Aug 15 05:50:48 PM PDT 24
Peak memory 216212 kb
Host smart-df2dfbf7-f0a2-471e-aab9-f0f35a7654bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739804346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1739804346
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1644686588
Short name T711
Test name
Test status
Simulation time 185355749 ps
CPU time 3.52 seconds
Started Aug 15 05:50:45 PM PDT 24
Finished Aug 15 05:50:49 PM PDT 24
Peak memory 218828 kb
Host smart-091587bc-5578-4ee8-b166-56c3a27a5e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644686588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1644686588
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.714450729
Short name T457
Test name
Test status
Simulation time 741355771 ps
CPU time 5.75 seconds
Started Aug 15 05:50:52 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 208828 kb
Host smart-5551e153-1c21-4c8e-ade8-296d7528f766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714450729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.714450729
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4225278879
Short name T619
Test name
Test status
Simulation time 129172126 ps
CPU time 2.77 seconds
Started Aug 15 05:50:49 PM PDT 24
Finished Aug 15 05:50:52 PM PDT 24
Peak memory 207456 kb
Host smart-a9fb9be6-2203-4e76-a1f9-dd98547b4ab4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225278879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4225278879
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.776404176
Short name T640
Test name
Test status
Simulation time 749175518 ps
CPU time 20.03 seconds
Started Aug 15 05:50:49 PM PDT 24
Finished Aug 15 05:51:10 PM PDT 24
Peak memory 208708 kb
Host smart-7c4bcc8d-7581-4f6b-b6c3-50c324928eaf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776404176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.776404176
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1810776316
Short name T653
Test name
Test status
Simulation time 514145465 ps
CPU time 4.12 seconds
Started Aug 15 05:50:43 PM PDT 24
Finished Aug 15 05:50:48 PM PDT 24
Peak memory 207456 kb
Host smart-c914e323-80f2-4e0f-ba1b-eeaa837d9c22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810776316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1810776316
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1655359998
Short name T471
Test name
Test status
Simulation time 226680486 ps
CPU time 2.78 seconds
Started Aug 15 05:50:50 PM PDT 24
Finished Aug 15 05:50:53 PM PDT 24
Peak memory 208068 kb
Host smart-4b6f7706-2cd5-42d1-861d-141782ea4b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655359998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1655359998
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3033214837
Short name T121
Test name
Test status
Simulation time 482828963 ps
CPU time 3.48 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 208488 kb
Host smart-e5f2e603-6f7f-4037-a81b-910b45e10a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033214837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3033214837
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1581010221
Short name T49
Test name
Test status
Simulation time 129284782 ps
CPU time 4.36 seconds
Started Aug 15 05:50:53 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 210640 kb
Host smart-065ee9ec-8cdc-4051-985f-994be67bbbc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581010221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1581010221
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.515743188
Short name T137
Test name
Test status
Simulation time 103556314 ps
CPU time 7.44 seconds
Started Aug 15 05:50:51 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 223128 kb
Host smart-f111446e-becb-4570-91f1-862658e6f0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515743188 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.515743188
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3388059428
Short name T772
Test name
Test status
Simulation time 1785072530 ps
CPU time 60.17 seconds
Started Aug 15 05:50:54 PM PDT 24
Finished Aug 15 05:51:54 PM PDT 24
Peak memory 209800 kb
Host smart-1c613f3c-c029-4eaa-af31-e76290d1c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388059428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3388059428
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2769613244
Short name T204
Test name
Test status
Simulation time 622004325 ps
CPU time 3.67 seconds
Started Aug 15 05:50:39 PM PDT 24
Finished Aug 15 05:50:43 PM PDT 24
Peak memory 210832 kb
Host smart-41a3a278-05c1-490c-807a-dc29d97d2e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769613244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2769613244
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.813989927
Short name T505
Test name
Test status
Simulation time 41706953 ps
CPU time 0.68 seconds
Started Aug 15 05:50:48 PM PDT 24
Finished Aug 15 05:50:49 PM PDT 24
Peak memory 206440 kb
Host smart-baa21aea-8872-42b1-b49e-4389e56c01e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813989927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.813989927
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.351901205
Short name T690
Test name
Test status
Simulation time 132118579 ps
CPU time 2.78 seconds
Started Aug 15 05:50:51 PM PDT 24
Finished Aug 15 05:50:54 PM PDT 24
Peak memory 214792 kb
Host smart-4212b7f6-ab68-4511-a39b-ea671ae81aa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351901205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.351901205
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1912143858
Short name T10
Test name
Test status
Simulation time 154681631 ps
CPU time 4.87 seconds
Started Aug 15 05:50:38 PM PDT 24
Finished Aug 15 05:50:43 PM PDT 24
Peak memory 216952 kb
Host smart-0f961285-8022-4a50-97a3-eacd496dcdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912143858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1912143858
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4134543731
Short name T339
Test name
Test status
Simulation time 72452100 ps
CPU time 2.36 seconds
Started Aug 15 05:50:41 PM PDT 24
Finished Aug 15 05:50:44 PM PDT 24
Peak memory 210484 kb
Host smart-3a3b5df8-9e68-49a7-9029-9fe4c124e94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134543731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4134543731
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.4100401674
Short name T103
Test name
Test status
Simulation time 71578666 ps
CPU time 2.23 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:50:58 PM PDT 24
Peak memory 214724 kb
Host smart-ed03f12f-fc3a-4e0c-b2b8-468686479853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100401674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.4100401674
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3561128089
Short name T516
Test name
Test status
Simulation time 81737798 ps
CPU time 2.21 seconds
Started Aug 15 05:50:41 PM PDT 24
Finished Aug 15 05:50:43 PM PDT 24
Peak memory 214736 kb
Host smart-07e0b8c7-bc26-4792-b623-f0f1f29c9d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561128089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3561128089
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_random.698798728
Short name T283
Test name
Test status
Simulation time 363857444 ps
CPU time 4.31 seconds
Started Aug 15 05:50:51 PM PDT 24
Finished Aug 15 05:50:55 PM PDT 24
Peak memory 214752 kb
Host smart-04e58182-af93-4a4e-9f5c-bd235f70fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698798728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.698798728
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2335609241
Short name T561
Test name
Test status
Simulation time 240920264 ps
CPU time 2.89 seconds
Started Aug 15 05:50:44 PM PDT 24
Finished Aug 15 05:50:47 PM PDT 24
Peak memory 207416 kb
Host smart-0c37f2b7-47e9-4a10-9e35-efa43b383d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335609241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2335609241
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3741692465
Short name T851
Test name
Test status
Simulation time 323202870 ps
CPU time 3.51 seconds
Started Aug 15 05:50:48 PM PDT 24
Finished Aug 15 05:50:52 PM PDT 24
Peak memory 209380 kb
Host smart-672c42b9-110f-49a9-b853-cd25a8480967
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741692465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3741692465
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.406740947
Short name T271
Test name
Test status
Simulation time 241623638 ps
CPU time 4.1 seconds
Started Aug 15 05:50:40 PM PDT 24
Finished Aug 15 05:50:44 PM PDT 24
Peak memory 208756 kb
Host smart-db408e51-fffc-462f-9854-669639aec2ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406740947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.406740947
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.522895962
Short name T481
Test name
Test status
Simulation time 51284143 ps
CPU time 2.55 seconds
Started Aug 15 05:50:43 PM PDT 24
Finished Aug 15 05:50:46 PM PDT 24
Peak memory 207996 kb
Host smart-95aed151-294a-4cfc-95ce-3f569e750172
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522895962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.522895962
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2504971663
Short name T2
Test name
Test status
Simulation time 2955946439 ps
CPU time 27.79 seconds
Started Aug 15 05:50:55 PM PDT 24
Finished Aug 15 05:51:23 PM PDT 24
Peak memory 209180 kb
Host smart-917933b3-f050-46af-b3f0-2e8fe54ff77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504971663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2504971663
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1843011183
Short name T529
Test name
Test status
Simulation time 33664269 ps
CPU time 2.42 seconds
Started Aug 15 05:51:09 PM PDT 24
Finished Aug 15 05:51:12 PM PDT 24
Peak memory 207764 kb
Host smart-12a62815-fbc4-4e6e-a154-bde6fc4a8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843011183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1843011183
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4198767737
Short name T742
Test name
Test status
Simulation time 144272712 ps
CPU time 4.97 seconds
Started Aug 15 05:50:46 PM PDT 24
Finished Aug 15 05:50:51 PM PDT 24
Peak memory 210064 kb
Host smart-baf2b9a3-4ee2-4aa6-8097-a6e1f8813c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198767737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4198767737
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3792930419
Short name T593
Test name
Test status
Simulation time 384677792 ps
CPU time 2.8 seconds
Started Aug 15 05:50:38 PM PDT 24
Finished Aug 15 05:50:41 PM PDT 24
Peak memory 210688 kb
Host smart-2116242e-a78f-4260-844e-46d297349fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792930419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3792930419
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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