Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
69.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	18	31	63.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	17	18	51.43	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	50	1			T16	1		T24	1		T25	2
auto[OpGenId]	5	1			T96	1		T92	1		T67	1
auto[OpGenSwOut]	24	1			T25	1		T26	1		T100	1
auto[OpGenHwOut]	21	1			T5	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1586	1			T24	1		T25	1		T64	2
auto[StInit]	97	1			T16	1		T24	1		T96	1
auto[StCreatorRootKey]	68	1			T37	1		T25	2		T26	1
auto[StOwnerIntKey]	49	1			T29	1		T40	1		T78	1
auto[StOwnerKey]	33	1			T68	1		T25	2		T128	1
auto[StDisabled]	448	1			T24	14		T25	13		T130	1
auto[StInvalid]	49	1			T14	1		T38	1		T39	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3319

1

T1

1

T2

1

T3

1

auto[1]

100

1

T16

1

T24

1

T25

3

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1583	1			T24	1		T25	1		T64	1
auto[StReset]	auto[1]	3	1			T64	1		T125	1		T126	1
auto[StInit]	auto[0]	47	1			T24	1		T78	2		T79	1
auto[StInit]	auto[1]	50	1			T16	1		T96	1		T100	1
auto[StCreatorRootKey]	auto[0]	46	1			T37	1		T64	3		T79	1
auto[StCreatorRootKey]	auto[1]	22	1			T25	2		T26	1		T79	1
auto[StOwnerIntKey]	auto[0]	38	1			T29	1		T40	1		T78	1
auto[StOwnerIntKey]	auto[1]	11	1			T5	1		T183	1		T184	1
auto[StOwnerKey]	auto[0]	28	1			T68	1		T25	1		T128	1
auto[StOwnerKey]	auto[1]	5	1			T25	1		T185	1		T186	1
auto[StDisabled]	auto[0]	439	1			T24	13		T25	13		T130	1
auto[StDisabled]	auto[1]	9	1			T24	1		T104	1		T187	1
auto[StInvalid]	auto[0]	49	1			T14	1		T38	1		T39	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	3	1			T64	1		T125	1		T126	1
auto[StInit]	auto[OpAdvance]	24	1			T16	1		T188	1		T121	1
auto[StInit]	auto[OpGenId]	3	1			T96	1		T67	1		T189	1
auto[StInit]	auto[OpGenSwOut]	10	1			T100	1		T5	1		T143	1
auto[StInit]	auto[OpGenHwOut]	13	1			T6	1		T7	1		T190	1
auto[StCreatorRootKey]	auto[OpAdvance]	13	1			T25	1		T79	1		T104	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T191	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T25	1		T26	1		T192	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T31	1		T193	1		T194	1
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T183	1		T195	1		T196	2
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T184	1		T197	1		T198	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T5	1		T199	1		T200	1
auto[StOwnerKey]	auto[OpAdvance]	4	1			T25	1		T185	1		T201	1
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T186	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	1	1			T24	1		-	-		-	-
auto[StDisabled]	auto[OpGenId]	1	1			T92	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	6	1			T104	1		T187	1		T202	1
auto[StDisabled]	auto[OpGenHwOut]	1	1			T108	1		-	-		-	-