Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4716

1

T1

1

T2

3

T3

19

auto[1]

574

1

T2

5

T47

3

T48

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4716

1

T1

1

T2

3

T3

19

auto[1]

574

1

T2

5

T47

3

T48

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4730

1

T1

1

T2

8

T3

16

auto[1]

560

1

T3

3

T11

1

T47

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4730

1

T1

1

T2

8

T3

16

auto[1]

560

1

T3

3

T11

1

T47

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T3	2		T11	1		T14	2
auto[OpGenId]	1085	1			T1	1		T3	3		T4	1
auto[OpGenSwOut]	1139	1			T3	7		T12	1		T13	1
auto[OpGenHwOut]	2575	1			T2	8		T3	7		T11	1
auto[OpDisable]	70	1			T15	1		T77	1		T24	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T3	2		T11	1		T14	2
auto[OpGenId]	1085	1			T1	1		T3	3		T4	1
auto[OpGenSwOut]	1139	1			T3	7		T12	1		T13	1
auto[OpGenHwOut]	2575	1			T2	8		T3	7		T11	1
auto[OpDisable]	70	1			T15	1		T77	1		T24	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4703

1

T1

1

T2

8

T3

4

auto[1]

587

1

T3

15

T12

2

T13

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4703

1

T1

1

T2

8

T3

4

auto[1]

587

1

T3

15

T12

2

T13

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5031

1

T1

1

T2

8

T3

6

auto[1]

259

1

T3

13

T47

4

T98

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1867	1			T1	1		T2	3		T3	3
auto[1]	694	1			T2	1		T3	10		T13	1
auto[2]	677	1			T2	2		T3	6		T12	1
auto[3]	698	1			T2	1		T14	1		T47	2
auto[4]	339	1			T2	1		T12	1		T47	2
auto[5]	319	1			T13	1		T14	3		T15	1
auto[6]	341	1			T47	1		T48	1		T77	1
auto[7]	355	1			T14	1		T47	1		T150	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1354	1			T2	1		T12	1		T13	1
clear_one[1]	694	1			T2	1		T3	10		T13	1
clear_one[2]	677	1			T2	2		T3	6		T12	1
clear_one[3]	698	1			T2	1		T14	1		T47	2
clear_none	1867	1			T1	1		T2	3		T3	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	972	1			T15	1		T48	1		T49	3
auto[StInit]	657	1			T2	1		T3	3		T4	1
auto[StCreatorRootKey]	558	1			T2	1		T3	3		T12	1
auto[StOwnerIntKey]	518	1			T2	1		T11	1		T12	1
auto[StOwnerKey]	482	1			T2	1		T3	5		T47	1
auto[StDisabled]	1828	1			T1	1		T2	4		T3	8
auto[StInvalid]	275	1			T14	5		T38	3		T39	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	972	1			T15	1		T48	1		T49	3
auto[StInit]	657	1			T2	1		T3	3		T4	1
auto[StCreatorRootKey]	558	1			T2	1		T3	3		T12	1
auto[StOwnerIntKey]	518	1			T2	1		T11	1		T12	1
auto[StOwnerKey]	482	1			T2	1		T3	5		T47	1
auto[StDisabled]	1828	1			T1	1		T2	4		T3	8
auto[StInvalid]	275	1			T14	5		T38	3		T39	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[3] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[3] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T203	1		T204	1		T205	2
auto[0]	auto[StReset]	auto[OpGenId]	163	1			T24	2		T25	2		T64	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	154	1			T15	1		T68	1		T24	4
auto[0]	auto[StReset]	auto[OpGenHwOut]	261	1			T48	1		T49	2		T150	1
auto[0]	auto[StInit]	auto[OpAdvance]	36	1			T11	1		T14	1		T24	2
auto[0]	auto[StInit]	auto[OpGenId]	93	1			T3	2		T4	1		T24	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	93	1			T47	1		T179	1		T64	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	201	1			T2	1		T3	1		T47	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	25	1			T95	1		T78	1		T83	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	47	1			T47	1		T25	1		T206	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	64	1			T13	1		T25	2		T78	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	67	1			T12	1		T24	4		T25	3
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T106	1		T207	1		T208	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	29	1			T23	1		T25	1		T99	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	30	1			T29	1		T79	1		T70	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	72	1			T11	1		T150	1		T174	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T24	1		T209	1		T210	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	18	1			T24	1		T25	1		T95	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	23	1			T24	1		T104	1		T145	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	59	1			T2	1		T47	1		T24	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	25	1			T49	1		T208	1		T210	1
auto[0]	auto[StDisabled]	auto[OpGenId]	64	1			T1	1		T13	1		T49	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T15	1		T24	1		T25	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	162	1			T2	1		T24	3		T174	1
auto[0]	auto[StDisabled]	auto[OpDisable]	18	1			T132	1		T152	1		T211	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	19	1			T39	1		T74	1		T212	1
auto[0]	auto[StInvalid]	auto[OpGenId]	17	1			T39	1		T52	1		T213	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	23	1			T214	1		T66	2		T215	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T39	1		T51	1		T213	1
auto[1]	auto[StReset]	auto[OpGenId]	14	1			T5	1		T75	1		T109	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	15	1			T49	1		T127	1		T69	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	34	1			T174	1		T21	1		T216	1
auto[1]	auto[StInit]	auto[OpAdvance]	6	1			T97	1		T105	1		T217	1
auto[1]	auto[StInit]	auto[OpGenId]	13	1			T24	1		T7	1		T110	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	11	1			T25	2		T104	1		T175	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	21	1			T49	1		T150	1		T73	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T24	2		T210	1		T202	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T70	1		T76	2		T218	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T219	1		T132	1		T105	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T181	1		T220	1		T219	2
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T221	1		T222	1		T129	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T25	1		T78	1		T223	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T24	1		T27	1		T224	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T2	1		T25	2		T64	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T69	1		T109	1		T225	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	10	1			T3	1		T24	1		T71	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T3	2		T25	1		T5	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T226	1		T227	1		T132	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	16	1			T5	1		T228	1		T224	1
auto[1]	auto[StDisabled]	auto[OpGenId]	68	1			T13	1		T25	2		T5	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T3	3		T24	2		T25	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	178	1			T3	4		T49	1		T150	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T77	1		T24	1		T175	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T212	1		T229	1		T230	1
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T52	1		T231	1		T232	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T233	1		T234	1		T235	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T39	1		T51	1		T212	1
auto[2]	auto[StReset]	auto[OpAdvance]	2	1			T236	1		T237	1		-	-
auto[2]	auto[StReset]	auto[OpGenId]	17	1			T104	1		T238	1		T65	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	23	1			T38	1		T20	1		T70	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	42	1			T150	1		T25	2		T97	2
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T239	1		T22	1		T186	1
auto[2]	auto[StInit]	auto[OpGenId]	8	1			T69	1		T210	1		T240	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	12	1			T241	1		T242	1		T243	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	25	1			T174	1		T216	1		T244	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T24	1		T245	1		T137	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T246	1		T91	1		T247	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T3	1		T25	2		T179	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	46	1			T3	2		T226	1		T70	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T248	1		T249	1		T250	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T12	1		T79	1		T251	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T5	1		T83	1		T252	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T25	1		T70	1		T216	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T3	2		T253	1		T254	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	4	1			T255	1		T195	1		T256	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T177	1		T257	1		T258	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T25	1		T64	1		T94	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T24	1		T25	2		T259	1
auto[2]	auto[StDisabled]	auto[OpGenId]	48	1			T24	2		T25	1		T64	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T3	1		T48	1		T70	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	150	1			T2	2		T13	1		T150	2
auto[2]	auto[StDisabled]	auto[OpDisable]	16	1			T132	1		T105	2		T210	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T260	1		T261	1		T262	1
auto[2]	auto[StInvalid]	auto[OpGenId]	16	1			T38	1		T51	2		T65	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T52	1		T53	1		T263	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T214	1		T66	1		T215	1
auto[3]	auto[StReset]	auto[OpGenId]	22	1			T25	1		T5	1		T264	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	18	1			T25	1		T91	1		T107	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	47	1			T181	1		T220	1		T5	1
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T265	1		T22	1		T266	1
auto[3]	auto[StInit]	auto[OpGenId]	5	1			T138	1		T267	1		T268	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	4	1			T48	1		T127	1		T105	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	29	1			T252	1		T269	1		T270	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T31	1		T152	1		T129	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T78	1		T271	1		T192	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T97	1		T70	2		T132	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T68	1		T174	1		T79	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T25	2		T132	1		T129	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T24	1		T5	1		T272	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T70	1		T134	1		T228	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T273	1		T105	1		T91	2
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T105	2		T176	1		T249	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	16	1			T24	1		T75	1		T132	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T23	1		T180	1		T70	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T182	1		T69	1		T104	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	23	1			T25	1		T78	1		T7	1
auto[3]	auto[StDisabled]	auto[OpGenId]	53	1			T47	1		T25	2		T27	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T24	2		T25	3		T180	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	148	1			T2	1		T47	1		T150	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T92	1		T274	1		T265	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T14	1		T275	1		T232	1
auto[3]	auto[StInvalid]	auto[OpGenId]	18	1			T74	1		T275	1		T213	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T65	1		T214	1		T233	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T276	1		T263	1		T277	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T25	1		T5	1		T278	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T252	1		T175	1		T279	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	20	1			T226	1		T149	1		T280	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T254	1		T281	1		T282	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T223	1		T56	1		T283	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T129	1		T284	1		T140	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	9	1			T220	1		T285	1		T286	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T210	1		T287	1		T248	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T75	1		T6	1		T107	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T5	1		T105	1		T92	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T2	1		T94	1		T216	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T76	3		T288	1		T289	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T290	1		T172	1		T291	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T79	1		T92	1		T196	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T24	2		T182	1		T181	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T76	3		T238	1		T292	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	10	1			T25	2		T104	1		T264	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T25	1		T93	1		T293	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T76	2		T149	1		T294	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	15	1			T47	1		T23	1		T5	1
auto[4]	auto[StDisabled]	auto[OpGenId]	23	1			T47	1		T25	2		T5	2
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T12	1		T103	1		T70	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T174	1		T79	1		T76	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T295	1		T296	1		T297	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T54	1		T66	1		T298	1
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T299	1		T300	1		T301	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T65	1		T229	1		T231	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T302	1		T303	1		T262	2
auto[5]	auto[StReset]	auto[OpGenId]	4	1			T24	1		T83	1		T129	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	9	1			T304	1		T192	1		T195	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	19	1			T25	1		T269	1		T305	1
auto[5]	auto[StInit]	auto[OpAdvance]	5	1			T22	1		T306	1		T258	1
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T35	1		T199	1		T307	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T83	1		T195	1		T308	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	6	1			T64	1		T309	1		T310	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T311	1		-	-		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T312	1		T313	1		T314	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T5	1		T142	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T91	1		T210	1		T313	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T313	1		T315	1		T250	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T25	1		T316	1		T281	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T25	1		T246	1		T192	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T13	1		T20	1		T269	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T317	1		T318	1		T319	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T78	1		T175	1		T152	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T210	1		T320	1		T129	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T150	1		T321	1		T322	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T5	1		T210	1		T323	1
auto[5]	auto[StDisabled]	auto[OpGenId]	26	1			T5	1		T273	1		T132	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T25	1		T91	1		T265	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T24	1		T64	1		T174	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T15	1		T324	1		T325	1
auto[5]	auto[StInvalid]	auto[OpGenId]	10	1			T14	3		T213	1		T326	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T65	1		T215	1		T327	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T38	1		T328	1		T53	1
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T7	1		T304	1		T329	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	6	1			T83	1		T330	1		T296	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	20	1			T216	1		T149	1		T244	1
auto[6]	auto[StInit]	auto[OpAdvance]	6	1			T20	1		T238	1		T92	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T134	1		T331	1		T177	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T332	1		T134	1		T245	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	14	1			T64	1		T65	1		T280	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T25	1		T203	1		T333	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T98	2		T134	1		T315	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T77	1		T130	1		T64	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T147	1		T334	1		T134	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T24	1		T110	1		T177	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T104	1		T7	1		T210	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T24	1		T238	1		T270	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T5	1		T335	1		T305	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T24	1		T333	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T130	1		T132	1		T336	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T78	1		T103	1		T219	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T83	1		T147	1		T337	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T338	1		T251	1		T339	1
auto[6]	auto[StDisabled]	auto[OpGenId]	28	1			T25	1		T95	1		T103	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T24	2		T98	2		T103	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	68	1			T47	1		T48	1		T98	1
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T340	1		T135	1		T176	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	5	1			T213	1		T53	1		T232	1
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T38	1		T260	1		T341	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T342	1		T260	1		T276	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T74	1		T343	1		T344	1
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T24	1		T175	1		T192	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	4	1			T134	1		T152	1		T195	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	33	1			T150	1		T25	1		T345	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T21	1		T346	1		T196	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T75	1		T105	1		T274	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	1	1			T264	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenHwOut]	9	1			T30	1		T305	1		T177	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T347	4		T346	1		T249	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T285	1		T329	1		T140	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T64	1		T199	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T150	1		T25	1		T348	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T349	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T70	1		T134	1		T347	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T24	1		T25	1		T105	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T94	1		T5	1		T92	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T350	1		T296	1		T351	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T69	1		T70	1		T347	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T5	2		T91	1		T352	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T25	1		T27	1		T353	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	12	1			T236	1		T110	3		T210	1
auto[7]	auto[StDisabled]	auto[OpGenId]	31	1			T47	1		T25	1		T132	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T24	1		T25	1		T69	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T24	1		T64	1		T94	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T132	1		T195	1		T186	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T213	1		T235	1		T354	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T212	1		T54	1		T66	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T14	1		T275	1		T214	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T275	1		T54	1		T328	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1354

1

T2

1

T12

1

T13

1

clear_one[1]

auto[0]

auto[0]

auto[0]

402

1

T2

1

T13

1

T77

1

clear_one[1]

auto[0]

auto[0]

auto[1]

123

1

T3

7

T49

1

T150

1

clear_one[1]

auto[0]

auto[1]

auto[0]

128

1

T24

2

T25

1

T64

1

clear_one[1]

auto[0]

auto[1]

auto[1]

41

1

T3

3

T24

1

T73

2

clear_one[2]

auto[0]

auto[0]

auto[0]

377

1

T3

1

T150

1

T24

2

clear_one[2]

auto[0]

auto[0]

auto[1]

138

1

T3

5

T12

1

T13

1

clear_one[2]

auto[1]

auto[0]

auto[0]

123

1

T2

2

T24

2

T25

1

clear_one[2]

auto[1]

auto[0]

auto[1]

39

1

T48

1

T25

2

T20

1

clear_one[3]

auto[0]

auto[0]

auto[0]

408

1

T14

1

T47

1

T48

1

clear_one[3]

auto[0]

auto[1]

auto[0]

111

1

T24

1

T25

1

T181

2

clear_one[3]

auto[1]

auto[0]

auto[0]

118

1

T2

1

T47

1

T24

1

clear_one[3]

auto[1]

auto[1]

auto[0]

61

1

T24

3

T25

1

T5

1

clear_none

auto[0]

auto[0]

auto[0]

1326

1

T1

1

T2

1

T3

3

clear_none

auto[0]

auto[0]

auto[1]

149

1

T12

1

T49

1

T29

1

clear_none

auto[0]

auto[1]

auto[0]

124

1

T11

1

T24

1

T79

1

clear_none

auto[0]

auto[1]

auto[1]

35

1

T95

1

T104

1

T132

1

clear_none

auto[1]

auto[0]

auto[0]

136

1

T2

2

T24

1

T25

5

clear_none

auto[1]

auto[0]

auto[1]

37

1

T24

2

T25

1

T50

1

clear_none

auto[1]

auto[1]

auto[0]

35

1

T47

2

T24

1

T55

1

clear_none

auto[1]

auto[1]

auto[1]

25

1

T24

1

T25

1

T7

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1268	1			T2	1		T12	1		T13	1
clear_all	auto[1]	86	1			T47	1		T98	4		T76	12
clear_one[1]	auto[0]	654	1			T2	1		T3	3		T13	1
clear_one[1]	auto[1]	40	1			T3	7		T76	2		T219	2
clear_one[2]	auto[0]	646	1			T2	2		T3	2		T12	1
clear_one[2]	auto[1]	31	1			T3	4		T236	1		T237	6
clear_one[3]	auto[0]	665	1			T2	1		T14	1		T47	1
clear_one[3]	auto[1]	33	1			T47	1		T106	1		T110	2
clear_none	auto[0]	1798	1			T1	1		T2	3		T3	1
clear_none	auto[1]	69	1			T3	2		T47	2		T219	1