Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10978

1

T1

3

T2

6

T3

14

auto[Attestation]

7665

1

T1

2

T2

2

T3

12

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2704	1			T1	1		T3	1		T4	1
auto[Aes]	3332	1			T2	8		T3	1		T4	1
auto[Kmac]	3426	1			T3	9		T4	3		T11	5
auto[Otbn]	3492	1			T1	1		T3	8		T4	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7511	1			T1	1		T2	8		T3	8
auto[OpGenId]	5689	1			T1	3		T3	7		T4	1
auto[OpGenSwOut]	5882	1			T1	2		T3	11		T4	2
auto[OpGenHwOut]	7072	1			T2	8		T3	8		T4	7
auto[OpDisable]	159	1			T1	1		T12	1		T15	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10605

1

T1

2

T2

8

T3

12

auto[OpDoneFail]

15708

1

T1

5

T2

8

T3

22

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6325	1			T1	1		T2	1		T3	3
auto[StInit]	3785	1			T1	5		T2	2		T3	5
auto[StCreatorRootKey]	3213	1			T2	2		T3	6		T4	6
auto[StOwnerIntKey]	2790	1			T2	2		T3	1		T11	9
auto[StOwnerKey]	2361	1			T2	2		T3	3		T12	4
auto[StDisabled]	7839	1			T1	1		T2	7		T3	16

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	299	1			T15	1		T48	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T1	1		T4	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	105	1			T49	1		T25	4		T97	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	75	1			T68	1		T23	1		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	65	1			T24	2		T25	3		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	221	1			T12	1		T24	4		T25	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	308	1			T15	1		T24	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	77	1			T24	2		T25	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	85	1			T47	1		T37	1		T25	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	65	1			T11	1		T29	1		T24	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	38	1			T24	1		T25	1		T92	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	243	1			T49	1		T23	2		T24	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	326	1			T68	2		T24	5		T25	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	93	1			T40	1		T25	3		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T29	1		T24	3		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T24	1		T79	2		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	55	1			T12	1		T24	2		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	228	1			T3	3		T24	12		T25	6
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	321	1			T37	2		T68	1		T24	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	115	1			T4	1		T47	3		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T13	1		T24	2		T179	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T11	1		T25	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	61	1			T3	1		T47	1		T24	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	240	1			T3	1		T48	1		T77	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	85	1			T24	1		T38	1		T25	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T23	1		T24	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T25	2		T64	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T40	1		T24	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	58	1			T49	1		T25	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	221	1			T15	1		T24	6		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	72	1			T24	2		T38	1		T25	6
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	101	1			T12	1		T16	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	94	1			T48	1		T77	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	69	1			T25	1		T5	2		T73	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	57	1			T23	1		T24	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	214	1			T3	1		T24	5		T25	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	89	1			T24	1		T38	1		T25	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	100	1			T48	1		T29	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	64	1			T3	1		T47	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T11	1		T40	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	64	1			T180	1		T103	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	203	1			T3	2		T23	1		T24	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T24	1		T38	2		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	113	1			T1	1		T15	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T3	1		T11	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T24	2		T25	1		T179	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	57	1			T47	1		T23	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	211	1			T3	1		T12	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	248	1			T15	1		T48	3		T49	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	101	1			T49	1		T24	2		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	67	1			T11	1		T24	1		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	54	1			T68	1		T24	3		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	49	1			T47	1		T24	1		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	178	1			T3	1		T24	6		T25	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	425	1			T24	1		T25	4		T64	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T37	1		T29	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	120	1			T2	1		T47	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	124	1			T2	1		T11	1		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T2	1		T48	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	263	1			T2	3		T47	2		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	536	1			T68	1		T24	3		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T3	1		T15	1		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T37	1		T181	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	109	1			T11	1		T24	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	88	1			T24	1		T25	1		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	268	1			T12	1		T24	6		T25	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	486	1			T3	1		T37	1		T49	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	140	1			T4	1		T68	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	120	1			T3	1		T4	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T11	1		T150	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	89	1			T24	1		T25	3		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	257	1			T3	1		T13	1		T150	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T25	3		T64	1		T69	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	94	1			T40	1		T25	2		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T68	2		T25	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T24	2		T179	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	45	1			T25	2		T130	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	172	1			T49	1		T23	1		T24	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	67	1			T25	3		T64	2		T69	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	122	1			T2	1		T47	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	104	1			T4	1		T24	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	99	1			T11	1		T179	1		T174	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	88	1			T12	1		T24	1		T174	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	281	1			T2	1		T48	1		T24	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	52	1			T25	4		T69	1		T105	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	123	1			T3	1		T16	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T4	3		T11	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	108	1			T11	2		T68	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	92	1			T24	1		T25	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	260	1			T3	1		T77	1		T24	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	59	1			T24	2		T25	4		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	117	1			T150	1		T24	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	132	1			T3	1		T4	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T13	1		T24	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	80	1			T150	1		T24	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	304	1			T47	1		T48	2		T49	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	230	1			T49	1		T68	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	635	1			T1	1		T4	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	173	1			T11	1		T47	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	643	1			T15	1		T49	1		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	201	1			T12	1		T29	1		T24	6
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	657	1			T3	3		T68	2		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	226	1			T3	1		T11	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	688	1			T3	1		T4	1		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	192	1			T49	1		T40	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	423	1			T15	1		T23	1		T24	8
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	204	1			T48	1		T77	1		T24	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	403	1			T3	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T3	1		T11	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	403	1			T3	2		T48	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T3	1		T11	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	403	1			T1	1		T3	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	153	1			T11	1		T47	1		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	544	1			T3	1		T15	1		T48	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	322	1			T2	3		T11	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	826	1			T2	3		T47	2		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	283	1			T11	1		T37	1		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	941	1			T3	1		T12	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	289	1			T3	1		T4	1		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	896	1			T3	2		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	180	1			T68	2		T24	1		T25	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	347	1			T49	1		T23	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	273	1			T4	1		T11	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	488	1			T2	2		T47	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	292	1			T4	3		T11	3		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	453	1			T3	2		T16	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	296	1			T3	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	489	1			T47	1		T48	2		T49	1