Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32240

1

T1

8

T2

19

T3

38

auto[1]

272

1

T3

14

T47

6

T98

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32249	1			T1	8		T2	19		T3	39
auto[134217728:268435455]	5	1			T3	1		T47	1		T98	1
auto[268435456:402653183]	8	1			T3	1		T76	1		T106	1
auto[402653184:536870911]	4	1			T338	1		T378	1		T379	1
auto[536870912:671088639]	14	1			T3	1		T98	1		T219	2
auto[671088640:805306367]	9	1			T3	1		T110	2		T313	1
auto[805306368:939524095]	8	1			T3	2		T47	1		T76	1
auto[939524096:1073741823]	13	1			T3	2		T110	1		T338	2
auto[1073741824:1207959551]	6	1			T47	1		T103	1		T76	1
auto[1207959552:1342177279]	12	1			T103	1		T110	1		T339	3
auto[1342177280:1476395007]	7	1			T76	1		T237	1		T366	1
auto[1476395008:1610612735]	10	1			T110	1		T313	1		T237	1
auto[1610612736:1744830463]	6	1			T3	1		T347	1		T380	2
auto[1744830464:1879048191]	8	1			T98	1		T103	1		T76	1
auto[1879048192:2013265919]	4	1			T381	1		T382	1		T383	1
auto[2013265920:2147483647]	3	1			T3	1		T382	1		T384	1
auto[2147483648:2281701375]	11	1			T106	1		T237	1		T366	2
auto[2281701376:2415919103]	8	1			T259	1		T110	2		T347	1
auto[2415919104:2550136831]	7	1			T3	1		T313	1		T249	1
auto[2550136832:2684354559]	7	1			T47	1		T98	1		T219	1
auto[2684354560:2818572287]	11	1			T98	1		T76	1		T219	1
auto[2818572288:2952790015]	5	1			T259	1		T366	1		T385	1
auto[2952790016:3087007743]	12	1			T3	2		T47	1		T98	1
auto[3087007744:3221225471]	11	1			T98	1		T103	1		T338	2
auto[3221225472:3355443199]	11	1			T106	1		T347	1		T386	1
auto[3355443200:3489660927]	10	1			T76	1		T110	1		T365	1
auto[3489660928:3623878655]	10	1			T76	1		T219	1		T365	1
auto[3623878656:3758096383]	13	1			T76	1		T106	2		T110	1
auto[3758096384:3892314111]	6	1			T76	1		T106	1		T225	1
auto[3892314112:4026531839]	6	1			T110	1		T365	1		T339	1
auto[4026531840:4160749567]	10	1			T98	1		T76	1		T106	1
auto[4160749568:4294967295]	8	1			T47	1		T98	1		T365	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32240	1			T1	8		T2	19		T3	38
auto[0:134217727]	auto[1]	9	1			T3	1		T347	1		T237	1
auto[134217728:268435455]	auto[1]	5	1			T3	1		T47	1		T98	1
auto[268435456:402653183]	auto[1]	8	1			T3	1		T76	1		T106	1
auto[402653184:536870911]	auto[1]	4	1			T338	1		T378	1		T379	1
auto[536870912:671088639]	auto[1]	14	1			T3	1		T98	1		T219	2
auto[671088640:805306367]	auto[1]	9	1			T3	1		T110	2		T313	1
auto[805306368:939524095]	auto[1]	8	1			T3	2		T47	1		T76	1
auto[939524096:1073741823]	auto[1]	13	1			T3	2		T110	1		T338	2
auto[1073741824:1207959551]	auto[1]	6	1			T47	1		T103	1		T76	1
auto[1207959552:1342177279]	auto[1]	12	1			T103	1		T110	1		T339	3
auto[1342177280:1476395007]	auto[1]	7	1			T76	1		T237	1		T366	1
auto[1476395008:1610612735]	auto[1]	10	1			T110	1		T313	1		T237	1
auto[1610612736:1744830463]	auto[1]	6	1			T3	1		T347	1		T380	2
auto[1744830464:1879048191]	auto[1]	8	1			T98	1		T103	1		T76	1
auto[1879048192:2013265919]	auto[1]	4	1			T381	1		T382	1		T383	1
auto[2013265920:2147483647]	auto[1]	3	1			T3	1		T382	1		T384	1
auto[2147483648:2281701375]	auto[1]	11	1			T106	1		T237	1		T366	2
auto[2281701376:2415919103]	auto[1]	8	1			T259	1		T110	2		T347	1
auto[2415919104:2550136831]	auto[1]	7	1			T3	1		T313	1		T249	1
auto[2550136832:2684354559]	auto[1]	7	1			T47	1		T98	1		T219	1
auto[2684354560:2818572287]	auto[1]	11	1			T98	1		T76	1		T219	1
auto[2818572288:2952790015]	auto[1]	5	1			T259	1		T366	1		T385	1
auto[2952790016:3087007743]	auto[1]	12	1			T3	2		T47	1		T98	1
auto[3087007744:3221225471]	auto[1]	11	1			T98	1		T103	1		T338	2
auto[3221225472:3355443199]	auto[1]	11	1			T106	1		T347	1		T386	1
auto[3355443200:3489660927]	auto[1]	10	1			T76	1		T110	1		T365	1
auto[3489660928:3623878655]	auto[1]	10	1			T76	1		T219	1		T365	1
auto[3623878656:3758096383]	auto[1]	13	1			T76	1		T106	2		T110	1
auto[3758096384:3892314111]	auto[1]	6	1			T76	1		T106	1		T225	1
auto[3892314112:4026531839]	auto[1]	6	1			T110	1		T365	1		T339	1
auto[4026531840:4160749567]	auto[1]	10	1			T98	1		T76	1		T106	1
auto[4160749568:4294967295]	auto[1]	8	1			T47	1		T98	1		T365	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1598

1

T3

2

T11

1

T12

1

auto[1]

1792

1

T1

1

T3

1

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T49	1		T29	1		T24	1
auto[134217728:268435455]	114	1			T4	1		T49	1		T68	1
auto[268435456:402653183]	101	1			T24	2		T25	3		T97	1
auto[402653184:536870911]	101	1			T38	1		T96	1		T98	1
auto[536870912:671088639]	102	1			T3	1		T24	3		T25	2
auto[671088640:805306367]	126	1			T24	4		T25	1		T64	1
auto[805306368:939524095]	120	1			T15	1		T68	1		T24	1
auto[939524096:1073741823]	90	1			T12	2		T24	1		T38	1
auto[1073741824:1207959551]	89	1			T16	1		T24	1		T25	2
auto[1207959552:1342177279]	112	1			T68	1		T24	2		T25	5
auto[1342177280:1476395007]	110	1			T11	1		T24	1		T25	2
auto[1476395008:1610612735]	94	1			T14	1		T38	1		T25	1
auto[1610612736:1744830463]	97	1			T12	1		T25	2		T26	1
auto[1744830464:1879048191]	108	1			T1	1		T47	1		T25	3
auto[1879048192:2013265919]	112	1			T49	1		T24	1		T25	1
auto[2013265920:2147483647]	109	1			T24	3		T25	3		T130	1
auto[2147483648:2281701375]	95	1			T77	1		T24	1		T5	1
auto[2281701376:2415919103]	100	1			T68	1		T24	3		T25	4
auto[2415919104:2550136831]	96	1			T24	4		T25	1		T26	1
auto[2550136832:2684354559]	106	1			T23	1		T38	1		T179	1
auto[2684354560:2818572287]	112	1			T24	2		T38	1		T25	3
auto[2818572288:2952790015]	103	1			T23	1		T24	3		T25	3
auto[2952790016:3087007743]	99	1			T77	1		T25	2		T96	1
auto[3087007744:3221225471]	107	1			T3	2		T11	1		T14	1
auto[3221225472:3355443199]	100	1			T49	1		T24	2		T25	1
auto[3355443200:3489660927]	106	1			T24	1		T25	4		T95	1
auto[3489660928:3623878655]	99	1			T47	1		T49	1		T68	1
auto[3623878656:3758096383]	111	1			T47	1		T77	1		T24	2
auto[3758096384:3892314111]	117	1			T14	1		T68	1		T24	2
auto[3892314112:4026531839]	110	1			T4	1		T68	1		T24	2
auto[4026531840:4160749567]	127	1			T15	1		T23	2		T24	3
auto[4160749568:4294967295]	109	1			T49	1		T23	1		T25	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T49	1		T179	1		T5	3
auto[0:134217727]	auto[1]	55	1			T29	1		T24	1		T79	1
auto[134217728:268435455]	auto[0]	49	1			T49	1		T68	1		T38	1
auto[134217728:268435455]	auto[1]	65	1			T4	1		T24	1		T78	2
auto[268435456:402653183]	auto[0]	43	1			T24	1		T25	2		T79	1
auto[268435456:402653183]	auto[1]	58	1			T24	1		T25	1		T97	1
auto[402653184:536870911]	auto[0]	56	1			T38	1		T96	1		T99	1
auto[402653184:536870911]	auto[1]	45	1			T98	1		T51	1		T223	1
auto[536870912:671088639]	auto[0]	42	1			T3	1		T24	2		T20	1
auto[536870912:671088639]	auto[1]	60	1			T24	1		T25	2		T79	1
auto[671088640:805306367]	auto[0]	63	1			T24	2		T223	2		T5	1
auto[671088640:805306367]	auto[1]	63	1			T24	2		T25	1		T64	1
auto[805306368:939524095]	auto[0]	57	1			T15	1		T25	2		T130	1
auto[805306368:939524095]	auto[1]	63	1			T68	1		T24	1		T25	2
auto[939524096:1073741823]	auto[0]	48	1			T12	1		T24	1		T25	4
auto[939524096:1073741823]	auto[1]	42	1			T12	1		T38	1		T25	1
auto[1073741824:1207959551]	auto[0]	54	1			T24	1		T25	1		T103	1
auto[1073741824:1207959551]	auto[1]	35	1			T16	1		T25	1		T5	1
auto[1207959552:1342177279]	auto[0]	54	1			T68	1		T25	3		T20	1
auto[1207959552:1342177279]	auto[1]	58	1			T24	2		T25	2		T130	1
auto[1342177280:1476395007]	auto[0]	51	1			T24	1		T25	2		T96	1
auto[1342177280:1476395007]	auto[1]	59	1			T11	1		T64	1		T50	1
auto[1476395008:1610612735]	auto[0]	44	1			T14	1		T38	1		T180	1
auto[1476395008:1610612735]	auto[1]	50	1			T25	1		T64	1		T78	1
auto[1610612736:1744830463]	auto[0]	56	1			T25	1		T26	1		T79	1
auto[1610612736:1744830463]	auto[1]	41	1			T12	1		T25	1		T5	1
auto[1744830464:1879048191]	auto[0]	46	1			T25	1		T213	1		T30	1
auto[1744830464:1879048191]	auto[1]	62	1			T1	1		T47	1		T25	2
auto[1879048192:2013265919]	auto[0]	52	1			T39	1		T5	2		T188	2
auto[1879048192:2013265919]	auto[1]	60	1			T49	1		T24	1		T25	1
auto[2013265920:2147483647]	auto[0]	44	1			T24	1		T25	1		T5	1
auto[2013265920:2147483647]	auto[1]	65	1			T24	2		T25	2		T130	1
auto[2147483648:2281701375]	auto[0]	53	1			T5	1		T70	1		T104	2
auto[2147483648:2281701375]	auto[1]	42	1			T77	1		T24	1		T71	1
auto[2281701376:2415919103]	auto[0]	52	1			T68	1		T25	3		T20	1
auto[2281701376:2415919103]	auto[1]	48	1			T24	3		T25	1		T69	1
auto[2415919104:2550136831]	auto[0]	39	1			T24	4		T25	1		T26	1
auto[2415919104:2550136831]	auto[1]	57	1			T5	1		T83	1		T92	1
auto[2550136832:2684354559]	auto[0]	44	1			T38	1		T64	1		T51	1
auto[2550136832:2684354559]	auto[1]	62	1			T23	1		T179	1		T130	1
auto[2684354560:2818572287]	auto[0]	52	1			T24	2		T38	1		T25	1
auto[2684354560:2818572287]	auto[1]	60	1			T25	2		T39	1		T50	1
auto[2818572288:2952790015]	auto[0]	49	1			T23	1		T24	1		T25	1
auto[2818572288:2952790015]	auto[1]	54	1			T24	2		T25	2		T79	1
auto[2952790016:3087007743]	auto[0]	44	1			T77	1		T5	1		T70	1
auto[2952790016:3087007743]	auto[1]	55	1			T25	2		T96	1		T5	2
auto[3087007744:3221225471]	auto[0]	54	1			T3	1		T11	1		T47	1
auto[3087007744:3221225471]	auto[1]	53	1			T3	1		T14	1		T47	1
auto[3221225472:3355443199]	auto[0]	45	1			T24	2		T5	1		T83	1
auto[3221225472:3355443199]	auto[1]	55	1			T49	1		T25	1		T64	1
auto[3355443200:3489660927]	auto[0]	40	1			T25	1		T96	1		T223	1
auto[3355443200:3489660927]	auto[1]	66	1			T24	1		T25	3		T95	1
auto[3489660928:3623878655]	auto[0]	44	1			T49	1		T68	1		T25	1
auto[3489660928:3623878655]	auto[1]	55	1			T47	1		T24	2		T25	1
auto[3623878656:3758096383]	auto[0]	53	1			T24	1		T95	1		T5	1
auto[3623878656:3758096383]	auto[1]	58	1			T47	1		T77	1		T24	1
auto[3758096384:3892314111]	auto[0]	56	1			T14	1		T24	1		T26	1
auto[3758096384:3892314111]	auto[1]	61	1			T68	1		T24	1		T25	3
auto[3892314112:4026531839]	auto[0]	48	1			T68	1		T24	2		T25	3
auto[3892314112:4026531839]	auto[1]	62	1			T4	1		T25	2		T78	1
auto[4026531840:4160749567]	auto[0]	65	1			T24	2		T25	1		T130	1
auto[4026531840:4160749567]	auto[1]	62	1			T15	1		T23	2		T24	1
auto[4160749568:4294967295]	auto[0]	48	1			T49	1		T25	1		T96	1
auto[4160749568:4294967295]	auto[1]	61	1			T23	1		T64	1		T96	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T3

1

T11

1

T12

1

auto[1]

1790

1

T1

1

T3

2

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T24	2		T25	5		T64	1
auto[134217728:268435455]	115	1			T1	1		T49	1		T24	1
auto[268435456:402653183]	113	1			T15	1		T23	1		T24	2
auto[402653184:536870911]	109	1			T14	1		T24	2		T96	1
auto[536870912:671088639]	104	1			T49	1		T24	2		T25	2
auto[671088640:805306367]	106	1			T12	1		T24	1		T38	1
auto[805306368:939524095]	98	1			T11	1		T14	1		T68	1
auto[939524096:1073741823]	105	1			T49	1		T68	1		T38	1
auto[1073741824:1207959551]	107	1			T3	1		T24	2		T25	2
auto[1207959552:1342177279]	113	1			T3	1		T24	2		T25	2
auto[1342177280:1476395007]	113	1			T47	1		T25	1		T26	1
auto[1476395008:1610612735]	98	1			T24	4		T79	2		T223	1
auto[1610612736:1744830463]	117	1			T3	1		T11	1		T24	6
auto[1744830464:1879048191]	111	1			T15	1		T68	1		T24	4
auto[1879048192:2013265919]	116	1			T49	2		T25	1		T78	1
auto[2013265920:2147483647]	112	1			T20	1		T5	1		T104	1
auto[2147483648:2281701375]	99	1			T23	1		T24	2		T25	2
auto[2281701376:2415919103]	104	1			T49	1		T25	2		T100	1
auto[2415919104:2550136831]	110	1			T47	1		T77	2		T23	1
auto[2550136832:2684354559]	119	1			T24	1		T25	3		T78	2
auto[2684354560:2818572287]	90	1			T24	4		T223	2		T83	1
auto[2818572288:2952790015]	106	1			T4	1		T47	1		T25	2
auto[2952790016:3087007743]	100	1			T12	2		T24	1		T26	1
auto[3087007744:3221225471]	109	1			T14	1		T68	1		T38	1
auto[3221225472:3355443199]	103	1			T25	2		T64	1		T39	1
auto[3355443200:3489660927]	120	1			T47	1		T24	3		T25	2
auto[3489660928:3623878655]	108	1			T23	1		T24	3		T38	1
auto[3623878656:3758096383]	92	1			T29	1		T24	1		T25	3
auto[3758096384:3892314111]	107	1			T68	1		T25	1		T130	1
auto[3892314112:4026531839]	103	1			T4	1		T68	1		T25	3
auto[4026531840:4160749567]	95	1			T16	1		T47	1		T68	1
auto[4160749568:4294967295]	90	1			T77	1		T23	1		T24	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T24	1		T25	4		T64	1
auto[0:134217727]	auto[1]	49	1			T24	1		T25	1		T96	1
auto[134217728:268435455]	auto[0]	51	1			T25	2		T95	1		T39	1
auto[134217728:268435455]	auto[1]	64	1			T1	1		T49	1		T24	1
auto[268435456:402653183]	auto[0]	61	1			T15	1		T24	2		T5	1
auto[268435456:402653183]	auto[1]	52	1			T23	1		T79	1		T5	1
auto[402653184:536870911]	auto[0]	59	1			T14	1		T5	2		T71	1
auto[402653184:536870911]	auto[1]	50	1			T24	2		T96	1		T104	1
auto[536870912:671088639]	auto[0]	56	1			T49	1		T24	1		T25	2
auto[536870912:671088639]	auto[1]	48	1			T24	1		T130	1		T79	2
auto[671088640:805306367]	auto[0]	54	1			T38	1		T97	1		T79	1
auto[671088640:805306367]	auto[1]	52	1			T12	1		T24	1		T97	1
auto[805306368:939524095]	auto[0]	50	1			T14	1		T68	1		T24	2
auto[805306368:939524095]	auto[1]	48	1			T11	1		T24	1		T25	2
auto[939524096:1073741823]	auto[0]	50	1			T49	1		T68	1		T38	1
auto[939524096:1073741823]	auto[1]	55	1			T25	4		T179	1		T50	1
auto[1073741824:1207959551]	auto[0]	48	1			T24	2		T64	1		T69	1
auto[1073741824:1207959551]	auto[1]	59	1			T3	1		T25	2		T97	1
auto[1207959552:1342177279]	auto[0]	60	1			T3	1		T24	1		T25	1
auto[1207959552:1342177279]	auto[1]	53	1			T24	1		T25	1		T179	1
auto[1342177280:1476395007]	auto[0]	46	1			T25	1		T26	1		T99	1
auto[1342177280:1476395007]	auto[1]	67	1			T47	1		T64	1		T79	1
auto[1476395008:1610612735]	auto[0]	44	1			T79	1		T127	1		T5	1
auto[1476395008:1610612735]	auto[1]	54	1			T24	4		T79	1		T223	1
auto[1610612736:1744830463]	auto[0]	58	1			T11	1		T24	3		T25	3
auto[1610612736:1744830463]	auto[1]	59	1			T3	1		T24	3		T25	4
auto[1744830464:1879048191]	auto[0]	47	1			T15	1		T24	1		T25	2
auto[1744830464:1879048191]	auto[1]	64	1			T68	1		T24	3		T25	1
auto[1879048192:2013265919]	auto[0]	56	1			T25	1		T5	1		T69	1
auto[1879048192:2013265919]	auto[1]	60	1			T49	2		T78	1		T99	1
auto[2013265920:2147483647]	auto[0]	44	1			T104	1		T132	1		T52	1
auto[2013265920:2147483647]	auto[1]	68	1			T20	1		T5	1		T105	1
auto[2147483648:2281701375]	auto[0]	50	1			T24	1		T20	1		T103	1
auto[2147483648:2281701375]	auto[1]	49	1			T23	1		T24	1		T25	2
auto[2281701376:2415919103]	auto[0]	44	1			T49	1		T25	1		T79	1
auto[2281701376:2415919103]	auto[1]	60	1			T25	1		T100	1		T79	1
auto[2415919104:2550136831]	auto[0]	48	1			T77	1		T23	1		T25	1
auto[2415919104:2550136831]	auto[1]	62	1			T47	1		T77	1		T25	5
auto[2550136832:2684354559]	auto[0]	55	1			T24	1		T25	2		T273	1
auto[2550136832:2684354559]	auto[1]	64	1			T25	1		T78	2		T103	1
auto[2684354560:2818572287]	auto[0]	40	1			T24	1		T83	1		T73	1
auto[2684354560:2818572287]	auto[1]	50	1			T24	3		T223	2		T188	1
auto[2818572288:2952790015]	auto[0]	48	1			T25	1		T96	1		T100	1
auto[2818572288:2952790015]	auto[1]	58	1			T4	1		T47	1		T25	1
auto[2952790016:3087007743]	auto[0]	43	1			T12	1		T24	1		T26	1
auto[2952790016:3087007743]	auto[1]	57	1			T12	1		T97	1		T98	1
auto[3087007744:3221225471]	auto[0]	45	1			T38	1		T25	1		T130	1
auto[3087007744:3221225471]	auto[1]	64	1			T14	1		T68	1		T69	2
auto[3221225472:3355443199]	auto[0]	51	1			T25	1		T39	1		T78	1
auto[3221225472:3355443199]	auto[1]	52	1			T25	1		T64	1		T5	1
auto[3355443200:3489660927]	auto[0]	68	1			T24	2		T25	2		T5	2
auto[3355443200:3489660927]	auto[1]	52	1			T47	1		T24	1		T96	1
auto[3489660928:3623878655]	auto[0]	52	1			T24	1		T38	1		T25	1
auto[3489660928:3623878655]	auto[1]	56	1			T23	1		T24	2		T78	1
auto[3623878656:3758096383]	auto[0]	43	1			T25	2		T83	1		T69	2
auto[3623878656:3758096383]	auto[1]	49	1			T29	1		T24	1		T25	1
auto[3758096384:3892314111]	auto[0]	58	1			T68	1		T130	1		T99	1
auto[3758096384:3892314111]	auto[1]	49	1			T25	1		T5	2		T238	1
auto[3892314112:4026531839]	auto[0]	41	1			T68	1		T25	1		T39	1
auto[3892314112:4026531839]	auto[1]	62	1			T4	1		T25	2		T27	1
auto[4026531840:4160749567]	auto[0]	36	1			T68	1		T25	2		T105	1
auto[4026531840:4160749567]	auto[1]	59	1			T16	1		T47	1		T24	1
auto[4160749568:4294967295]	auto[0]	45	1			T24	1		T38	1		T83	1
auto[4160749568:4294967295]	auto[1]	45	1			T77	1		T23	1		T38	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1594

1

T1

1

T3

2

T11

2

auto[1]

1796

1

T3

1

T4

2

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T47	1		T24	2		T25	1
auto[134217728:268435455]	112	1			T14	1		T23	1		T24	2
auto[268435456:402653183]	105	1			T47	1		T24	1		T25	3
auto[402653184:536870911]	114	1			T16	1		T24	4		T25	2
auto[536870912:671088639]	108	1			T14	1		T39	1		T98	1
auto[671088640:805306367]	122	1			T25	1		T130	1		T96	1
auto[805306368:939524095]	105	1			T77	1		T49	1		T24	2
auto[939524096:1073741823]	102	1			T77	1		T68	1		T23	1
auto[1073741824:1207959551]	101	1			T3	1		T24	3		T25	3
auto[1207959552:1342177279]	114	1			T11	1		T14	1		T15	2
auto[1342177280:1476395007]	109	1			T12	1		T24	2		T25	3
auto[1476395008:1610612735]	110	1			T38	1		T25	3		T130	1
auto[1610612736:1744830463]	111	1			T68	1		T24	2		T25	3
auto[1744830464:1879048191]	106	1			T68	1		T23	1		T24	4
auto[1879048192:2013265919]	94	1			T24	1		T25	1		T26	1
auto[2013265920:2147483647]	101	1			T23	1		T25	3		T79	1
auto[2147483648:2281701375]	114	1			T47	1		T38	1		T25	2
auto[2281701376:2415919103]	101	1			T4	1		T23	1		T24	4
auto[2415919104:2550136831]	89	1			T24	1		T25	3		T99	1
auto[2550136832:2684354559]	103	1			T3	1		T24	1		T25	3
auto[2684354560:2818572287]	106	1			T4	1		T24	1		T25	3
auto[2818572288:2952790015]	108	1			T49	1		T24	2		T25	1
auto[2952790016:3087007743]	106	1			T11	1		T49	1		T24	2
auto[3087007744:3221225471]	94	1			T12	1		T29	1		T24	1
auto[3221225472:3355443199]	107	1			T49	1		T79	2		T51	1
auto[3355443200:3489660927]	100	1			T77	1		T68	2		T24	1
auto[3489660928:3623878655]	115	1			T3	1		T24	2		T38	1
auto[3623878656:3758096383]	96	1			T1	1		T12	1		T68	1
auto[3758096384:3892314111]	133	1			T47	1		T49	1		T24	2
auto[3892314112:4026531839]	100	1			T24	1		T25	2		T5	1
auto[4026531840:4160749567]	104	1			T68	1		T24	2		T38	1
auto[4160749568:4294967295]	105	1			T47	1		T24	3		T25	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T24	1		T179	1		T64	1
auto[0:134217727]	auto[1]	47	1			T47	1		T24	1		T25	1
auto[134217728:268435455]	auto[0]	61	1			T14	1		T24	1		T25	1
auto[134217728:268435455]	auto[1]	51	1			T23	1		T24	1		T99	1
auto[268435456:402653183]	auto[0]	54	1			T47	1		T25	3		T99	1
auto[268435456:402653183]	auto[1]	51	1			T24	1		T50	1		T69	1
auto[402653184:536870911]	auto[0]	55	1			T25	1		T96	1		T78	1
auto[402653184:536870911]	auto[1]	59	1			T16	1		T24	4		T25	1
auto[536870912:671088639]	auto[0]	44	1			T39	1		T98	1		T20	1
auto[536870912:671088639]	auto[1]	64	1			T14	1		T223	1		T5	1
auto[671088640:805306367]	auto[0]	54	1			T96	1		T127	1		T188	1
auto[671088640:805306367]	auto[1]	68	1			T25	1		T130	1		T98	1
auto[805306368:939524095]	auto[0]	47	1			T49	1		T39	1		T5	1
auto[805306368:939524095]	auto[1]	58	1			T77	1		T24	2		T25	2
auto[939524096:1073741823]	auto[0]	39	1			T68	1		T24	1		T103	1
auto[939524096:1073741823]	auto[1]	63	1			T77	1		T23	1		T25	1
auto[1073741824:1207959551]	auto[0]	47	1			T24	1		T25	2		T103	1
auto[1073741824:1207959551]	auto[1]	54	1			T3	1		T24	2		T25	1
auto[1207959552:1342177279]	auto[0]	47	1			T11	1		T14	1		T15	2
auto[1207959552:1342177279]	auto[1]	67	1			T25	2		T96	2		T5	1
auto[1342177280:1476395007]	auto[0]	55	1			T24	1		T25	1		T5	1
auto[1342177280:1476395007]	auto[1]	54	1			T12	1		T24	1		T25	2
auto[1476395008:1610612735]	auto[0]	44	1			T25	2		T130	1		T51	1
auto[1476395008:1610612735]	auto[1]	66	1			T38	1		T25	1		T79	1
auto[1610612736:1744830463]	auto[0]	56	1			T68	1		T24	2		T25	2
auto[1610612736:1744830463]	auto[1]	55	1			T25	1		T64	1		T95	1
auto[1744830464:1879048191]	auto[0]	49	1			T68	1		T24	1		T25	1
auto[1744830464:1879048191]	auto[1]	57	1			T23	1		T24	3		T25	1
auto[1879048192:2013265919]	auto[0]	52	1			T26	1		T95	1		T100	1
auto[1879048192:2013265919]	auto[1]	42	1			T24	1		T25	1		T103	1
auto[2013265920:2147483647]	auto[0]	53	1			T23	1		T25	1		T5	2
auto[2013265920:2147483647]	auto[1]	48	1			T25	2		T79	1		T83	1
auto[2147483648:2281701375]	auto[0]	63	1			T38	1		T25	1		T103	1
auto[2147483648:2281701375]	auto[1]	51	1			T47	1		T25	1		T103	1
auto[2281701376:2415919103]	auto[0]	45	1			T23	1		T24	1		T25	1
auto[2281701376:2415919103]	auto[1]	56	1			T4	1		T24	3		T25	3
auto[2415919104:2550136831]	auto[0]	46	1			T24	1		T25	2		T99	1
auto[2415919104:2550136831]	auto[1]	43	1			T25	1		T71	1		T104	1
auto[2550136832:2684354559]	auto[0]	42	1			T3	1		T25	2		T99	1
auto[2550136832:2684354559]	auto[1]	61	1			T24	1		T25	1		T98	1
auto[2684354560:2818572287]	auto[0]	53	1			T25	1		T103	1		T5	2
auto[2684354560:2818572287]	auto[1]	53	1			T4	1		T24	1		T25	2
auto[2818572288:2952790015]	auto[0]	42	1			T49	1		T25	1		T64	1
auto[2818572288:2952790015]	auto[1]	66	1			T24	2		T64	1		T78	1
auto[2952790016:3087007743]	auto[0]	59	1			T11	1		T24	1		T25	2
auto[2952790016:3087007743]	auto[1]	47	1			T49	1		T24	1		T25	2
auto[3087007744:3221225471]	auto[0]	43	1			T12	1		T38	1		T71	1
auto[3087007744:3221225471]	auto[1]	51	1			T29	1		T24	1		T25	1
auto[3221225472:3355443199]	auto[0]	42	1			T49	1		T73	1		T104	1
auto[3221225472:3355443199]	auto[1]	65	1			T79	2		T51	1		T5	1
auto[3355443200:3489660927]	auto[0]	49	1			T77	1		T68	2		T83	1
auto[3355443200:3489660927]	auto[1]	51	1			T24	1		T25	2		T83	1
auto[3489660928:3623878655]	auto[0]	49	1			T3	1		T24	2		T38	1
auto[3489660928:3623878655]	auto[1]	66	1			T25	1		T179	1		T130	1
auto[3623878656:3758096383]	auto[0]	35	1			T1	1		T38	1		T96	1
auto[3623878656:3758096383]	auto[1]	61	1			T12	1		T68	1		T24	1
auto[3758096384:3892314111]	auto[0]	64	1			T49	1		T24	1		T79	1
auto[3758096384:3892314111]	auto[1]	69	1			T47	1		T24	1		T25	2
auto[3892314112:4026531839]	auto[0]	55	1			T24	1		T25	1		T104	1
auto[3892314112:4026531839]	auto[1]	45	1			T25	1		T5	1		T69	1
auto[4026531840:4160749567]	auto[0]	60	1			T24	2		T38	1		T127	1
auto[4026531840:4160749567]	auto[1]	44	1			T68	1		T25	2		T78	1
auto[4160749568:4294967295]	auto[0]	42	1			T47	1		T24	2		T25	1
auto[4160749568:4294967295]	auto[1]	63	1			T24	1		T25	1		T64	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1581

1

T1

1

T3

2

T11

2

auto[1]

1809

1

T3

1

T4

2

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	79	1			T24	2		T103	1		T5	3
auto[134217728:268435455]	118	1			T24	2		T25	2		T64	1
auto[268435456:402653183]	114	1			T14	1		T24	1		T25	4
auto[402653184:536870911]	109	1			T14	1		T77	1		T24	1
auto[536870912:671088639]	109	1			T24	2		T25	4		T64	1
auto[671088640:805306367]	101	1			T23	1		T25	2		T39	1
auto[805306368:939524095]	108	1			T47	1		T29	1		T24	2
auto[939524096:1073741823]	95	1			T24	1		T38	2		T25	1
auto[1073741824:1207959551]	110	1			T68	1		T24	2		T99	1
auto[1207959552:1342177279]	108	1			T24	2		T25	1		T26	1
auto[1342177280:1476395007]	117	1			T1	1		T77	1		T24	2
auto[1476395008:1610612735]	101	1			T47	1		T68	1		T24	2
auto[1610612736:1744830463]	111	1			T23	1		T24	2		T25	4
auto[1744830464:1879048191]	97	1			T25	1		T179	1		T5	5
auto[1879048192:2013265919]	102	1			T14	1		T24	1		T25	1
auto[2013265920:2147483647]	94	1			T68	1		T23	1		T24	2
auto[2147483648:2281701375]	120	1			T4	1		T49	1		T24	2
auto[2281701376:2415919103]	103	1			T15	1		T49	1		T68	1
auto[2415919104:2550136831]	124	1			T24	2		T38	1		T25	3
auto[2550136832:2684354559]	114	1			T3	1		T4	1		T47	1
auto[2684354560:2818572287]	108	1			T47	1		T24	1		T25	2
auto[2818572288:2952790015]	107	1			T49	1		T24	1		T39	1
auto[2952790016:3087007743]	119	1			T24	1		T25	4		T96	1
auto[3087007744:3221225471]	93	1			T16	1		T38	1		T25	1
auto[3221225472:3355443199]	115	1			T49	1		T24	4		T25	3
auto[3355443200:3489660927]	91	1			T3	1		T25	2		T78	1
auto[3489660928:3623878655]	98	1			T11	1		T15	1		T49	1
auto[3623878656:3758096383]	106	1			T68	1		T24	2		T25	2
auto[3758096384:3892314111]	96	1			T12	1		T25	3		T96	1
auto[3892314112:4026531839]	115	1			T12	1		T49	1		T23	1
auto[4026531840:4160749567]	106	1			T11	1		T12	1		T47	1
auto[4160749568:4294967295]	102	1			T3	1		T77	1		T23	1