Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2935

1

T1

1

T3

3

T4

2

auto[1]

261

1

T3

8

T47

3

T98

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T3	1		T47	1		T24	1
auto[134217728:268435455]	85	1			T25	2		T98	1		T99	1
auto[268435456:402653183]	99	1			T1	1		T24	1		T25	1
auto[402653184:536870911]	106	1			T15	1		T47	1		T23	1
auto[536870912:671088639]	96	1			T47	1		T96	1		T78	2
auto[671088640:805306367]	108	1			T3	2		T47	1		T49	1
auto[805306368:939524095]	84	1			T14	1		T24	2		T25	2
auto[939524096:1073741823]	61	1			T24	1		T25	1		T97	1
auto[1073741824:1207959551]	94	1			T77	1		T24	2		T25	1
auto[1207959552:1342177279]	109	1			T3	1		T49	1		T25	3
auto[1342177280:1476395007]	98	1			T3	1		T4	1		T23	1
auto[1476395008:1610612735]	106	1			T14	1		T23	1		T24	2
auto[1610612736:1744830463]	101	1			T12	1		T49	1		T25	1
auto[1744830464:1879048191]	91	1			T24	1		T25	1		T130	1
auto[1879048192:2013265919]	111	1			T25	1		T97	1		T99	1
auto[2013265920:2147483647]	110	1			T68	1		T24	2		T25	3
auto[2147483648:2281701375]	95	1			T3	1		T24	3		T25	1
auto[2281701376:2415919103]	92	1			T3	1		T25	2		T98	1
auto[2415919104:2550136831]	86	1			T47	1		T25	4		T78	1
auto[2550136832:2684354559]	118	1			T4	1		T49	1		T24	2
auto[2684354560:2818572287]	104	1			T11	1		T68	1		T23	1
auto[2818572288:2952790015]	91	1			T47	1		T49	1		T24	1
auto[2952790016:3087007743]	114	1			T14	1		T29	1		T24	2
auto[3087007744:3221225471]	119	1			T3	2		T15	1		T68	1
auto[3221225472:3355443199]	88	1			T24	3		T26	1		T64	1
auto[3355443200:3489660927]	99	1			T68	1		T24	1		T25	2
auto[3489660928:3623878655]	106	1			T77	1		T68	1		T24	1
auto[3623878656:3758096383]	111	1			T3	2		T12	1		T77	1
auto[3758096384:3892314111]	98	1			T38	1		T25	3		T179	1
auto[3892314112:4026531839]	112	1			T47	1		T49	1		T24	2
auto[4026531840:4160749567]	92	1			T11	1		T12	1		T24	1
auto[4160749568:4294967295]	106	1			T47	1		T23	1		T24	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	99	1			T3	1		T47	1		T24	1
auto[0:134217727]	auto[1]	7	1			T110	1		T366	1		T317	1
auto[134217728:268435455]	auto[0]	74	1			T25	2		T99	1		T79	3
auto[134217728:268435455]	auto[1]	11	1			T98	1		T76	1		T338	2
auto[268435456:402653183]	auto[0]	92	1			T1	1		T24	1		T25	1
auto[268435456:402653183]	auto[1]	7	1			T106	1		T366	2		T203	1
auto[402653184:536870911]	auto[0]	100	1			T15	1		T23	1		T24	2
auto[402653184:536870911]	auto[1]	6	1			T47	1		T76	1		T347	1
auto[536870912:671088639]	auto[0]	88	1			T96	1		T78	2		T98	1
auto[536870912:671088639]	auto[1]	8	1			T47	1		T106	1		T338	1
auto[671088640:805306367]	auto[0]	97	1			T47	1		T49	1		T24	1
auto[671088640:805306367]	auto[1]	11	1			T3	2		T98	1		T103	1
auto[805306368:939524095]	auto[0]	77	1			T14	1		T24	2		T25	2
auto[805306368:939524095]	auto[1]	7	1			T103	1		T76	1		T313	1
auto[939524096:1073741823]	auto[0]	57	1			T24	1		T25	1		T97	1
auto[939524096:1073741823]	auto[1]	4	1			T110	1		T237	1		T367	1
auto[1073741824:1207959551]	auto[0]	88	1			T77	1		T24	2		T25	1
auto[1073741824:1207959551]	auto[1]	6	1			T98	1		T293	1		T204	2
auto[1207959552:1342177279]	auto[0]	99	1			T49	1		T25	3		T64	1
auto[1207959552:1342177279]	auto[1]	10	1			T3	1		T98	1		T106	1
auto[1342177280:1476395007]	auto[0]	90	1			T4	1		T23	1		T24	2
auto[1342177280:1476395007]	auto[1]	8	1			T3	1		T76	1		T337	1
auto[1476395008:1610612735]	auto[0]	95	1			T14	1		T23	1		T24	2
auto[1476395008:1610612735]	auto[1]	11	1			T106	1		T109	1		T365	1
auto[1610612736:1744830463]	auto[0]	95	1			T12	1		T49	1		T25	1
auto[1610612736:1744830463]	auto[1]	6	1			T237	1		T366	1		T388	2
auto[1744830464:1879048191]	auto[0]	84	1			T24	1		T25	1		T130	1
auto[1744830464:1879048191]	auto[1]	7	1			T76	1		T106	1		T365	1
auto[1879048192:2013265919]	auto[0]	100	1			T25	1		T97	1		T99	1
auto[1879048192:2013265919]	auto[1]	11	1			T76	1		T237	1		T225	2
auto[2013265920:2147483647]	auto[0]	104	1			T68	1		T24	2		T25	3
auto[2013265920:2147483647]	auto[1]	6	1			T365	1		T339	1		T366	1
auto[2147483648:2281701375]	auto[0]	88	1			T24	3		T25	1		T130	1
auto[2147483648:2281701375]	auto[1]	7	1			T3	1		T225	2		T389	1
auto[2281701376:2415919103]	auto[0]	80	1			T25	2		T99	1		T5	1
auto[2281701376:2415919103]	auto[1]	12	1			T3	1		T98	1		T338	1
auto[2415919104:2550136831]	auto[0]	80	1			T47	1		T25	4		T78	1
auto[2415919104:2550136831]	auto[1]	6	1			T219	1		T106	1		T110	1
auto[2550136832:2684354559]	auto[0]	107	1			T4	1		T49	1		T24	2
auto[2550136832:2684354559]	auto[1]	11	1			T76	1		T339	1		T237	1
auto[2684354560:2818572287]	auto[0]	94	1			T11	1		T68	1		T23	1
auto[2684354560:2818572287]	auto[1]	10	1			T236	1		T347	2		T237	1
auto[2818572288:2952790015]	auto[0]	85	1			T47	1		T49	1		T24	1
auto[2818572288:2952790015]	auto[1]	6	1			T98	1		T106	1		T347	1
auto[2952790016:3087007743]	auto[0]	109	1			T14	1		T29	1		T24	2
auto[2952790016:3087007743]	auto[1]	5	1			T219	1		T106	2		T339	1
auto[3087007744:3221225471]	auto[0]	114	1			T3	1		T15	1		T68	1
auto[3087007744:3221225471]	auto[1]	5	1			T3	1		T106	1		T347	1
auto[3221225472:3355443199]	auto[0]	84	1			T24	3		T26	1		T64	1
auto[3221225472:3355443199]	auto[1]	4	1			T237	1		T366	1		T384	1
auto[3355443200:3489660927]	auto[0]	86	1			T68	1		T24	1		T25	2
auto[3355443200:3489660927]	auto[1]	13	1			T106	2		T259	1		T347	1
auto[3489660928:3623878655]	auto[0]	98	1			T77	1		T68	1		T24	1
auto[3489660928:3623878655]	auto[1]	8	1			T365	1		T346	1		T388	1
auto[3623878656:3758096383]	auto[0]	105	1			T3	1		T12	1		T77	1
auto[3623878656:3758096383]	auto[1]	6	1			T3	1		T76	1		T236	1
auto[3758096384:3892314111]	auto[0]	90	1			T38	1		T25	3		T179	1
auto[3758096384:3892314111]	auto[1]	8	1			T259	2		T365	1		T388	1
auto[3892314112:4026531839]	auto[0]	97	1			T49	1		T24	2		T25	2
auto[3892314112:4026531839]	auto[1]	15	1			T47	1		T103	1		T76	2
auto[4026531840:4160749567]	auto[0]	84	1			T11	1		T12	1		T24	1
auto[4026531840:4160749567]	auto[1]	8	1			T76	1		T110	2		T293	1
auto[4160749568:4294967295]	auto[0]	95	1			T47	1		T23	1		T24	3
auto[4160749568:4294967295]	auto[1]	11	1			T76	2		T110	1		T365	1