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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.40 99.00 98.07 98.32 97.67 98.93 98.63 91.14


Total test records in report: 1089
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T161 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2511689543 Aug 16 04:53:24 PM PDT 24 Aug 16 04:53:29 PM PDT 24 123377009 ps
T1007 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.22389795 Aug 16 04:53:15 PM PDT 24 Aug 16 04:53:18 PM PDT 24 156574700 ps
T1008 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1136528605 Aug 16 04:53:46 PM PDT 24 Aug 16 04:53:52 PM PDT 24 223412572 ps
T1009 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.4207573169 Aug 16 04:53:38 PM PDT 24 Aug 16 04:53:39 PM PDT 24 27301815 ps
T1010 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4058518178 Aug 16 04:53:24 PM PDT 24 Aug 16 04:53:29 PM PDT 24 149194605 ps
T1011 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.129163026 Aug 16 04:53:05 PM PDT 24 Aug 16 04:53:06 PM PDT 24 17888079 ps
T1012 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3410805769 Aug 16 04:53:27 PM PDT 24 Aug 16 04:53:28 PM PDT 24 114079169 ps
T1013 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1879978055 Aug 16 04:53:14 PM PDT 24 Aug 16 04:53:15 PM PDT 24 164329276 ps
T1014 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2499617951 Aug 16 04:53:11 PM PDT 24 Aug 16 04:53:14 PM PDT 24 51080047 ps
T1015 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1991274017 Aug 16 04:53:30 PM PDT 24 Aug 16 04:53:32 PM PDT 24 179013364 ps
T1016 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.70185634 Aug 16 04:53:35 PM PDT 24 Aug 16 04:53:36 PM PDT 24 77354438 ps
T1017 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1330947729 Aug 16 04:53:53 PM PDT 24 Aug 16 04:53:54 PM PDT 24 12239932 ps
T1018 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2643810864 Aug 16 04:53:30 PM PDT 24 Aug 16 04:53:33 PM PDT 24 678452484 ps
T1019 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.165170449 Aug 16 04:53:40 PM PDT 24 Aug 16 04:53:42 PM PDT 24 189494116 ps
T1020 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2322008225 Aug 16 04:53:41 PM PDT 24 Aug 16 04:53:41 PM PDT 24 14384704 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2080895711 Aug 16 04:53:13 PM PDT 24 Aug 16 04:53:14 PM PDT 24 44921457 ps
T1022 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.509780562 Aug 16 04:53:47 PM PDT 24 Aug 16 04:53:48 PM PDT 24 34999446 ps
T1023 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2476496167 Aug 16 04:53:39 PM PDT 24 Aug 16 04:53:42 PM PDT 24 154691026 ps
T1024 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1496062112 Aug 16 04:53:37 PM PDT 24 Aug 16 04:53:40 PM PDT 24 139108887 ps
T1025 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2315936551 Aug 16 04:53:18 PM PDT 24 Aug 16 04:53:20 PM PDT 24 203868247 ps
T1026 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1542946872 Aug 16 04:53:39 PM PDT 24 Aug 16 04:53:40 PM PDT 24 15844148 ps
T1027 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.634434767 Aug 16 04:53:25 PM PDT 24 Aug 16 04:53:27 PM PDT 24 116844639 ps
T156 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3356786250 Aug 16 04:53:31 PM PDT 24 Aug 16 04:53:37 PM PDT 24 182512318 ps
T165 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.683674410 Aug 16 04:53:16 PM PDT 24 Aug 16 04:53:19 PM PDT 24 81471913 ps
T1028 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1786216681 Aug 16 04:53:26 PM PDT 24 Aug 16 04:53:27 PM PDT 24 47202549 ps
T1029 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3231832051 Aug 16 04:53:15 PM PDT 24 Aug 16 04:53:20 PM PDT 24 274971324 ps
T1030 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2449315484 Aug 16 04:53:53 PM PDT 24 Aug 16 04:53:54 PM PDT 24 11562569 ps
T1031 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2710000644 Aug 16 04:53:57 PM PDT 24 Aug 16 04:53:58 PM PDT 24 15083626 ps
T1032 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3526133510 Aug 16 04:53:22 PM PDT 24 Aug 16 04:53:38 PM PDT 24 2952070875 ps
T1033 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2146662978 Aug 16 04:53:12 PM PDT 24 Aug 16 04:53:14 PM PDT 24 26001989 ps
T1034 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3166551084 Aug 16 04:53:14 PM PDT 24 Aug 16 04:53:17 PM PDT 24 295413796 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1342380839 Aug 16 04:53:11 PM PDT 24 Aug 16 04:53:12 PM PDT 24 14147331 ps
T1036 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3608134118 Aug 16 04:53:24 PM PDT 24 Aug 16 04:53:26 PM PDT 24 41923454 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1218263453 Aug 16 04:53:14 PM PDT 24 Aug 16 04:53:16 PM PDT 24 29579687 ps
T1038 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1085798332 Aug 16 04:53:15 PM PDT 24 Aug 16 04:53:18 PM PDT 24 215956601 ps
T1039 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2468833962 Aug 16 04:53:16 PM PDT 24 Aug 16 04:53:18 PM PDT 24 74734791 ps
T1040 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1979945242 Aug 16 04:53:52 PM PDT 24 Aug 16 04:53:53 PM PDT 24 40379550 ps
T1041 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2000040067 Aug 16 04:53:11 PM PDT 24 Aug 16 04:53:13 PM PDT 24 722787542 ps
T159 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.981402375 Aug 16 04:53:18 PM PDT 24 Aug 16 04:53:21 PM PDT 24 53142659 ps
T1042 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3550994741 Aug 16 04:53:43 PM PDT 24 Aug 16 04:53:43 PM PDT 24 36724157 ps
T164 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1159979831 Aug 16 04:53:11 PM PDT 24 Aug 16 04:53:19 PM PDT 24 562061274 ps
T1043 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4073504499 Aug 16 04:53:26 PM PDT 24 Aug 16 04:53:27 PM PDT 24 58699334 ps
T1044 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1730213169 Aug 16 04:53:31 PM PDT 24 Aug 16 04:53:34 PM PDT 24 303935972 ps
T1045 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.577922020 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:49 PM PDT 24 25564005 ps
T1046 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2711659890 Aug 16 04:53:23 PM PDT 24 Aug 16 04:53:24 PM PDT 24 22834700 ps
T1047 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4193158455 Aug 16 04:53:19 PM PDT 24 Aug 16 04:53:21 PM PDT 24 22601386 ps
T1048 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1064678343 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:49 PM PDT 24 18110507 ps
T1049 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3024903464 Aug 16 04:53:26 PM PDT 24 Aug 16 04:53:27 PM PDT 24 11555812 ps
T1050 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1680736191 Aug 16 04:53:17 PM PDT 24 Aug 16 04:53:31 PM PDT 24 927859800 ps
T1051 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1680705451 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:51 PM PDT 24 185023196 ps
T1052 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2357215183 Aug 16 04:53:17 PM PDT 24 Aug 16 04:53:19 PM PDT 24 31332440 ps
T1053 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3462369351 Aug 16 04:53:36 PM PDT 24 Aug 16 04:53:37 PM PDT 24 13480936 ps
T1054 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2923095105 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:49 PM PDT 24 91849433 ps
T1055 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2762575780 Aug 16 04:53:16 PM PDT 24 Aug 16 04:53:17 PM PDT 24 43929794 ps
T1056 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.557705548 Aug 16 04:53:20 PM PDT 24 Aug 16 04:53:27 PM PDT 24 194086184 ps
T1057 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2314270470 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:50 PM PDT 24 341724025 ps
T1058 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2399835238 Aug 16 04:53:44 PM PDT 24 Aug 16 04:53:45 PM PDT 24 19261737 ps
T1059 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2833150154 Aug 16 04:53:15 PM PDT 24 Aug 16 04:53:16 PM PDT 24 38309596 ps
T1060 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3577703485 Aug 16 04:53:29 PM PDT 24 Aug 16 04:53:30 PM PDT 24 40836066 ps
T1061 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1818967832 Aug 16 04:53:17 PM PDT 24 Aug 16 04:53:18 PM PDT 24 38100073 ps
T1062 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.263703204 Aug 16 04:53:10 PM PDT 24 Aug 16 04:53:12 PM PDT 24 35670703 ps
T1063 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.538809965 Aug 16 04:53:31 PM PDT 24 Aug 16 04:53:35 PM PDT 24 197306801 ps
T1064 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.382230298 Aug 16 04:53:13 PM PDT 24 Aug 16 04:53:14 PM PDT 24 12903630 ps
T1065 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3149434302 Aug 16 04:53:17 PM PDT 24 Aug 16 04:53:23 PM PDT 24 759411707 ps
T1066 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.368953950 Aug 16 04:53:23 PM PDT 24 Aug 16 04:53:25 PM PDT 24 257310194 ps
T1067 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.48611918 Aug 16 04:53:22 PM PDT 24 Aug 16 04:53:25 PM PDT 24 264549035 ps
T1068 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3326709046 Aug 16 04:53:08 PM PDT 24 Aug 16 04:53:12 PM PDT 24 69049370 ps
T1069 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.308725315 Aug 16 04:53:45 PM PDT 24 Aug 16 04:53:47 PM PDT 24 36504242 ps
T1070 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2759899273 Aug 16 04:53:26 PM PDT 24 Aug 16 04:53:27 PM PDT 24 14204737 ps
T1071 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4137797377 Aug 16 04:53:47 PM PDT 24 Aug 16 04:53:48 PM PDT 24 11013243 ps
T1072 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.523524484 Aug 16 04:53:40 PM PDT 24 Aug 16 04:53:41 PM PDT 24 24505980 ps
T1073 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1649683627 Aug 16 04:53:37 PM PDT 24 Aug 16 04:53:40 PM PDT 24 133914090 ps
T1074 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1630505276 Aug 16 04:53:39 PM PDT 24 Aug 16 04:53:40 PM PDT 24 18556531 ps
T1075 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2738049723 Aug 16 04:53:41 PM PDT 24 Aug 16 04:53:43 PM PDT 24 86639299 ps
T1076 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2853431843 Aug 16 04:53:17 PM PDT 24 Aug 16 04:53:20 PM PDT 24 65109247 ps
T1077 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1198009019 Aug 16 04:53:17 PM PDT 24 Aug 16 04:53:18 PM PDT 24 29905396 ps
T1078 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3820101492 Aug 16 04:53:36 PM PDT 24 Aug 16 04:53:37 PM PDT 24 15655080 ps
T1079 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4212481268 Aug 16 04:53:23 PM PDT 24 Aug 16 04:53:25 PM PDT 24 32335687 ps
T1080 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2738674376 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:53 PM PDT 24 127132783 ps
T1081 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.899529345 Aug 16 04:53:31 PM PDT 24 Aug 16 04:53:34 PM PDT 24 107331021 ps
T1082 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2067695819 Aug 16 04:53:15 PM PDT 24 Aug 16 04:53:23 PM PDT 24 220980956 ps
T1083 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.961811538 Aug 16 04:53:47 PM PDT 24 Aug 16 04:53:55 PM PDT 24 259314095 ps
T1084 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3641507852 Aug 16 04:53:23 PM PDT 24 Aug 16 04:53:28 PM PDT 24 274910710 ps
T1085 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.477363815 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:49 PM PDT 24 9895320 ps
T1086 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1486445570 Aug 16 04:53:15 PM PDT 24 Aug 16 04:53:17 PM PDT 24 199768680 ps
T1087 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1020717817 Aug 16 04:53:11 PM PDT 24 Aug 16 04:53:14 PM PDT 24 115885730 ps
T1088 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2336851633 Aug 16 04:53:50 PM PDT 24 Aug 16 04:53:51 PM PDT 24 22951769 ps
T1089 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3708931465 Aug 16 04:53:37 PM PDT 24 Aug 16 04:53:39 PM PDT 24 86920263 ps
T158 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2441858967 Aug 16 04:53:25 PM PDT 24 Aug 16 04:53:31 PM PDT 24 272436574 ps

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2649597326
Short name T3
Test name
Test status
Simulation time 164008967 ps
CPU time 8.5 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 214924 kb
Host smart-6a7ba86d-6781-45ce-a3b4-cb5d818678bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649597326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2649597326
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.4173734398
Short name T25
Test name
Test status
Simulation time 7329620168 ps
CPU time 52.87 seconds
Started Aug 16 05:52:37 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 223012 kb
Host smart-3318d44f-482a-40a3-b31f-caedf6487f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173734398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.4173734398
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1629757048
Short name T24
Test name
Test status
Simulation time 1769103803 ps
CPU time 28.71 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:45 PM PDT 24
Peak memory 216704 kb
Host smart-fe8bd6da-a2af-4353-9edc-b4ef587deaa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629757048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1629757048
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1677965784
Short name T78
Test name
Test status
Simulation time 769517169 ps
CPU time 15.4 seconds
Started Aug 16 05:53:49 PM PDT 24
Finished Aug 16 05:54:04 PM PDT 24
Peak memory 223028 kb
Host smart-f1fb0a33-7cbc-4413-9177-9a7a1a280a75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677965784 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1677965784
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3553705455
Short name T8
Test name
Test status
Simulation time 783200097 ps
CPU time 11.42 seconds
Started Aug 16 05:53:06 PM PDT 24
Finished Aug 16 05:53:18 PM PDT 24
Peak memory 231016 kb
Host smart-2c5c7b14-7f0a-4900-afc4-d663cf9b8e40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553705455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3553705455
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3313993789
Short name T14
Test name
Test status
Simulation time 89747650 ps
CPU time 2.25 seconds
Started Aug 16 05:53:41 PM PDT 24
Finished Aug 16 05:53:43 PM PDT 24
Peak memory 217560 kb
Host smart-1438b84f-df5b-4d2e-a2b8-e6c78fca8a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313993789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3313993789
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3842185011
Short name T175
Test name
Test status
Simulation time 28924904323 ps
CPU time 148 seconds
Started Aug 16 05:54:22 PM PDT 24
Finished Aug 16 05:56:50 PM PDT 24
Peak memory 216712 kb
Host smart-ecfa1fd2-1e4f-490b-a552-a56d491e41dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842185011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3842185011
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3006029411
Short name T64
Test name
Test status
Simulation time 894418992 ps
CPU time 17.8 seconds
Started Aug 16 05:54:55 PM PDT 24
Finished Aug 16 05:55:13 PM PDT 24
Peak memory 221784 kb
Host smart-5c7531b9-20c7-4993-b8a6-1683cb6683b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006029411 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3006029411
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3666582064
Short name T81
Test name
Test status
Simulation time 506875151 ps
CPU time 15.91 seconds
Started Aug 16 04:53:14 PM PDT 24
Finished Aug 16 04:53:30 PM PDT 24
Peak memory 214936 kb
Host smart-cb0d4306-d32b-4d6f-a2d5-8b13020221ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666582064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3666582064
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.382376291
Short name T76
Test name
Test status
Simulation time 149022505 ps
CPU time 8.18 seconds
Started Aug 16 05:53:02 PM PDT 24
Finished Aug 16 05:53:10 PM PDT 24
Peak memory 215888 kb
Host smart-04afaf90-4d38-46a7-a583-af29e095790b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382376291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.382376291
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2791619752
Short name T5
Test name
Test status
Simulation time 1418156337 ps
CPU time 46.41 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:55:18 PM PDT 24
Peak memory 221516 kb
Host smart-637426da-ac74-4fe5-a5a1-8137d617b9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791619752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2791619752
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3729716432
Short name T21
Test name
Test status
Simulation time 299014354 ps
CPU time 3.98 seconds
Started Aug 16 05:52:32 PM PDT 24
Finished Aug 16 05:52:36 PM PDT 24
Peak memory 214804 kb
Host smart-e3eb23f0-ac08-43ff-b006-854ff3279b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729716432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3729716432
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1939352085
Short name T110
Test name
Test status
Simulation time 195055625 ps
CPU time 10.38 seconds
Started Aug 16 05:54:33 PM PDT 24
Finished Aug 16 05:54:43 PM PDT 24
Peak memory 216188 kb
Host smart-d96c1989-3a7c-4358-96ab-093f31f8dbfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939352085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1939352085
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2803011036
Short name T69
Test name
Test status
Simulation time 1904921008 ps
CPU time 17.06 seconds
Started Aug 16 05:53:19 PM PDT 24
Finished Aug 16 05:53:36 PM PDT 24
Peak memory 221100 kb
Host smart-ddd81598-dbb7-4e1e-8a40-e05e0c723830
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803011036 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2803011036
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2712620318
Short name T31
Test name
Test status
Simulation time 133647609 ps
CPU time 2.33 seconds
Started Aug 16 05:53:36 PM PDT 24
Finished Aug 16 05:53:38 PM PDT 24
Peak memory 222124 kb
Host smart-ac32ffe6-102b-49b1-9159-40ee3860abde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712620318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2712620318
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2002168845
Short name T47
Test name
Test status
Simulation time 404270144 ps
CPU time 10.44 seconds
Started Aug 16 05:54:48 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 214756 kb
Host smart-bbfb534a-95f3-45e1-81dc-732e80b881b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002168845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2002168845
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.512172626
Short name T382
Test name
Test status
Simulation time 3334575619 ps
CPU time 47.6 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:54 PM PDT 24
Peak memory 222996 kb
Host smart-f8333e4d-75d7-4f3a-b3e8-8af6dd68e7d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512172626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.512172626
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2671121953
Short name T132
Test name
Test status
Simulation time 7455817682 ps
CPU time 68.59 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:54:36 PM PDT 24
Peak memory 217288 kb
Host smart-135bd721-e88a-435a-ba49-e1fe32a5a864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671121953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2671121953
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1007654254
Short name T88
Test name
Test status
Simulation time 165654175 ps
CPU time 4.67 seconds
Started Aug 16 04:53:25 PM PDT 24
Finished Aug 16 04:53:30 PM PDT 24
Peak memory 214880 kb
Host smart-39aac8ac-2889-451d-8798-5144878a1d76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007654254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1007654254
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.4267634903
Short name T106
Test name
Test status
Simulation time 813359772 ps
CPU time 11.65 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 214736 kb
Host smart-900146d4-683b-4c96-8334-609822dff69d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267634903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4267634903
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1672133926
Short name T54
Test name
Test status
Simulation time 329475488 ps
CPU time 3.2 seconds
Started Aug 16 05:54:03 PM PDT 24
Finished Aug 16 05:54:07 PM PDT 24
Peak memory 214788 kb
Host smart-ef9bbc53-26f7-465d-bc43-2b92bc4ba5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672133926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1672133926
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3028826362
Short name T19
Test name
Test status
Simulation time 678443328 ps
CPU time 2.56 seconds
Started Aug 16 05:53:35 PM PDT 24
Finished Aug 16 05:53:38 PM PDT 24
Peak memory 217896 kb
Host smart-81147a7c-df04-40e8-bfae-9bf4a01b63fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028826362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3028826362
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3703192978
Short name T16
Test name
Test status
Simulation time 89232814 ps
CPU time 3.27 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:51 PM PDT 24
Peak memory 210056 kb
Host smart-e589c61d-3aa4-4604-a009-def210c8fbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703192978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3703192978
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3504120070
Short name T191
Test name
Test status
Simulation time 141431185 ps
CPU time 2.62 seconds
Started Aug 16 05:54:09 PM PDT 24
Finished Aug 16 05:54:11 PM PDT 24
Peak memory 208876 kb
Host smart-16b20f82-e25f-4898-8119-a092dd320568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504120070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3504120070
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3383143033
Short name T338
Test name
Test status
Simulation time 214241545 ps
CPU time 11.25 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:27 PM PDT 24
Peak memory 214820 kb
Host smart-2105c56a-15ca-4fd4-8315-d63d0e08f78e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383143033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3383143033
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1260336169
Short name T152
Test name
Test status
Simulation time 330354294 ps
CPU time 11.9 seconds
Started Aug 16 05:52:57 PM PDT 24
Finished Aug 16 05:53:09 PM PDT 24
Peak memory 223016 kb
Host smart-1a6c8d77-246d-43cf-8cf4-64522f0d714f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260336169 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1260336169
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2737791593
Short name T119
Test name
Test status
Simulation time 79463830 ps
CPU time 3.55 seconds
Started Aug 16 05:53:39 PM PDT 24
Finished Aug 16 05:53:43 PM PDT 24
Peak memory 218428 kb
Host smart-d56f54fc-182a-4974-9e0c-7eb349487e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737791593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2737791593
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1615991321
Short name T105
Test name
Test status
Simulation time 10314647084 ps
CPU time 31.78 seconds
Started Aug 16 05:53:54 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 221536 kb
Host smart-e43c1095-1dda-4fba-95ff-b8a321b03d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615991321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1615991321
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4059676806
Short name T293
Test name
Test status
Simulation time 19345864057 ps
CPU time 93.93 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 214916 kb
Host smart-69942f69-524e-40fb-8dc1-998d90355d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4059676806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4059676806
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2783946052
Short name T128
Test name
Test status
Simulation time 134222412 ps
CPU time 2.56 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:46 PM PDT 24
Peak memory 211072 kb
Host smart-10461830-1679-4a04-b887-29503c8fc60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783946052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2783946052
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2506953025
Short name T151
Test name
Test status
Simulation time 101471763 ps
CPU time 5.29 seconds
Started Aug 16 04:53:33 PM PDT 24
Finished Aug 16 04:53:39 PM PDT 24
Peak memory 206308 kb
Host smart-8ad9f883-eb0b-4b14-8091-ce2e95cdbd83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506953025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2506953025
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1194522015
Short name T134
Test name
Test status
Simulation time 345209197 ps
CPU time 16.34 seconds
Started Aug 16 05:54:41 PM PDT 24
Finished Aug 16 05:54:58 PM PDT 24
Peak memory 216348 kb
Host smart-6786d20a-1eb6-4a82-83a4-31e5efc06afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194522015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1194522015
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1092947499
Short name T18
Test name
Test status
Simulation time 847249899 ps
CPU time 6.59 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 209448 kb
Host smart-c6eb24c4-6a40-4126-8138-1161693f541e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092947499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1092947499
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2529189974
Short name T62
Test name
Test status
Simulation time 24124052 ps
CPU time 0.74 seconds
Started Aug 16 05:52:54 PM PDT 24
Finished Aug 16 05:52:55 PM PDT 24
Peak memory 206488 kb
Host smart-0bc1d24e-bc7d-474c-9835-a70768529769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529189974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2529189974
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1604115714
Short name T351
Test name
Test status
Simulation time 737726157 ps
CPU time 6.44 seconds
Started Aug 16 05:54:10 PM PDT 24
Finished Aug 16 05:54:17 PM PDT 24
Peak memory 219352 kb
Host smart-b520f939-2bf4-49e0-bc9d-aed9c2d3271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604115714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1604115714
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4063366523
Short name T346
Test name
Test status
Simulation time 158241691 ps
CPU time 3.57 seconds
Started Aug 16 05:53:06 PM PDT 24
Finished Aug 16 05:53:09 PM PDT 24
Peak memory 215400 kb
Host smart-a4d32400-ff9c-4e63-b2ed-83e59de2fc62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063366523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4063366523
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1962909537
Short name T129
Test name
Test status
Simulation time 5110519224 ps
CPU time 45.86 seconds
Started Aug 16 05:54:38 PM PDT 24
Finished Aug 16 05:55:24 PM PDT 24
Peak memory 216588 kb
Host smart-7c3c0e6f-5fc7-43c3-8672-6df4ce4e0f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962909537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1962909537
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3356786250
Short name T156
Test name
Test status
Simulation time 182512318 ps
CPU time 5.36 seconds
Started Aug 16 04:53:31 PM PDT 24
Finished Aug 16 04:53:37 PM PDT 24
Peak memory 214472 kb
Host smart-374ffada-ec16-44ee-9522-f016cd9a5059
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356786250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3356786250
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1835958203
Short name T366
Test name
Test status
Simulation time 54675816 ps
CPU time 3.53 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 215572 kb
Host smart-28751d84-5c4b-4ddb-9ae8-cadf9cf890e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835958203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1835958203
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1348115505
Short name T53
Test name
Test status
Simulation time 47795131 ps
CPU time 2.54 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 214792 kb
Host smart-1ce4b853-49b2-4b10-b17f-5caa998a1fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348115505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1348115505
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1543325665
Short name T391
Test name
Test status
Simulation time 1655670827 ps
CPU time 42.22 seconds
Started Aug 16 05:54:02 PM PDT 24
Finished Aug 16 05:54:45 PM PDT 24
Peak memory 215820 kb
Host smart-77f183f7-9f2b-4099-97e0-79ee28920f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543325665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1543325665
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1306183224
Short name T276
Test name
Test status
Simulation time 117049551 ps
CPU time 3.58 seconds
Started Aug 16 05:52:39 PM PDT 24
Finished Aug 16 05:52:42 PM PDT 24
Peak memory 222836 kb
Host smart-f432c539-df76-4366-977d-32074da06e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306183224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1306183224
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2260584970
Short name T214
Test name
Test status
Simulation time 394849420 ps
CPU time 5.37 seconds
Started Aug 16 05:53:06 PM PDT 24
Finished Aug 16 05:53:12 PM PDT 24
Peak memory 222884 kb
Host smart-73afdc36-eb02-4969-8afd-036ad98bc2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260584970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2260584970
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.534283098
Short name T92
Test name
Test status
Simulation time 539969077 ps
CPU time 21.83 seconds
Started Aug 16 05:54:41 PM PDT 24
Finished Aug 16 05:55:03 PM PDT 24
Peak memory 222992 kb
Host smart-98a0824f-2e9a-40d7-8bc5-479b61c382dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534283098 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.534283098
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.20085029
Short name T160
Test name
Test status
Simulation time 445261216 ps
CPU time 8.39 seconds
Started Aug 16 04:53:34 PM PDT 24
Finished Aug 16 04:53:43 PM PDT 24
Peak memory 214504 kb
Host smart-0f16ba1e-de25-42a2-ba0b-006044cfb353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20085029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.20085029
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.750835610
Short name T50
Test name
Test status
Simulation time 450461149 ps
CPU time 7.62 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:20 PM PDT 24
Peak memory 210156 kb
Host smart-7c3f2c0c-e03f-4e60-b573-8c69d3779043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750835610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.750835610
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3134989831
Short name T83
Test name
Test status
Simulation time 564574896 ps
CPU time 17.45 seconds
Started Aug 16 05:53:20 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 222860 kb
Host smart-e621918f-7471-4d2f-95e4-148260ed49d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134989831 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3134989831
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.564569598
Short name T361
Test name
Test status
Simulation time 86650626 ps
CPU time 1.54 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 210576 kb
Host smart-23320be4-f574-42ea-a10e-a030fd6b2e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564569598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.564569598
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1467469853
Short name T282
Test name
Test status
Simulation time 3016995264 ps
CPU time 25.21 seconds
Started Aug 16 05:54:12 PM PDT 24
Finished Aug 16 05:54:37 PM PDT 24
Peak memory 214816 kb
Host smart-bf102131-f056-406b-8193-951e559c5966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467469853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1467469853
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3884852511
Short name T177
Test name
Test status
Simulation time 6169967674 ps
CPU time 40.24 seconds
Started Aug 16 05:52:49 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 216956 kb
Host smart-bf3c800d-4c26-4e47-ae34-93c53fe6d300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884852511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3884852511
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1496613381
Short name T84
Test name
Test status
Simulation time 625067052 ps
CPU time 2.57 seconds
Started Aug 16 04:53:23 PM PDT 24
Finished Aug 16 04:53:25 PM PDT 24
Peak memory 214868 kb
Host smart-66fcc21a-f258-48ef-8d6e-a520d842e075
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496613381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1496613381
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2807405796
Short name T10
Test name
Test status
Simulation time 3985747252 ps
CPU time 37.53 seconds
Started Aug 16 05:52:34 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 239316 kb
Host smart-14a07484-39e9-478c-ab6b-0c136285ed50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807405796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2807405796
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3574409830
Short name T44
Test name
Test status
Simulation time 309329846 ps
CPU time 8.58 seconds
Started Aug 16 05:54:44 PM PDT 24
Finished Aug 16 05:54:53 PM PDT 24
Peak memory 211508 kb
Host smart-c83163cd-6bfd-4613-8417-a3730e062872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574409830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3574409830
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2513054198
Short name T204
Test name
Test status
Simulation time 50038602 ps
CPU time 3.27 seconds
Started Aug 16 05:53:03 PM PDT 24
Finished Aug 16 05:53:06 PM PDT 24
Peak memory 214672 kb
Host smart-bdf9be3d-8fae-488b-9698-9ac05d86c8a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513054198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2513054198
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3022031469
Short name T285
Test name
Test status
Simulation time 269545159 ps
CPU time 3.86 seconds
Started Aug 16 05:53:01 PM PDT 24
Finished Aug 16 05:53:05 PM PDT 24
Peak memory 209168 kb
Host smart-48ddf365-52ee-4bb2-adc9-cd994a7c8e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022031469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3022031469
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3936280699
Short name T22
Test name
Test status
Simulation time 1034871060 ps
CPU time 5.02 seconds
Started Aug 16 05:53:25 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 222088 kb
Host smart-6da7f518-d0e5-4a69-ad2c-3f695a587833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936280699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3936280699
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3616674994
Short name T260
Test name
Test status
Simulation time 243306473 ps
CPU time 3.91 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 214784 kb
Host smart-c02bf6d5-ef07-4b66-abe0-83da92889b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616674994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3616674994
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1485108391
Short name T195
Test name
Test status
Simulation time 2713088511 ps
CPU time 30.44 seconds
Started Aug 16 05:53:02 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 216968 kb
Host smart-bd1caacb-7f53-4bf0-a75b-055a89f48f63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485108391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1485108391
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2769175760
Short name T118
Test name
Test status
Simulation time 127814491 ps
CPU time 5.1 seconds
Started Aug 16 05:53:38 PM PDT 24
Finished Aug 16 05:53:43 PM PDT 24
Peak memory 221972 kb
Host smart-48ee0167-ddf2-41b0-8af4-845dcfb142c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769175760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2769175760
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.178561064
Short name T123
Test name
Test status
Simulation time 472234179 ps
CPU time 7.64 seconds
Started Aug 16 05:53:27 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 217748 kb
Host smart-42ee4634-e52b-4b36-bb55-5e60c98cdc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178561064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.178561064
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1271431252
Short name T122
Test name
Test status
Simulation time 98366524 ps
CPU time 3.48 seconds
Started Aug 16 05:53:35 PM PDT 24
Finished Aug 16 05:53:39 PM PDT 24
Peak memory 217856 kb
Host smart-bd75badb-1657-4d23-bcd1-346a815e5df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271431252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1271431252
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4159629490
Short name T124
Test name
Test status
Simulation time 99592346 ps
CPU time 4.55 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 223040 kb
Host smart-fa00f41c-8cf4-4428-8131-079a8152ab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159629490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4159629490
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.846347293
Short name T120
Test name
Test status
Simulation time 176768041 ps
CPU time 3.23 seconds
Started Aug 16 05:54:30 PM PDT 24
Finished Aug 16 05:54:33 PM PDT 24
Peak memory 223132 kb
Host smart-3413558a-348c-4aab-b642-7ad412c4e3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846347293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.846347293
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3578267633
Short name T121
Test name
Test status
Simulation time 224410314 ps
CPU time 2.89 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 223128 kb
Host smart-faf1475a-a277-4d8c-919f-eaa89f04c654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578267633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3578267633
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3368954843
Short name T267
Test name
Test status
Simulation time 174484161 ps
CPU time 4.64 seconds
Started Aug 16 05:52:58 PM PDT 24
Finished Aug 16 05:53:03 PM PDT 24
Peak memory 214680 kb
Host smart-d4c564c1-527a-482f-aad4-bedb3cfcb888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368954843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3368954843
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_random.175073091
Short name T349
Test name
Test status
Simulation time 1007798965 ps
CPU time 7.72 seconds
Started Aug 16 05:53:17 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 209960 kb
Host smart-7c679aae-a77a-4fce-b13c-e84af7709603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175073091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.175073091
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2776128421
Short name T213
Test name
Test status
Simulation time 43906134 ps
CPU time 2.88 seconds
Started Aug 16 05:53:43 PM PDT 24
Finished Aug 16 05:53:46 PM PDT 24
Peak memory 214736 kb
Host smart-178504ca-fb00-463e-93ba-7bd66129f6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776128421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2776128421
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.375510795
Short name T365
Test name
Test status
Simulation time 235838266 ps
CPU time 4.62 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:20 PM PDT 24
Peak memory 214796 kb
Host smart-3a32985c-afa4-4734-bb48-9070eecd81d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375510795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.375510795
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4183646690
Short name T98
Test name
Test status
Simulation time 598447362 ps
CPU time 7.96 seconds
Started Aug 16 05:52:29 PM PDT 24
Finished Aug 16 05:52:37 PM PDT 24
Peak memory 214724 kb
Host smart-22bd9536-f9e8-4428-8f6f-809559f78242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183646690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4183646690
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.245332040
Short name T250
Test name
Test status
Simulation time 2159169415 ps
CPU time 41.42 seconds
Started Aug 16 05:53:26 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 217716 kb
Host smart-ec0447c2-3285-4e21-92ed-85f94fab4036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245332040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.245332040
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3781927551
Short name T230
Test name
Test status
Simulation time 124636242 ps
CPU time 2.51 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 220344 kb
Host smart-d94ca944-99d4-495a-bc27-c30a03bc2fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781927551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3781927551
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.248891565
Short name T300
Test name
Test status
Simulation time 123689626 ps
CPU time 4.33 seconds
Started Aug 16 05:54:35 PM PDT 24
Finished Aug 16 05:54:39 PM PDT 24
Peak memory 222848 kb
Host smart-13088a41-a6a7-4b12-8e26-196b91a0e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248891565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.248891565
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.630504051
Short name T257
Test name
Test status
Simulation time 2388693583 ps
CPU time 21.82 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 221532 kb
Host smart-cdd4c66d-c1c6-45d4-99a7-49d2e89235ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630504051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.630504051
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1159979831
Short name T164
Test name
Test status
Simulation time 562061274 ps
CPU time 7.38 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:19 PM PDT 24
Peak memory 206308 kb
Host smart-11d13995-d9ea-4db2-80a6-2da3f45991db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159979831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1159979831
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2538818269
Short name T157
Test name
Test status
Simulation time 207592849 ps
CPU time 5.23 seconds
Started Aug 16 04:53:43 PM PDT 24
Finished Aug 16 04:53:48 PM PDT 24
Peak memory 215588 kb
Host smart-c9057f4b-da2d-49ea-831c-7c24384a3a20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538818269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2538818269
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2511689543
Short name T161
Test name
Test status
Simulation time 123377009 ps
CPU time 4.83 seconds
Started Aug 16 04:53:24 PM PDT 24
Finished Aug 16 04:53:29 PM PDT 24
Peak memory 214516 kb
Host smart-89b3d57c-6e3f-43c3-8251-80c954f1d44a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511689543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2511689543
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.683674410
Short name T165
Test name
Test status
Simulation time 81471913 ps
CPU time 3.06 seconds
Started Aug 16 04:53:16 PM PDT 24
Finished Aug 16 04:53:19 PM PDT 24
Peak memory 213408 kb
Host smart-9a1a64b8-4d61-4bc7-82e9-dee10574d8cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683674410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
683674410
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2500419797
Short name T167
Test name
Test status
Simulation time 89197535 ps
CPU time 2.76 seconds
Started Aug 16 04:53:20 PM PDT 24
Finished Aug 16 04:53:23 PM PDT 24
Peak memory 214592 kb
Host smart-cfd5b33e-b933-4bae-bb88-6d51bdf040d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500419797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2500419797
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.981402375
Short name T159
Test name
Test status
Simulation time 53142659 ps
CPU time 2.57 seconds
Started Aug 16 04:53:18 PM PDT 24
Finished Aug 16 04:53:21 PM PDT 24
Peak memory 214460 kb
Host smart-6e3b525f-fe01-4582-9396-25d346c4b79a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981402375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
981402375
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1413303036
Short name T154
Test name
Test status
Simulation time 91487701 ps
CPU time 2.64 seconds
Started Aug 16 04:53:19 PM PDT 24
Finished Aug 16 04:53:22 PM PDT 24
Peak memory 214480 kb
Host smart-5a0027c0-4ee1-4707-8a44-7a11deaf1276
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413303036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1413303036
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3548818551
Short name T45
Test name
Test status
Simulation time 4006338864 ps
CPU time 17.9 seconds
Started Aug 16 05:53:08 PM PDT 24
Finished Aug 16 05:53:26 PM PDT 24
Peak memory 232392 kb
Host smart-42e30807-cf9c-4ad1-891c-fe5e31539027
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548818551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3548818551
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.277020091
Short name T35
Test name
Test status
Simulation time 162296615 ps
CPU time 4.32 seconds
Started Aug 16 05:52:54 PM PDT 24
Finished Aug 16 05:52:59 PM PDT 24
Peak memory 222528 kb
Host smart-7bd11707-a06f-47f3-a1de-ae197d01bee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277020091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.277020091
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2154862613
Short name T828
Test name
Test status
Simulation time 273373391 ps
CPU time 5.2 seconds
Started Aug 16 05:52:44 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 208584 kb
Host smart-5cb61dd8-228f-4992-9819-80b4245cda5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154862613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2154862613
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1409339430
Short name T608
Test name
Test status
Simulation time 56311224 ps
CPU time 2.75 seconds
Started Aug 16 05:53:03 PM PDT 24
Finished Aug 16 05:53:06 PM PDT 24
Peak memory 208804 kb
Host smart-4ee6cd27-6e78-408c-aefb-6fee6e17629e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409339430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1409339430
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1934878370
Short name T198
Test name
Test status
Simulation time 70912903 ps
CPU time 2.84 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 208644 kb
Host smart-904f802c-31af-49e5-a5e3-33a71048cf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934878370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1934878370
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.961389610
Short name T319
Test name
Test status
Simulation time 4606732682 ps
CPU time 25.57 seconds
Started Aug 16 05:52:55 PM PDT 24
Finished Aug 16 05:53:21 PM PDT 24
Peak memory 222360 kb
Host smart-87ea1382-8f29-41d9-b985-6b51f497104b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961389610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.961389610
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_random.2778170015
Short name T264
Test name
Test status
Simulation time 151349309 ps
CPU time 6.33 seconds
Started Aug 16 05:52:56 PM PDT 24
Finished Aug 16 05:53:02 PM PDT 24
Peak memory 214744 kb
Host smart-8cd36bb6-ce43-4d3d-9d5a-79757c4fb05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778170015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2778170015
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4125544454
Short name T358
Test name
Test status
Simulation time 57556196 ps
CPU time 1.61 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:13 PM PDT 24
Peak memory 210008 kb
Host smart-be13e12d-50ba-4579-a5f2-f55cf3a1c96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125544454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4125544454
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.545121143
Short name T237
Test name
Test status
Simulation time 1219888845 ps
CPU time 14.3 seconds
Started Aug 16 05:53:34 PM PDT 24
Finished Aug 16 05:53:49 PM PDT 24
Peak memory 215044 kb
Host smart-2c131fa7-c9e9-49b3-8741-6d81e33f0f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=545121143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.545121143
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.204658863
Short name T379
Test name
Test status
Simulation time 684661282 ps
CPU time 35.23 seconds
Started Aug 16 05:53:14 PM PDT 24
Finished Aug 16 05:53:50 PM PDT 24
Peak memory 215704 kb
Host smart-43cdb014-6a43-4f86-b68d-867303e3d97d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204658863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.204658863
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.878429140
Short name T56
Test name
Test status
Simulation time 3702974407 ps
CPU time 6.72 seconds
Started Aug 16 05:53:52 PM PDT 24
Finished Aug 16 05:54:04 PM PDT 24
Peak memory 214804 kb
Host smart-2cf3604f-19b6-408d-8c9e-310de0d0da8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878429140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.878429140
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.886489901
Short name T176
Test name
Test status
Simulation time 2624988055 ps
CPU time 50.54 seconds
Started Aug 16 05:53:13 PM PDT 24
Finished Aug 16 05:54:03 PM PDT 24
Peak memory 222976 kb
Host smart-b499b540-525b-44d6-9d39-5f80e99ce891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886489901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.886489901
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2847128023
Short name T775
Test name
Test status
Simulation time 1254143235 ps
CPU time 4.68 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:42 PM PDT 24
Peak memory 210608 kb
Host smart-932eae9b-992a-453e-b197-8c3fa7ae54ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847128023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2847128023
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.988145943
Short name T65
Test name
Test status
Simulation time 112587905 ps
CPU time 3.53 seconds
Started Aug 16 05:53:49 PM PDT 24
Finished Aug 16 05:53:53 PM PDT 24
Peak memory 222876 kb
Host smart-114b81f9-84c2-4a9f-b1c7-bd6671ad6d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988145943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.988145943
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2851755753
Short name T343
Test name
Test status
Simulation time 383970651 ps
CPU time 3.16 seconds
Started Aug 16 05:53:45 PM PDT 24
Finished Aug 16 05:53:48 PM PDT 24
Peak memory 214916 kb
Host smart-a60da826-88f4-4bd6-a596-a025fcbbf995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851755753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2851755753
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3260027096
Short name T96
Test name
Test status
Simulation time 329712600 ps
CPU time 2.57 seconds
Started Aug 16 05:53:24 PM PDT 24
Finished Aug 16 05:53:26 PM PDT 24
Peak memory 215788 kb
Host smart-b2256d52-8812-4601-88d7-d7737e05995c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260027096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3260027096
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1523779339
Short name T311
Test name
Test status
Simulation time 156505793 ps
CPU time 2.97 seconds
Started Aug 16 05:53:51 PM PDT 24
Finished Aug 16 05:53:55 PM PDT 24
Peak memory 215660 kb
Host smart-70381521-da4e-482c-ad67-e4ab9a3d0b02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523779339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1523779339
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3940714092
Short name T15
Test name
Test status
Simulation time 319956499 ps
CPU time 4.04 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:35 PM PDT 24
Peak memory 222916 kb
Host smart-fe7f9c0e-890d-4d49-8a00-190cab154700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940714092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3940714092
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2116417496
Short name T302
Test name
Test status
Simulation time 250430247 ps
CPU time 2.67 seconds
Started Aug 16 05:53:34 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 214776 kb
Host smart-b74b2a65-d718-4a1a-8286-9d644a2a1744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116417496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2116417496
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3916757522
Short name T108
Test name
Test status
Simulation time 36031750 ps
CPU time 2.59 seconds
Started Aug 16 05:54:40 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 214768 kb
Host smart-7d3dcc31-e0de-4e68-9b83-4a3359350147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916757522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3916757522
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2762499293
Short name T186
Test name
Test status
Simulation time 8741264664 ps
CPU time 31.74 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:54 PM PDT 24
Peak memory 215824 kb
Host smart-cd3e3c4f-8e38-425e-9b85-e84ba7cb02b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762499293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2762499293
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3641507852
Short name T1084
Test name
Test status
Simulation time 274910710 ps
CPU time 4.74 seconds
Started Aug 16 04:53:23 PM PDT 24
Finished Aug 16 04:53:28 PM PDT 24
Peak memory 205376 kb
Host smart-2ce9eb14-f494-4830-b304-756bea2c7981
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641507852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
641507852
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1712522372
Short name T920
Test name
Test status
Simulation time 1255644710 ps
CPU time 14.76 seconds
Started Aug 16 04:53:27 PM PDT 24
Finished Aug 16 04:53:42 PM PDT 24
Peak memory 206364 kb
Host smart-748888af-5c88-49d2-ac71-649e2ab02808
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712522372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
712522372
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.129163026
Short name T1011
Test name
Test status
Simulation time 17888079 ps
CPU time 0.93 seconds
Started Aug 16 04:53:05 PM PDT 24
Finished Aug 16 04:53:06 PM PDT 24
Peak memory 206160 kb
Host smart-f1ba6f87-b334-4f2d-a38c-67791241328a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129163026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.129163026
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.263703204
Short name T1062
Test name
Test status
Simulation time 35670703 ps
CPU time 1.71 seconds
Started Aug 16 04:53:10 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 214648 kb
Host smart-aef55578-d84a-44cc-bf33-99f1ee02cf6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263703204 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.263703204
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3697553985
Short name T933
Test name
Test status
Simulation time 47266762 ps
CPU time 1.1 seconds
Started Aug 16 04:53:04 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 206276 kb
Host smart-ff8df9e7-5ed6-4c85-a899-fe362198ac21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697553985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3697553985
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3577703485
Short name T1060
Test name
Test status
Simulation time 40836066 ps
CPU time 0.76 seconds
Started Aug 16 04:53:29 PM PDT 24
Finished Aug 16 04:53:30 PM PDT 24
Peak memory 206028 kb
Host smart-657a015c-4256-4eb3-8fe6-3425bbaf0eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577703485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3577703485
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3231590860
Short name T940
Test name
Test status
Simulation time 136333621 ps
CPU time 2.54 seconds
Started Aug 16 04:53:07 PM PDT 24
Finished Aug 16 04:53:10 PM PDT 24
Peak memory 206376 kb
Host smart-3502df67-a33a-49e9-bbdd-131afefa3aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231590860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3231590860
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2468833962
Short name T1039
Test name
Test status
Simulation time 74734791 ps
CPU time 2 seconds
Started Aug 16 04:53:16 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 214920 kb
Host smart-c01cbd7c-2367-41af-b632-67432f04cc5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468833962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2468833962
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2740999845
Short name T89
Test name
Test status
Simulation time 372901439 ps
CPU time 12.66 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:24 PM PDT 24
Peak memory 214872 kb
Host smart-c1501c98-5d83-47b2-a048-b34919ad6267
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740999845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2740999845
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1020717817
Short name T1087
Test name
Test status
Simulation time 115885730 ps
CPU time 2.55 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 215852 kb
Host smart-6dd83505-7376-4a5e-b36b-69310a64fd3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020717817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1020717817
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3326709046
Short name T1068
Test name
Test status
Simulation time 69049370 ps
CPU time 4.31 seconds
Started Aug 16 04:53:08 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 206332 kb
Host smart-d0cdd7da-b577-40b6-ad57-4e9104fac5c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326709046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
326709046
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3526133510
Short name T1032
Test name
Test status
Simulation time 2952070875 ps
CPU time 15.75 seconds
Started Aug 16 04:53:22 PM PDT 24
Finished Aug 16 04:53:38 PM PDT 24
Peak memory 206316 kb
Host smart-86e91f30-df62-4e46-81da-19681417b640
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526133510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
526133510
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1198009019
Short name T1077
Test name
Test status
Simulation time 29905396 ps
CPU time 1.18 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 206348 kb
Host smart-33f943e1-7e43-4841-af53-8a758280bc89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198009019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
198009019
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.4042791181
Short name T959
Test name
Test status
Simulation time 118178574 ps
CPU time 2.31 seconds
Started Aug 16 04:53:13 PM PDT 24
Finished Aug 16 04:53:15 PM PDT 24
Peak memory 214552 kb
Host smart-fa02ff32-8688-4851-a279-ae373cbb9c51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042791181 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.4042791181
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1851458989
Short name T997
Test name
Test status
Simulation time 13065408 ps
CPU time 0.93 seconds
Started Aug 16 04:53:13 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 206016 kb
Host smart-1e2e2440-2853-434d-a80f-e2a65f115f94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851458989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1851458989
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.382230298
Short name T1064
Test name
Test status
Simulation time 12903630 ps
CPU time 0.74 seconds
Started Aug 16 04:53:13 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 205980 kb
Host smart-c48c3e6c-b955-4b83-be46-3b21334205f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382230298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.382230298
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1486445570
Short name T1086
Test name
Test status
Simulation time 199768680 ps
CPU time 2.27 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:17 PM PDT 24
Peak memory 206296 kb
Host smart-6984326e-5d62-42ca-ba18-3f1f84fb84d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486445570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1486445570
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3166551084
Short name T1034
Test name
Test status
Simulation time 295413796 ps
CPU time 2.7 seconds
Started Aug 16 04:53:14 PM PDT 24
Finished Aug 16 04:53:17 PM PDT 24
Peak memory 219692 kb
Host smart-bfba98fe-e679-4d89-8c84-b35bdd12b765
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166551084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3166551084
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2067695819
Short name T1082
Test name
Test status
Simulation time 220980956 ps
CPU time 7.85 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:23 PM PDT 24
Peak memory 214888 kb
Host smart-7cef1c5b-b546-46fd-a101-94154f790948
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067695819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2067695819
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.115155030
Short name T931
Test name
Test status
Simulation time 68804429 ps
CPU time 2.85 seconds
Started Aug 16 04:53:07 PM PDT 24
Finished Aug 16 04:53:10 PM PDT 24
Peak memory 217052 kb
Host smart-a216517b-5b6b-421a-a797-64fce9ab6e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115155030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.115155030
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1054774170
Short name T926
Test name
Test status
Simulation time 188472647 ps
CPU time 3.2 seconds
Started Aug 16 04:53:38 PM PDT 24
Finished Aug 16 04:53:41 PM PDT 24
Peak memory 214548 kb
Host smart-aa991c51-69bb-44b1-9064-788e8b59e741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054774170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1054774170
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4193158455
Short name T1047
Test name
Test status
Simulation time 22601386 ps
CPU time 1.11 seconds
Started Aug 16 04:53:19 PM PDT 24
Finished Aug 16 04:53:21 PM PDT 24
Peak memory 206144 kb
Host smart-72ebfe87-3461-4888-9004-fc36e7fc2a7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193158455 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.4193158455
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3691596164
Short name T112
Test name
Test status
Simulation time 55952214 ps
CPU time 1.51 seconds
Started Aug 16 04:53:30 PM PDT 24
Finished Aug 16 04:53:32 PM PDT 24
Peak memory 206388 kb
Host smart-4748bb33-d128-41ca-90c4-a4637c0e8736
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691596164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3691596164
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3024903464
Short name T1049
Test name
Test status
Simulation time 11555812 ps
CPU time 0.79 seconds
Started Aug 16 04:53:26 PM PDT 24
Finished Aug 16 04:53:27 PM PDT 24
Peak memory 206080 kb
Host smart-c930b856-f249-4415-8eeb-a36a36d4fd01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024903464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3024903464
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1991274017
Short name T1015
Test name
Test status
Simulation time 179013364 ps
CPU time 2.28 seconds
Started Aug 16 04:53:30 PM PDT 24
Finished Aug 16 04:53:32 PM PDT 24
Peak memory 206396 kb
Host smart-20a575d6-0f32-4c23-ae34-4f899224ef21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991274017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1991274017
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4277635706
Short name T982
Test name
Test status
Simulation time 213560578 ps
CPU time 2.18 seconds
Started Aug 16 04:53:29 PM PDT 24
Finished Aug 16 04:53:32 PM PDT 24
Peak memory 214828 kb
Host smart-84e6491a-988b-4025-9382-d48868804e93
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277635706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4277635706
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.557705548
Short name T1056
Test name
Test status
Simulation time 194086184 ps
CPU time 7.59 seconds
Started Aug 16 04:53:20 PM PDT 24
Finished Aug 16 04:53:27 PM PDT 24
Peak memory 214884 kb
Host smart-1e9ec22f-9868-4cd2-991f-afa5d15a4f7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557705548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.557705548
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3976069733
Short name T943
Test name
Test status
Simulation time 94015257 ps
CPU time 1.57 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 214448 kb
Host smart-987416e6-5486-4a4c-8af4-ebf950cdd404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976069733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3976069733
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3231109821
Short name T166
Test name
Test status
Simulation time 103573376 ps
CPU time 3.45 seconds
Started Aug 16 04:53:16 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 214580 kb
Host smart-49772262-4246-4178-b64b-0ead9a7651f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231109821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3231109821
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1206893644
Short name T949
Test name
Test status
Simulation time 26265687 ps
CPU time 1.97 seconds
Started Aug 16 04:53:36 PM PDT 24
Finished Aug 16 04:53:39 PM PDT 24
Peak memory 214612 kb
Host smart-0c61a245-4749-4982-81c3-d09a7edbd5b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206893644 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1206893644
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.70185634
Short name T1016
Test name
Test status
Simulation time 77354438 ps
CPU time 1.07 seconds
Started Aug 16 04:53:35 PM PDT 24
Finished Aug 16 04:53:36 PM PDT 24
Peak memory 206084 kb
Host smart-fec368d2-cb09-4539-8a79-b8b8c4e6e54a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70185634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.70185634
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3031053647
Short name T942
Test name
Test status
Simulation time 35823368 ps
CPU time 0.72 seconds
Started Aug 16 04:53:32 PM PDT 24
Finished Aug 16 04:53:33 PM PDT 24
Peak memory 206064 kb
Host smart-40acdbeb-983c-40fe-bbd1-8f6cacb89254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031053647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3031053647
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2442782323
Short name T117
Test name
Test status
Simulation time 389378897 ps
CPU time 4.2 seconds
Started Aug 16 04:53:32 PM PDT 24
Finished Aug 16 04:53:37 PM PDT 24
Peak memory 206360 kb
Host smart-208169ce-95dc-4a05-abe6-e882403d6aa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442782323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2442782323
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.989278343
Short name T994
Test name
Test status
Simulation time 646997098 ps
CPU time 5.9 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:24 PM PDT 24
Peak memory 214876 kb
Host smart-ef8f44aa-ca66-4f74-b961-5f3c990b3645
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989278343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.989278343
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1496062112
Short name T1024
Test name
Test status
Simulation time 139108887 ps
CPU time 2.68 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:40 PM PDT 24
Peak memory 217884 kb
Host smart-c9996e4b-6039-4d3c-bd21-8de22242bb51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496062112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1496062112
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2787812098
Short name T936
Test name
Test status
Simulation time 420615225 ps
CPU time 6.23 seconds
Started Aug 16 04:53:34 PM PDT 24
Finished Aug 16 04:53:40 PM PDT 24
Peak memory 214532 kb
Host smart-fa3025b1-b65a-464f-9e5b-5a4734dcc8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787812098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2787812098
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.523524484
Short name T1072
Test name
Test status
Simulation time 24505980 ps
CPU time 1.39 seconds
Started Aug 16 04:53:40 PM PDT 24
Finished Aug 16 04:53:41 PM PDT 24
Peak memory 218048 kb
Host smart-772ecb7b-7e39-45ec-9fae-8868f3815348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523524484 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.523524484
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4073504499
Short name T1043
Test name
Test status
Simulation time 58699334 ps
CPU time 1.26 seconds
Started Aug 16 04:53:26 PM PDT 24
Finished Aug 16 04:53:27 PM PDT 24
Peak memory 206336 kb
Host smart-0a1ee306-fbd1-4c6f-b668-03b315871c35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073504499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4073504499
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4018011720
Short name T948
Test name
Test status
Simulation time 12074573 ps
CPU time 0.72 seconds
Started Aug 16 04:53:43 PM PDT 24
Finished Aug 16 04:53:43 PM PDT 24
Peak memory 206064 kb
Host smart-82a35331-a168-4ce2-a542-a098d7da401f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018011720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4018011720
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2643810864
Short name T1018
Test name
Test status
Simulation time 678452484 ps
CPU time 2.4 seconds
Started Aug 16 04:53:30 PM PDT 24
Finished Aug 16 04:53:33 PM PDT 24
Peak memory 214532 kb
Host smart-c4eb1217-6c3d-43ce-b7e6-41d187220ff8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643810864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2643810864
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4143075636
Short name T82
Test name
Test status
Simulation time 62067743 ps
CPU time 1.6 seconds
Started Aug 16 04:53:33 PM PDT 24
Finished Aug 16 04:53:35 PM PDT 24
Peak memory 214868 kb
Host smart-7caf7bc6-63c2-4bf0-9196-4d0ed4a3cd68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143075636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.4143075636
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2209528336
Short name T87
Test name
Test status
Simulation time 385945009 ps
CPU time 8.88 seconds
Started Aug 16 04:53:26 PM PDT 24
Finished Aug 16 04:53:35 PM PDT 24
Peak memory 214996 kb
Host smart-ae8a20ac-7108-4df4-b031-03e5e9d3ddd2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209528336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2209528336
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3863065127
Short name T986
Test name
Test status
Simulation time 155526388 ps
CPU time 5.51 seconds
Started Aug 16 04:53:40 PM PDT 24
Finished Aug 16 04:53:46 PM PDT 24
Peak memory 214712 kb
Host smart-64a5449b-915f-491a-8568-d56592ee128a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863065127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3863065127
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2170521941
Short name T968
Test name
Test status
Simulation time 111949376 ps
CPU time 4.88 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:42 PM PDT 24
Peak memory 206428 kb
Host smart-b9891d59-bffd-43dc-996f-c5a9a804f349
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170521941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2170521941
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.634434767
Short name T1027
Test name
Test status
Simulation time 116844639 ps
CPU time 1.68 seconds
Started Aug 16 04:53:25 PM PDT 24
Finished Aug 16 04:53:27 PM PDT 24
Peak memory 214604 kb
Host smart-fdb7c18c-a9e6-4d41-81ec-198ffba3809d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634434767 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.634434767
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1810095927
Short name T954
Test name
Test status
Simulation time 18416285 ps
CPU time 0.97 seconds
Started Aug 16 04:53:34 PM PDT 24
Finished Aug 16 04:53:35 PM PDT 24
Peak memory 206080 kb
Host smart-84211df1-9966-4b8e-88f0-156dafadf890
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810095927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1810095927
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1039539507
Short name T935
Test name
Test status
Simulation time 14040600 ps
CPU time 0.72 seconds
Started Aug 16 04:53:36 PM PDT 24
Finished Aug 16 04:53:37 PM PDT 24
Peak memory 206096 kb
Host smart-37f04aed-dd64-4597-b4da-ee823889c31f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039539507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1039539507
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2993759666
Short name T973
Test name
Test status
Simulation time 161965494 ps
CPU time 1.47 seconds
Started Aug 16 04:53:31 PM PDT 24
Finished Aug 16 04:53:32 PM PDT 24
Peak memory 206328 kb
Host smart-fe071ea4-6485-45c1-acf0-2e2fd8f00270
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993759666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2993759666
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2738674376
Short name T1080
Test name
Test status
Simulation time 127132783 ps
CPU time 4.4 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:53 PM PDT 24
Peak memory 214888 kb
Host smart-0bb5b85b-e846-4932-a6a9-abb1d79b08bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738674376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2738674376
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1680705451
Short name T1051
Test name
Test status
Simulation time 185023196 ps
CPU time 3.45 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:51 PM PDT 24
Peak memory 214568 kb
Host smart-abe53a67-a16b-4d77-ad2e-c1330a716e65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680705451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1680705451
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3410805769
Short name T1012
Test name
Test status
Simulation time 114079169 ps
CPU time 1.18 seconds
Started Aug 16 04:53:27 PM PDT 24
Finished Aug 16 04:53:28 PM PDT 24
Peak memory 214704 kb
Host smart-bcf5a595-1ea4-4e06-a8c6-182f4a6c7792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410805769 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3410805769
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3820101492
Short name T1078
Test name
Test status
Simulation time 15655080 ps
CPU time 1.3 seconds
Started Aug 16 04:53:36 PM PDT 24
Finished Aug 16 04:53:37 PM PDT 24
Peak memory 206288 kb
Host smart-9ac458b0-7ae1-4016-a790-d7452d2adbea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820101492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3820101492
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2759899273
Short name T1070
Test name
Test status
Simulation time 14204737 ps
CPU time 0.86 seconds
Started Aug 16 04:53:26 PM PDT 24
Finished Aug 16 04:53:27 PM PDT 24
Peak memory 205944 kb
Host smart-402d0934-c23e-4c51-ad55-a6b93a00a898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759899273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2759899273
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.165170449
Short name T1019
Test name
Test status
Simulation time 189494116 ps
CPU time 2.28 seconds
Started Aug 16 04:53:40 PM PDT 24
Finished Aug 16 04:53:42 PM PDT 24
Peak memory 206408 kb
Host smart-01773b8a-6546-4859-8fee-3b165ce9db8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165170449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.165170449
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2730231109
Short name T85
Test name
Test status
Simulation time 246667102 ps
CPU time 2.44 seconds
Started Aug 16 04:53:31 PM PDT 24
Finished Aug 16 04:53:34 PM PDT 24
Peak memory 214860 kb
Host smart-0aba42a4-342e-4270-84cc-167ff95f7c67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730231109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2730231109
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3516789030
Short name T1002
Test name
Test status
Simulation time 484283661 ps
CPU time 4.32 seconds
Started Aug 16 04:53:26 PM PDT 24
Finished Aug 16 04:53:30 PM PDT 24
Peak memory 214824 kb
Host smart-153bfee8-ec62-4922-bdaa-360af021ea3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516789030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3516789030
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1841592049
Short name T988
Test name
Test status
Simulation time 44256502 ps
CPU time 3.16 seconds
Started Aug 16 04:53:31 PM PDT 24
Finished Aug 16 04:53:34 PM PDT 24
Peak memory 216740 kb
Host smart-2b7ed9f7-9764-4af2-91c1-a01f8b313007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841592049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1841592049
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.4239666028
Short name T163
Test name
Test status
Simulation time 492246850 ps
CPU time 3.82 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:52 PM PDT 24
Peak memory 214532 kb
Host smart-4802e531-763d-4313-a17a-a7a52b07fc8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239666028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.4239666028
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.6181445
Short name T956
Test name
Test status
Simulation time 18892630 ps
CPU time 1.26 seconds
Started Aug 16 04:53:31 PM PDT 24
Finished Aug 16 04:53:32 PM PDT 24
Peak memory 206348 kb
Host smart-230ed58e-5fb9-4112-b331-1030952d669e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6181445 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.6181445
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1226709093
Short name T930
Test name
Test status
Simulation time 31183813 ps
CPU time 1.33 seconds
Started Aug 16 04:53:47 PM PDT 24
Finished Aug 16 04:53:48 PM PDT 24
Peak memory 206444 kb
Host smart-1a462907-1dab-4a39-8e75-45b8a1edd6d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226709093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1226709093
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2916837831
Short name T950
Test name
Test status
Simulation time 13290844 ps
CPU time 0.77 seconds
Started Aug 16 04:53:25 PM PDT 24
Finished Aug 16 04:53:25 PM PDT 24
Peak memory 206044 kb
Host smart-69819360-d563-42e8-9219-e6cf0cf99c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916837831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2916837831
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3708931465
Short name T1089
Test name
Test status
Simulation time 86920263 ps
CPU time 2.32 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:39 PM PDT 24
Peak memory 206360 kb
Host smart-f23b314a-b1fd-40e8-91e6-5c82d150ed09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708931465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3708931465
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1730213169
Short name T1044
Test name
Test status
Simulation time 303935972 ps
CPU time 2.7 seconds
Started Aug 16 04:53:31 PM PDT 24
Finished Aug 16 04:53:34 PM PDT 24
Peak memory 214960 kb
Host smart-8e9b9bed-f2d1-4ea1-a59a-b52fffb66c02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730213169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1730213169
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3290958601
Short name T1003
Test name
Test status
Simulation time 230814322 ps
CPU time 5.59 seconds
Started Aug 16 04:53:44 PM PDT 24
Finished Aug 16 04:53:49 PM PDT 24
Peak memory 214788 kb
Host smart-64992512-1b69-48be-b4ee-ec21906ad43e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290958601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3290958601
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4283052178
Short name T978
Test name
Test status
Simulation time 67444938 ps
CPU time 2.95 seconds
Started Aug 16 04:53:36 PM PDT 24
Finished Aug 16 04:53:39 PM PDT 24
Peak memory 214500 kb
Host smart-5440bc2e-a1ae-4780-8043-b11f1ce2a70a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283052178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4283052178
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3388190459
Short name T155
Test name
Test status
Simulation time 148080420 ps
CPU time 3.33 seconds
Started Aug 16 04:53:27 PM PDT 24
Finished Aug 16 04:53:30 PM PDT 24
Peak memory 214520 kb
Host smart-e18630d1-70e7-47eb-b7e7-9583daff556d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388190459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3388190459
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2480486813
Short name T955
Test name
Test status
Simulation time 52855320 ps
CPU time 1.5 seconds
Started Aug 16 04:53:38 PM PDT 24
Finished Aug 16 04:53:45 PM PDT 24
Peak memory 206380 kb
Host smart-18b48139-12f0-4d18-b927-460c982b08e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480486813 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2480486813
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1358760671
Short name T952
Test name
Test status
Simulation time 66211753 ps
CPU time 1.16 seconds
Started Aug 16 04:53:34 PM PDT 24
Finished Aug 16 04:53:36 PM PDT 24
Peak memory 206400 kb
Host smart-755a4b86-864c-4536-adda-9b3062c0a435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358760671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1358760671
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3409081761
Short name T918
Test name
Test status
Simulation time 19326771 ps
CPU time 0.76 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:37 PM PDT 24
Peak memory 206092 kb
Host smart-9423da8a-4b1c-4081-8b4c-75a856cc4dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409081761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3409081761
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2841023754
Short name T995
Test name
Test status
Simulation time 82164766 ps
CPU time 3.26 seconds
Started Aug 16 04:53:41 PM PDT 24
Finished Aug 16 04:53:45 PM PDT 24
Peak memory 206312 kb
Host smart-321a49d5-98c6-4727-9d01-814b272d4683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841023754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2841023754
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2613922555
Short name T989
Test name
Test status
Simulation time 197085372 ps
CPU time 3.98 seconds
Started Aug 16 04:53:47 PM PDT 24
Finished Aug 16 04:53:51 PM PDT 24
Peak memory 214948 kb
Host smart-e18d9dd8-d5a5-46bf-9e62-4787c68daa47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613922555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2613922555
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3806704947
Short name T953
Test name
Test status
Simulation time 1315884182 ps
CPU time 8.31 seconds
Started Aug 16 04:53:26 PM PDT 24
Finished Aug 16 04:53:35 PM PDT 24
Peak memory 221000 kb
Host smart-7d2a68c0-5dc8-4463-930d-7941efe0749e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806704947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3806704947
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3778683711
Short name T917
Test name
Test status
Simulation time 42346521 ps
CPU time 3.19 seconds
Started Aug 16 04:53:35 PM PDT 24
Finished Aug 16 04:53:38 PM PDT 24
Peak memory 214624 kb
Host smart-4743be64-72d3-49ac-b387-487d50c98077
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778683711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3778683711
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.899529345
Short name T1081
Test name
Test status
Simulation time 107331021 ps
CPU time 2.21 seconds
Started Aug 16 04:53:31 PM PDT 24
Finished Aug 16 04:53:34 PM PDT 24
Peak memory 214532 kb
Host smart-11b1c8b3-18fd-43d8-83f3-bdae692b3a1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899529345 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.899529345
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1381034316
Short name T113
Test name
Test status
Simulation time 72502176 ps
CPU time 1.18 seconds
Started Aug 16 04:53:42 PM PDT 24
Finished Aug 16 04:53:43 PM PDT 24
Peak memory 206360 kb
Host smart-e40c1201-c49c-4492-9e43-1a2c7fd99bd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381034316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1381034316
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3462369351
Short name T1053
Test name
Test status
Simulation time 13480936 ps
CPU time 0.78 seconds
Started Aug 16 04:53:36 PM PDT 24
Finished Aug 16 04:53:37 PM PDT 24
Peak memory 206068 kb
Host smart-a8c5f2d4-cb92-4e1b-bcde-f98e6e2471ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462369351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3462369351
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.308725315
Short name T1069
Test name
Test status
Simulation time 36504242 ps
CPU time 2.14 seconds
Started Aug 16 04:53:45 PM PDT 24
Finished Aug 16 04:53:47 PM PDT 24
Peak memory 214488 kb
Host smart-0f4d313f-d067-426e-a7e3-d90594abde19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308725315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.308725315
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1086101049
Short name T975
Test name
Test status
Simulation time 2205112891 ps
CPU time 3.14 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:40 PM PDT 24
Peak memory 215008 kb
Host smart-7fe7b460-e5e6-4db1-a61f-290878310b77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086101049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1086101049
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1401804222
Short name T944
Test name
Test status
Simulation time 1065579988 ps
CPU time 5.44 seconds
Started Aug 16 04:53:26 PM PDT 24
Finished Aug 16 04:53:31 PM PDT 24
Peak memory 214880 kb
Host smart-78550460-af71-4e41-a444-040c58b19907
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401804222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1401804222
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2738049723
Short name T1075
Test name
Test status
Simulation time 86639299 ps
CPU time 2.09 seconds
Started Aug 16 04:53:41 PM PDT 24
Finished Aug 16 04:53:43 PM PDT 24
Peak memory 215684 kb
Host smart-5b743750-74a0-42ec-872b-82b4e7d2b7e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738049723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2738049723
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2476496167
Short name T1023
Test name
Test status
Simulation time 154691026 ps
CPU time 2.32 seconds
Started Aug 16 04:53:39 PM PDT 24
Finished Aug 16 04:53:42 PM PDT 24
Peak memory 214608 kb
Host smart-3d6a954c-d147-42e8-ac6d-99f8bb4d369c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476496167 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2476496167
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.4207573169
Short name T1009
Test name
Test status
Simulation time 27301815 ps
CPU time 0.91 seconds
Started Aug 16 04:53:38 PM PDT 24
Finished Aug 16 04:53:39 PM PDT 24
Peak memory 206084 kb
Host smart-4a53babd-3138-4fa0-91a3-7b083c89a097
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207573169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.4207573169
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1786216681
Short name T1028
Test name
Test status
Simulation time 47202549 ps
CPU time 0.85 seconds
Started Aug 16 04:53:26 PM PDT 24
Finished Aug 16 04:53:27 PM PDT 24
Peak memory 206040 kb
Host smart-4941e0ed-c7f1-46e3-8546-f2ed688b5f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786216681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1786216681
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2314270470
Short name T1057
Test name
Test status
Simulation time 341724025 ps
CPU time 2.11 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:50 PM PDT 24
Peak memory 206324 kb
Host smart-435c2287-ac3b-4ae2-9be0-398cd24c295e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314270470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2314270470
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1649683627
Short name T1073
Test name
Test status
Simulation time 133914090 ps
CPU time 1.95 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:40 PM PDT 24
Peak memory 214936 kb
Host smart-72c5426f-01b8-4b42-b67e-f61397e5a25d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649683627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1649683627
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3225539264
Short name T80
Test name
Test status
Simulation time 318989051 ps
CPU time 8.44 seconds
Started Aug 16 04:53:27 PM PDT 24
Finished Aug 16 04:53:35 PM PDT 24
Peak memory 214728 kb
Host smart-c10ea384-3565-4fd4-a411-3a9b47e0cdcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225539264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3225539264
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1791563202
Short name T972
Test name
Test status
Simulation time 191679986 ps
CPU time 2.76 seconds
Started Aug 16 04:53:33 PM PDT 24
Finished Aug 16 04:53:36 PM PDT 24
Peak memory 214612 kb
Host smart-3fa017d1-8e8c-4f09-a4a8-fa7c9ab17e12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791563202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1791563202
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2441858967
Short name T158
Test name
Test status
Simulation time 272436574 ps
CPU time 5.67 seconds
Started Aug 16 04:53:25 PM PDT 24
Finished Aug 16 04:53:31 PM PDT 24
Peak memory 214620 kb
Host smart-354521b0-54da-4f48-97a6-55b7e346ce0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441858967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2441858967
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.577922020
Short name T1045
Test name
Test status
Simulation time 25564005 ps
CPU time 1.42 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:49 PM PDT 24
Peak memory 206452 kb
Host smart-b077cc38-6ccc-48fc-ac6f-655ac81f3afd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577922020 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.577922020
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2147227969
Short name T1005
Test name
Test status
Simulation time 17791237 ps
CPU time 1.3 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:38 PM PDT 24
Peak memory 206336 kb
Host smart-f13a7406-18ee-4d85-8010-7bf925e6b3b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147227969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2147227969
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.897105105
Short name T981
Test name
Test status
Simulation time 12276440 ps
CPU time 0.85 seconds
Started Aug 16 04:53:38 PM PDT 24
Finished Aug 16 04:53:39 PM PDT 24
Peak memory 206012 kb
Host smart-7c63c3cb-4edb-4a08-a601-cb415511c49e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897105105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.897105105
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4103084062
Short name T970
Test name
Test status
Simulation time 41375256 ps
CPU time 1.66 seconds
Started Aug 16 04:53:44 PM PDT 24
Finished Aug 16 04:53:46 PM PDT 24
Peak memory 206236 kb
Host smart-fd99718a-3641-4dfd-9607-7d11f0840048
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103084062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.4103084062
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.97449006
Short name T960
Test name
Test status
Simulation time 601254813 ps
CPU time 1.67 seconds
Started Aug 16 04:53:38 PM PDT 24
Finished Aug 16 04:53:39 PM PDT 24
Peak memory 214876 kb
Host smart-02968a2c-643f-48a6-bf73-0f59f7b6d20f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97449006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow
_reg_errors.97449006
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1136528605
Short name T1008
Test name
Test status
Simulation time 223412572 ps
CPU time 5.87 seconds
Started Aug 16 04:53:46 PM PDT 24
Finished Aug 16 04:53:52 PM PDT 24
Peak memory 214792 kb
Host smart-06ddb1f5-d6cd-4714-8353-422a78dbf488
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136528605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1136528605
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.496726243
Short name T945
Test name
Test status
Simulation time 99201630 ps
CPU time 2.51 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:53:59 PM PDT 24
Peak memory 214596 kb
Host smart-33be8078-bfec-48b5-b892-a22fe84b7448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496726243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.496726243
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1230822210
Short name T963
Test name
Test status
Simulation time 152314484 ps
CPU time 5.34 seconds
Started Aug 16 04:53:38 PM PDT 24
Finished Aug 16 04:53:43 PM PDT 24
Peak memory 214520 kb
Host smart-73714ca6-86e8-4d0b-8206-ef77eef6d499
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230822210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1230822210
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3231832051
Short name T1029
Test name
Test status
Simulation time 274971324 ps
CPU time 4.55 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 206280 kb
Host smart-df650469-8c34-42fe-a61a-0f4f7949d263
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231832051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
231832051
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2589411096
Short name T939
Test name
Test status
Simulation time 881179231 ps
CPU time 25.98 seconds
Started Aug 16 04:53:13 PM PDT 24
Finished Aug 16 04:53:39 PM PDT 24
Peak memory 206252 kb
Host smart-36f3c569-bfe0-41ec-80ac-659d3e1b939e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589411096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
589411096
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1231205472
Short name T1004
Test name
Test status
Simulation time 30544498 ps
CPU time 0.96 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:16 PM PDT 24
Peak memory 206116 kb
Host smart-becdc5f0-38e0-44e6-9e99-a65b08704d3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231205472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
231205472
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3958734341
Short name T996
Test name
Test status
Simulation time 22773742 ps
CPU time 1.6 seconds
Started Aug 16 04:53:16 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 222756 kb
Host smart-d9b1a769-2da4-4935-80ec-2b6de8fc0d07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958734341 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3958734341
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2146662978
Short name T1033
Test name
Test status
Simulation time 26001989 ps
CPU time 1.1 seconds
Started Aug 16 04:53:12 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 206396 kb
Host smart-a2247e73-96b8-469c-8ac5-b7b807639c35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146662978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2146662978
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1342380839
Short name T1035
Test name
Test status
Simulation time 14147331 ps
CPU time 0.72 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 206096 kb
Host smart-1935dbee-57d2-48e0-832e-92aeab73a9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342380839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1342380839
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2891201801
Short name T934
Test name
Test status
Simulation time 382225760 ps
CPU time 2.86 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 206336 kb
Host smart-577c27cb-e0aa-4dec-834a-5347ce184fe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891201801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2891201801
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.22389795
Short name T1007
Test name
Test status
Simulation time 156574700 ps
CPU time 2.48 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 214876 kb
Host smart-2109d74e-d679-4183-8816-110be2c3241a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22389795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_
reg_errors.22389795
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4058518178
Short name T1010
Test name
Test status
Simulation time 149194605 ps
CPU time 4.49 seconds
Started Aug 16 04:53:24 PM PDT 24
Finished Aug 16 04:53:29 PM PDT 24
Peak memory 214904 kb
Host smart-dd338a22-e8d6-4a7d-b924-89c1c9cf188d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058518178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4058518178
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1218263453
Short name T1037
Test name
Test status
Simulation time 29579687 ps
CPU time 2.04 seconds
Started Aug 16 04:53:14 PM PDT 24
Finished Aug 16 04:53:16 PM PDT 24
Peak memory 214568 kb
Host smart-407aec0f-5bf1-4dc0-af5b-46df758aa872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218263453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1218263453
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1064678343
Short name T1048
Test name
Test status
Simulation time 18110507 ps
CPU time 0.75 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:49 PM PDT 24
Peak memory 206096 kb
Host smart-ac29c0f1-2f7a-4fe8-b3c2-0a618dcea198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064678343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1064678343
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3857697721
Short name T922
Test name
Test status
Simulation time 30407524 ps
CPU time 0.74 seconds
Started Aug 16 04:53:33 PM PDT 24
Finished Aug 16 04:53:34 PM PDT 24
Peak memory 206104 kb
Host smart-81c4c747-c517-4920-92a1-144eb12640df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857697721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3857697721
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.136639766
Short name T1001
Test name
Test status
Simulation time 11915054 ps
CPU time 0.86 seconds
Started Aug 16 04:53:47 PM PDT 24
Finished Aug 16 04:53:48 PM PDT 24
Peak memory 206024 kb
Host smart-15c92a6d-4aab-4dc3-ace6-e52634a9ff56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136639766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.136639766
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.783574096
Short name T951
Test name
Test status
Simulation time 34293852 ps
CPU time 0.71 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:49 PM PDT 24
Peak memory 206128 kb
Host smart-cf62a3ee-b913-4432-9d8e-45999cc8e3cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783574096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.783574096
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.319313827
Short name T985
Test name
Test status
Simulation time 13833370 ps
CPU time 0.87 seconds
Started Aug 16 04:53:36 PM PDT 24
Finished Aug 16 04:53:37 PM PDT 24
Peak memory 206252 kb
Host smart-8701bc9d-6662-4af3-9705-8c446c9708e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319313827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.319313827
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4211836220
Short name T992
Test name
Test status
Simulation time 14042487 ps
CPU time 0.79 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:38 PM PDT 24
Peak memory 206160 kb
Host smart-6e067e73-0173-461e-9c10-20c5cf628e2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211836220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4211836220
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1542946872
Short name T1026
Test name
Test status
Simulation time 15844148 ps
CPU time 0.72 seconds
Started Aug 16 04:53:39 PM PDT 24
Finished Aug 16 04:53:40 PM PDT 24
Peak memory 206128 kb
Host smart-687dbfc9-c863-46a4-b249-a257fd6ecfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542946872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1542946872
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3550994741
Short name T1042
Test name
Test status
Simulation time 36724157 ps
CPU time 0.74 seconds
Started Aug 16 04:53:43 PM PDT 24
Finished Aug 16 04:53:43 PM PDT 24
Peak memory 206040 kb
Host smart-218b34f7-8f88-41b2-b846-6231f2dceb21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550994741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3550994741
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2322008225
Short name T1020
Test name
Test status
Simulation time 14384704 ps
CPU time 0.74 seconds
Started Aug 16 04:53:41 PM PDT 24
Finished Aug 16 04:53:41 PM PDT 24
Peak memory 205944 kb
Host smart-fefd40d9-085f-40e7-8609-54f0f9ae87a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322008225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2322008225
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1725547451
Short name T925
Test name
Test status
Simulation time 164205268 ps
CPU time 0.74 seconds
Started Aug 16 04:53:38 PM PDT 24
Finished Aug 16 04:53:39 PM PDT 24
Peak memory 206032 kb
Host smart-9e5d4a3f-b4cc-4689-9812-33ebb39ad21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725547451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1725547451
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1223337255
Short name T967
Test name
Test status
Simulation time 465118984 ps
CPU time 12.92 seconds
Started Aug 16 04:53:14 PM PDT 24
Finished Aug 16 04:53:27 PM PDT 24
Peak memory 206304 kb
Host smart-70096868-82b8-402f-aa00-fa5b6a9cbdbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223337255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
223337255
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1680736191
Short name T1050
Test name
Test status
Simulation time 927859800 ps
CPU time 13.14 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:31 PM PDT 24
Peak memory 206264 kb
Host smart-ae7455ee-b485-4585-bc6e-c9318af016fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680736191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
680736191
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2762575780
Short name T1055
Test name
Test status
Simulation time 43929794 ps
CPU time 0.88 seconds
Started Aug 16 04:53:16 PM PDT 24
Finished Aug 16 04:53:17 PM PDT 24
Peak memory 206140 kb
Host smart-ef9108c8-cb45-4410-a801-f29a8efc5815
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762575780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
762575780
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2949235249
Short name T958
Test name
Test status
Simulation time 66694841 ps
CPU time 1.25 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 214540 kb
Host smart-8cd31d41-aa51-4d0f-96a8-7e71f595be46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949235249 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2949235249
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1879978055
Short name T1013
Test name
Test status
Simulation time 164329276 ps
CPU time 1.26 seconds
Started Aug 16 04:53:14 PM PDT 24
Finished Aug 16 04:53:15 PM PDT 24
Peak memory 206300 kb
Host smart-a653c6c5-cdd4-42c8-9abe-9a82e11c7b2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879978055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1879978055
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1818967832
Short name T1061
Test name
Test status
Simulation time 38100073 ps
CPU time 0.71 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 206068 kb
Host smart-6955560e-7f12-4f72-9c20-ed8f0cba5c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818967832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1818967832
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1906292461
Short name T932
Test name
Test status
Simulation time 123480636 ps
CPU time 1.92 seconds
Started Aug 16 04:53:12 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 206324 kb
Host smart-f7c4a84c-73f7-440e-b17c-191e4054487e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906292461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1906292461
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2000040067
Short name T1041
Test name
Test status
Simulation time 722787542 ps
CPU time 2.31 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:13 PM PDT 24
Peak memory 214932 kb
Host smart-d61cb732-006e-4a95-8acd-9df9d35ab9e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000040067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2000040067
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4285611165
Short name T974
Test name
Test status
Simulation time 259836978 ps
CPU time 3.77 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:15 PM PDT 24
Peak memory 217012 kb
Host smart-ae74c026-051e-460e-94da-1feb1d50b738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285611165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4285611165
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.54142129
Short name T962
Test name
Test status
Simulation time 107539960 ps
CPU time 2.65 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 215652 kb
Host smart-348b866f-43a6-42a7-a8e4-6530159c9a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54142129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.54142129
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1630505276
Short name T1074
Test name
Test status
Simulation time 18556531 ps
CPU time 0.71 seconds
Started Aug 16 04:53:39 PM PDT 24
Finished Aug 16 04:53:40 PM PDT 24
Peak memory 206032 kb
Host smart-073b2275-811b-4d1e-b2ca-33ddfc9c195c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630505276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1630505276
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4255579924
Short name T919
Test name
Test status
Simulation time 25036502 ps
CPU time 0.8 seconds
Started Aug 16 04:53:41 PM PDT 24
Finished Aug 16 04:53:42 PM PDT 24
Peak memory 206104 kb
Host smart-55134ac2-c601-4953-8332-a0f98f126ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255579924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.4255579924
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.477363815
Short name T1085
Test name
Test status
Simulation time 9895320 ps
CPU time 0.82 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:49 PM PDT 24
Peak memory 206108 kb
Host smart-00ac6dad-99ce-403d-98d8-85282e359f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477363815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.477363815
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2463452952
Short name T991
Test name
Test status
Simulation time 64227071 ps
CPU time 0.73 seconds
Started Aug 16 04:53:50 PM PDT 24
Finished Aug 16 04:53:51 PM PDT 24
Peak memory 206020 kb
Host smart-294ef2c0-0bb3-46af-9876-f10898dc56d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463452952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2463452952
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2399835238
Short name T1058
Test name
Test status
Simulation time 19261737 ps
CPU time 0.76 seconds
Started Aug 16 04:53:44 PM PDT 24
Finished Aug 16 04:53:45 PM PDT 24
Peak memory 206036 kb
Host smart-a987b403-10a7-451c-a686-8eb40ce588d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399835238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2399835238
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.509780562
Short name T1022
Test name
Test status
Simulation time 34999446 ps
CPU time 0.74 seconds
Started Aug 16 04:53:47 PM PDT 24
Finished Aug 16 04:53:48 PM PDT 24
Peak memory 206100 kb
Host smart-51380481-4336-4b5b-9e54-de423d259d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509780562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.509780562
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4167368567
Short name T979
Test name
Test status
Simulation time 18770697 ps
CPU time 0.85 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:38 PM PDT 24
Peak memory 206116 kb
Host smart-d373a320-9e09-45dd-b8d4-3b85ffdce076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167368567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4167368567
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3901982321
Short name T923
Test name
Test status
Simulation time 11000386 ps
CPU time 0.84 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:53:53 PM PDT 24
Peak memory 206016 kb
Host smart-4fb102d9-9a2f-4733-8aaa-275d1ed7adde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901982321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3901982321
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1330947729
Short name T1017
Test name
Test status
Simulation time 12239932 ps
CPU time 0.73 seconds
Started Aug 16 04:53:53 PM PDT 24
Finished Aug 16 04:53:54 PM PDT 24
Peak memory 206016 kb
Host smart-e1a3c9ce-58cf-4079-a50a-e9c8528a51aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330947729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1330947729
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3965450686
Short name T928
Test name
Test status
Simulation time 11649468 ps
CPU time 0.86 seconds
Started Aug 16 04:53:49 PM PDT 24
Finished Aug 16 04:53:50 PM PDT 24
Peak memory 206100 kb
Host smart-d63acc0a-30bc-4b37-8e1a-db512864a6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965450686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3965450686
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.961811538
Short name T1083
Test name
Test status
Simulation time 259314095 ps
CPU time 7.32 seconds
Started Aug 16 04:53:47 PM PDT 24
Finished Aug 16 04:53:55 PM PDT 24
Peak memory 206320 kb
Host smart-4d2968a7-eb76-42d7-8f22-a2dd8ba66b58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961811538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.961811538
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.558246410
Short name T947
Test name
Test status
Simulation time 260505297 ps
CPU time 11.97 seconds
Started Aug 16 04:53:20 PM PDT 24
Finished Aug 16 04:53:32 PM PDT 24
Peak memory 206292 kb
Host smart-c08e7578-9468-4e7f-b9aa-87b529efab78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558246410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.558246410
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2833150154
Short name T1059
Test name
Test status
Simulation time 38309596 ps
CPU time 0.95 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:16 PM PDT 24
Peak memory 206076 kb
Host smart-202fdb9b-e039-4998-be55-60c49403c298
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833150154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
833150154
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2499617951
Short name T1014
Test name
Test status
Simulation time 51080047 ps
CPU time 2.21 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 217416 kb
Host smart-0f64d447-4ff3-495b-aa5d-0f37c89bd43d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499617951 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2499617951
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2080895711
Short name T1021
Test name
Test status
Simulation time 44921457 ps
CPU time 0.92 seconds
Started Aug 16 04:53:13 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 206120 kb
Host smart-1050444d-8187-4843-bca9-a6f973d5084a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080895711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2080895711
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.32587304
Short name T961
Test name
Test status
Simulation time 16420323 ps
CPU time 0.71 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 206132 kb
Host smart-bc35ac54-7229-4687-bbf5-39560edde280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32587304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.32587304
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3608134118
Short name T1036
Test name
Test status
Simulation time 41923454 ps
CPU time 1.73 seconds
Started Aug 16 04:53:24 PM PDT 24
Finished Aug 16 04:53:26 PM PDT 24
Peak memory 206368 kb
Host smart-2d1b6d23-601f-4ffe-90bc-a04fdc8767e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608134118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3608134118
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1419642890
Short name T946
Test name
Test status
Simulation time 115006181 ps
CPU time 1.39 seconds
Started Aug 16 04:53:16 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 214988 kb
Host smart-88ed2101-fafd-4dae-9fa2-8ad7eb10a8c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419642890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1419642890
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3385999491
Short name T937
Test name
Test status
Simulation time 1341391501 ps
CPU time 8.76 seconds
Started Aug 16 04:53:20 PM PDT 24
Finished Aug 16 04:53:29 PM PDT 24
Peak memory 214968 kb
Host smart-48c8796e-2223-42b6-a71f-747e5a84daca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385999491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3385999491
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1623009188
Short name T964
Test name
Test status
Simulation time 30883762 ps
CPU time 2.26 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 214524 kb
Host smart-2d8d84f1-aebc-46dc-ac8e-b6672db93385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623009188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1623009188
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3366182936
Short name T998
Test name
Test status
Simulation time 210440471 ps
CPU time 4.8 seconds
Started Aug 16 04:53:30 PM PDT 24
Finished Aug 16 04:53:35 PM PDT 24
Peak memory 214440 kb
Host smart-fbc75b07-646c-4b15-92f5-d96a2f40baa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366182936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3366182936
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.624461169
Short name T921
Test name
Test status
Simulation time 15359635 ps
CPU time 0.89 seconds
Started Aug 16 04:53:37 PM PDT 24
Finished Aug 16 04:53:38 PM PDT 24
Peak memory 206100 kb
Host smart-91795040-f121-4625-bee5-ce9966e24987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624461169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.624461169
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.784876590
Short name T927
Test name
Test status
Simulation time 47856859 ps
CPU time 0.78 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:49 PM PDT 24
Peak memory 206088 kb
Host smart-e243c0ef-ced9-414a-b371-569011c3d125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784876590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.784876590
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4137797377
Short name T1071
Test name
Test status
Simulation time 11013243 ps
CPU time 0.87 seconds
Started Aug 16 04:53:47 PM PDT 24
Finished Aug 16 04:53:48 PM PDT 24
Peak memory 205968 kb
Host smart-c610e890-536e-4623-b316-d9552b9e0aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137797377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4137797377
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3850478829
Short name T999
Test name
Test status
Simulation time 15045568 ps
CPU time 0.74 seconds
Started Aug 16 04:53:46 PM PDT 24
Finished Aug 16 04:53:47 PM PDT 24
Peak memory 206144 kb
Host smart-1921126f-f118-4306-9b97-59c5bbf78cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850478829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3850478829
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2923095105
Short name T1054
Test name
Test status
Simulation time 91849433 ps
CPU time 0.71 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:49 PM PDT 24
Peak memory 206100 kb
Host smart-c9586da2-ea75-4fad-8a21-f676a023c00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923095105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2923095105
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2449315484
Short name T1030
Test name
Test status
Simulation time 11562569 ps
CPU time 0.84 seconds
Started Aug 16 04:53:53 PM PDT 24
Finished Aug 16 04:53:54 PM PDT 24
Peak memory 206016 kb
Host smart-ad00279e-9382-4f98-a371-956e7cfbf4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449315484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2449315484
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2710000644
Short name T1031
Test name
Test status
Simulation time 15083626 ps
CPU time 0.81 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:53:58 PM PDT 24
Peak memory 206128 kb
Host smart-db503de9-123b-4223-9531-de6675e145cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710000644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2710000644
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.269380469
Short name T965
Test name
Test status
Simulation time 53754154 ps
CPU time 0.72 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:53:59 PM PDT 24
Peak memory 206092 kb
Host smart-f3180d40-4936-4476-9f5f-d3c4de1c11fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269380469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.269380469
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2336851633
Short name T1088
Test name
Test status
Simulation time 22951769 ps
CPU time 0.78 seconds
Started Aug 16 04:53:50 PM PDT 24
Finished Aug 16 04:53:51 PM PDT 24
Peak memory 206100 kb
Host smart-d67d1001-252f-47d3-8094-c0ecab5177e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336851633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2336851633
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1979945242
Short name T1040
Test name
Test status
Simulation time 40379550 ps
CPU time 0.75 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:53:53 PM PDT 24
Peak memory 206120 kb
Host smart-2ed77aaa-fcc4-4255-8641-db396c48b24a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979945242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1979945242
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3414307886
Short name T987
Test name
Test status
Simulation time 52578467 ps
CPU time 1.56 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:13 PM PDT 24
Peak memory 214636 kb
Host smart-69a76301-7f47-48fd-8603-27a19b184bb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414307886 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3414307886
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2365945022
Short name T115
Test name
Test status
Simulation time 69751329 ps
CPU time 0.83 seconds
Started Aug 16 04:53:22 PM PDT 24
Finished Aug 16 04:53:23 PM PDT 24
Peak memory 206168 kb
Host smart-e20b7652-9777-4b3d-a9ee-29dae1f8c161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365945022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2365945022
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2320909117
Short name T916
Test name
Test status
Simulation time 19808876 ps
CPU time 0.81 seconds
Started Aug 16 04:53:20 PM PDT 24
Finished Aug 16 04:53:21 PM PDT 24
Peak memory 206096 kb
Host smart-22b17b5c-96cb-43e5-9c02-e67bdb4fb319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320909117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2320909117
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3689917976
Short name T114
Test name
Test status
Simulation time 36308253 ps
CPU time 2.11 seconds
Started Aug 16 04:53:16 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 206348 kb
Host smart-577a6a92-dab3-4025-8330-73998df39e43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689917976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3689917976
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.122996531
Short name T976
Test name
Test status
Simulation time 137934387 ps
CPU time 4.12 seconds
Started Aug 16 04:53:16 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 214884 kb
Host smart-03ec6784-3863-4571-a1fb-c5e9abd564dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122996531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.122996531
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3839295447
Short name T90
Test name
Test status
Simulation time 312566700 ps
CPU time 6.69 seconds
Started Aug 16 04:53:25 PM PDT 24
Finished Aug 16 04:53:32 PM PDT 24
Peak memory 214880 kb
Host smart-55630890-aea1-4393-9d8e-3c390144e8f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839295447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3839295447
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.538809965
Short name T1063
Test name
Test status
Simulation time 197306801 ps
CPU time 4.16 seconds
Started Aug 16 04:53:31 PM PDT 24
Finished Aug 16 04:53:35 PM PDT 24
Peak memory 214596 kb
Host smart-eab8ce58-f8c3-4607-8933-631f1e55ceac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538809965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.538809965
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2711659890
Short name T1046
Test name
Test status
Simulation time 22834700 ps
CPU time 1.22 seconds
Started Aug 16 04:53:23 PM PDT 24
Finished Aug 16 04:53:24 PM PDT 24
Peak memory 214576 kb
Host smart-0e50c5f0-573f-4738-b51b-661385587b93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711659890 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2711659890
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3051973215
Short name T1000
Test name
Test status
Simulation time 37367504 ps
CPU time 0.95 seconds
Started Aug 16 04:53:20 PM PDT 24
Finished Aug 16 04:53:21 PM PDT 24
Peak memory 206076 kb
Host smart-b1a4a902-935a-4a07-87a9-66a884b3e7ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051973215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3051973215
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1485109941
Short name T924
Test name
Test status
Simulation time 14715505 ps
CPU time 0.84 seconds
Started Aug 16 04:53:19 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 206036 kb
Host smart-49d20afc-ab68-4f67-87c3-64be601e9286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485109941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1485109941
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1853787922
Short name T971
Test name
Test status
Simulation time 35981885 ps
CPU time 2 seconds
Started Aug 16 04:53:25 PM PDT 24
Finished Aug 16 04:53:27 PM PDT 24
Peak memory 206360 kb
Host smart-29746d75-7b8a-4b08-8c85-f3577857ec0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853787922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1853787922
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1085798332
Short name T1038
Test name
Test status
Simulation time 215956601 ps
CPU time 2.23 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 213788 kb
Host smart-e8926013-85c8-40ce-87bf-c8dfc6478501
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085798332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1085798332
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.316873550
Short name T941
Test name
Test status
Simulation time 416431393 ps
CPU time 9.68 seconds
Started Aug 16 04:53:16 PM PDT 24
Finished Aug 16 04:53:26 PM PDT 24
Peak memory 214976 kb
Host smart-5829a4a4-26b5-4daf-806c-3ff81b6dd971
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316873550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.316873550
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2553896571
Short name T957
Test name
Test status
Simulation time 1992063888 ps
CPU time 3.92 seconds
Started Aug 16 04:53:34 PM PDT 24
Finished Aug 16 04:53:38 PM PDT 24
Peak memory 217208 kb
Host smart-46547742-48aa-4360-968f-90a2a18bbc67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553896571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2553896571
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2315936551
Short name T1025
Test name
Test status
Simulation time 203868247 ps
CPU time 1.63 seconds
Started Aug 16 04:53:18 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 214636 kb
Host smart-ea91bca7-39c2-4729-bb54-1ed02d28e81e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315936551 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2315936551
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2357215183
Short name T1052
Test name
Test status
Simulation time 31332440 ps
CPU time 1.08 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:19 PM PDT 24
Peak memory 206236 kb
Host smart-558dab86-af90-4d5e-a8de-5367d7f43abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357215183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2357215183
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3560274249
Short name T980
Test name
Test status
Simulation time 41699583 ps
CPU time 0.74 seconds
Started Aug 16 04:53:29 PM PDT 24
Finished Aug 16 04:53:30 PM PDT 24
Peak memory 206092 kb
Host smart-d5239775-a069-48a6-af28-afef6452d969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560274249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3560274249
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.306879920
Short name T990
Test name
Test status
Simulation time 49541561 ps
CPU time 1.58 seconds
Started Aug 16 04:53:23 PM PDT 24
Finished Aug 16 04:53:25 PM PDT 24
Peak memory 206344 kb
Host smart-7627f942-43b1-44ac-88d3-11751f8ea4cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306879920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.306879920
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3465971166
Short name T983
Test name
Test status
Simulation time 189417038 ps
CPU time 3.12 seconds
Started Aug 16 04:53:19 PM PDT 24
Finished Aug 16 04:53:23 PM PDT 24
Peak memory 214792 kb
Host smart-5f50a46d-a737-4aaa-a52b-119984f66f43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465971166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3465971166
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3149434302
Short name T1065
Test name
Test status
Simulation time 759411707 ps
CPU time 6.67 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:23 PM PDT 24
Peak memory 223040 kb
Host smart-bd00b8a0-fd9d-4925-9113-9bcbe20c32b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149434302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3149434302
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4212481268
Short name T1079
Test name
Test status
Simulation time 32335687 ps
CPU time 2.31 seconds
Started Aug 16 04:53:23 PM PDT 24
Finished Aug 16 04:53:25 PM PDT 24
Peak memory 214612 kb
Host smart-950e577e-71b3-4132-af37-a284632d06b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212481268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4212481268
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2853431843
Short name T1076
Test name
Test status
Simulation time 65109247 ps
CPU time 2.43 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 214568 kb
Host smart-b733a478-7184-454a-ae23-302d7d22ef2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853431843 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2853431843
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1614390247
Short name T938
Test name
Test status
Simulation time 44065684 ps
CPU time 1.06 seconds
Started Aug 16 04:53:22 PM PDT 24
Finished Aug 16 04:53:23 PM PDT 24
Peak memory 206288 kb
Host smart-2af58783-f56b-4568-87f2-01d6f218c04b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614390247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1614390247
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3773371389
Short name T993
Test name
Test status
Simulation time 15487388 ps
CPU time 0.74 seconds
Started Aug 16 04:53:23 PM PDT 24
Finished Aug 16 04:53:24 PM PDT 24
Peak memory 206064 kb
Host smart-92751315-2bd7-46d4-bb6a-38549f365d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773371389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3773371389
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1443700109
Short name T1006
Test name
Test status
Simulation time 2191357420 ps
CPU time 4.57 seconds
Started Aug 16 04:53:19 PM PDT 24
Finished Aug 16 04:53:24 PM PDT 24
Peak memory 206468 kb
Host smart-e5d474a7-deec-4549-8929-500b5d4af38e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443700109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1443700109
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2916385402
Short name T86
Test name
Test status
Simulation time 128212919 ps
CPU time 2.53 seconds
Started Aug 16 04:53:23 PM PDT 24
Finished Aug 16 04:53:26 PM PDT 24
Peak memory 214940 kb
Host smart-ca2f3f44-5916-4c68-a475-3feb0a1f759c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916385402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2916385402
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2993076433
Short name T116
Test name
Test status
Simulation time 739375920 ps
CPU time 5.14 seconds
Started Aug 16 04:53:22 PM PDT 24
Finished Aug 16 04:53:27 PM PDT 24
Peak memory 214844 kb
Host smart-937c1ff3-8fac-4d80-bac5-f629fe5df42a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993076433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2993076433
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3299960870
Short name T929
Test name
Test status
Simulation time 194285554 ps
CPU time 2.36 seconds
Started Aug 16 04:53:26 PM PDT 24
Finished Aug 16 04:53:28 PM PDT 24
Peak memory 214568 kb
Host smart-0e3dbcb1-91ef-4062-81d9-652391e5157f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299960870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3299960870
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.48611918
Short name T1067
Test name
Test status
Simulation time 264549035 ps
CPU time 2.23 seconds
Started Aug 16 04:53:22 PM PDT 24
Finished Aug 16 04:53:25 PM PDT 24
Peak memory 214572 kb
Host smart-de275f47-62b4-4722-b580-b93b82d971d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48611918 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.48611918
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.15471666
Short name T111
Test name
Test status
Simulation time 19366081 ps
CPU time 0.9 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:19 PM PDT 24
Peak memory 205988 kb
Host smart-76cb1340-9ac0-4564-88b8-8c5543e90c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.15471666
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1163100211
Short name T969
Test name
Test status
Simulation time 23572657 ps
CPU time 0.83 seconds
Started Aug 16 04:53:34 PM PDT 24
Finished Aug 16 04:53:35 PM PDT 24
Peak memory 205576 kb
Host smart-5eff061b-003f-4ac3-a759-c0862e0900d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163100211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1163100211
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.368953950
Short name T1066
Test name
Test status
Simulation time 257310194 ps
CPU time 2.05 seconds
Started Aug 16 04:53:23 PM PDT 24
Finished Aug 16 04:53:25 PM PDT 24
Peak memory 206248 kb
Host smart-618980f3-5b22-470e-acf5-d13202df525d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368953950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.368953950
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3455390440
Short name T977
Test name
Test status
Simulation time 365433897 ps
CPU time 2.35 seconds
Started Aug 16 04:53:18 PM PDT 24
Finished Aug 16 04:53:21 PM PDT 24
Peak memory 215016 kb
Host smart-f458771c-0c44-4cce-9f56-9f2a7ff0fdf6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455390440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3455390440
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1668496172
Short name T984
Test name
Test status
Simulation time 158541514 ps
CPU time 4.5 seconds
Started Aug 16 04:53:18 PM PDT 24
Finished Aug 16 04:53:23 PM PDT 24
Peak memory 214876 kb
Host smart-099dc4ba-6e97-405c-a16f-0779070e59e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668496172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1668496172
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1231010080
Short name T966
Test name
Test status
Simulation time 156856124 ps
CPU time 3.76 seconds
Started Aug 16 04:53:18 PM PDT 24
Finished Aug 16 04:53:22 PM PDT 24
Peak memory 214664 kb
Host smart-e0f34050-b2c9-44f1-9e26-2404a2653d33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231010080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1231010080
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3068811273
Short name T438
Test name
Test status
Simulation time 11903326 ps
CPU time 0.91 seconds
Started Aug 16 05:52:29 PM PDT 24
Finished Aug 16 05:52:30 PM PDT 24
Peak memory 206344 kb
Host smart-1e895bba-f2c6-4558-ab06-24ec8a2d5750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068811273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3068811273
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1773908963
Short name T274
Test name
Test status
Simulation time 73145858 ps
CPU time 3.09 seconds
Started Aug 16 05:52:55 PM PDT 24
Finished Aug 16 05:52:58 PM PDT 24
Peak memory 209888 kb
Host smart-35875756-d003-4fb2-9464-be27a07e9816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773908963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1773908963
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1174604522
Short name T234
Test name
Test status
Simulation time 102139223 ps
CPU time 3.23 seconds
Started Aug 16 05:52:49 PM PDT 24
Finished Aug 16 05:52:52 PM PDT 24
Peak memory 214808 kb
Host smart-fcbfd8f6-12de-449a-9c9c-b243a2681393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174604522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1174604522
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4235731890
Short name T143
Test name
Test status
Simulation time 133450363 ps
CPU time 2.26 seconds
Started Aug 16 05:52:27 PM PDT 24
Finished Aug 16 05:52:29 PM PDT 24
Peak memory 215052 kb
Host smart-72bfb23f-be32-4d1d-a7c4-4690ac846633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235731890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4235731890
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1746131134
Short name T606
Test name
Test status
Simulation time 160216790 ps
CPU time 2.7 seconds
Started Aug 16 05:52:28 PM PDT 24
Finished Aug 16 05:52:31 PM PDT 24
Peak memory 208700 kb
Host smart-8ea32fab-ea00-4e26-aa2b-bc54461143bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746131134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1746131134
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4104837944
Short name T467
Test name
Test status
Simulation time 1028796051 ps
CPU time 4.5 seconds
Started Aug 16 05:52:44 PM PDT 24
Finished Aug 16 05:52:49 PM PDT 24
Peak memory 207184 kb
Host smart-0ba78852-d220-47ef-b2ed-7daa26704ca4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104837944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4104837944
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2890315048
Short name T899
Test name
Test status
Simulation time 1633255703 ps
CPU time 19.82 seconds
Started Aug 16 05:52:29 PM PDT 24
Finished Aug 16 05:52:49 PM PDT 24
Peak memory 208596 kb
Host smart-1c0c1d0f-d3fb-4b33-aac8-0d8241b952cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890315048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2890315048
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2684579961
Short name T322
Test name
Test status
Simulation time 358386560 ps
CPU time 2.4 seconds
Started Aug 16 05:52:27 PM PDT 24
Finished Aug 16 05:52:29 PM PDT 24
Peak memory 207436 kb
Host smart-c174a86f-8a67-45b9-b666-c8a42ff65666
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684579961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2684579961
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.349746661
Short name T307
Test name
Test status
Simulation time 357394265 ps
CPU time 10.58 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:22 PM PDT 24
Peak memory 210056 kb
Host smart-4bd934fb-7d71-4d74-b886-0d6f4cab942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349746661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.349746661
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.339561959
Short name T510
Test name
Test status
Simulation time 35133589 ps
CPU time 2.33 seconds
Started Aug 16 05:52:22 PM PDT 24
Finished Aug 16 05:52:25 PM PDT 24
Peak memory 208832 kb
Host smart-07b8f19b-d3be-44ee-9618-5142ab463920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339561959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.339561959
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2176038633
Short name T913
Test name
Test status
Simulation time 706550034 ps
CPU time 5.6 seconds
Started Aug 16 05:52:55 PM PDT 24
Finished Aug 16 05:53:00 PM PDT 24
Peak memory 216720 kb
Host smart-64ef350b-689c-419e-9da8-db3d4c42faad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176038633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2176038633
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3899800161
Short name T355
Test name
Test status
Simulation time 220243018 ps
CPU time 8.84 seconds
Started Aug 16 05:52:37 PM PDT 24
Finished Aug 16 05:52:46 PM PDT 24
Peak memory 218856 kb
Host smart-4cfb00dc-6e43-45b4-a2cf-4c8043025e14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899800161 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3899800161
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2079205266
Short name T314
Test name
Test status
Simulation time 942468520 ps
CPU time 30.17 seconds
Started Aug 16 05:52:28 PM PDT 24
Finished Aug 16 05:52:58 PM PDT 24
Peak memory 208804 kb
Host smart-a79384e8-9e9e-4020-b6bd-9ca35e3651a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079205266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2079205266
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.799031180
Short name T839
Test name
Test status
Simulation time 357862031 ps
CPU time 2.55 seconds
Started Aug 16 05:52:27 PM PDT 24
Finished Aug 16 05:52:30 PM PDT 24
Peak memory 210616 kb
Host smart-d9c5ab65-054f-478a-9611-143278642d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799031180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.799031180
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3060887572
Short name T681
Test name
Test status
Simulation time 31205771 ps
CPU time 0.76 seconds
Started Aug 16 05:53:05 PM PDT 24
Finished Aug 16 05:53:06 PM PDT 24
Peak memory 206340 kb
Host smart-29d1148b-d742-41b2-bc1c-670f555cd990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060887572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3060887572
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1516159930
Short name T238
Test name
Test status
Simulation time 45581576 ps
CPU time 3.42 seconds
Started Aug 16 05:52:40 PM PDT 24
Finished Aug 16 05:52:44 PM PDT 24
Peak memory 216008 kb
Host smart-7537bc59-c881-46e0-ba6c-6eb732ade9ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516159930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1516159930
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2510019316
Short name T718
Test name
Test status
Simulation time 147113276 ps
CPU time 3.6 seconds
Started Aug 16 05:52:39 PM PDT 24
Finished Aug 16 05:52:43 PM PDT 24
Peak memory 211412 kb
Host smart-c2da1003-5f35-4db8-8cc7-f22ff3cab7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510019316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2510019316
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3559233473
Short name T750
Test name
Test status
Simulation time 35603929 ps
CPU time 1.94 seconds
Started Aug 16 05:52:30 PM PDT 24
Finished Aug 16 05:52:32 PM PDT 24
Peak memory 214732 kb
Host smart-43a9a71d-c922-41c9-af77-82097af33f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559233473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3559233473
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2298521425
Short name T830
Test name
Test status
Simulation time 974540243 ps
CPU time 7.65 seconds
Started Aug 16 05:52:37 PM PDT 24
Finished Aug 16 05:52:45 PM PDT 24
Peak memory 219632 kb
Host smart-5722797b-a3b7-4484-a8de-fb99c499021f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298521425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2298521425
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2145997576
Short name T255
Test name
Test status
Simulation time 479822388 ps
CPU time 5.94 seconds
Started Aug 16 05:52:29 PM PDT 24
Finished Aug 16 05:52:36 PM PDT 24
Peak memory 210364 kb
Host smart-c601ab8b-cfdf-406d-939e-72debeea840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145997576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2145997576
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3246999277
Short name T46
Test name
Test status
Simulation time 799371839 ps
CPU time 6.88 seconds
Started Aug 16 05:52:49 PM PDT 24
Finished Aug 16 05:52:56 PM PDT 24
Peak memory 234060 kb
Host smart-6d8ed502-72ec-4bf4-80d7-137dd2cef957
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246999277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3246999277
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2388852115
Short name T763
Test name
Test status
Simulation time 294432025 ps
CPU time 2.65 seconds
Started Aug 16 05:52:29 PM PDT 24
Finished Aug 16 05:52:32 PM PDT 24
Peak memory 207300 kb
Host smart-6ae5c99a-44c9-4f61-9eaa-258dd7fc514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388852115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2388852115
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2557303149
Short name T227
Test name
Test status
Simulation time 64629940 ps
CPU time 2.89 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:10 PM PDT 24
Peak memory 207284 kb
Host smart-f1d6e1de-e076-4f34-bb49-10c732bf1fd1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557303149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2557303149
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2802320463
Short name T412
Test name
Test status
Simulation time 436636544 ps
CPU time 3.65 seconds
Started Aug 16 05:52:39 PM PDT 24
Finished Aug 16 05:52:43 PM PDT 24
Peak memory 207444 kb
Host smart-99bace0b-0b6f-44f1-b4a5-a14e63ca5868
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802320463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2802320463
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3262930477
Short name T620
Test name
Test status
Simulation time 507565560 ps
CPU time 4.34 seconds
Started Aug 16 05:52:36 PM PDT 24
Finished Aug 16 05:52:40 PM PDT 24
Peak memory 216628 kb
Host smart-90748ec8-b99d-45be-9e20-861cae762419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262930477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3262930477
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2784430520
Short name T473
Test name
Test status
Simulation time 93994383 ps
CPU time 3.47 seconds
Started Aug 16 05:52:27 PM PDT 24
Finished Aug 16 05:52:31 PM PDT 24
Peak memory 207236 kb
Host smart-47e529ef-f155-41d4-b80e-f035c5edc1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784430520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2784430520
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.84399080
Short name T199
Test name
Test status
Simulation time 3680269487 ps
CPU time 33.78 seconds
Started Aug 16 05:52:48 PM PDT 24
Finished Aug 16 05:53:22 PM PDT 24
Peak memory 222984 kb
Host smart-18b3805f-ef9d-43fc-87c1-068a83eb24a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84399080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.84399080
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.871072954
Short name T271
Test name
Test status
Simulation time 319419127 ps
CPU time 6.07 seconds
Started Aug 16 05:52:57 PM PDT 24
Finished Aug 16 05:53:03 PM PDT 24
Peak memory 207872 kb
Host smart-b8b80b03-657d-4b10-b942-911429724490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871072954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.871072954
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1528386958
Short name T655
Test name
Test status
Simulation time 218133983 ps
CPU time 1.99 seconds
Started Aug 16 05:52:30 PM PDT 24
Finished Aug 16 05:52:33 PM PDT 24
Peak memory 210476 kb
Host smart-eaec696b-1d98-4569-a873-8b41a7519c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528386958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1528386958
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3465411804
Short name T596
Test name
Test status
Simulation time 37608481 ps
CPU time 0.82 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:16 PM PDT 24
Peak memory 206396 kb
Host smart-cbf33086-2624-49af-810c-1e3ab0a6d45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465411804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3465411804
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3658947111
Short name T390
Test name
Test status
Simulation time 129126681 ps
CPU time 2.98 seconds
Started Aug 16 05:52:56 PM PDT 24
Finished Aug 16 05:53:00 PM PDT 24
Peak memory 214764 kb
Host smart-21ef7198-f780-492b-8c4f-6f262cb61922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658947111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3658947111
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1757297745
Short name T860
Test name
Test status
Simulation time 70350290 ps
CPU time 3.73 seconds
Started Aug 16 05:53:24 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 222052 kb
Host smart-4f214afe-61a4-4fe8-9013-2818775351a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757297745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1757297745
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.835598831
Short name T514
Test name
Test status
Simulation time 649503376 ps
CPU time 6.68 seconds
Started Aug 16 05:53:49 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 208608 kb
Host smart-2ccdacd1-bb22-4a08-ae86-5126b81514ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835598831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.835598831
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.128037902
Short name T39
Test name
Test status
Simulation time 226906245 ps
CPU time 3.14 seconds
Started Aug 16 05:53:37 PM PDT 24
Finished Aug 16 05:53:45 PM PDT 24
Peak memory 214696 kb
Host smart-c802cace-39f5-4436-81ba-74689de87e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128037902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.128037902
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.4075098659
Short name T373
Test name
Test status
Simulation time 537544951 ps
CPU time 10.26 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:26 PM PDT 24
Peak memory 208472 kb
Host smart-3805513b-a771-4275-aa48-ca3182b0f40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075098659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4075098659
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.4109834822
Short name T822
Test name
Test status
Simulation time 31265289 ps
CPU time 1.9 seconds
Started Aug 16 05:53:12 PM PDT 24
Finished Aug 16 05:53:14 PM PDT 24
Peak memory 208416 kb
Host smart-34bec678-bba8-451f-aa05-8759255615b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109834822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.4109834822
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3167310163
Short name T787
Test name
Test status
Simulation time 19655391 ps
CPU time 1.76 seconds
Started Aug 16 05:52:51 PM PDT 24
Finished Aug 16 05:52:53 PM PDT 24
Peak memory 207336 kb
Host smart-8247b88f-be4e-4189-b4c8-1268faf5760e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167310163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3167310163
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1403347308
Short name T424
Test name
Test status
Simulation time 189877038 ps
CPU time 5.08 seconds
Started Aug 16 05:52:52 PM PDT 24
Finished Aug 16 05:52:57 PM PDT 24
Peak memory 208448 kb
Host smart-2e465c50-ac74-4218-b580-8d16ef8930b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403347308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1403347308
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3735537834
Short name T400
Test name
Test status
Simulation time 330696352 ps
CPU time 6.62 seconds
Started Aug 16 05:52:57 PM PDT 24
Finished Aug 16 05:53:04 PM PDT 24
Peak memory 208784 kb
Host smart-1f737e31-4db0-414b-900e-6e7226095fc2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735537834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3735537834
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2272294281
Short name T279
Test name
Test status
Simulation time 263966029 ps
CPU time 3.09 seconds
Started Aug 16 05:53:05 PM PDT 24
Finished Aug 16 05:53:08 PM PDT 24
Peak memory 214772 kb
Host smart-e552221b-1a32-4c29-b45e-4ce1f0e335e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272294281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2272294281
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1672213593
Short name T643
Test name
Test status
Simulation time 22908613756 ps
CPU time 65.1 seconds
Started Aug 16 05:53:24 PM PDT 24
Finished Aug 16 05:54:29 PM PDT 24
Peak memory 208972 kb
Host smart-83fce234-a726-4c88-979c-61fe8703a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672213593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1672213593
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3875191866
Short name T246
Test name
Test status
Simulation time 3647526267 ps
CPU time 7.02 seconds
Started Aug 16 05:53:17 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 208240 kb
Host smart-0af49f01-c120-4417-b704-79f236a40804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875191866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3875191866
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.208555996
Short name T357
Test name
Test status
Simulation time 1201260749 ps
CPU time 12.31 seconds
Started Aug 16 05:53:14 PM PDT 24
Finished Aug 16 05:53:26 PM PDT 24
Peak memory 211296 kb
Host smart-426d0374-71bf-49be-81df-a7e92eda47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208555996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.208555996
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.51253300
Short name T731
Test name
Test status
Simulation time 19171723 ps
CPU time 0.81 seconds
Started Aug 16 05:53:05 PM PDT 24
Finished Aug 16 05:53:06 PM PDT 24
Peak memory 206400 kb
Host smart-398996fb-0825-4fb5-81bd-72c6fed11cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51253300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.51253300
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1662236728
Short name T26
Test name
Test status
Simulation time 2820391757 ps
CPU time 5.31 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:14 PM PDT 24
Peak memory 215012 kb
Host smart-78db8894-76c5-4e27-9620-2ed03ebd5417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662236728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1662236728
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2587900370
Short name T665
Test name
Test status
Simulation time 122880638 ps
CPU time 2.26 seconds
Started Aug 16 05:53:40 PM PDT 24
Finished Aug 16 05:53:43 PM PDT 24
Peak memory 218812 kb
Host smart-b164e386-e91e-4279-bd88-a2c87ec0a81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587900370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2587900370
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.476089545
Short name T751
Test name
Test status
Simulation time 116870860 ps
CPU time 4.88 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 214712 kb
Host smart-d6ce50b1-471f-48de-8e0d-0f0677c0347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476089545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.476089545
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3132465939
Short name T328
Test name
Test status
Simulation time 126344900 ps
CPU time 3.95 seconds
Started Aug 16 05:53:27 PM PDT 24
Finished Aug 16 05:53:31 PM PDT 24
Peak memory 222848 kb
Host smart-78ed4554-d54a-4dc1-a069-56cb58fdbb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132465939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3132465939
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3129488746
Short name T107
Test name
Test status
Simulation time 1863619097 ps
CPU time 6.98 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:39 PM PDT 24
Peak memory 210616 kb
Host smart-8fff1db7-915e-45a2-b23b-511530f16b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129488746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3129488746
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2494960851
Short name T769
Test name
Test status
Simulation time 89905602 ps
CPU time 4.68 seconds
Started Aug 16 05:52:54 PM PDT 24
Finished Aug 16 05:52:58 PM PDT 24
Peak memory 207992 kb
Host smart-77fdb150-f44c-405e-8f4d-df2ffb93ffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494960851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2494960851
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2490758028
Short name T558
Test name
Test status
Simulation time 849002248 ps
CPU time 24.57 seconds
Started Aug 16 05:53:36 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 208700 kb
Host smart-75af30ec-ae28-40f5-adbc-2f2c9cf91149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490758028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2490758028
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.596402068
Short name T648
Test name
Test status
Simulation time 250432189 ps
CPU time 5.37 seconds
Started Aug 16 05:53:50 PM PDT 24
Finished Aug 16 05:53:55 PM PDT 24
Peak memory 209248 kb
Host smart-22696ec6-ac5c-4f98-bdb8-e22645afdc50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596402068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.596402068
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.675534017
Short name T406
Test name
Test status
Simulation time 35630197 ps
CPU time 2.5 seconds
Started Aug 16 05:53:45 PM PDT 24
Finished Aug 16 05:53:48 PM PDT 24
Peak memory 208740 kb
Host smart-ff5b4537-a64f-469f-803e-8a4f577eee6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675534017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.675534017
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.4058580713
Short name T434
Test name
Test status
Simulation time 250332616 ps
CPU time 5.8 seconds
Started Aug 16 05:53:18 PM PDT 24
Finished Aug 16 05:53:24 PM PDT 24
Peak memory 209216 kb
Host smart-3ec83b3e-7ae1-4a69-8301-93094aa9fe5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058580713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.4058580713
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2829855464
Short name T460
Test name
Test status
Simulation time 223215051 ps
CPU time 2.4 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 208748 kb
Host smart-baa62256-7e6a-4355-8936-f0b40782ff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829855464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2829855464
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1328385114
Short name T694
Test name
Test status
Simulation time 89649527 ps
CPU time 2.22 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 207040 kb
Host smart-c51132d5-6893-4e42-b5ba-fcfad9fda1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328385114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1328385114
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3176989492
Short name T125
Test name
Test status
Simulation time 951855376 ps
CPU time 9.91 seconds
Started Aug 16 05:53:08 PM PDT 24
Finished Aug 16 05:53:18 PM PDT 24
Peak memory 219272 kb
Host smart-00f1a1ee-42d8-44b3-9263-b95d450374ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176989492 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3176989492
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2846995533
Short name T239
Test name
Test status
Simulation time 2355787068 ps
CPU time 36.33 seconds
Started Aug 16 05:52:53 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 214800 kb
Host smart-cba0775d-c034-41f2-884f-b5d1c66ddd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846995533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2846995533
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.960911178
Short name T463
Test name
Test status
Simulation time 760808581 ps
CPU time 3.32 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:13 PM PDT 24
Peak memory 210920 kb
Host smart-a8e86c59-e95e-4111-9afb-729a285b582a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960911178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.960911178
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1230960427
Short name T272
Test name
Test status
Simulation time 313518941 ps
CPU time 3.75 seconds
Started Aug 16 05:53:47 PM PDT 24
Finished Aug 16 05:53:50 PM PDT 24
Peak memory 218856 kb
Host smart-9f1ba529-b7a4-4628-8268-7c1539fc71e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230960427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1230960427
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.936742658
Short name T915
Test name
Test status
Simulation time 124736120 ps
CPU time 1.75 seconds
Started Aug 16 05:53:19 PM PDT 24
Finished Aug 16 05:53:21 PM PDT 24
Peak memory 208044 kb
Host smart-6cc1cf68-050a-4359-96c0-a8978e6a800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936742658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.936742658
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.4219532437
Short name T100
Test name
Test status
Simulation time 117200607 ps
CPU time 2.82 seconds
Started Aug 16 05:53:05 PM PDT 24
Finished Aug 16 05:53:08 PM PDT 24
Peak memory 215648 kb
Host smart-a224b5bb-c06f-4847-923f-e14023bffd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219532437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.4219532437
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload.402026692
Short name T445
Test name
Test status
Simulation time 126831882 ps
CPU time 1.62 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 207236 kb
Host smart-7d2cfb28-b2f6-4c98-b353-876ea6c5f9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402026692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.402026692
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.512291650
Short name T883
Test name
Test status
Simulation time 153784965 ps
CPU time 4.51 seconds
Started Aug 16 05:53:36 PM PDT 24
Finished Aug 16 05:53:41 PM PDT 24
Peak memory 208300 kb
Host smart-3f8ed1a5-abcc-4523-bd76-6331b4d3f5cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512291650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.512291650
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4090546456
Short name T407
Test name
Test status
Simulation time 460987437 ps
CPU time 3.91 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 209164 kb
Host smart-bbbe6dd2-fef8-45be-aeb7-aaf7a4e778ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090546456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4090546456
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3139324729
Short name T518
Test name
Test status
Simulation time 71897424 ps
CPU time 3.37 seconds
Started Aug 16 05:53:27 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 208872 kb
Host smart-de7d0445-8f3d-4182-ab64-3931dc3fd372
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139324729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3139324729
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.952442869
Short name T418
Test name
Test status
Simulation time 264814301 ps
CPU time 7.15 seconds
Started Aug 16 05:53:44 PM PDT 24
Finished Aug 16 05:53:51 PM PDT 24
Peak memory 208256 kb
Host smart-bfd51bd8-d73f-4daa-a5ae-dc851453305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952442869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.952442869
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1313168128
Short name T397
Test name
Test status
Simulation time 1988560769 ps
CPU time 30.26 seconds
Started Aug 16 05:53:06 PM PDT 24
Finished Aug 16 05:53:36 PM PDT 24
Peak memory 208416 kb
Host smart-07de06ea-1e7b-4e4f-b13e-80fc6b3a9ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313168128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1313168128
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.363106778
Short name T906
Test name
Test status
Simulation time 3403939083 ps
CPU time 13.47 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:24 PM PDT 24
Peak memory 222960 kb
Host smart-248a526d-2225-4a63-9b48-1ea69f6d4a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363106778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.363106778
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.724133647
Short name T724
Test name
Test status
Simulation time 147802288 ps
CPU time 5.78 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:13 PM PDT 24
Peak memory 210780 kb
Host smart-0fa06a6c-64f0-4465-87fe-14059f32c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724133647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.724133647
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1976991317
Short name T525
Test name
Test status
Simulation time 9314142 ps
CPU time 0.73 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:53:58 PM PDT 24
Peak memory 206420 kb
Host smart-76619898-1159-4420-b193-2f09812fd289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976991317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1976991317
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2986419428
Short name T789
Test name
Test status
Simulation time 314273483 ps
CPU time 3.64 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 223292 kb
Host smart-46524dd0-9e7a-4915-86c7-197dd7b2de7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986419428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2986419428
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1584693915
Short name T892
Test name
Test status
Simulation time 64216339 ps
CPU time 2.71 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 209708 kb
Host smart-da200110-77fb-4220-9ead-db1e746d0892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584693915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1584693915
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.4205605966
Short name T672
Test name
Test status
Simulation time 224829841 ps
CPU time 3.05 seconds
Started Aug 16 05:53:19 PM PDT 24
Finished Aug 16 05:53:22 PM PDT 24
Peak memory 222868 kb
Host smart-0cd87329-9870-42fd-974a-a065bd1e198c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205605966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.4205605966
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1789081438
Short name T187
Test name
Test status
Simulation time 227541077 ps
CPU time 3.38 seconds
Started Aug 16 05:53:21 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 208392 kb
Host smart-02d0e6af-4ca2-48ee-be70-586b26356467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789081438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1789081438
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1057088187
Short name T818
Test name
Test status
Simulation time 71330743 ps
CPU time 2.79 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 208520 kb
Host smart-19f9255c-b941-44dc-ac30-b785b760c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057088187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1057088187
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1000622339
Short name T675
Test name
Test status
Simulation time 509485553 ps
CPU time 3.16 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:13 PM PDT 24
Peak memory 209224 kb
Host smart-367410aa-ab65-4492-b0d6-6cbc1515d903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000622339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1000622339
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1800926414
Short name T759
Test name
Test status
Simulation time 48208274 ps
CPU time 2.43 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 209012 kb
Host smart-cdcb0b85-bc12-4f79-b912-075d2cbc7b75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800926414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1800926414
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1668962969
Short name T914
Test name
Test status
Simulation time 90241145 ps
CPU time 2.52 seconds
Started Aug 16 05:53:39 PM PDT 24
Finished Aug 16 05:53:42 PM PDT 24
Peak memory 207372 kb
Host smart-bfd2f50d-11e5-486f-863e-91176a695ed9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668962969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1668962969
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.963791969
Short name T414
Test name
Test status
Simulation time 66799562 ps
CPU time 2.89 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:14 PM PDT 24
Peak memory 207324 kb
Host smart-ebbf9122-c0e1-413c-8cdd-fe9b515e384a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963791969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.963791969
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.4142072966
Short name T784
Test name
Test status
Simulation time 92389632 ps
CPU time 2.32 seconds
Started Aug 16 05:53:37 PM PDT 24
Finished Aug 16 05:53:39 PM PDT 24
Peak memory 208952 kb
Host smart-9b577455-dc94-4b01-97f6-5c923ddb560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142072966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.4142072966
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2787880863
Short name T601
Test name
Test status
Simulation time 54268987 ps
CPU time 2.72 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:10 PM PDT 24
Peak memory 208668 kb
Host smart-2455dd79-6f42-4ac6-9e61-47cb90c37ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787880863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2787880863
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3355156327
Short name T140
Test name
Test status
Simulation time 52740132331 ps
CPU time 165.1 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 217280 kb
Host smart-1e8c664b-aeb1-4361-8314-793ea09aa263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355156327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3355156327
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1719729723
Short name T336
Test name
Test status
Simulation time 3095573672 ps
CPU time 20.36 seconds
Started Aug 16 05:53:18 PM PDT 24
Finished Aug 16 05:53:38 PM PDT 24
Peak memory 223052 kb
Host smart-77d69ff5-0614-4eca-9563-89f13b85595b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719729723 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1719729723
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2518644027
Short name T484
Test name
Test status
Simulation time 283561652 ps
CPU time 6 seconds
Started Aug 16 05:52:52 PM PDT 24
Finished Aug 16 05:52:58 PM PDT 24
Peak memory 214816 kb
Host smart-8de8df0f-acb9-40b6-81ec-f4a72e34e287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518644027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2518644027
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1832346232
Short name T603
Test name
Test status
Simulation time 890788747 ps
CPU time 6.86 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:22 PM PDT 24
Peak memory 211496 kb
Host smart-96ee3cee-d8a2-44d8-abfe-6bd98dc3e856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832346232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1832346232
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.887156368
Short name T408
Test name
Test status
Simulation time 35477150 ps
CPU time 0.72 seconds
Started Aug 16 05:53:51 PM PDT 24
Finished Aug 16 05:53:52 PM PDT 24
Peak memory 206340 kb
Host smart-31b4cbba-dea9-43f4-a9a6-8213afc8da1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887156368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.887156368
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2982196743
Short name T259
Test name
Test status
Simulation time 141483115 ps
CPU time 3.01 seconds
Started Aug 16 05:53:14 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 214788 kb
Host smart-4808813a-dc84-41fb-a684-3268b9819279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982196743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2982196743
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.271686569
Short name T647
Test name
Test status
Simulation time 719973485 ps
CPU time 3.82 seconds
Started Aug 16 05:53:51 PM PDT 24
Finished Aug 16 05:53:55 PM PDT 24
Peak memory 214776 kb
Host smart-d5951fb3-da76-454a-b53c-25d6ebc9526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271686569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.271686569
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3926091977
Short name T834
Test name
Test status
Simulation time 402713053 ps
CPU time 3.81 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:20 PM PDT 24
Peak memory 222056 kb
Host smart-f3d3026e-1e84-4c83-8600-c742b7b09d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926091977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3926091977
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2155212335
Short name T354
Test name
Test status
Simulation time 447710741 ps
CPU time 3.15 seconds
Started Aug 16 05:53:13 PM PDT 24
Finished Aug 16 05:53:16 PM PDT 24
Peak memory 214712 kb
Host smart-9a390601-d517-4ce8-8b79-c5c8576b626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155212335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2155212335
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1750527503
Short name T704
Test name
Test status
Simulation time 193139745 ps
CPU time 2.38 seconds
Started Aug 16 05:53:59 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 217152 kb
Host smart-dc2c0585-8635-43af-b54b-0926ec8e2833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750527503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1750527503
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2819858197
Short name T479
Test name
Test status
Simulation time 200863916 ps
CPU time 2.86 seconds
Started Aug 16 05:52:59 PM PDT 24
Finished Aug 16 05:53:02 PM PDT 24
Peak memory 209288 kb
Host smart-2684cb7e-f7a5-4c7a-9263-3e493d0361aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819858197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2819858197
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2563131452
Short name T780
Test name
Test status
Simulation time 1873758163 ps
CPU time 34.42 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:51 PM PDT 24
Peak memory 209092 kb
Host smart-c25ce1e6-d57e-4815-8186-45dec155fb0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563131452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2563131452
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3927088641
Short name T305
Test name
Test status
Simulation time 3853008478 ps
CPU time 15.9 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 209168 kb
Host smart-1a8c83b0-d36a-4394-94ae-d9a10d80da8f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927088641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3927088641
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2728748519
Short name T536
Test name
Test status
Simulation time 18694263 ps
CPU time 1.6 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:33 PM PDT 24
Peak memory 207380 kb
Host smart-f30671de-0f84-4270-b730-41c3f74736f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728748519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2728748519
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3376126832
Short name T179
Test name
Test status
Simulation time 153436490 ps
CPU time 5.53 seconds
Started Aug 16 05:53:13 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 209700 kb
Host smart-f866291a-f79d-44ea-b14e-e6e8d0b275ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376126832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3376126832
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.227806948
Short name T770
Test name
Test status
Simulation time 76899473 ps
CPU time 1.62 seconds
Started Aug 16 05:53:25 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 207176 kb
Host smart-0cd179a7-7482-4fe8-bb65-a1639b10a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227806948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.227806948
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.986192427
Short name T136
Test name
Test status
Simulation time 1895991597 ps
CPU time 14.13 seconds
Started Aug 16 05:53:18 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 215620 kb
Host smart-f219cd91-404c-4ea5-add6-f328ff959f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986192427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.986192427
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2898484692
Short name T781
Test name
Test status
Simulation time 88853779 ps
CPU time 3.84 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:14 PM PDT 24
Peak memory 207684 kb
Host smart-9f13585b-e5a2-4eaa-94b5-0833973b8c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898484692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2898484692
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3806038416
Short name T449
Test name
Test status
Simulation time 184242966 ps
CPU time 3.7 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:20 PM PDT 24
Peak memory 210896 kb
Host smart-4463f481-821b-45f0-9403-3b2184e157ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806038416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3806038416
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3369802705
Short name T481
Test name
Test status
Simulation time 12608831 ps
CPU time 0.79 seconds
Started Aug 16 05:53:14 PM PDT 24
Finished Aug 16 05:53:15 PM PDT 24
Peak memory 206372 kb
Host smart-bef4b7dc-0f12-41bc-8d1b-bbb861dafe6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369802705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3369802705
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.440717765
Short name T203
Test name
Test status
Simulation time 185452593 ps
CPU time 3.68 seconds
Started Aug 16 05:53:36 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 214792 kb
Host smart-980bf9a3-cdae-4f48-a153-a7594fc1934e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440717765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.440717765
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1625965453
Short name T777
Test name
Test status
Simulation time 1485104361 ps
CPU time 14.69 seconds
Started Aug 16 05:53:39 PM PDT 24
Finished Aug 16 05:53:55 PM PDT 24
Peak memory 220312 kb
Host smart-a75c7cf0-f2cc-42d4-996e-db7062533cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625965453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1625965453
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3246560345
Short name T256
Test name
Test status
Simulation time 199202005 ps
CPU time 2.75 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 209068 kb
Host smart-af51acae-15ad-4a5e-a412-112b8110cdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246560345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3246560345
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1222959819
Short name T517
Test name
Test status
Simulation time 40067029 ps
CPU time 1.73 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 207800 kb
Host smart-2054185f-2ca7-40e1-9fc2-766ab4375e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222959819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1222959819
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2678651838
Short name T911
Test name
Test status
Simulation time 236223592 ps
CPU time 3.83 seconds
Started Aug 16 05:53:45 PM PDT 24
Finished Aug 16 05:53:49 PM PDT 24
Peak memory 208536 kb
Host smart-d14c7bdb-4faf-4d6f-936f-cf27afa7ac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678651838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2678651838
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1629443188
Short name T320
Test name
Test status
Simulation time 65635225 ps
CPU time 2.82 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:53:58 PM PDT 24
Peak memory 208988 kb
Host smart-c1674d91-0b97-4554-91ad-aab40288c023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629443188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1629443188
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3932716802
Short name T335
Test name
Test status
Simulation time 67946768 ps
CPU time 2.6 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 209332 kb
Host smart-351ade37-f98e-4d6b-a4a7-daf28ef567a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932716802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3932716802
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2944006284
Short name T838
Test name
Test status
Simulation time 438205922 ps
CPU time 11.94 seconds
Started Aug 16 05:53:40 PM PDT 24
Finished Aug 16 05:53:52 PM PDT 24
Peak memory 209148 kb
Host smart-7fb079ea-36df-4c0c-b918-0b453c370669
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944006284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2944006284
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.4262496387
Short name T713
Test name
Test status
Simulation time 133876328 ps
CPU time 4.32 seconds
Started Aug 16 05:53:18 PM PDT 24
Finished Aug 16 05:53:22 PM PDT 24
Peak memory 208604 kb
Host smart-136022f2-a692-45a3-8ab0-cc01195af808
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262496387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4262496387
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2702219732
Short name T886
Test name
Test status
Simulation time 71591957 ps
CPU time 1.84 seconds
Started Aug 16 05:53:52 PM PDT 24
Finished Aug 16 05:53:54 PM PDT 24
Peak memory 216344 kb
Host smart-00c420c2-cfdc-47c0-9819-4d60ba2e4baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702219732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2702219732
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3426198476
Short name T448
Test name
Test status
Simulation time 270599669 ps
CPU time 2.66 seconds
Started Aug 16 05:53:37 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 208820 kb
Host smart-9decb6f3-1775-4e9b-bb53-935c4534201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426198476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3426198476
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2324694562
Short name T350
Test name
Test status
Simulation time 1986138248 ps
CPU time 64.71 seconds
Started Aug 16 05:53:36 PM PDT 24
Finished Aug 16 05:54:41 PM PDT 24
Peak memory 216128 kb
Host smart-c65e2ded-c537-45ae-a234-513f74c29d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324694562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2324694562
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2707690842
Short name T716
Test name
Test status
Simulation time 110744939 ps
CPU time 3.96 seconds
Started Aug 16 05:53:17 PM PDT 24
Finished Aug 16 05:53:21 PM PDT 24
Peak memory 218612 kb
Host smart-55580386-2830-432a-a696-a5506644e402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707690842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2707690842
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.801377358
Short name T486
Test name
Test status
Simulation time 83991950 ps
CPU time 3.09 seconds
Started Aug 16 05:53:26 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 210988 kb
Host smart-f80a5d44-476f-48d3-a62a-2bc9c589e408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801377358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.801377358
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2541526573
Short name T63
Test name
Test status
Simulation time 40155652 ps
CPU time 0.87 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:16 PM PDT 24
Peak memory 206380 kb
Host smart-4125e16c-2f3d-43fe-8cf2-42150bca52f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541526573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2541526573
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2507762622
Short name T833
Test name
Test status
Simulation time 81626843 ps
CPU time 3.68 seconds
Started Aug 16 05:53:17 PM PDT 24
Finished Aug 16 05:53:20 PM PDT 24
Peak memory 208720 kb
Host smart-f8837915-7033-4f29-ab6b-bb4608bf7ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507762622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2507762622
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1514154706
Short name T413
Test name
Test status
Simulation time 226636510 ps
CPU time 2.15 seconds
Started Aug 16 05:53:18 PM PDT 24
Finished Aug 16 05:53:20 PM PDT 24
Peak memory 208356 kb
Host smart-c0c60769-1a83-45c1-83d8-c35bdd426a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514154706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1514154706
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2485186378
Short name T581
Test name
Test status
Simulation time 407160927 ps
CPU time 4.06 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 209128 kb
Host smart-aeb43b27-2db1-403f-ad61-003c134e3160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485186378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2485186378
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3252386135
Short name T722
Test name
Test status
Simulation time 156096754 ps
CPU time 4.29 seconds
Started Aug 16 05:53:53 PM PDT 24
Finished Aug 16 05:53:57 PM PDT 24
Peak memory 222904 kb
Host smart-a7272dde-002e-455a-b976-a55ad07f1689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252386135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3252386135
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3457216394
Short name T304
Test name
Test status
Simulation time 373621223 ps
CPU time 3.02 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 214732 kb
Host smart-3981688c-bdc6-4652-89ab-8300649feddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457216394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3457216394
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3168982076
Short name T206
Test name
Test status
Simulation time 620271316 ps
CPU time 3.35 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 209292 kb
Host smart-6a512d19-3411-4e15-a887-7469983748ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168982076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3168982076
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1367288030
Short name T812
Test name
Test status
Simulation time 658030388 ps
CPU time 5.19 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:35 PM PDT 24
Peak memory 208368 kb
Host smart-dcfc5c3c-5b88-4d51-a75c-1497e9cfcb08
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367288030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1367288030
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.152588476
Short name T404
Test name
Test status
Simulation time 751124399 ps
CPU time 5.9 seconds
Started Aug 16 05:53:21 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 209092 kb
Host smart-231c9334-ba4d-4c82-a88c-9f33489148a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152588476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.152588476
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.672632816
Short name T797
Test name
Test status
Simulation time 194109488 ps
CPU time 4.17 seconds
Started Aug 16 05:53:48 PM PDT 24
Finished Aug 16 05:53:52 PM PDT 24
Peak memory 207380 kb
Host smart-f2e20847-faea-44aa-b947-0d3f47f92bbf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672632816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.672632816
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1271514872
Short name T522
Test name
Test status
Simulation time 35426636 ps
CPU time 1.57 seconds
Started Aug 16 05:53:38 PM PDT 24
Finished Aug 16 05:53:39 PM PDT 24
Peak memory 208744 kb
Host smart-f816382f-fc00-41d7-a022-51f1959e2be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271514872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1271514872
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.934852980
Short name T631
Test name
Test status
Simulation time 91114992 ps
CPU time 1.87 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:53:59 PM PDT 24
Peak memory 208756 kb
Host smart-2326a3ac-b4a1-44cc-b280-86ac8c350fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934852980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.934852980
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1550413073
Short name T768
Test name
Test status
Simulation time 477783981 ps
CPU time 18.71 seconds
Started Aug 16 05:53:48 PM PDT 24
Finished Aug 16 05:54:06 PM PDT 24
Peak memory 215772 kb
Host smart-545800a4-1a26-43ed-8ffd-210364153e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550413073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1550413073
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3618295699
Short name T153
Test name
Test status
Simulation time 435290735 ps
CPU time 8.27 seconds
Started Aug 16 05:53:19 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 222988 kb
Host smart-5e4c334e-8567-475d-baa7-8710b9dfed80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618295699 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3618295699
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2863007008
Short name T450
Test name
Test status
Simulation time 164947216 ps
CPU time 3.58 seconds
Started Aug 16 05:53:52 PM PDT 24
Finished Aug 16 05:53:56 PM PDT 24
Peak memory 208516 kb
Host smart-60695eb4-c777-4cd3-8f1c-3aed96fd3550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863007008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2863007008
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3102799233
Short name T456
Test name
Test status
Simulation time 145298392 ps
CPU time 2.17 seconds
Started Aug 16 05:53:49 PM PDT 24
Finished Aug 16 05:53:51 PM PDT 24
Peak memory 210508 kb
Host smart-29cf67da-a4f5-49da-9b2d-723584a0cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102799233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3102799233
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1005787157
Short name T474
Test name
Test status
Simulation time 45096175 ps
CPU time 0.83 seconds
Started Aug 16 05:53:12 PM PDT 24
Finished Aug 16 05:53:13 PM PDT 24
Peak memory 206336 kb
Host smart-5ddd17f5-21d4-4208-8d29-3a0f9f8c37fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005787157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1005787157
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.4268654417
Short name T236
Test name
Test status
Simulation time 149895833 ps
CPU time 2.82 seconds
Started Aug 16 05:53:42 PM PDT 24
Finished Aug 16 05:53:45 PM PDT 24
Peak memory 216364 kb
Host smart-dc1f0096-e76a-470b-a76b-044bf1a032e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268654417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.4268654417
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.412682331
Short name T42
Test name
Test status
Simulation time 75650530 ps
CPU time 2.8 seconds
Started Aug 16 05:53:17 PM PDT 24
Finished Aug 16 05:53:20 PM PDT 24
Peak memory 220620 kb
Host smart-0c2a6bdd-347b-4d06-b74d-d4820cfda936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412682331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.412682331
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.488964204
Short name T810
Test name
Test status
Simulation time 85555648 ps
CPU time 3.3 seconds
Started Aug 16 05:53:43 PM PDT 24
Finished Aug 16 05:53:47 PM PDT 24
Peak memory 214688 kb
Host smart-31d89dcd-59ac-46e7-a216-9fd9e559d933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488964204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.488964204
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3453805206
Short name T315
Test name
Test status
Simulation time 399650781 ps
CPU time 4.56 seconds
Started Aug 16 05:53:36 PM PDT 24
Finished Aug 16 05:53:41 PM PDT 24
Peak memory 214796 kb
Host smart-f14edb6c-cd50-493e-82d9-313cdd413b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453805206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3453805206
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.4198082535
Short name T636
Test name
Test status
Simulation time 105117903 ps
CPU time 2.78 seconds
Started Aug 16 05:53:14 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 208600 kb
Host smart-72a6e22b-308d-41b2-9a0c-ab4eaf400d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198082535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.4198082535
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.4264588704
Short name T843
Test name
Test status
Simulation time 222609067 ps
CPU time 3.45 seconds
Started Aug 16 05:53:36 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 207520 kb
Host smart-222f5874-c88c-4ae6-a541-e36ca7386b6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264588704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4264588704
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2986201263
Short name T881
Test name
Test status
Simulation time 138241674 ps
CPU time 2.81 seconds
Started Aug 16 05:53:29 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 209360 kb
Host smart-25efda91-545f-44ff-b3be-7fd8a157b48e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986201263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2986201263
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2707179535
Short name T538
Test name
Test status
Simulation time 125495899 ps
CPU time 3.29 seconds
Started Aug 16 05:53:14 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 208916 kb
Host smart-775606b3-83d8-43c2-8275-b41cccb0a905
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707179535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2707179535
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2968939244
Short name T868
Test name
Test status
Simulation time 627631324 ps
CPU time 4.57 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 218664 kb
Host smart-9081620c-af8d-4a0f-b2d1-4388020eb99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968939244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2968939244
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2026143241
Short name T642
Test name
Test status
Simulation time 127246343 ps
CPU time 2.29 seconds
Started Aug 16 05:53:18 PM PDT 24
Finished Aug 16 05:53:20 PM PDT 24
Peak memory 207316 kb
Host smart-c1229641-d4d7-4d14-9755-119950f8847c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026143241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2026143241
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.176055803
Short name T297
Test name
Test status
Simulation time 269964869 ps
CPU time 9.68 seconds
Started Aug 16 05:53:44 PM PDT 24
Finished Aug 16 05:53:54 PM PDT 24
Peak memory 223076 kb
Host smart-b8bb17a2-7fc2-4ef5-8fd3-8097126948ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176055803 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.176055803
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3450643381
Short name T674
Test name
Test status
Simulation time 1112102471 ps
CPU time 20.17 seconds
Started Aug 16 05:53:20 PM PDT 24
Finished Aug 16 05:53:41 PM PDT 24
Peak memory 218908 kb
Host smart-8817c67b-ecf8-4e10-ae02-c9a1a227d210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450643381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3450643381
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4291441848
Short name T362
Test name
Test status
Simulation time 260260899 ps
CPU time 7.58 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:22 PM PDT 24
Peak memory 211052 kb
Host smart-6aba2a5d-6b56-4190-bfdc-75fec516f79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291441848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4291441848
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2441546318
Short name T677
Test name
Test status
Simulation time 10815569 ps
CPU time 0.69 seconds
Started Aug 16 05:53:45 PM PDT 24
Finished Aug 16 05:53:46 PM PDT 24
Peak memory 206236 kb
Host smart-636ba14d-cbb5-40d7-b9c2-452e3855d828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441546318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2441546318
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.636646184
Short name T219
Test name
Test status
Simulation time 41047054 ps
CPU time 2.83 seconds
Started Aug 16 05:53:40 PM PDT 24
Finished Aug 16 05:53:43 PM PDT 24
Peak memory 214748 kb
Host smart-50b26cda-a261-426a-bc27-af10fcc24834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636646184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.636646184
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3467822778
Short name T77
Test name
Test status
Simulation time 465366171 ps
CPU time 2.85 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:18 PM PDT 24
Peak memory 208440 kb
Host smart-0511ff99-0fa4-4f26-b6f0-72db1695687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467822778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3467822778
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2519856939
Short name T904
Test name
Test status
Simulation time 266997658 ps
CPU time 4.37 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 214720 kb
Host smart-4fffee60-1d07-492b-8cdd-ea1cd62d32d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519856939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2519856939
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1962288906
Short name T38
Test name
Test status
Simulation time 46806671 ps
CPU time 2.71 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 214704 kb
Host smart-92678170-ddb4-47d5-8c60-47a874892741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962288906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1962288906
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.420177233
Short name T217
Test name
Test status
Simulation time 151643767 ps
CPU time 3.81 seconds
Started Aug 16 05:53:43 PM PDT 24
Finished Aug 16 05:53:46 PM PDT 24
Peak memory 210676 kb
Host smart-d2133207-002e-45e3-ba16-ebad0afa6801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420177233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.420177233
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2934694677
Short name T598
Test name
Test status
Simulation time 51011331 ps
CPU time 3.23 seconds
Started Aug 16 05:53:53 PM PDT 24
Finished Aug 16 05:53:56 PM PDT 24
Peak memory 208860 kb
Host smart-7867dec5-e79e-43fc-af7c-becf6fa0671d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934694677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2934694677
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.288899335
Short name T475
Test name
Test status
Simulation time 396630828 ps
CPU time 8.35 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 209172 kb
Host smart-8d3c743b-4a7b-45d4-93b9-82fa3484dbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288899335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.288899335
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.972908952
Short name T817
Test name
Test status
Simulation time 97372007 ps
CPU time 2.83 seconds
Started Aug 16 05:53:54 PM PDT 24
Finished Aug 16 05:53:57 PM PDT 24
Peak memory 207404 kb
Host smart-14896576-73bb-4bb2-8b08-4e4cd9e3fa10
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972908952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.972908952
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.921106074
Short name T829
Test name
Test status
Simulation time 943367961 ps
CPU time 4.02 seconds
Started Aug 16 05:53:17 PM PDT 24
Finished Aug 16 05:53:21 PM PDT 24
Peak memory 209564 kb
Host smart-5c3ad063-685c-4116-b346-eb7fd439a121
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921106074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.921106074
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1354519591
Short name T94
Test name
Test status
Simulation time 2721815687 ps
CPU time 26.61 seconds
Started Aug 16 05:53:12 PM PDT 24
Finished Aug 16 05:53:38 PM PDT 24
Peak memory 208540 kb
Host smart-e2023e4a-f0cf-459b-b96a-bed77d5b007d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354519591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1354519591
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3853309375
Short name T645
Test name
Test status
Simulation time 115632340 ps
CPU time 1.77 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:35 PM PDT 24
Peak memory 210516 kb
Host smart-c3186d01-731c-49c2-a99e-a11d3a3fcc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853309375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3853309375
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.530977829
Short name T597
Test name
Test status
Simulation time 380368733 ps
CPU time 4.01 seconds
Started Aug 16 05:53:26 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 207356 kb
Host smart-aa461d59-bcc3-48df-b19c-f02dd92e42c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530977829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.530977829
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.922521288
Short name T745
Test name
Test status
Simulation time 97981793 ps
CPU time 3.05 seconds
Started Aug 16 05:53:14 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 210572 kb
Host smart-5e780e8c-9b4c-49e1-b89d-5e3d045b98bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922521288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.922521288
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3927591681
Short name T462
Test name
Test status
Simulation time 15724509 ps
CPU time 0.78 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:53:56 PM PDT 24
Peak memory 206388 kb
Host smart-6c4806eb-7ddb-457b-8c49-8f76f839a81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927591681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3927591681
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4225803083
Short name T139
Test name
Test status
Simulation time 76750925 ps
CPU time 2.49 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:53:59 PM PDT 24
Peak memory 208792 kb
Host smart-75f8b94f-d9b3-4548-9c69-7c7d3f464c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225803083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4225803083
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1985976353
Short name T697
Test name
Test status
Simulation time 697517141 ps
CPU time 20.11 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 214776 kb
Host smart-35db27ca-eb1d-4fd0-ac81-397a17d7e9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985976353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1985976353
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1090866658
Short name T734
Test name
Test status
Simulation time 2060635074 ps
CPU time 6.76 seconds
Started Aug 16 05:53:40 PM PDT 24
Finished Aug 16 05:53:47 PM PDT 24
Peak memory 215484 kb
Host smart-6a992836-2217-4d11-a4c2-26d40eadf009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090866658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1090866658
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2299725777
Short name T273
Test name
Test status
Simulation time 123986391 ps
CPU time 5.27 seconds
Started Aug 16 05:53:42 PM PDT 24
Finished Aug 16 05:53:48 PM PDT 24
Peak memory 209208 kb
Host smart-43e8f6ed-6def-40c0-897d-2447c3044ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299725777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2299725777
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3297859440
Short name T586
Test name
Test status
Simulation time 66747719 ps
CPU time 3.28 seconds
Started Aug 16 05:53:53 PM PDT 24
Finished Aug 16 05:53:57 PM PDT 24
Peak memory 209100 kb
Host smart-591d244b-6a5b-48f3-a13d-a95a474511b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297859440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3297859440
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3269117068
Short name T630
Test name
Test status
Simulation time 251552503 ps
CPU time 3.42 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:20 PM PDT 24
Peak memory 209076 kb
Host smart-2ac416dc-4cbb-4448-acaf-25782187ccc2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269117068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3269117068
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1577781034
Short name T557
Test name
Test status
Simulation time 1401062053 ps
CPU time 8.73 seconds
Started Aug 16 05:53:59 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 207416 kb
Host smart-a21141c7-3c86-4ca8-b1a2-6d93fc79600f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577781034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1577781034
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1536331250
Short name T700
Test name
Test status
Simulation time 88082582 ps
CPU time 3.48 seconds
Started Aug 16 05:53:40 PM PDT 24
Finished Aug 16 05:53:44 PM PDT 24
Peak memory 209032 kb
Host smart-1f482bfa-1b2c-4814-9327-27db24ee9ec8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536331250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1536331250
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3144716147
Short name T508
Test name
Test status
Simulation time 46620500 ps
CPU time 2.42 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 209408 kb
Host smart-532ed1ee-d3cd-47f5-a7c1-5723fbf256b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144716147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3144716147
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.70571122
Short name T415
Test name
Test status
Simulation time 77932210 ps
CPU time 2.05 seconds
Started Aug 16 05:53:20 PM PDT 24
Finished Aug 16 05:53:22 PM PDT 24
Peak memory 207192 kb
Host smart-7473862a-75fc-4e57-9e75-22457c6cdeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70571122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.70571122
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.103793136
Short name T576
Test name
Test status
Simulation time 560874079 ps
CPU time 16.13 seconds
Started Aug 16 05:53:20 PM PDT 24
Finished Aug 16 05:53:36 PM PDT 24
Peak memory 216152 kb
Host smart-0b67e374-a09e-4e84-9ce2-353c1a1916f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103793136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.103793136
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2573900859
Short name T410
Test name
Test status
Simulation time 2006944776 ps
CPU time 12.47 seconds
Started Aug 16 05:53:38 PM PDT 24
Finished Aug 16 05:53:50 PM PDT 24
Peak memory 209988 kb
Host smart-c8d25c67-5145-4863-b650-b80bf914cdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573900859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2573900859
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2097519226
Short name T363
Test name
Test status
Simulation time 231099924 ps
CPU time 2.32 seconds
Started Aug 16 05:53:49 PM PDT 24
Finished Aug 16 05:53:51 PM PDT 24
Peak memory 210232 kb
Host smart-89c65d12-9134-4004-9284-e603bd6ab78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097519226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2097519226
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1614178725
Short name T573
Test name
Test status
Simulation time 12040554 ps
CPU time 0.86 seconds
Started Aug 16 05:52:36 PM PDT 24
Finished Aug 16 05:52:37 PM PDT 24
Peak memory 206400 kb
Host smart-d286ba15-fc84-48b2-be92-7419e26de910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614178725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1614178725
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.857713808
Short name T529
Test name
Test status
Simulation time 276720067 ps
CPU time 3.14 seconds
Started Aug 16 05:52:40 PM PDT 24
Finished Aug 16 05:52:43 PM PDT 24
Peak memory 210288 kb
Host smart-c80c2ba1-93fa-43ed-9806-d47af3f1c038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857713808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.857713808
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.650938973
Short name T1
Test name
Test status
Simulation time 1679042706 ps
CPU time 3.73 seconds
Started Aug 16 05:52:39 PM PDT 24
Finished Aug 16 05:52:43 PM PDT 24
Peak memory 208552 kb
Host smart-0d4f3b76-205d-41f7-ba93-6235c47167e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650938973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.650938973
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3814264289
Short name T444
Test name
Test status
Simulation time 193110340 ps
CPU time 4.4 seconds
Started Aug 16 05:52:40 PM PDT 24
Finished Aug 16 05:52:45 PM PDT 24
Peak memory 214724 kb
Host smart-d1b23041-5cc3-4aaa-9e8a-a385d9e93b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814264289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3814264289
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1229907119
Short name T870
Test name
Test status
Simulation time 302925709 ps
CPU time 4.82 seconds
Started Aug 16 05:52:29 PM PDT 24
Finished Aug 16 05:52:34 PM PDT 24
Peak memory 214792 kb
Host smart-f4826dc2-79df-44a4-a4ff-7b39477b63b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229907119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1229907119
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3887038174
Short name T197
Test name
Test status
Simulation time 126229575 ps
CPU time 4.17 seconds
Started Aug 16 05:52:27 PM PDT 24
Finished Aug 16 05:52:32 PM PDT 24
Peak memory 214724 kb
Host smart-d7131529-4bb5-498d-a7f1-a3a12896c136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887038174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3887038174
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.113957944
Short name T633
Test name
Test status
Simulation time 81548812 ps
CPU time 3.5 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 209360 kb
Host smart-ae02c9ab-6615-4414-9046-334005d8c067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113957944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.113957944
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.4192180615
Short name T809
Test name
Test status
Simulation time 72006144 ps
CPU time 2.44 seconds
Started Aug 16 05:52:28 PM PDT 24
Finished Aug 16 05:52:30 PM PDT 24
Peak memory 207536 kb
Host smart-9c7ebdb6-1307-44bf-ad26-5b4e69e5413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192180615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.4192180615
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.838475925
Short name T147
Test name
Test status
Simulation time 16462819556 ps
CPU time 63.59 seconds
Started Aug 16 05:52:40 PM PDT 24
Finished Aug 16 05:53:44 PM PDT 24
Peak memory 208616 kb
Host smart-cf13c6c1-c3d5-451d-a332-fa46d6567a26
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838475925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.838475925
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1944448761
Short name T530
Test name
Test status
Simulation time 6661921658 ps
CPU time 65.51 seconds
Started Aug 16 05:52:45 PM PDT 24
Finished Aug 16 05:53:50 PM PDT 24
Peak memory 209152 kb
Host smart-91e1bdb3-8222-4d47-9ecf-da3eb29b50da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944448761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1944448761
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3277045343
Short name T629
Test name
Test status
Simulation time 92106388 ps
CPU time 3.56 seconds
Started Aug 16 05:52:34 PM PDT 24
Finished Aug 16 05:52:38 PM PDT 24
Peak memory 207468 kb
Host smart-95e0b55b-2eaa-4c44-882d-13796d07a315
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277045343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3277045343
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3201122503
Short name T488
Test name
Test status
Simulation time 26722463 ps
CPU time 1.98 seconds
Started Aug 16 05:52:54 PM PDT 24
Finished Aug 16 05:52:56 PM PDT 24
Peak memory 208016 kb
Host smart-94ca1e68-626a-41cc-ab29-f2ea74960731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201122503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3201122503
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.668814467
Short name T372
Test name
Test status
Simulation time 37465835 ps
CPU time 2.44 seconds
Started Aug 16 05:52:31 PM PDT 24
Finished Aug 16 05:52:34 PM PDT 24
Peak memory 208756 kb
Host smart-677e707f-1c72-4443-a652-abb475d0580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668814467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.668814467
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2542472342
Short name T296
Test name
Test status
Simulation time 1687052197 ps
CPU time 36.63 seconds
Started Aug 16 05:52:32 PM PDT 24
Finished Aug 16 05:53:09 PM PDT 24
Peak memory 220476 kb
Host smart-ffc9085d-3ecf-48fe-b669-043cd1e36726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542472342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2542472342
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2412982479
Short name T251
Test name
Test status
Simulation time 42374573 ps
CPU time 2.91 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 218932 kb
Host smart-ef42a840-8d27-4d05-a2e1-32ade1114082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412982479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2412982479
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1689742323
Short name T101
Test name
Test status
Simulation time 234256619 ps
CPU time 5.52 seconds
Started Aug 16 05:52:39 PM PDT 24
Finished Aug 16 05:52:44 PM PDT 24
Peak memory 211136 kb
Host smart-63f970bf-8520-46aa-940e-537182a5498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689742323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1689742323
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1124832584
Short name T396
Test name
Test status
Simulation time 24417952 ps
CPU time 0.7 seconds
Started Aug 16 05:53:49 PM PDT 24
Finished Aug 16 05:53:50 PM PDT 24
Peak memory 206404 kb
Host smart-2e8e597c-b0ea-4ab3-b856-f9980786e251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124832584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1124832584
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1650219309
Short name T385
Test name
Test status
Simulation time 46681048 ps
CPU time 3.21 seconds
Started Aug 16 05:53:20 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 215920 kb
Host smart-55afe967-32dd-4b76-a359-bd625bc29d76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650219309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1650219309
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3786475516
Short name T29
Test name
Test status
Simulation time 735875646 ps
CPU time 2.76 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:26 PM PDT 24
Peak memory 210260 kb
Host smart-36a7adbb-5963-4896-ad43-46754d834755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786475516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3786475516
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2942694660
Short name T729
Test name
Test status
Simulation time 180158757 ps
CPU time 2.59 seconds
Started Aug 16 05:53:52 PM PDT 24
Finished Aug 16 05:53:55 PM PDT 24
Peak memory 207892 kb
Host smart-a877019b-aaff-4bb3-8687-9c515ce91e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942694660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2942694660
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1757124076
Short name T799
Test name
Test status
Simulation time 396430775 ps
CPU time 3.15 seconds
Started Aug 16 05:53:18 PM PDT 24
Finished Aug 16 05:53:21 PM PDT 24
Peak memory 214812 kb
Host smart-982e2757-274d-489c-93ae-4d5e96f9e1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757124076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1757124076
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.616398164
Short name T327
Test name
Test status
Simulation time 2003002661 ps
CPU time 5.4 seconds
Started Aug 16 05:53:59 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 221280 kb
Host smart-ff685fe8-e4fe-4736-8440-f86b7576db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616398164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.616398164
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3841395217
Short name T183
Test name
Test status
Simulation time 346582940 ps
CPU time 4.71 seconds
Started Aug 16 05:53:26 PM PDT 24
Finished Aug 16 05:53:31 PM PDT 24
Peak memory 210252 kb
Host smart-213a7195-4416-48c7-93ae-342220485471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841395217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3841395217
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1449962864
Short name T875
Test name
Test status
Simulation time 94802181 ps
CPU time 3.05 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 208520 kb
Host smart-cae3b8f8-f7e1-4665-84b8-48185830bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449962864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1449962864
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3458409467
Short name T894
Test name
Test status
Simulation time 261289808 ps
CPU time 5.4 seconds
Started Aug 16 05:53:17 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 208468 kb
Host smart-9c60ed09-6aa9-4356-85e0-c7eaa21b86a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458409467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3458409467
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3833207317
Short name T580
Test name
Test status
Simulation time 339000271 ps
CPU time 4.74 seconds
Started Aug 16 05:53:19 PM PDT 24
Finished Aug 16 05:53:24 PM PDT 24
Peak memory 209240 kb
Host smart-8e6dee12-acf1-46e7-87d3-951f5a5de1c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833207317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3833207317
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1046146217
Short name T832
Test name
Test status
Simulation time 1140544670 ps
CPU time 7.62 seconds
Started Aug 16 05:53:42 PM PDT 24
Finished Aug 16 05:53:49 PM PDT 24
Peak memory 208964 kb
Host smart-15025a65-23b2-4337-8824-42101218ede3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046146217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1046146217
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1355863048
Short name T710
Test name
Test status
Simulation time 793838397 ps
CPU time 9.12 seconds
Started Aug 16 05:53:45 PM PDT 24
Finished Aug 16 05:53:54 PM PDT 24
Peak memory 209076 kb
Host smart-d6fe8b39-dfed-4922-b30e-74dc349616e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355863048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1355863048
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1218990969
Short name T221
Test name
Test status
Simulation time 348553034 ps
CPU time 3.26 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 208248 kb
Host smart-0d75537d-c3cf-41a2-8be6-9f1d18722928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218990969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1218990969
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.871826761
Short name T431
Test name
Test status
Simulation time 45533388 ps
CPU time 2.38 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 209204 kb
Host smart-b5ec8512-9730-438f-a6bc-fdf3ab5eb3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871826761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.871826761
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.843474133
Short name T308
Test name
Test status
Simulation time 275405520 ps
CPU time 6.48 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 214824 kb
Host smart-0064fa10-3814-4b0e-a856-55dc63d8725c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843474133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.843474133
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2583325450
Short name T169
Test name
Test status
Simulation time 360138991 ps
CPU time 6.83 seconds
Started Aug 16 05:53:25 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 223012 kb
Host smart-791de27b-466e-47af-a55a-e42a7fd3ff2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583325450 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2583325450
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3178920475
Short name T730
Test name
Test status
Simulation time 244680043 ps
CPU time 6.13 seconds
Started Aug 16 05:53:24 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 209756 kb
Host smart-b9e47da7-2af2-4ccd-b633-6bbd78c38a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178920475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3178920475
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3201835356
Short name T178
Test name
Test status
Simulation time 58961561 ps
CPU time 1.69 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 210200 kb
Host smart-1d71a2fd-312e-4d45-8037-8d4dd1fe00d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201835356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3201835356
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2378855704
Short name T468
Test name
Test status
Simulation time 28653298 ps
CPU time 0.82 seconds
Started Aug 16 05:53:52 PM PDT 24
Finished Aug 16 05:53:53 PM PDT 24
Peak memory 206392 kb
Host smart-d81e9c38-ef92-4dfe-9dda-07fae6ed6c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378855704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2378855704
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3850603598
Short name T249
Test name
Test status
Simulation time 1947665302 ps
CPU time 28.61 seconds
Started Aug 16 05:53:20 PM PDT 24
Finished Aug 16 05:53:49 PM PDT 24
Peak memory 216100 kb
Host smart-494ec33a-232a-4674-8f10-aca166ebe3cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850603598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3850603598
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3708998719
Short name T837
Test name
Test status
Simulation time 845067962 ps
CPU time 4.24 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 221904 kb
Host smart-b5f89aa8-3f2f-49d7-9506-b1e9c9a0fc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708998719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3708998719
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4098081820
Short name T893
Test name
Test status
Simulation time 285729916 ps
CPU time 2.38 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 208028 kb
Host smart-4a1768c3-863c-4377-994b-5d17c97d6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098081820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4098081820
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3984194178
Short name T233
Test name
Test status
Simulation time 116372298 ps
CPU time 2.83 seconds
Started Aug 16 05:54:03 PM PDT 24
Finished Aug 16 05:54:06 PM PDT 24
Peak memory 217080 kb
Host smart-a44c3e34-0f58-4f47-9e54-aa0bdfda748b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984194178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3984194178
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3852458334
Short name T190
Test name
Test status
Simulation time 611167457 ps
CPU time 3.7 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 222980 kb
Host smart-88a62d0e-8182-41f9-81d3-6dbae3358dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852458334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3852458334
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.746652654
Short name T99
Test name
Test status
Simulation time 175733875 ps
CPU time 4.34 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:02 PM PDT 24
Peak memory 214812 kb
Host smart-34054e9b-c784-45c6-b7a7-8066f0d87842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746652654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.746652654
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.396637366
Short name T588
Test name
Test status
Simulation time 677320243 ps
CPU time 5.42 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:28 PM PDT 24
Peak memory 209212 kb
Host smart-2cd48347-abb6-4b76-a600-68e43709ab4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396637366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.396637366
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.239257173
Short name T698
Test name
Test status
Simulation time 3951436493 ps
CPU time 26.05 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 208776 kb
Host smart-17a67d3a-b5a1-4749-9ab8-ea47176c35c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239257173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.239257173
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2280890377
Short name T776
Test name
Test status
Simulation time 71137586 ps
CPU time 2.41 seconds
Started Aug 16 05:53:44 PM PDT 24
Finished Aug 16 05:53:46 PM PDT 24
Peak memory 207336 kb
Host smart-b42104c3-4544-4a36-aa5a-84a8152abe12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280890377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2280890377
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1623699366
Short name T369
Test name
Test status
Simulation time 155473582 ps
CPU time 2.96 seconds
Started Aug 16 05:53:20 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 208172 kb
Host smart-401fc4b5-76e1-48c2-bd75-2d65bfe0d1e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623699366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1623699366
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1191421237
Short name T862
Test name
Test status
Simulation time 525056632 ps
CPU time 16.75 seconds
Started Aug 16 05:53:15 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 209628 kb
Host smart-53a65db3-5b01-4102-af87-6ebd6d27528a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191421237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1191421237
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.743608446
Short name T509
Test name
Test status
Simulation time 62060734 ps
CPU time 2.62 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 207160 kb
Host smart-4afd24c4-f31a-45a9-ba6a-1ea6fe20cc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743608446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.743608446
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1706664313
Short name T842
Test name
Test status
Simulation time 19832530133 ps
CPU time 51.12 seconds
Started Aug 16 05:53:37 PM PDT 24
Finished Aug 16 05:54:29 PM PDT 24
Peak memory 222996 kb
Host smart-9b6dcca6-d17a-42e5-a0d1-9258b82be0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706664313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1706664313
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2385343462
Short name T266
Test name
Test status
Simulation time 2670617111 ps
CPU time 27.32 seconds
Started Aug 16 05:53:47 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 223144 kb
Host smart-8682155a-2b6f-49e6-a814-3992ab03c8f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385343462 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2385343462
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.946552406
Short name T668
Test name
Test status
Simulation time 1788902938 ps
CPU time 9.98 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:33 PM PDT 24
Peak memory 208936 kb
Host smart-836fb989-71de-4c23-8ff4-4e5bdcc80211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946552406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.946552406
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.486238200
Short name T72
Test name
Test status
Simulation time 243499935 ps
CPU time 2.84 seconds
Started Aug 16 05:53:52 PM PDT 24
Finished Aug 16 05:53:55 PM PDT 24
Peak memory 210316 kb
Host smart-06c52354-fff9-4677-b41f-5a0f7862ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486238200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.486238200
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3648503506
Short name T61
Test name
Test status
Simulation time 10636074 ps
CPU time 0.85 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 206424 kb
Host smart-413eba71-e3d1-48f4-a9f3-b3c43e8f3b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648503506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3648503506
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.394046404
Short name T388
Test name
Test status
Simulation time 544165313 ps
CPU time 5.47 seconds
Started Aug 16 05:53:26 PM PDT 24
Finished Aug 16 05:53:31 PM PDT 24
Peak memory 214764 kb
Host smart-a53157de-031d-4e5a-a1d3-970a45adeb17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=394046404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.394046404
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2954066398
Short name T27
Test name
Test status
Simulation time 626562731 ps
CPU time 6.35 seconds
Started Aug 16 05:53:24 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 210364 kb
Host smart-f1cb9a04-c4cc-48d1-acc5-54eb87c3f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954066398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2954066398
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3430900530
Short name T141
Test name
Test status
Simulation time 349654033 ps
CPU time 6.5 seconds
Started Aug 16 05:53:24 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 210272 kb
Host smart-d6fcce7b-8b30-42ec-84ae-f293667724f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430900530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3430900530
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2238549532
Short name T212
Test name
Test status
Simulation time 153583642 ps
CPU time 2.02 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:33 PM PDT 24
Peak memory 214772 kb
Host smart-ce584463-6c39-4f30-8013-752db0e3c498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238549532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2238549532
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2195042618
Short name T733
Test name
Test status
Simulation time 59835277 ps
CPU time 2.01 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 214748 kb
Host smart-d7aafaad-37a1-4d41-93a7-268fc2283bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195042618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2195042618
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2979256503
Short name T688
Test name
Test status
Simulation time 376655733 ps
CPU time 3 seconds
Started Aug 16 05:53:48 PM PDT 24
Finished Aug 16 05:53:52 PM PDT 24
Peak memory 221164 kb
Host smart-b4fd2b06-5f17-46cd-b051-00bbad42ce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979256503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2979256503
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.949787950
Short name T524
Test name
Test status
Simulation time 783442927 ps
CPU time 5.47 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:04 PM PDT 24
Peak memory 208540 kb
Host smart-5518b2b9-e4ca-4912-a63e-cffafc9c82ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949787950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.949787950
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3744042627
Short name T760
Test name
Test status
Simulation time 5401525485 ps
CPU time 35.11 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:54:30 PM PDT 24
Peak memory 209032 kb
Host smart-afbb9fba-8516-4560-bf29-b5c6c096c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744042627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3744042627
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1416839538
Short name T637
Test name
Test status
Simulation time 81237760 ps
CPU time 1.95 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 208076 kb
Host smart-87840298-ace5-4c8d-83d3-c5b2011c51bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416839538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1416839538
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.543761795
Short name T348
Test name
Test status
Simulation time 369252285 ps
CPU time 3.49 seconds
Started Aug 16 05:53:20 PM PDT 24
Finished Aug 16 05:53:24 PM PDT 24
Peak memory 207256 kb
Host smart-93121568-3d28-4fac-8f3c-a33d4d4a5d95
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543761795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.543761795
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2811240011
Short name T371
Test name
Test status
Simulation time 136259392 ps
CPU time 2.53 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 209256 kb
Host smart-6234947c-bd98-43db-a4e2-49f3e87707f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811240011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2811240011
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3370695493
Short name T859
Test name
Test status
Simulation time 793790794 ps
CPU time 4.43 seconds
Started Aug 16 05:53:37 PM PDT 24
Finished Aug 16 05:53:42 PM PDT 24
Peak memory 210244 kb
Host smart-1715da8d-1263-4e9c-9347-9e94a404d40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370695493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3370695493
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3066274595
Short name T405
Test name
Test status
Simulation time 1879777913 ps
CPU time 3.61 seconds
Started Aug 16 05:53:19 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 207328 kb
Host smart-3de249fd-449f-4ca3-8f48-5f3ca20006e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066274595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3066274595
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1755385176
Short name T329
Test name
Test status
Simulation time 631499275 ps
CPU time 13.86 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:54:12 PM PDT 24
Peak memory 215500 kb
Host smart-c798724d-4b1c-4c5c-82c8-117c91189d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755385176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1755385176
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.92396239
Short name T79
Test name
Test status
Simulation time 611320510 ps
CPU time 14.29 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:42 PM PDT 24
Peak memory 222924 kb
Host smart-d6e6ae7e-f2e4-4d17-87a0-3324d8bb71d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92396239 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.92396239
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.305518041
Short name T23
Test name
Test status
Simulation time 35200064 ps
CPU time 2.59 seconds
Started Aug 16 05:53:54 PM PDT 24
Finished Aug 16 05:53:57 PM PDT 24
Peak memory 207928 kb
Host smart-bb174b77-7ed0-4ae2-ae94-2467c313697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305518041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.305518041
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.243865126
Short name T360
Test name
Test status
Simulation time 61301955 ps
CPU time 1.59 seconds
Started Aug 16 05:53:21 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 210188 kb
Host smart-95a6444c-693f-4856-859c-04e6cba114b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243865126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.243865126
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2470218905
Short name T575
Test name
Test status
Simulation time 14528104 ps
CPU time 0.81 seconds
Started Aug 16 05:53:59 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 206496 kb
Host smart-6a96a3e0-4fc3-45eb-a847-3c2026065780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470218905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2470218905
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1411014775
Short name T505
Test name
Test status
Simulation time 251528527 ps
CPU time 5.49 seconds
Started Aug 16 05:53:24 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 209980 kb
Host smart-48c5163f-bab5-4dea-8dcd-cd96cc101705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411014775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1411014775
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3418127218
Short name T497
Test name
Test status
Simulation time 595160851 ps
CPU time 4.71 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 208696 kb
Host smart-68a02c69-f2b9-4a3d-a7ec-14bf765b583d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418127218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3418127218
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2528483482
Short name T562
Test name
Test status
Simulation time 73141011 ps
CPU time 3.31 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 222828 kb
Host smart-bf41e84c-2930-4cec-9783-add4b0f471dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528483482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2528483482
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2201199167
Short name T589
Test name
Test status
Simulation time 97387806 ps
CPU time 3.51 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 211172 kb
Host smart-0049d8cb-aa13-42ff-a085-879c901a9207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201199167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2201199167
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_random.798195450
Short name T208
Test name
Test status
Simulation time 321876259 ps
CPU time 3.77 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:26 PM PDT 24
Peak memory 209640 kb
Host smart-fd5fb942-ef16-4f66-a4a6-6289ff2a7f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798195450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.798195450
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.83934115
Short name T903
Test name
Test status
Simulation time 73994070 ps
CPU time 3.06 seconds
Started Aug 16 05:53:53 PM PDT 24
Finished Aug 16 05:53:56 PM PDT 24
Peak memory 208560 kb
Host smart-9cf167de-763c-405b-a86a-3cec20782285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83934115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.83934115
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1841848040
Short name T353
Test name
Test status
Simulation time 907520694 ps
CPU time 24.09 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:46 PM PDT 24
Peak memory 208768 kb
Host smart-de143369-7dbf-47b3-addc-67df8301767a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841848040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1841848040
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4179479584
Short name T841
Test name
Test status
Simulation time 94390957 ps
CPU time 3.2 seconds
Started Aug 16 05:53:20 PM PDT 24
Finished Aug 16 05:53:24 PM PDT 24
Peak memory 207244 kb
Host smart-e90b4632-a67a-4dcf-a895-b17ef9c84566
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179479584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4179479584
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4035022134
Short name T632
Test name
Test status
Simulation time 27546536 ps
CPU time 2.25 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:53:58 PM PDT 24
Peak memory 209296 kb
Host smart-95db86d3-6c4f-4529-aaf2-c98b610bb477
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035022134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4035022134
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3034255143
Short name T742
Test name
Test status
Simulation time 143889128 ps
CPU time 2.01 seconds
Started Aug 16 05:53:25 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 209488 kb
Host smart-ec6ac63b-ca4f-46e8-9cb7-7dbc2682e63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034255143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3034255143
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3986550314
Short name T772
Test name
Test status
Simulation time 22198724 ps
CPU time 1.58 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 207488 kb
Host smart-ac4571ae-b64b-4dd3-bac9-db78d286caba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986550314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3986550314
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1110645991
Short name T265
Test name
Test status
Simulation time 60691120 ps
CPU time 3.65 seconds
Started Aug 16 05:54:12 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 216804 kb
Host smart-3fa246cd-8f7e-42e8-91a7-29c77132e70c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110645991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1110645991
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4743089
Short name T253
Test name
Test status
Simulation time 216573526 ps
CPU time 5.26 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 210612 kb
Host smart-be30cd91-0c5f-4fd6-81b5-69e6b270e63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4743089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4743089
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2775338405
Short name T821
Test name
Test status
Simulation time 120528344 ps
CPU time 2.8 seconds
Started Aug 16 05:53:41 PM PDT 24
Finished Aug 16 05:53:44 PM PDT 24
Peak memory 210308 kb
Host smart-4d6dd71d-0e02-4161-bb45-facedea6cb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775338405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2775338405
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3000051493
Short name T720
Test name
Test status
Simulation time 12316074 ps
CPU time 0.81 seconds
Started Aug 16 05:54:01 PM PDT 24
Finished Aug 16 05:54:02 PM PDT 24
Peak memory 206260 kb
Host smart-f4b47c5f-517c-4d72-9a1d-72f489ad306b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000051493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3000051493
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.142930461
Short name T758
Test name
Test status
Simulation time 83151030 ps
CPU time 3.34 seconds
Started Aug 16 05:54:01 PM PDT 24
Finished Aug 16 05:54:04 PM PDT 24
Peak memory 222360 kb
Host smart-6e296047-3ee6-4c78-bb4c-c70f60847758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142930461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.142930461
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2698312849
Short name T804
Test name
Test status
Simulation time 403914198 ps
CPU time 4.31 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 218844 kb
Host smart-0619cdb3-f27f-46e0-af35-336a4e6b90bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698312849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2698312849
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2891287493
Short name T790
Test name
Test status
Simulation time 23288113 ps
CPU time 2 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:54:04 PM PDT 24
Peak memory 214856 kb
Host smart-8029d9b6-deb7-4b8c-a030-edefffbad607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891287493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2891287493
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1837124548
Short name T298
Test name
Test status
Simulation time 553597220 ps
CPU time 2.56 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:31 PM PDT 24
Peak memory 222772 kb
Host smart-133f14b6-199a-48b9-8b0e-c75091c0d735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837124548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1837124548
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3037292194
Short name T454
Test name
Test status
Simulation time 122572509 ps
CPU time 3.83 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 218728 kb
Host smart-a2b1e9d5-6582-4868-a035-e94729ef0fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037292194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3037292194
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3644327848
Short name T207
Test name
Test status
Simulation time 277984482 ps
CPU time 3.34 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 209148 kb
Host smart-08bb2ddc-7d0e-42e3-8a6c-a0fbe7004485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644327848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3644327848
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.111970289
Short name T544
Test name
Test status
Simulation time 1209876803 ps
CPU time 18.72 seconds
Started Aug 16 05:53:53 PM PDT 24
Finished Aug 16 05:54:12 PM PDT 24
Peak memory 208536 kb
Host smart-52d43d48-b2ef-4b7e-acc2-42e5b50abc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111970289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.111970289
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2974607579
Short name T149
Test name
Test status
Simulation time 1457604182 ps
CPU time 12.26 seconds
Started Aug 16 05:53:42 PM PDT 24
Finished Aug 16 05:53:54 PM PDT 24
Peak memory 209236 kb
Host smart-0722f835-3142-438c-a455-994ad12c2afa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974607579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2974607579
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1112212667
Short name T569
Test name
Test status
Simulation time 203341912 ps
CPU time 7.47 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 209080 kb
Host smart-7ba6829e-130f-431c-8eaf-4fc5931cc043
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112212667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1112212667
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.365665940
Short name T310
Test name
Test status
Simulation time 127767147 ps
CPU time 3.24 seconds
Started Aug 16 05:53:25 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 209412 kb
Host smart-e2281d3a-72e3-43ac-9a50-1a25fa5661eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365665940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.365665940
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1933389372
Short name T4
Test name
Test status
Simulation time 191061106 ps
CPU time 2.63 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 209864 kb
Host smart-6717cea7-2e0e-4634-9893-2f2afcbc3ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933389372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1933389372
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.978339423
Short name T401
Test name
Test status
Simulation time 36981821 ps
CPU time 1.58 seconds
Started Aug 16 05:53:25 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 207292 kb
Host smart-024a2d0a-4abf-40c5-9823-24d890957d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978339423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.978339423
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3689177724
Short name T281
Test name
Test status
Simulation time 1730075547 ps
CPU time 21.51 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:50 PM PDT 24
Peak memory 217156 kb
Host smart-9cd8a7d2-735b-4558-b11c-362d7e744706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689177724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3689177724
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1137787776
Short name T651
Test name
Test status
Simulation time 613645022 ps
CPU time 14.37 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:44 PM PDT 24
Peak memory 222984 kb
Host smart-9fa46dc1-5e9c-47fd-8bb8-cdaeff96c238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137787776 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1137787776
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1558310798
Short name T815
Test name
Test status
Simulation time 108442889 ps
CPU time 4.77 seconds
Started Aug 16 05:53:53 PM PDT 24
Finished Aug 16 05:53:59 PM PDT 24
Peak memory 208532 kb
Host smart-0162f7de-784e-4a30-ad2b-e9c8ec1c7a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558310798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1558310798
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1933525218
Short name T411
Test name
Test status
Simulation time 20044711 ps
CPU time 0.74 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 206392 kb
Host smart-2fa3bc2b-f1be-4167-879b-4097a05a1c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933525218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1933525218
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.4231095591
Short name T339
Test name
Test status
Simulation time 1259376271 ps
CPU time 30.12 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 214824 kb
Host smart-910f4d70-608c-4c21-b96a-bc2acaf22a0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231095591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.4231095591
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2081764669
Short name T735
Test name
Test status
Simulation time 142772533 ps
CPU time 5.33 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 210696 kb
Host smart-c08507e6-73f1-45b4-ad8c-051b7b36e2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081764669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2081764669
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1607846203
Short name T340
Test name
Test status
Simulation time 978619836 ps
CPU time 15.1 seconds
Started Aug 16 05:53:54 PM PDT 24
Finished Aug 16 05:54:09 PM PDT 24
Peak memory 220304 kb
Host smart-78d72bd8-e4f0-4038-b285-656caf357161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607846203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1607846203
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.4184731252
Short name T261
Test name
Test status
Simulation time 117636807 ps
CPU time 3.07 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:53:59 PM PDT 24
Peak memory 214796 kb
Host smart-6d0d8dfa-54fa-4fbf-aa47-944c81dfab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184731252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4184731252
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2041663881
Short name T66
Test name
Test status
Simulation time 425953571 ps
CPU time 3.66 seconds
Started Aug 16 05:53:51 PM PDT 24
Finished Aug 16 05:53:55 PM PDT 24
Peak memory 214708 kb
Host smart-794472a1-b2c8-4fcc-ad48-8453fdfe8d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041663881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2041663881
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1595073020
Short name T200
Test name
Test status
Simulation time 575142749 ps
CPU time 2.53 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 216496 kb
Host smart-00cf290f-c280-4ba0-ba6a-f3ac1a2fca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595073020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1595073020
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3633570069
Short name T513
Test name
Test status
Simulation time 600503948 ps
CPU time 13.24 seconds
Started Aug 16 05:54:08 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 218844 kb
Host smart-550f2b33-c0b4-48b2-934b-c6adc55e4355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633570069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3633570069
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3088922080
Short name T658
Test name
Test status
Simulation time 144180322 ps
CPU time 4.31 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:33 PM PDT 24
Peak memory 209300 kb
Host smart-19524973-1243-45cd-8576-e698cbf184f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088922080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3088922080
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2184578967
Short name T2
Test name
Test status
Simulation time 1426939334 ps
CPU time 17.19 seconds
Started Aug 16 05:53:21 PM PDT 24
Finished Aug 16 05:53:39 PM PDT 24
Peak memory 208808 kb
Host smart-0af04326-eb7e-436e-9e79-8204d5867367
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184578967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2184578967
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2966201251
Short name T644
Test name
Test status
Simulation time 60490617 ps
CPU time 2.62 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:53:57 PM PDT 24
Peak memory 207304 kb
Host smart-6fbd75fe-a350-4d29-adfc-f0caba4dc8c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966201251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2966201251
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3328336124
Short name T595
Test name
Test status
Simulation time 990537740 ps
CPU time 3.51 seconds
Started Aug 16 05:53:54 PM PDT 24
Finished Aug 16 05:53:58 PM PDT 24
Peak memory 207308 kb
Host smart-03646cfa-154e-425d-80d5-d9c9f41ddefd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328336124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3328336124
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2342461715
Short name T532
Test name
Test status
Simulation time 118283864 ps
CPU time 3.54 seconds
Started Aug 16 05:53:28 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 214716 kb
Host smart-e8b5f5be-c71a-4e51-80c3-91bdb8bbb7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342461715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2342461715
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1749203670
Short name T786
Test name
Test status
Simulation time 282625063 ps
CPU time 3.2 seconds
Started Aug 16 05:53:54 PM PDT 24
Finished Aug 16 05:53:57 PM PDT 24
Peak memory 208940 kb
Host smart-b8709379-c8c9-42ee-a7a4-e0ef7fc06ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749203670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1749203670
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3720222052
Short name T480
Test name
Test status
Simulation time 661738047 ps
CPU time 15.55 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:54:12 PM PDT 24
Peak memory 209728 kb
Host smart-369924b1-2071-4229-a48a-27a48f1fff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720222052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3720222052
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1552129916
Short name T37
Test name
Test status
Simulation time 407397517 ps
CPU time 9.46 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 211524 kb
Host smart-416752fe-4345-46f6-9cec-3d7ddf5a2e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552129916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1552129916
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.579525624
Short name T552
Test name
Test status
Simulation time 43053387 ps
CPU time 0.87 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:53:58 PM PDT 24
Peak memory 206412 kb
Host smart-06c68f19-7f3b-44c3-90af-9280c10a4a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579525624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.579525624
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.756515905
Short name T201
Test name
Test status
Simulation time 114144820 ps
CPU time 4.79 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 215036 kb
Host smart-c59d4503-ce65-49d2-b063-aa4da04c5191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756515905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.756515905
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1716342896
Short name T556
Test name
Test status
Simulation time 78744816 ps
CPU time 2.73 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:03 PM PDT 24
Peak memory 210644 kb
Host smart-de558117-f094-4dd1-b884-017631fd65ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716342896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1716342896
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.256443624
Short name T229
Test name
Test status
Simulation time 33010621 ps
CPU time 1.74 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 214720 kb
Host smart-16dab995-92b3-4b44-bfdb-1196c3bf7e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256443624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.256443624
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.4234057497
Short name T708
Test name
Test status
Simulation time 404664079 ps
CPU time 3.29 seconds
Started Aug 16 05:54:21 PM PDT 24
Finished Aug 16 05:54:24 PM PDT 24
Peak memory 210372 kb
Host smart-482f19be-3c2d-4747-864b-3c470f9f45c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234057497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.4234057497
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2707840296
Short name T312
Test name
Test status
Simulation time 768481095 ps
CPU time 5.77 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:06 PM PDT 24
Peak memory 214748 kb
Host smart-b2b3b685-36eb-462f-b9ae-816d34003870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707840296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2707840296
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.260035872
Short name T451
Test name
Test status
Simulation time 140269587 ps
CPU time 2.96 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 207272 kb
Host smart-af344367-a13b-4f70-8c54-da123fea10cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260035872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.260035872
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2557775418
Short name T534
Test name
Test status
Simulation time 95507417 ps
CPU time 2.35 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:33 PM PDT 24
Peak memory 207304 kb
Host smart-cfa38986-ed30-42eb-b66e-d11dc0024263
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557775418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2557775418
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2072933484
Short name T679
Test name
Test status
Simulation time 110959100 ps
CPU time 2.24 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:53:58 PM PDT 24
Peak memory 207928 kb
Host smart-315214d7-4008-4227-a3a1-b49f9f96cf36
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072933484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2072933484
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1671530053
Short name T150
Test name
Test status
Simulation time 1803610045 ps
CPU time 23.53 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:54 PM PDT 24
Peak memory 209384 kb
Host smart-f6b6c661-ebe5-446d-ba6e-c0ceae94a64c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671530053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1671530053
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1309900738
Short name T278
Test name
Test status
Simulation time 124929146 ps
CPU time 2.6 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:35 PM PDT 24
Peak memory 210552 kb
Host smart-92b402e1-efeb-46c7-b244-9d0e937f9bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309900738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1309900738
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2292212026
Short name T501
Test name
Test status
Simulation time 2019604855 ps
CPU time 4.68 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 208068 kb
Host smart-de1b1bec-1e8b-4359-8e18-f8d2b2e8e7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292212026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2292212026
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.4254941633
Short name T623
Test name
Test status
Simulation time 328939479 ps
CPU time 17.95 seconds
Started Aug 16 05:53:59 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 221540 kb
Host smart-e6d0517d-9d82-4a72-85f0-fa505ce726e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254941633 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.4254941633
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1552834822
Short name T209
Test name
Test status
Simulation time 82902317 ps
CPU time 3.86 seconds
Started Aug 16 05:53:29 PM PDT 24
Finished Aug 16 05:53:33 PM PDT 24
Peak memory 208284 kb
Host smart-a19f9fa5-1cbb-4039-8259-0687622dfef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552834822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1552834822
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.316753295
Short name T364
Test name
Test status
Simulation time 102411664 ps
CPU time 2.13 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:53:57 PM PDT 24
Peak memory 210816 kb
Host smart-f9b32c1d-ffbe-44ed-af03-b09af2ea75d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316753295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.316753295
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3900556772
Short name T908
Test name
Test status
Simulation time 10202061 ps
CPU time 0.75 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 206400 kb
Host smart-758f3f8e-5a65-4871-87fa-1f4ab7f87c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900556772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3900556772
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.706151425
Short name T205
Test name
Test status
Simulation time 76481334 ps
CPU time 4.03 seconds
Started Aug 16 05:54:07 PM PDT 24
Finished Aug 16 05:54:11 PM PDT 24
Peak memory 214792 kb
Host smart-4e8c83a7-e57b-4002-9082-11656b91d9b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706151425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.706151425
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1314614767
Short name T67
Test name
Test status
Simulation time 233144010 ps
CPU time 3.41 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 214772 kb
Host smart-f4ede380-be7a-4c6e-8111-7e867cc370ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314614767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1314614767
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1403647293
Short name T590
Test name
Test status
Simulation time 27046197 ps
CPU time 1.34 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:31 PM PDT 24
Peak memory 207596 kb
Host smart-72bad92b-b509-42c2-a694-5f7b8efb87da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403647293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1403647293
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.275549923
Short name T773
Test name
Test status
Simulation time 3779892382 ps
CPU time 67.99 seconds
Started Aug 16 05:53:54 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 214868 kb
Host smart-1dfa6d47-4388-4c36-8150-e080d6075a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275549923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.275549923
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1150005331
Short name T755
Test name
Test status
Simulation time 1287811908 ps
CPU time 6.02 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:39 PM PDT 24
Peak memory 222928 kb
Host smart-72f3eb98-9788-4f57-9303-857eda095de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150005331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1150005331
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1693778479
Short name T880
Test name
Test status
Simulation time 650411419 ps
CPU time 5.06 seconds
Started Aug 16 05:53:26 PM PDT 24
Finished Aug 16 05:53:31 PM PDT 24
Peak memory 210532 kb
Host smart-44830e7c-4f78-48ce-ba2c-4073bf986a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693778479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1693778479
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3974133107
Short name T240
Test name
Test status
Simulation time 92677954 ps
CPU time 3.21 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:03 PM PDT 24
Peak memory 209212 kb
Host smart-1078ec41-3f3d-4fd5-9a62-4553eaf540b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974133107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3974133107
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2290732048
Short name T436
Test name
Test status
Simulation time 93051661 ps
CPU time 1.87 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 207448 kb
Host smart-a04062cf-31e0-4562-9c65-7a8af5a6de34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290732048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2290732048
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2481396262
Short name T494
Test name
Test status
Simulation time 897634400 ps
CPU time 22.51 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 208876 kb
Host smart-a97ab42f-0901-41f0-8def-321edd6cce7b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481396262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2481396262
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4188623678
Short name T827
Test name
Test status
Simulation time 1077622895 ps
CPU time 6.69 seconds
Started Aug 16 05:53:52 PM PDT 24
Finished Aug 16 05:53:59 PM PDT 24
Peak memory 208872 kb
Host smart-e09d4d68-71d6-4580-bbca-5522c5fb1d45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188623678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4188623678
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2860276971
Short name T559
Test name
Test status
Simulation time 36866704 ps
CPU time 2.04 seconds
Started Aug 16 05:53:27 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 209804 kb
Host smart-656baa81-2981-4e33-9948-0f863dac7b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860276971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2860276971
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2295565308
Short name T399
Test name
Test status
Simulation time 48306054 ps
CPU time 2.33 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 207232 kb
Host smart-72fca0e4-34c9-4ec9-ba95-516b6b5151b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295565308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2295565308
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1223517366
Short name T170
Test name
Test status
Simulation time 253262439 ps
CPU time 8.39 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 222952 kb
Host smart-2b72f7f4-884d-4424-a913-cf23958d6f4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223517366 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1223517366
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3980679819
Short name T639
Test name
Test status
Simulation time 5898629501 ps
CPU time 39.11 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 218748 kb
Host smart-9eb105dd-5e82-4abd-a13f-04feb8806bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980679819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3980679819
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2710955297
Short name T520
Test name
Test status
Simulation time 174122433 ps
CPU time 2.19 seconds
Started Aug 16 05:54:03 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 210684 kb
Host smart-d02646d7-18cb-428d-b2b3-96642bad65b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710955297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2710955297
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.4237417692
Short name T578
Test name
Test status
Simulation time 17012954 ps
CPU time 0.76 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 206436 kb
Host smart-80ffd249-cc24-488c-8ca1-9d6d79d8e913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237417692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.4237417692
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.367136978
Short name T43
Test name
Test status
Simulation time 188455607 ps
CPU time 3.84 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:24 PM PDT 24
Peak memory 209492 kb
Host smart-c5ca680d-51f2-4838-88f2-9c7d1d749704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367136978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.367136978
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.946761135
Short name T270
Test name
Test status
Simulation time 143875127 ps
CPU time 4.26 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 218704 kb
Host smart-5289eee6-5844-4236-9808-4367039cccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946761135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.946761135
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3901763224
Short name T762
Test name
Test status
Simulation time 642078135 ps
CPU time 5.1 seconds
Started Aug 16 05:53:35 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 214752 kb
Host smart-950faab2-8a94-4624-8c13-3c2be6fc9f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901763224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3901763224
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2531682177
Short name T301
Test name
Test status
Simulation time 97705393 ps
CPU time 2.99 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 214820 kb
Host smart-328b8f98-911b-4879-ad4d-07fad8ee9182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531682177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2531682177
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.42610262
Short name T477
Test name
Test status
Simulation time 119967518 ps
CPU time 3.04 seconds
Started Aug 16 05:53:29 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 210024 kb
Host smart-4207b119-ec1b-47c0-b4c9-969a33b51a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42610262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.42610262
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1225482064
Short name T393
Test name
Test status
Simulation time 96545167 ps
CPU time 4.17 seconds
Started Aug 16 05:54:04 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 214656 kb
Host smart-6c42d3dc-aab2-4362-9bfe-73e9b8c984d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225482064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1225482064
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3781191137
Short name T442
Test name
Test status
Simulation time 39430366 ps
CPU time 2.26 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:53:59 PM PDT 24
Peak memory 207496 kb
Host smart-368dec14-fdb5-4dcc-9cfa-c8042c5eb0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781191137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3781191137
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1446111518
Short name T432
Test name
Test status
Simulation time 145495410 ps
CPU time 4.37 seconds
Started Aug 16 05:54:04 PM PDT 24
Finished Aug 16 05:54:09 PM PDT 24
Peak memory 207360 kb
Host smart-b7dcf1c7-ab48-4b02-a82a-2c04043ac0a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446111518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1446111518
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4056030260
Short name T687
Test name
Test status
Simulation time 88945143 ps
CPU time 2.32 seconds
Started Aug 16 05:54:01 PM PDT 24
Finished Aug 16 05:54:03 PM PDT 24
Peak memory 209380 kb
Host smart-a63aa163-9a85-4cd0-a4c0-7d69a30eb490
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056030260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4056030260
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.582238528
Short name T548
Test name
Test status
Simulation time 319697295 ps
CPU time 3.66 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 209412 kb
Host smart-76bd11aa-4bc7-4de0-8ebf-d3c4133d4972
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582238528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.582238528
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2259596809
Short name T736
Test name
Test status
Simulation time 273574709 ps
CPU time 3.5 seconds
Started Aug 16 05:53:45 PM PDT 24
Finished Aug 16 05:53:48 PM PDT 24
Peak memory 211088 kb
Host smart-19f7b051-37e9-4a46-894f-962dcaef0733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259596809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2259596809
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.63216045
Short name T900
Test name
Test status
Simulation time 179338851 ps
CPU time 2.84 seconds
Started Aug 16 05:53:51 PM PDT 24
Finished Aug 16 05:53:54 PM PDT 24
Peak memory 209028 kb
Host smart-41983b9a-d43e-4844-adfe-1da211bdb220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63216045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.63216045
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.4012240829
Short name T897
Test name
Test status
Simulation time 1392613989 ps
CPU time 45.68 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 216952 kb
Host smart-9b614bd8-08d2-434c-9b27-583a62f763bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012240829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.4012240829
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2527866375
Short name T610
Test name
Test status
Simulation time 62708269 ps
CPU time 4.38 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 222888 kb
Host smart-08fd75b2-9e74-4ea9-a864-24a0ea734e8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527866375 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2527866375
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1817236386
Short name T715
Test name
Test status
Simulation time 379197971 ps
CPU time 6.16 seconds
Started Aug 16 05:53:41 PM PDT 24
Finished Aug 16 05:53:47 PM PDT 24
Peak memory 210436 kb
Host smart-5222c882-60d4-4ff4-b2b1-afabba17e652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817236386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1817236386
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3304337202
Short name T884
Test name
Test status
Simulation time 75026328 ps
CPU time 1.95 seconds
Started Aug 16 05:54:10 PM PDT 24
Finished Aug 16 05:54:12 PM PDT 24
Peak memory 210460 kb
Host smart-3d87035f-1ceb-491e-b2f9-cf86dae1f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304337202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3304337202
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2612632957
Short name T527
Test name
Test status
Simulation time 15237013 ps
CPU time 0.72 seconds
Started Aug 16 05:54:02 PM PDT 24
Finished Aug 16 05:54:02 PM PDT 24
Peak memory 206244 kb
Host smart-02f709c8-249e-4d89-bb46-f6c8e4477432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612632957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2612632957
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.600645355
Short name T389
Test name
Test status
Simulation time 147150528 ps
CPU time 4.09 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 214724 kb
Host smart-6e271dbd-2027-4c12-81c0-4ff485a76673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600645355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.600645355
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1150094333
Short name T193
Test name
Test status
Simulation time 209799993 ps
CPU time 3.28 seconds
Started Aug 16 05:54:14 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 218848 kb
Host smart-1377210b-c88c-4f5d-ba39-a00dd38c7443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150094333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1150094333
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.362114974
Short name T634
Test name
Test status
Simulation time 46284254 ps
CPU time 1.81 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:53:59 PM PDT 24
Peak memory 214800 kb
Host smart-cb8f1c6f-abea-4b39-817c-5f1c019e6c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362114974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.362114974
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.922430683
Short name T263
Test name
Test status
Simulation time 70426214 ps
CPU time 2.35 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 214724 kb
Host smart-b651bc60-f75f-4176-8a5c-df5b829ec8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922430683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.922430683
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.4068908859
Short name T669
Test name
Test status
Simulation time 572923065 ps
CPU time 3.85 seconds
Started Aug 16 05:54:14 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 209236 kb
Host smart-04af8cca-537a-4312-9f0e-707ee7878aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068908859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.4068908859
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3012988349
Short name T542
Test name
Test status
Simulation time 1011768141 ps
CPU time 24.73 seconds
Started Aug 16 05:53:34 PM PDT 24
Finished Aug 16 05:54:03 PM PDT 24
Peak memory 214756 kb
Host smart-af529778-486b-4b5e-8c65-58bf86aca4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012988349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3012988349
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3416299241
Short name T649
Test name
Test status
Simulation time 39510483 ps
CPU time 2.42 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 208776 kb
Host smart-531c87c8-6e93-4cd6-99ed-9f04deda2b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416299241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3416299241
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.910098480
Short name T244
Test name
Test status
Simulation time 154691386 ps
CPU time 2.69 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 208900 kb
Host smart-273ebecd-65ad-4184-b635-08ec88c0a703
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910098480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.910098480
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1899732554
Short name T604
Test name
Test status
Simulation time 196299599 ps
CPU time 2.79 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 209100 kb
Host smart-c7c0b211-b772-4bf6-a85d-c6a2fd5e02b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899732554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1899732554
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.68135646
Short name T680
Test name
Test status
Simulation time 1058035048 ps
CPU time 14.44 seconds
Started Aug 16 05:54:04 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 208860 kb
Host smart-e20a1eda-82c7-42a2-bd3e-0acc2722bc04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68135646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.68135646
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2112784504
Short name T831
Test name
Test status
Simulation time 56760549 ps
CPU time 1.66 seconds
Started Aug 16 05:54:25 PM PDT 24
Finished Aug 16 05:54:27 PM PDT 24
Peak memory 207988 kb
Host smart-55f91a01-8b3f-4445-9d20-102c5c3199eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112784504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2112784504
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.377121737
Short name T785
Test name
Test status
Simulation time 281729854 ps
CPU time 2.95 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:03 PM PDT 24
Peak memory 209172 kb
Host smart-f7ff343e-3972-43a9-b873-675d5582b622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377121737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.377121737
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.739297279
Short name T247
Test name
Test status
Simulation time 10540051195 ps
CPU time 49.54 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:55:09 PM PDT 24
Peak memory 222992 kb
Host smart-235e38e0-145a-4eca-99d1-cc0cd5347d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739297279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.739297279
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.4246517460
Short name T803
Test name
Test status
Simulation time 806424928 ps
CPU time 4.89 seconds
Started Aug 16 05:54:26 PM PDT 24
Finished Aug 16 05:54:31 PM PDT 24
Peak memory 220392 kb
Host smart-1f204ff0-b692-4553-8fd0-aec4b3cf9777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246517460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.4246517460
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1829979852
Short name T476
Test name
Test status
Simulation time 106544222 ps
CPU time 2.02 seconds
Started Aug 16 05:53:45 PM PDT 24
Finished Aug 16 05:53:47 PM PDT 24
Peak memory 210312 kb
Host smart-937996b4-1b99-4364-ae33-e4443fc58005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829979852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1829979852
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2885296332
Short name T873
Test name
Test status
Simulation time 13031481 ps
CPU time 0.7 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:10 PM PDT 24
Peak memory 206256 kb
Host smart-88c86077-0434-4492-a9bc-ab2765363fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885296332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2885296332
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1756374277
Short name T36
Test name
Test status
Simulation time 362010738 ps
CPU time 3.86 seconds
Started Aug 16 05:52:35 PM PDT 24
Finished Aug 16 05:52:39 PM PDT 24
Peak memory 221720 kb
Host smart-139f696f-fda6-4637-ae41-79033da0f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756374277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1756374277
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.968077593
Short name T902
Test name
Test status
Simulation time 71072232 ps
CPU time 3.02 seconds
Started Aug 16 05:53:05 PM PDT 24
Finished Aug 16 05:53:08 PM PDT 24
Peak memory 211024 kb
Host smart-86736730-1dee-47aa-89ea-0585f97d2483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968077593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.968077593
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.247774647
Short name T57
Test name
Test status
Simulation time 199738147 ps
CPU time 5.03 seconds
Started Aug 16 05:52:43 PM PDT 24
Finished Aug 16 05:52:48 PM PDT 24
Peak memory 209612 kb
Host smart-f3200276-74e3-44d8-a4e8-c433a8f668c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247774647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.247774647
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.341364870
Short name T824
Test name
Test status
Simulation time 277732919 ps
CPU time 3.67 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:14 PM PDT 24
Peak memory 211656 kb
Host smart-2fc457d7-f92c-48ed-b632-c196075a531e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341364870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.341364870
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1020001222
Short name T782
Test name
Test status
Simulation time 144187856 ps
CPU time 4.34 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:26 PM PDT 24
Peak memory 220612 kb
Host smart-f1541ba9-c021-42de-8b49-fb8298977a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020001222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1020001222
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1432758520
Short name T489
Test name
Test status
Simulation time 103795173 ps
CPU time 4.72 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:16 PM PDT 24
Peak memory 209124 kb
Host smart-41cef72c-8c47-4021-a6e9-ec01b6e4390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432758520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1432758520
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3123547250
Short name T330
Test name
Test status
Simulation time 728545210 ps
CPU time 8.84 seconds
Started Aug 16 05:52:43 PM PDT 24
Finished Aug 16 05:52:52 PM PDT 24
Peak memory 208884 kb
Host smart-65a93b1c-84c4-4d61-afef-e794e2dd0ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123547250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3123547250
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2663713153
Short name T493
Test name
Test status
Simulation time 330761072 ps
CPU time 4.79 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:16 PM PDT 24
Peak memory 209296 kb
Host smart-d4cefc34-d014-4d4a-bb2f-e685eb3ef4f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663713153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2663713153
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.624882582
Short name T684
Test name
Test status
Simulation time 47554181 ps
CPU time 2.45 seconds
Started Aug 16 05:52:38 PM PDT 24
Finished Aug 16 05:52:41 PM PDT 24
Peak memory 207200 kb
Host smart-7efb43bb-b7ec-48d4-810f-f4aff9949169
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624882582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.624882582
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2389340554
Short name T711
Test name
Test status
Simulation time 468967879 ps
CPU time 3.65 seconds
Started Aug 16 05:53:01 PM PDT 24
Finished Aug 16 05:53:05 PM PDT 24
Peak memory 209284 kb
Host smart-01ca5a8b-a47a-486c-9f8e-7691a8012a8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389340554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2389340554
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1462044396
Short name T11
Test name
Test status
Simulation time 283086369 ps
CPU time 2.79 seconds
Started Aug 16 05:52:42 PM PDT 24
Finished Aug 16 05:52:45 PM PDT 24
Peak memory 209524 kb
Host smart-64ec380b-c249-4e50-afe7-4f520fd6561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462044396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1462044396
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2757476692
Short name T526
Test name
Test status
Simulation time 47155887 ps
CPU time 1.84 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 208924 kb
Host smart-e8a45831-007f-4c1e-a569-bb8959489799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757476692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2757476692
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.840149043
Short name T196
Test name
Test status
Simulation time 1583805441 ps
CPU time 52.49 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:54:25 PM PDT 24
Peak memory 222892 kb
Host smart-adcbcdb4-88b8-40d7-a2f1-4efecb73d838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840149043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.840149043
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.821518157
Short name T70
Test name
Test status
Simulation time 394147170 ps
CPU time 18.99 seconds
Started Aug 16 05:53:04 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 222956 kb
Host smart-44318bef-e56c-49d7-8837-e5366bc546b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821518157 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.821518157
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3080193587
Short name T287
Test name
Test status
Simulation time 1895203410 ps
CPU time 4.69 seconds
Started Aug 16 05:53:05 PM PDT 24
Finished Aug 16 05:53:10 PM PDT 24
Peak memory 208176 kb
Host smart-19226047-f093-41a8-9f8b-5aa74493b1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080193587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3080193587
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3350433386
Short name T864
Test name
Test status
Simulation time 40851732 ps
CPU time 1.99 seconds
Started Aug 16 05:52:37 PM PDT 24
Finished Aug 16 05:52:39 PM PDT 24
Peak memory 210544 kb
Host smart-6964ac2f-fde8-4461-8fe0-c1a0a0509a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350433386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3350433386
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3367298799
Short name T144
Test name
Test status
Simulation time 11892250 ps
CPU time 0.77 seconds
Started Aug 16 05:53:48 PM PDT 24
Finished Aug 16 05:53:49 PM PDT 24
Peak memory 206548 kb
Host smart-691fa6e0-8425-4221-801d-f835f4247b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367298799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3367298799
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.926609216
Short name T653
Test name
Test status
Simulation time 66086898 ps
CPU time 2.41 seconds
Started Aug 16 05:53:30 PM PDT 24
Finished Aug 16 05:53:33 PM PDT 24
Peak memory 210492 kb
Host smart-6b91307e-fe7c-41e0-9946-dd4044f7ce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926609216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.926609216
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3288144836
Short name T277
Test name
Test status
Simulation time 48662774 ps
CPU time 2.12 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 221028 kb
Host smart-f1accadc-5bd5-45ea-bf2e-30973259dd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288144836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3288144836
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2174166054
Short name T796
Test name
Test status
Simulation time 357868579 ps
CPU time 5.51 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:54:03 PM PDT 24
Peak memory 222916 kb
Host smart-522b3a1a-9a32-4a3d-a773-510b69fc7c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174166054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2174166054
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3198583968
Short name T726
Test name
Test status
Simulation time 168045682 ps
CPU time 3.1 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 208672 kb
Host smart-31909f88-b9ab-4754-8390-ef2c12ed4682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198583968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3198583968
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1906328242
Short name T602
Test name
Test status
Simulation time 1183499215 ps
CPU time 29.5 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:54:02 PM PDT 24
Peak memory 208672 kb
Host smart-a82011be-8b49-49fe-9720-feaddeb075aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906328242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1906328242
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.935119341
Short name T692
Test name
Test status
Simulation time 166844692 ps
CPU time 4.7 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 208572 kb
Host smart-73f36298-6aae-477f-897b-49fcec675c8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935119341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.935119341
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1138553191
Short name T612
Test name
Test status
Simulation time 11121817933 ps
CPU time 27.39 seconds
Started Aug 16 05:53:37 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 209260 kb
Host smart-9bd1017b-0aa0-46f5-a25d-aba3343ff557
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138553191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1138553191
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.629716590
Short name T533
Test name
Test status
Simulation time 1008736519 ps
CPU time 3.16 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 207328 kb
Host smart-a8a528c6-5fa4-44fc-8d96-0e69f77eac53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629716590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.629716590
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.4222620699
Short name T419
Test name
Test status
Simulation time 93414343 ps
CPU time 2.47 seconds
Started Aug 16 05:54:07 PM PDT 24
Finished Aug 16 05:54:09 PM PDT 24
Peak memory 207384 kb
Host smart-4c92edc2-6134-4f6b-adad-b6846c0489c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222620699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4222620699
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1410910919
Short name T583
Test name
Test status
Simulation time 415853074 ps
CPU time 3.31 seconds
Started Aug 16 05:53:34 PM PDT 24
Finished Aug 16 05:53:38 PM PDT 24
Peak memory 209004 kb
Host smart-d0adcabc-0ba8-47e6-ba92-a86b9aabed7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410910919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1410910919
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.631001553
Short name T7
Test name
Test status
Simulation time 6947978085 ps
CPU time 111.36 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:55:23 PM PDT 24
Peak memory 216208 kb
Host smart-cc6a7606-acf0-4c84-9d71-eb384116f58a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631001553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.631001553
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1846257919
Short name T6
Test name
Test status
Simulation time 1052125471 ps
CPU time 14.01 seconds
Started Aug 16 05:53:37 PM PDT 24
Finished Aug 16 05:53:51 PM PDT 24
Peak memory 222904 kb
Host smart-3cae29cc-c178-4513-b15b-dceacee55c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846257919 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1846257919
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.702254602
Short name T896
Test name
Test status
Simulation time 64259981 ps
CPU time 3.4 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:35 PM PDT 24
Peak memory 209732 kb
Host smart-fca931b7-505f-4eb0-9d4f-a6fdd3080163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702254602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.702254602
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3468443570
Short name T40
Test name
Test status
Simulation time 1522181851 ps
CPU time 15.3 seconds
Started Aug 16 05:53:55 PM PDT 24
Finished Aug 16 05:54:11 PM PDT 24
Peak memory 211396 kb
Host smart-087dd0f6-279f-48af-acd9-0a37f1ddd767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468443570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3468443570
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.173503102
Short name T568
Test name
Test status
Simulation time 51227392 ps
CPU time 0.76 seconds
Started Aug 16 05:54:01 PM PDT 24
Finished Aug 16 05:54:02 PM PDT 24
Peak memory 206408 kb
Host smart-822a736f-ed56-4089-9d5d-37ade516fd47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173503102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.173503102
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4073897300
Short name T347
Test name
Test status
Simulation time 907805982 ps
CPU time 15.22 seconds
Started Aug 16 05:53:59 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 216092 kb
Host smart-0a653ee5-aa3d-4edf-9fbe-c84aa2924cc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073897300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4073897300
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.905224349
Short name T492
Test name
Test status
Simulation time 80820804 ps
CPU time 3.48 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 209972 kb
Host smart-d6df583f-fd5f-482b-b4b4-fa8fa7acfefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905224349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.905224349
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3244748756
Short name T574
Test name
Test status
Simulation time 33389261 ps
CPU time 2.25 seconds
Started Aug 16 05:53:42 PM PDT 24
Finished Aug 16 05:53:45 PM PDT 24
Peak memory 214816 kb
Host smart-66197a8f-95c6-46f0-8e92-b1922027f39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244748756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3244748756
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.580653396
Short name T819
Test name
Test status
Simulation time 176259684 ps
CPU time 3.99 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 214800 kb
Host smart-52a8c50e-db39-4de2-ad30-8c574bc20f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580653396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.580653396
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4138947894
Short name T584
Test name
Test status
Simulation time 153064141 ps
CPU time 6.4 seconds
Started Aug 16 05:54:30 PM PDT 24
Finished Aug 16 05:54:37 PM PDT 24
Peak memory 218848 kb
Host smart-a532e15a-1d05-487b-9b02-1f847db62e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138947894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4138947894
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1604962201
Short name T368
Test name
Test status
Simulation time 98660973 ps
CPU time 3.62 seconds
Started Aug 16 05:53:34 PM PDT 24
Finished Aug 16 05:53:38 PM PDT 24
Peak memory 207264 kb
Host smart-76f20ff2-9305-4aa3-a848-18226acd0966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604962201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1604962201
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.892128783
Short name T502
Test name
Test status
Simulation time 21142539 ps
CPU time 1.85 seconds
Started Aug 16 05:53:38 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 207312 kb
Host smart-f43ee34b-a0bf-4f6c-93fc-e2f25a0d6682
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892128783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.892128783
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3279223177
Short name T181
Test name
Test status
Simulation time 341744452 ps
CPU time 4.17 seconds
Started Aug 16 05:53:36 PM PDT 24
Finished Aug 16 05:53:40 PM PDT 24
Peak memory 209208 kb
Host smart-f431cd03-fdbe-49e3-81a3-0d539ae89316
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279223177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3279223177
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4124379480
Short name T879
Test name
Test status
Simulation time 128939313 ps
CPU time 2.38 seconds
Started Aug 16 05:53:54 PM PDT 24
Finished Aug 16 05:53:57 PM PDT 24
Peak memory 209080 kb
Host smart-fcfe871d-eb8a-4798-95f2-c08a6640166d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124379480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4124379480
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1266323423
Short name T500
Test name
Test status
Simulation time 1056957114 ps
CPU time 5.97 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:38 PM PDT 24
Peak memory 208708 kb
Host smart-54a660a0-11bc-4ff7-b55f-7754c0e65ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266323423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1266323423
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.972555638
Short name T435
Test name
Test status
Simulation time 146425023 ps
CPU time 2.33 seconds
Started Aug 16 05:53:29 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 208412 kb
Host smart-62b936dd-2b99-4692-a3a4-ae03d34f3b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972555638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.972555638
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1749615518
Short name T802
Test name
Test status
Simulation time 9160276147 ps
CPU time 60.81 seconds
Started Aug 16 05:54:08 PM PDT 24
Finished Aug 16 05:55:14 PM PDT 24
Peak memory 209084 kb
Host smart-d1a71401-c2c8-4085-95d0-2e661e026d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749615518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1749615518
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3643305946
Short name T495
Test name
Test status
Simulation time 677656724 ps
CPU time 2.47 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:35 PM PDT 24
Peak memory 210692 kb
Host smart-11c3633d-a783-4256-9ac9-5e8ad3b2ad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643305946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3643305946
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2599001194
Short name T443
Test name
Test status
Simulation time 88340687 ps
CPU time 0.74 seconds
Started Aug 16 05:53:51 PM PDT 24
Finished Aug 16 05:53:52 PM PDT 24
Peak memory 206364 kb
Host smart-f12472ed-c33b-43e1-a6b5-3154fd8e3ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599001194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2599001194
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3083688956
Short name T337
Test name
Test status
Simulation time 130891075 ps
CPU time 2.88 seconds
Started Aug 16 05:53:59 PM PDT 24
Finished Aug 16 05:54:03 PM PDT 24
Peak memory 214812 kb
Host smart-7162e74e-72d3-4499-8ca0-2ccfe92d2d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083688956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3083688956
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2630497924
Short name T615
Test name
Test status
Simulation time 185463124 ps
CPU time 2.5 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 208840 kb
Host smart-b2319c10-6d34-4fea-8819-a79de78a387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630497924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2630497924
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1037598247
Short name T135
Test name
Test status
Simulation time 295974885 ps
CPU time 2.94 seconds
Started Aug 16 05:54:05 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 207744 kb
Host smart-4f4cc8cb-0a39-4bc3-a6c0-41c8cc43a112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037598247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1037598247
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2332780353
Short name T59
Test name
Test status
Simulation time 212298794 ps
CPU time 5.49 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:11 PM PDT 24
Peak memory 209760 kb
Host smart-b1294f47-0a4c-4e96-a426-7cddff6f0119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332780353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2332780353
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1899090312
Short name T275
Test name
Test status
Simulation time 81220393 ps
CPU time 1.45 seconds
Started Aug 16 05:54:28 PM PDT 24
Finished Aug 16 05:54:30 PM PDT 24
Peak memory 214708 kb
Host smart-18a30d5c-7a0d-415a-a041-2b25f80ca05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899090312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1899090312
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1727068529
Short name T284
Test name
Test status
Simulation time 153119246 ps
CPU time 4.67 seconds
Started Aug 16 05:53:36 PM PDT 24
Finished Aug 16 05:53:41 PM PDT 24
Peak memory 214756 kb
Host smart-a1427215-a672-4fe5-86a0-4a7aae59084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727068529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1727068529
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2462493756
Short name T531
Test name
Test status
Simulation time 46058666 ps
CPU time 2.8 seconds
Started Aug 16 05:54:16 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 218736 kb
Host smart-853c0a1e-f4ab-4bff-a721-2ac1f0776667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462493756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2462493756
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3693805905
Short name T13
Test name
Test status
Simulation time 8553433242 ps
CPU time 24.17 seconds
Started Aug 16 05:53:34 PM PDT 24
Finished Aug 16 05:53:59 PM PDT 24
Peak memory 208612 kb
Host smart-de493179-f7a3-4387-8017-9229478cf538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693805905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3693805905
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.457341623
Short name T823
Test name
Test status
Simulation time 357998862 ps
CPU time 3.63 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:02 PM PDT 24
Peak memory 209288 kb
Host smart-7c264703-8774-496e-bf8a-0d6ac4b2a587
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457341623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.457341623
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1629741710
Short name T376
Test name
Test status
Simulation time 140037275 ps
CPU time 3.62 seconds
Started Aug 16 05:53:35 PM PDT 24
Finished Aug 16 05:53:44 PM PDT 24
Peak memory 209400 kb
Host smart-7e35c684-f511-4808-8889-b750fa56b986
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629741710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1629741710
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.619429818
Short name T866
Test name
Test status
Simulation time 153172510 ps
CPU time 4.55 seconds
Started Aug 16 05:54:17 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 209312 kb
Host smart-41e18ae6-0bd2-4401-95b8-d8d145d6e4a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619429818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.619429818
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2413999076
Short name T97
Test name
Test status
Simulation time 50771322 ps
CPU time 2.36 seconds
Started Aug 16 05:53:53 PM PDT 24
Finished Aug 16 05:53:56 PM PDT 24
Peak memory 218840 kb
Host smart-a7964e32-92df-4e86-83b8-ca2a5f48f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413999076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2413999076
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1380104607
Short name T794
Test name
Test status
Simulation time 119668395 ps
CPU time 2.83 seconds
Started Aug 16 05:53:34 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 207160 kb
Host smart-ed3f2f92-ad43-4827-88af-35b2cc7749ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380104607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1380104607
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2085115164
Short name T325
Test name
Test status
Simulation time 358687439 ps
CPU time 2.08 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:13 PM PDT 24
Peak memory 211120 kb
Host smart-2459ad59-1fb7-4e91-92b1-0d4f809e6061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085115164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2085115164
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3699476628
Short name T71
Test name
Test status
Simulation time 1481874432 ps
CPU time 4.38 seconds
Started Aug 16 05:53:44 PM PDT 24
Finished Aug 16 05:53:49 PM PDT 24
Peak memory 207980 kb
Host smart-a258aa44-9745-4b27-aaa3-050c6d36ae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699476628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3699476628
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2372238962
Short name T555
Test name
Test status
Simulation time 1083435948 ps
CPU time 16.8 seconds
Started Aug 16 05:54:26 PM PDT 24
Finished Aug 16 05:54:43 PM PDT 24
Peak memory 211432 kb
Host smart-62acede4-b3c4-4d52-947e-a80a8c6eba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372238962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2372238962
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.835460496
Short name T807
Test name
Test status
Simulation time 20112157 ps
CPU time 0.73 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 206272 kb
Host smart-5d32d000-b3b5-4f4a-8b82-a3746ba8b317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835460496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.835460496
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3924667343
Short name T17
Test name
Test status
Simulation time 224883133 ps
CPU time 3.61 seconds
Started Aug 16 05:54:17 PM PDT 24
Finished Aug 16 05:54:20 PM PDT 24
Peak memory 209648 kb
Host smart-0a86f7e9-6077-4410-a335-5ed61944db1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924667343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3924667343
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2736127089
Short name T577
Test name
Test status
Simulation time 68145395 ps
CPU time 1.98 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 214764 kb
Host smart-254cdefc-b266-4250-947b-4f6588b25cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736127089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2736127089
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3679132989
Short name T567
Test name
Test status
Simulation time 921398292 ps
CPU time 2.72 seconds
Started Aug 16 05:53:52 PM PDT 24
Finished Aug 16 05:53:55 PM PDT 24
Peak memory 214784 kb
Host smart-473695bf-2319-49ab-9b33-76e52e75dab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679132989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3679132989
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.834391402
Short name T374
Test name
Test status
Simulation time 225687585 ps
CPU time 3.32 seconds
Started Aug 16 05:54:29 PM PDT 24
Finished Aug 16 05:54:33 PM PDT 24
Peak memory 214724 kb
Host smart-367e6302-3338-4fbd-bf78-708c0b1c5c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834391402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.834391402
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2204122798
Short name T504
Test name
Test status
Simulation time 286550534 ps
CPU time 6.6 seconds
Started Aug 16 05:53:45 PM PDT 24
Finished Aug 16 05:53:52 PM PDT 24
Peak memory 209052 kb
Host smart-c3a80044-29a0-4d10-bdcc-f6b85bebcb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204122798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2204122798
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1041943137
Short name T48
Test name
Test status
Simulation time 797753217 ps
CPU time 5.22 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:23 PM PDT 24
Peak memory 208948 kb
Host smart-675f494f-d2b0-41f8-9111-9f209eef6b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041943137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1041943137
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2859999904
Short name T855
Test name
Test status
Simulation time 785492721 ps
CPU time 4.42 seconds
Started Aug 16 05:54:12 PM PDT 24
Finished Aug 16 05:54:17 PM PDT 24
Peak memory 207288 kb
Host smart-525ff959-20fc-4397-ac67-933cf4ac0c8e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859999904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2859999904
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1634108678
Short name T447
Test name
Test status
Simulation time 92397097 ps
CPU time 2.42 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:13 PM PDT 24
Peak memory 207224 kb
Host smart-57128b75-b05e-4857-a307-8ce78efa7bc6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634108678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1634108678
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.823472937
Short name T425
Test name
Test status
Simulation time 346920557 ps
CPU time 3.2 seconds
Started Aug 16 05:54:07 PM PDT 24
Finished Aug 16 05:54:10 PM PDT 24
Peak memory 207400 kb
Host smart-d3f535ec-95a4-44d1-b8aa-280318c9a76e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823472937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.823472937
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3648766372
Short name T452
Test name
Test status
Simulation time 54022583 ps
CPU time 2.84 seconds
Started Aug 16 05:53:44 PM PDT 24
Finished Aug 16 05:53:47 PM PDT 24
Peak memory 210136 kb
Host smart-f6e5279d-bf0d-4eda-b5b0-700a20774468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648766372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3648766372
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3223439853
Short name T624
Test name
Test status
Simulation time 5391256349 ps
CPU time 26.87 seconds
Started Aug 16 05:53:50 PM PDT 24
Finished Aug 16 05:54:17 PM PDT 24
Peak memory 209388 kb
Host smart-6afc8655-f74a-4da6-a80c-0b39ac9c2b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223439853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3223439853
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1660674650
Short name T210
Test name
Test status
Simulation time 473160219 ps
CPU time 24.17 seconds
Started Aug 16 05:53:40 PM PDT 24
Finished Aug 16 05:54:04 PM PDT 24
Peak memory 215632 kb
Host smart-2d50d3d3-ac7a-4b3a-9da5-9c01fd74901a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660674650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1660674650
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.405996714
Short name T377
Test name
Test status
Simulation time 728848207 ps
CPU time 8.57 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:54:32 PM PDT 24
Peak memory 219052 kb
Host smart-88735716-27fc-4b78-a72f-e9b2c6098113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405996714 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.405996714
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1724420716
Short name T222
Test name
Test status
Simulation time 84122632 ps
CPU time 3.49 seconds
Started Aug 16 05:54:35 PM PDT 24
Finished Aug 16 05:54:39 PM PDT 24
Peak memory 209616 kb
Host smart-5cb5f70e-f9b4-484f-8605-3cabc91dcf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724420716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1724420716
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2854208462
Short name T757
Test name
Test status
Simulation time 45326203 ps
CPU time 2.42 seconds
Started Aug 16 05:54:12 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 210272 kb
Host smart-c297937c-db0c-4781-89dc-f1a2b7fc1c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854208462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2854208462
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.4213899759
Short name T146
Test name
Test status
Simulation time 129242141 ps
CPU time 0.84 seconds
Started Aug 16 05:53:51 PM PDT 24
Finished Aug 16 05:53:52 PM PDT 24
Peak memory 206396 kb
Host smart-ed8b2199-6feb-40bf-adc1-8a95e3adab79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213899759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4213899759
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2493409970
Short name T386
Test name
Test status
Simulation time 63883055 ps
CPU time 4.29 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:17 PM PDT 24
Peak memory 222872 kb
Host smart-8d60c33d-017e-4bac-8113-814d146c1248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493409970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2493409970
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.247709737
Short name T252
Test name
Test status
Simulation time 142825004 ps
CPU time 3.84 seconds
Started Aug 16 05:54:15 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 214704 kb
Host smart-fc268d16-fba8-4dd5-a56a-d69e085a2f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247709737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.247709737
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2944162312
Short name T725
Test name
Test status
Simulation time 70758602 ps
CPU time 2.03 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 214712 kb
Host smart-acf5afe4-179d-461d-bea8-064504fe7b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944162312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2944162312
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2800750623
Short name T621
Test name
Test status
Simulation time 94154594 ps
CPU time 3.67 seconds
Started Aug 16 05:54:02 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 210556 kb
Host smart-caa54031-8aab-452a-9905-501ec75d6daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800750623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2800750623
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2342051454
Short name T678
Test name
Test status
Simulation time 612382521 ps
CPU time 6.21 seconds
Started Aug 16 05:54:02 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 214796 kb
Host smart-69130a98-6095-4254-a593-33c954e7d473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342051454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2342051454
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1721190453
Short name T75
Test name
Test status
Simulation time 1097486055 ps
CPU time 3.92 seconds
Started Aug 16 05:54:10 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 209172 kb
Host smart-56996b80-be7b-4481-b096-55bff6428840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721190453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1721190453
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.371318299
Short name T375
Test name
Test status
Simulation time 89268883 ps
CPU time 1.72 seconds
Started Aug 16 05:54:29 PM PDT 24
Finished Aug 16 05:54:31 PM PDT 24
Peak memory 207360 kb
Host smart-7dc56b25-65f4-465f-a259-199356a64790
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371318299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.371318299
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2438684115
Short name T778
Test name
Test status
Simulation time 57204086 ps
CPU time 2.78 seconds
Started Aug 16 05:53:53 PM PDT 24
Finished Aug 16 05:53:55 PM PDT 24
Peak memory 208972 kb
Host smart-d84787a6-a91d-4d17-8217-363b263d2fa4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438684115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2438684115
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.387307858
Short name T482
Test name
Test status
Simulation time 140479535 ps
CPU time 3.76 seconds
Started Aug 16 05:54:08 PM PDT 24
Finished Aug 16 05:54:17 PM PDT 24
Peak memory 207272 kb
Host smart-1ccc4345-8a8f-47cb-a7bc-ccbb65ea311c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387307858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.387307858
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4155859933
Short name T882
Test name
Test status
Simulation time 88972416 ps
CPU time 2.7 seconds
Started Aug 16 05:53:38 PM PDT 24
Finished Aug 16 05:53:41 PM PDT 24
Peak memory 214752 kb
Host smart-93184ac6-ac58-48ca-82e9-80b194bc3058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155859933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4155859933
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1225580662
Short name T657
Test name
Test status
Simulation time 267373541 ps
CPU time 3.98 seconds
Started Aug 16 05:54:21 PM PDT 24
Finished Aug 16 05:54:25 PM PDT 24
Peak memory 207256 kb
Host smart-53eaf096-a5fa-436b-8022-e2bc64ffd81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225580662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1225580662
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3924893931
Short name T744
Test name
Test status
Simulation time 402267756 ps
CPU time 5.41 seconds
Started Aug 16 05:53:38 PM PDT 24
Finished Aug 16 05:53:43 PM PDT 24
Peak memory 208520 kb
Host smart-f4f23774-6150-463d-8694-e2f09466dbea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924893931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3924893931
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2528290494
Short name T93
Test name
Test status
Simulation time 511213715 ps
CPU time 21 seconds
Started Aug 16 05:53:44 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 220364 kb
Host smart-eeaca85a-2f43-40b2-ad53-7398c4dfbf95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528290494 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2528290494
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3837588375
Short name T788
Test name
Test status
Simulation time 71121148 ps
CPU time 3.09 seconds
Started Aug 16 05:53:54 PM PDT 24
Finished Aug 16 05:53:57 PM PDT 24
Peak memory 209748 kb
Host smart-920630ec-1cd5-4d57-8277-070f5660c917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837588375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3837588375
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1226960406
Short name T512
Test name
Test status
Simulation time 110893722 ps
CPU time 2.52 seconds
Started Aug 16 05:53:46 PM PDT 24
Finished Aug 16 05:53:48 PM PDT 24
Peak memory 210336 kb
Host smart-0239af9b-3c8a-4cf1-9f61-ab4fa0b759ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226960406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1226960406
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1075316512
Short name T402
Test name
Test status
Simulation time 158569892 ps
CPU time 0.78 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:54:32 PM PDT 24
Peak memory 206340 kb
Host smart-f6edd8d8-747a-4cad-a915-77247bb796e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075316512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1075316512
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1865629531
Short name T384
Test name
Test status
Simulation time 1251482847 ps
CPU time 16.96 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 222908 kb
Host smart-c75a2eac-95b3-4bd7-8fe1-84f7fe0bb436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1865629531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1865629531
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3825726627
Short name T131
Test name
Test status
Simulation time 70431133 ps
CPU time 1.63 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:02 PM PDT 24
Peak memory 216764 kb
Host smart-d24b0aa7-678b-46b1-bc0d-d960b1021f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825726627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3825726627
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.4165203432
Short name T646
Test name
Test status
Simulation time 141743683 ps
CPU time 5.38 seconds
Started Aug 16 05:54:15 PM PDT 24
Finished Aug 16 05:54:20 PM PDT 24
Peak memory 209152 kb
Host smart-85cd6d6c-9e8d-45a6-a710-e22e25436ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165203432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.4165203432
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1467209068
Short name T515
Test name
Test status
Simulation time 541260070 ps
CPU time 4.42 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 214700 kb
Host smart-4d3217a3-a999-4260-8917-160cb562e76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467209068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1467209068
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4056800612
Short name T126
Test name
Test status
Simulation time 92400690 ps
CPU time 3.41 seconds
Started Aug 16 05:54:30 PM PDT 24
Finished Aug 16 05:54:33 PM PDT 24
Peak memory 214752 kb
Host smart-aa893bc5-2376-48de-8206-6dcf7a67a8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056800612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4056800612
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3899692204
Short name T49
Test name
Test status
Simulation time 87668469 ps
CPU time 3.6 seconds
Started Aug 16 05:53:58 PM PDT 24
Finished Aug 16 05:54:02 PM PDT 24
Peak memory 220200 kb
Host smart-64e53745-aaa3-416a-a2c7-efce29da61b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899692204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3899692204
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.309289165
Short name T876
Test name
Test status
Simulation time 52700879 ps
CPU time 2.44 seconds
Started Aug 16 05:54:31 PM PDT 24
Finished Aug 16 05:54:33 PM PDT 24
Peak memory 207232 kb
Host smart-d4c3a4b6-5f9c-4f04-a91a-9bd5d46cc0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309289165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.309289165
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3175355717
Short name T571
Test name
Test status
Simulation time 311713268 ps
CPU time 3.91 seconds
Started Aug 16 05:54:05 PM PDT 24
Finished Aug 16 05:54:09 PM PDT 24
Peak memory 209164 kb
Host smart-84e8c35c-9e0a-461d-afab-0560f6c71b3d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175355717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3175355717
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.242098632
Short name T545
Test name
Test status
Simulation time 61060193 ps
CPU time 3.14 seconds
Started Aug 16 05:53:44 PM PDT 24
Finished Aug 16 05:53:47 PM PDT 24
Peak memory 209388 kb
Host smart-5fa1492d-5650-44be-8d9e-8facf90762ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242098632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.242098632
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.791785264
Short name T717
Test name
Test status
Simulation time 389955370 ps
CPU time 5.67 seconds
Started Aug 16 05:54:10 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 208908 kb
Host smart-1da0b7fe-edaa-40e5-beec-f62400f43f90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791785264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.791785264
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1369559657
Short name T572
Test name
Test status
Simulation time 121528908 ps
CPU time 2.67 seconds
Started Aug 16 05:54:04 PM PDT 24
Finished Aug 16 05:54:06 PM PDT 24
Peak memory 218780 kb
Host smart-7110072d-6cd9-4f8c-bf0c-325ca366095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369559657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1369559657
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2787838452
Short name T437
Test name
Test status
Simulation time 706118555 ps
CPU time 6.39 seconds
Started Aug 16 05:54:28 PM PDT 24
Finished Aug 16 05:54:35 PM PDT 24
Peak memory 207396 kb
Host smart-ddf9493a-9c1e-48cb-9fcd-4fd6063e3f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787838452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2787838452
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.64040831
Short name T521
Test name
Test status
Simulation time 619454032 ps
CPU time 10.54 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:54:07 PM PDT 24
Peak memory 223144 kb
Host smart-afb59133-51f0-423a-a9f4-e8e977910d5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64040831 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.64040831
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1071098054
Short name T254
Test name
Test status
Simulation time 762833870 ps
CPU time 6.7 seconds
Started Aug 16 05:54:01 PM PDT 24
Finished Aug 16 05:54:07 PM PDT 24
Peak memory 214716 kb
Host smart-8a1d4561-004f-4708-a295-dcb4af3dba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071098054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1071098054
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.168370917
Short name T846
Test name
Test status
Simulation time 55353536 ps
CPU time 2.16 seconds
Started Aug 16 05:54:08 PM PDT 24
Finished Aug 16 05:54:10 PM PDT 24
Peak memory 210836 kb
Host smart-4f995842-d746-492e-92e3-592a213632cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168370917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.168370917
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.128307921
Short name T466
Test name
Test status
Simulation time 110457582 ps
CPU time 0.79 seconds
Started Aug 16 05:54:04 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 206396 kb
Host smart-5dce4870-5217-4ccd-9a11-c87c70283a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128307921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.128307921
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2097669669
Short name T383
Test name
Test status
Simulation time 166151356 ps
CPU time 9.12 seconds
Started Aug 16 05:54:34 PM PDT 24
Finished Aug 16 05:54:44 PM PDT 24
Peak memory 214964 kb
Host smart-f217e902-2152-4083-8d8d-ae046808078e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097669669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2097669669
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3967128664
Short name T617
Test name
Test status
Simulation time 92408030 ps
CPU time 1.99 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:13 PM PDT 24
Peak memory 208540 kb
Host smart-fe7dd2e0-0a32-4c7c-8505-7ba67fdd3dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967128664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3967128664
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3345145962
Short name T491
Test name
Test status
Simulation time 354820857 ps
CPU time 3.48 seconds
Started Aug 16 05:54:28 PM PDT 24
Finished Aug 16 05:54:32 PM PDT 24
Peak memory 219024 kb
Host smart-93ebb02f-343c-4e14-9e5a-43f627c420d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345145962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3345145962
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2561160365
Short name T503
Test name
Test status
Simulation time 55804530 ps
CPU time 2.03 seconds
Started Aug 16 05:54:03 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 214820 kb
Host smart-a7303d35-ed7a-40c2-aca5-13c15770651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561160365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2561160365
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.598110066
Short name T609
Test name
Test status
Simulation time 58904000 ps
CPU time 3.1 seconds
Started Aug 16 05:54:22 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 214708 kb
Host smart-e8fc8946-bbce-42c3-929d-0f57750900fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598110066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.598110066
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2489047758
Short name T811
Test name
Test status
Simulation time 202339962 ps
CPU time 2.69 seconds
Started Aug 16 05:54:22 PM PDT 24
Finished Aug 16 05:54:25 PM PDT 24
Peak memory 220372 kb
Host smart-ad124dd6-00e7-41b9-8148-21554fb28bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489047758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2489047758
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1881308766
Short name T739
Test name
Test status
Simulation time 427202124 ps
CPU time 7.03 seconds
Started Aug 16 05:53:57 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 218860 kb
Host smart-dc6aba62-34ca-4303-ae84-473ab932cbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881308766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1881308766
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.852091785
Short name T695
Test name
Test status
Simulation time 4977851535 ps
CPU time 19.62 seconds
Started Aug 16 05:54:35 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 209300 kb
Host smart-6015fe5d-b8fa-493e-8648-04dd66a69eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852091785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.852091785
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2304880051
Short name T618
Test name
Test status
Simulation time 106712444 ps
CPU time 3.01 seconds
Started Aug 16 05:54:44 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 207412 kb
Host smart-7747d785-6faf-4ec8-aa60-73ae842519a7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304880051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2304880051
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3967702981
Short name T912
Test name
Test status
Simulation time 104161710 ps
CPU time 3.46 seconds
Started Aug 16 05:53:59 PM PDT 24
Finished Aug 16 05:54:03 PM PDT 24
Peak memory 209180 kb
Host smart-a13bce77-8c6f-47e7-aa3f-3fc072302ee2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967702981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3967702981
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3481227302
Short name T662
Test name
Test status
Simulation time 156028634 ps
CPU time 5.16 seconds
Started Aug 16 05:54:02 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 209364 kb
Host smart-78b71b5f-a124-473b-a214-e2e08785ab46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481227302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3481227302
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2721163096
Short name T148
Test name
Test status
Simulation time 22562948 ps
CPU time 1.65 seconds
Started Aug 16 05:54:04 PM PDT 24
Finished Aug 16 05:54:06 PM PDT 24
Peak memory 208332 kb
Host smart-1e76bb51-d0cf-4e80-afd9-3858075205eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721163096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2721163096
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1686472968
Short name T696
Test name
Test status
Simulation time 359896615 ps
CPU time 4.18 seconds
Started Aug 16 05:54:45 PM PDT 24
Finished Aug 16 05:54:49 PM PDT 24
Peak memory 208272 kb
Host smart-de6ab281-cc16-4b10-8276-76a9c8c19450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686472968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1686472968
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2472064346
Short name T137
Test name
Test status
Simulation time 1639173556 ps
CPU time 36.5 seconds
Started Aug 16 05:54:04 PM PDT 24
Finished Aug 16 05:54:40 PM PDT 24
Peak memory 221572 kb
Host smart-37807a19-d001-4f9b-91b9-2294e5728f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472064346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2472064346
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.340185112
Short name T172
Test name
Test status
Simulation time 1240823739 ps
CPU time 14.21 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:58 PM PDT 24
Peak memory 222836 kb
Host smart-40262eab-f3a0-4ad4-b5fb-de5114d93f5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340185112 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.340185112
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3514366319
Short name T910
Test name
Test status
Simulation time 1527945906 ps
CPU time 10.18 seconds
Started Aug 16 05:54:16 PM PDT 24
Finished Aug 16 05:54:27 PM PDT 24
Peak memory 210792 kb
Host smart-d820d9d8-9c65-41a4-bc6c-fa8084a81d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514366319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3514366319
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3095951989
Short name T607
Test name
Test status
Simulation time 35864967 ps
CPU time 1.43 seconds
Started Aug 16 05:54:03 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 210052 kb
Host smart-83d8553e-3cee-4241-90f8-d80810e88669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095951989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3095951989
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1635471283
Short name T483
Test name
Test status
Simulation time 20886986 ps
CPU time 0.81 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:53:58 PM PDT 24
Peak memory 206428 kb
Host smart-13fb4aa2-c6bc-4a06-9e1b-b0e53c1e0798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635471283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1635471283
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3221021
Short name T380
Test name
Test status
Simulation time 49953541 ps
CPU time 3.7 seconds
Started Aug 16 05:54:33 PM PDT 24
Finished Aug 16 05:54:36 PM PDT 24
Peak memory 214748 kb
Host smart-a22adf1c-dca9-4043-b058-947189d9da2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3221021
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.4216111007
Short name T202
Test name
Test status
Simulation time 195310665 ps
CPU time 3.02 seconds
Started Aug 16 05:54:55 PM PDT 24
Finished Aug 16 05:54:59 PM PDT 24
Peak memory 210096 kb
Host smart-efb1cdb2-6a5f-4889-85b4-eeddb06f185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216111007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.4216111007
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1901674274
Short name T808
Test name
Test status
Simulation time 536573224 ps
CPU time 4.38 seconds
Started Aug 16 05:54:01 PM PDT 24
Finished Aug 16 05:54:06 PM PDT 24
Peak memory 210096 kb
Host smart-b3b02203-cfca-4da9-93e3-412cc2438052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901674274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1901674274
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.657920846
Short name T215
Test name
Test status
Simulation time 62934291 ps
CPU time 2.61 seconds
Started Aug 16 05:54:37 PM PDT 24
Finished Aug 16 05:54:40 PM PDT 24
Peak memory 214772 kb
Host smart-7b5c771b-5282-45b5-9773-990d039163b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657920846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.657920846
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3232830150
Short name T652
Test name
Test status
Simulation time 92783759 ps
CPU time 1.8 seconds
Started Aug 16 05:54:00 PM PDT 24
Finished Aug 16 05:54:02 PM PDT 24
Peak memory 214744 kb
Host smart-8a8fa558-bba2-4789-ad54-92a69ee2204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232830150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3232830150
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2659193824
Short name T243
Test name
Test status
Simulation time 624912162 ps
CPU time 3.87 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 210424 kb
Host smart-d7b425b3-59b8-4657-bc91-53597e215706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659193824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2659193824
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.348150337
Short name T95
Test name
Test status
Simulation time 94899182 ps
CPU time 4.26 seconds
Started Aug 16 05:54:07 PM PDT 24
Finished Aug 16 05:54:12 PM PDT 24
Peak memory 208360 kb
Host smart-e0752929-5aca-4e1e-ac2e-047e71f4f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348150337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.348150337
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3211137202
Short name T433
Test name
Test status
Simulation time 30882484 ps
CPU time 2.12 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 207132 kb
Host smart-03fbda0a-57a9-4211-952f-11beb98fd384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211137202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3211137202
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2910913376
Short name T806
Test name
Test status
Simulation time 91147867 ps
CPU time 3.14 seconds
Started Aug 16 05:54:39 PM PDT 24
Finished Aug 16 05:54:42 PM PDT 24
Peak memory 207388 kb
Host smart-65c25a36-b127-42c5-a952-57feae56707c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910913376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2910913376
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2863950070
Short name T783
Test name
Test status
Simulation time 22499089 ps
CPU time 1.92 seconds
Started Aug 16 05:54:36 PM PDT 24
Finished Aug 16 05:54:38 PM PDT 24
Peak memory 207116 kb
Host smart-10082d43-d6ff-48f1-bf52-3f5558020616
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863950070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2863950070
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3302664804
Short name T535
Test name
Test status
Simulation time 204501160 ps
CPU time 2.97 seconds
Started Aug 16 05:54:02 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 209228 kb
Host smart-baecf7a5-e100-4a06-9155-20a569fca7e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302664804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3302664804
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1220263316
Short name T801
Test name
Test status
Simulation time 39568577 ps
CPU time 2.16 seconds
Started Aug 16 05:54:05 PM PDT 24
Finished Aug 16 05:54:07 PM PDT 24
Peak memory 210060 kb
Host smart-ffa46281-8831-4e9a-ab42-c44be87cc2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220263316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1220263316
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2811265509
Short name T423
Test name
Test status
Simulation time 175074056 ps
CPU time 3.67 seconds
Started Aug 16 05:54:46 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 208824 kb
Host smart-6bf9213e-38ff-4461-82e7-47a29d3d69de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811265509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2811265509
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3722834716
Short name T706
Test name
Test status
Simulation time 1301824319 ps
CPU time 17.24 seconds
Started Aug 16 05:54:04 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 220552 kb
Host smart-3be37335-7ddf-4a4b-8628-764995868f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722834716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3722834716
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2165415393
Short name T224
Test name
Test status
Simulation time 8071461890 ps
CPU time 11.7 seconds
Started Aug 16 05:54:16 PM PDT 24
Finished Aug 16 05:54:28 PM PDT 24
Peak memory 208508 kb
Host smart-94f58812-50ad-42d8-b6d7-b19c4692d837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165415393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2165415393
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1531050280
Short name T546
Test name
Test status
Simulation time 267729715 ps
CPU time 4.08 seconds
Started Aug 16 05:54:03 PM PDT 24
Finished Aug 16 05:54:07 PM PDT 24
Peak memory 210988 kb
Host smart-b9e0200e-787e-4de0-9d69-d17216b74925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531050280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1531050280
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3099682350
Short name T625
Test name
Test status
Simulation time 37739862 ps
CPU time 0.87 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 206328 kb
Host smart-d92a3758-d525-47db-a83b-f202f8324f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099682350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3099682350
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4118068819
Short name T295
Test name
Test status
Simulation time 112885234 ps
CPU time 4.17 seconds
Started Aug 16 05:54:41 PM PDT 24
Finished Aug 16 05:54:45 PM PDT 24
Peak memory 218656 kb
Host smart-365e7940-4348-420e-8897-08533df93ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118068819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4118068819
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.274643452
Short name T356
Test name
Test status
Simulation time 142595490 ps
CPU time 5.08 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 208880 kb
Host smart-3a7feb94-c5e5-4b41-b1de-6b3a9d42291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274643452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.274643452
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2119969395
Short name T719
Test name
Test status
Simulation time 194108553 ps
CPU time 2.49 seconds
Started Aug 16 05:54:14 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 214704 kb
Host smart-485dc206-834b-4eb0-a11a-9b206f618c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119969395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2119969395
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2901136424
Short name T188
Test name
Test status
Simulation time 58932020 ps
CPU time 2.37 seconds
Started Aug 16 05:54:02 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 214884 kb
Host smart-a5675b66-403a-474e-9ba4-6750aa7a05d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901136424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2901136424
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3534104397
Short name T844
Test name
Test status
Simulation time 1403440165 ps
CPU time 9.45 seconds
Started Aug 16 05:54:42 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 214624 kb
Host smart-1323d8e1-b79c-4f40-8dc1-2d04cd625d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534104397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3534104397
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1735976916
Short name T585
Test name
Test status
Simulation time 218558235 ps
CPU time 3.76 seconds
Started Aug 16 05:53:56 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 207232 kb
Host smart-47da60e0-d4b0-4009-b079-812e76e0e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735976916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1735976916
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1899762419
Short name T721
Test name
Test status
Simulation time 200684992 ps
CPU time 2.85 seconds
Started Aug 16 05:54:02 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 207356 kb
Host smart-bc7b5630-cc9e-4edd-afc6-e212ac01e5d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899762419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1899762419
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1101519728
Short name T269
Test name
Test status
Simulation time 35599815 ps
CPU time 2.23 seconds
Started Aug 16 05:54:42 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 209064 kb
Host smart-62129277-957e-4fb4-8c44-f21bc33c89fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101519728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1101519728
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1207423828
Short name T878
Test name
Test status
Simulation time 124587412 ps
CPU time 2.47 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:45 PM PDT 24
Peak memory 207272 kb
Host smart-f166c64c-0e66-45f5-83c9-bcfb144d857d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207423828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1207423828
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1927928400
Short name T392
Test name
Test status
Simulation time 102396573 ps
CPU time 4 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:54:56 PM PDT 24
Peak memory 209200 kb
Host smart-1d2ae198-1640-4725-98d5-3524381cd7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927928400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1927928400
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.413829644
Short name T511
Test name
Test status
Simulation time 80812145 ps
CPU time 2.23 seconds
Started Aug 16 05:54:05 PM PDT 24
Finished Aug 16 05:54:07 PM PDT 24
Peak memory 207468 kb
Host smart-fdad8ec3-ac25-4e16-9491-c9713db5212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413829644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.413829644
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.144676998
Short name T142
Test name
Test status
Simulation time 391882580 ps
CPU time 20.07 seconds
Started Aug 16 05:54:10 PM PDT 24
Finished Aug 16 05:54:30 PM PDT 24
Peak memory 222852 kb
Host smart-a7e7ba0b-5386-4239-86ac-36e5c7709ace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144676998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.144676998
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3681009727
Short name T223
Test name
Test status
Simulation time 453861359 ps
CPU time 6.01 seconds
Started Aug 16 05:54:29 PM PDT 24
Finished Aug 16 05:54:35 PM PDT 24
Peak memory 220348 kb
Host smart-8686b58d-166e-4940-ac11-580f7b279c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681009727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3681009727
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3682087866
Short name T852
Test name
Test status
Simulation time 115102768 ps
CPU time 2.77 seconds
Started Aug 16 05:54:28 PM PDT 24
Finished Aug 16 05:54:31 PM PDT 24
Peak memory 211016 kb
Host smart-9057f9e4-d40e-400f-b668-f9b1990fdf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682087866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3682087866
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3872497301
Short name T654
Test name
Test status
Simulation time 17711716 ps
CPU time 0.82 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:54:25 PM PDT 24
Peak memory 206372 kb
Host smart-cfc63746-d124-420a-9da7-3d690c2a69f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872497301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3872497301
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.80421250
Short name T103
Test name
Test status
Simulation time 230766916 ps
CPU time 4.55 seconds
Started Aug 16 05:54:14 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 222932 kb
Host smart-55f4de3f-9d0f-4e7e-aaf6-ccaf61fd58d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80421250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.80421250
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3873435037
Short name T767
Test name
Test status
Simulation time 171925286 ps
CPU time 2.78 seconds
Started Aug 16 05:54:16 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 219384 kb
Host smart-87b65f28-2d88-47ae-b5ae-b67ccd2fb943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873435037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3873435037
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3762754049
Short name T800
Test name
Test status
Simulation time 927752531 ps
CPU time 6.44 seconds
Started Aug 16 05:54:28 PM PDT 24
Finished Aug 16 05:54:35 PM PDT 24
Peak memory 209508 kb
Host smart-0ba75252-17cf-4154-8c9c-0f9a1a1839cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762754049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3762754049
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3408388790
Short name T323
Test name
Test status
Simulation time 216146040 ps
CPU time 2.7 seconds
Started Aug 16 05:54:41 PM PDT 24
Finished Aug 16 05:54:44 PM PDT 24
Peak memory 209724 kb
Host smart-336a1475-34de-403e-9db6-59049c52ef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408388790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3408388790
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1092580368
Short name T593
Test name
Test status
Simulation time 1103989570 ps
CPU time 12.25 seconds
Started Aug 16 05:54:03 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 215004 kb
Host smart-1a3d2c4b-c114-4f5f-953a-a80827240d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092580368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1092580368
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.657171660
Short name T579
Test name
Test status
Simulation time 105803415 ps
CPU time 3.94 seconds
Started Aug 16 05:54:10 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 209452 kb
Host smart-c543fbb3-5e3b-4bfe-b097-f9a7097f8a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657171660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.657171660
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3707463035
Short name T549
Test name
Test status
Simulation time 2351656794 ps
CPU time 29.4 seconds
Started Aug 16 05:54:15 PM PDT 24
Finished Aug 16 05:54:45 PM PDT 24
Peak memory 209520 kb
Host smart-59f51970-36b6-4062-a37b-6c1696dea0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707463035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3707463035
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2959350749
Short name T441
Test name
Test status
Simulation time 122813976 ps
CPU time 2.89 seconds
Started Aug 16 05:54:28 PM PDT 24
Finished Aug 16 05:54:31 PM PDT 24
Peak memory 208800 kb
Host smart-f8161c0c-81a5-42be-864e-3c8797daa4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959350749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2959350749
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1135620631
Short name T901
Test name
Test status
Simulation time 837056013 ps
CPU time 28.85 seconds
Started Aug 16 05:54:33 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 209052 kb
Host smart-546fb546-3b6c-43f7-87a0-98aae41aee93
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135620631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1135620631
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3369907333
Short name T638
Test name
Test status
Simulation time 50359196 ps
CPU time 2.75 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 207412 kb
Host smart-9927944a-a96b-4b43-b121-33cf9b2d4043
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369907333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3369907333
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2595668311
Short name T478
Test name
Test status
Simulation time 164461110 ps
CPU time 4.19 seconds
Started Aug 16 05:54:05 PM PDT 24
Finished Aug 16 05:54:09 PM PDT 24
Peak memory 209084 kb
Host smart-3ed8389a-dee5-4bfa-b661-37b7087f82fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595668311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2595668311
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2766678357
Short name T395
Test name
Test status
Simulation time 70986306 ps
CPU time 2.46 seconds
Started Aug 16 05:54:45 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 210192 kb
Host smart-b650efd9-0e7b-4e70-9184-f9e8c8e90231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766678357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2766678357
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.769408045
Short name T761
Test name
Test status
Simulation time 1329520150 ps
CPU time 13.03 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:54:45 PM PDT 24
Peak memory 209368 kb
Host smart-3efa82eb-748e-461f-954d-c1e9af8d33c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769408045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.769408045
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1577401531
Short name T283
Test name
Test status
Simulation time 801285210 ps
CPU time 15.44 seconds
Started Aug 16 05:54:41 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 222956 kb
Host smart-49b39d9b-1dca-4c74-bfe3-9588fd42786e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577401531 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1577401531
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.613239785
Short name T333
Test name
Test status
Simulation time 927911146 ps
CPU time 5.59 seconds
Started Aug 16 05:54:38 PM PDT 24
Finished Aug 16 05:54:43 PM PDT 24
Peak memory 214664 kb
Host smart-1654f0ae-29de-4e41-9c11-cc38764a0b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613239785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.613239785
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1973756920
Short name T685
Test name
Test status
Simulation time 78121347 ps
CPU time 1.31 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 208956 kb
Host smart-cc0da92f-3da6-4583-85fb-473ee795bcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973756920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1973756920
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1069057433
Short name T614
Test name
Test status
Simulation time 47076216 ps
CPU time 0.8 seconds
Started Aug 16 05:52:37 PM PDT 24
Finished Aug 16 05:52:38 PM PDT 24
Peak memory 206340 kb
Host smart-0415b409-1cc4-463a-9e15-415e7fec66aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069057433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1069057433
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1867463027
Short name T709
Test name
Test status
Simulation time 111363064 ps
CPU time 2.49 seconds
Started Aug 16 05:53:03 PM PDT 24
Finished Aug 16 05:53:05 PM PDT 24
Peak memory 215720 kb
Host smart-f839dfac-7bc5-49d8-a9e7-3c2fca883b8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867463027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1867463027
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.16634657
Short name T428
Test name
Test status
Simulation time 191024799 ps
CPU time 5.55 seconds
Started Aug 16 05:52:41 PM PDT 24
Finished Aug 16 05:52:47 PM PDT 24
Peak memory 218756 kb
Host smart-91e66c25-15b9-4e3b-b989-1fd7ac5f35c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16634657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.16634657
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1886100935
Short name T12
Test name
Test status
Simulation time 1195059098 ps
CPU time 4.05 seconds
Started Aug 16 05:53:04 PM PDT 24
Finished Aug 16 05:53:08 PM PDT 24
Peak memory 208632 kb
Host smart-e3456d1b-2f50-48e9-ab44-ee50e233c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886100935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1886100935
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.4032283310
Short name T857
Test name
Test status
Simulation time 496476829 ps
CPU time 4.34 seconds
Started Aug 16 05:53:06 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 214848 kb
Host smart-2eb07718-1ea0-4bfd-a8ec-72abbe9a9672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032283310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4032283310
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3908529169
Short name T661
Test name
Test status
Simulation time 138692705 ps
CPU time 4.16 seconds
Started Aug 16 05:52:41 PM PDT 24
Finished Aug 16 05:52:45 PM PDT 24
Peak memory 222836 kb
Host smart-c4369c5c-1ba7-4575-9f28-d250c1312b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908529169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3908529169
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.443663235
Short name T835
Test name
Test status
Simulation time 69235104 ps
CPU time 3.2 seconds
Started Aug 16 05:52:40 PM PDT 24
Finished Aug 16 05:52:44 PM PDT 24
Peak memory 215044 kb
Host smart-63cbf881-5c1d-4f10-8efd-18103a598e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443663235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.443663235
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3399674694
Short name T793
Test name
Test status
Simulation time 371146947 ps
CPU time 3.33 seconds
Started Aug 16 05:53:03 PM PDT 24
Finished Aug 16 05:53:07 PM PDT 24
Peak memory 209484 kb
Host smart-23260172-3bc5-44aa-83a1-99682c5656b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399674694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3399674694
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.77798384
Short name T9
Test name
Test status
Simulation time 320916941 ps
CPU time 7.42 seconds
Started Aug 16 05:52:40 PM PDT 24
Finished Aug 16 05:52:48 PM PDT 24
Peak memory 238568 kb
Host smart-32d79fbf-cdf2-4efc-ae15-a2a0e743dae7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77798384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.77798384
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2557029433
Short name T455
Test name
Test status
Simulation time 116743886 ps
CPU time 2.2 seconds
Started Aug 16 05:52:40 PM PDT 24
Finished Aug 16 05:52:42 PM PDT 24
Peak memory 207344 kb
Host smart-021763b2-3773-47ca-9f45-fd54a43baa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557029433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2557029433
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3703016388
Short name T613
Test name
Test status
Simulation time 122816039 ps
CPU time 2.35 seconds
Started Aug 16 05:53:03 PM PDT 24
Finished Aug 16 05:53:06 PM PDT 24
Peak memory 207352 kb
Host smart-eab46a6b-e768-4c6f-8826-a27287c298f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703016388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3703016388
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1710597172
Short name T682
Test name
Test status
Simulation time 263732425 ps
CPU time 3.52 seconds
Started Aug 16 05:52:40 PM PDT 24
Finished Aug 16 05:52:44 PM PDT 24
Peak memory 209040 kb
Host smart-9ce13eac-5fca-4b1f-8e86-b586249f9ddd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710597172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1710597172
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3725330550
Short name T220
Test name
Test status
Simulation time 253777982 ps
CPU time 3.04 seconds
Started Aug 16 05:52:36 PM PDT 24
Finished Aug 16 05:52:39 PM PDT 24
Peak memory 209032 kb
Host smart-178015a3-b93e-40b1-be06-51f00026de55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725330550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3725330550
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.220901464
Short name T242
Test name
Test status
Simulation time 266962479 ps
CPU time 3.84 seconds
Started Aug 16 05:53:13 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 222772 kb
Host smart-8efbbefa-9e02-49b2-8bd3-56264398c3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220901464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.220901464
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.281643259
Short name T699
Test name
Test status
Simulation time 168850585 ps
CPU time 5.52 seconds
Started Aug 16 05:53:12 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 207172 kb
Host smart-176588da-ba47-4d77-983e-4f80ccef1b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281643259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.281643259
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.981138859
Short name T104
Test name
Test status
Simulation time 2147993130 ps
CPU time 21.31 seconds
Started Aug 16 05:53:13 PM PDT 24
Finished Aug 16 05:53:35 PM PDT 24
Peak memory 221376 kb
Host smart-4739174c-7f8b-4358-b30e-f960dc4da474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981138859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.981138859
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3570854531
Short name T743
Test name
Test status
Simulation time 238100506 ps
CPU time 7.24 seconds
Started Aug 16 05:53:08 PM PDT 24
Finished Aug 16 05:53:15 PM PDT 24
Peak memory 209828 kb
Host smart-3a206756-f32a-4890-85fc-689b178e7885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570854531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3570854531
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2217569099
Short name T891
Test name
Test status
Simulation time 793738604 ps
CPU time 20.59 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 211408 kb
Host smart-38c5e67d-785d-48da-bb8c-4ceefe7cd1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217569099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2217569099
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3808072493
Short name T714
Test name
Test status
Simulation time 44630116 ps
CPU time 0.78 seconds
Started Aug 16 05:54:05 PM PDT 24
Finished Aug 16 05:54:06 PM PDT 24
Peak memory 206396 kb
Host smart-17c1b4f2-f19a-4116-b13b-0b1e943a6ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808072493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3808072493
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2924325548
Short name T289
Test name
Test status
Simulation time 53285917 ps
CPU time 4.15 seconds
Started Aug 16 05:54:09 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 215948 kb
Host smart-c5825966-5fea-4a12-a990-d27c8de1e859
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924325548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2924325548
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2966257571
Short name T453
Test name
Test status
Simulation time 105627541 ps
CPU time 2.16 seconds
Started Aug 16 05:54:27 PM PDT 24
Finished Aug 16 05:54:29 PM PDT 24
Peak memory 210124 kb
Host smart-c4c6fdd3-f18f-4519-8e38-c24342472772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966257571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2966257571
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3381461489
Short name T324
Test name
Test status
Simulation time 60933892 ps
CPU time 3.05 seconds
Started Aug 16 05:54:09 PM PDT 24
Finished Aug 16 05:54:13 PM PDT 24
Peak memory 210764 kb
Host smart-1ee857b2-4249-4f58-9d41-877afc76248e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381461489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3381461489
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1731875946
Short name T303
Test name
Test status
Simulation time 710947799 ps
CPU time 3.03 seconds
Started Aug 16 05:54:37 PM PDT 24
Finished Aug 16 05:54:40 PM PDT 24
Peak memory 214700 kb
Host smart-11e3c762-1f92-42a8-969a-d4e38066a4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731875946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1731875946
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2262383443
Short name T592
Test name
Test status
Simulation time 103637062 ps
CPU time 3.32 seconds
Started Aug 16 05:54:09 PM PDT 24
Finished Aug 16 05:54:13 PM PDT 24
Peak memory 210308 kb
Host smart-e1853f9b-f4d5-4448-8fd3-09663823c181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262383443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2262383443
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1227931289
Short name T499
Test name
Test status
Simulation time 313439850 ps
CPU time 3.86 seconds
Started Aug 16 05:54:42 PM PDT 24
Finished Aug 16 05:54:46 PM PDT 24
Peak memory 207864 kb
Host smart-d5b1fe23-7378-41b2-a253-921516ad2fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227931289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1227931289
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.831189512
Short name T737
Test name
Test status
Simulation time 63442581 ps
CPU time 3.05 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 209260 kb
Host smart-c87653b8-1fc4-4925-bcba-b3262e9e4732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831189512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.831189512
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1864942109
Short name T890
Test name
Test status
Simulation time 564060847 ps
CPU time 3.01 seconds
Started Aug 16 05:54:41 PM PDT 24
Finished Aug 16 05:54:44 PM PDT 24
Peak memory 207304 kb
Host smart-121081a2-a6f0-424c-b9fd-4e0f14a27e7b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864942109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1864942109
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.623600448
Short name T566
Test name
Test status
Simulation time 225860542 ps
CPU time 2.98 seconds
Started Aug 16 05:54:04 PM PDT 24
Finished Aug 16 05:54:07 PM PDT 24
Peak memory 207492 kb
Host smart-109c8db6-5f17-4c9b-84d6-0dc01a37f6e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623600448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.623600448
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.37358753
Short name T216
Test name
Test status
Simulation time 914543405 ps
CPU time 6.36 seconds
Started Aug 16 05:54:40 PM PDT 24
Finished Aug 16 05:54:46 PM PDT 24
Peak memory 209144 kb
Host smart-22ef0003-fd96-42b3-9a80-275290445eca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37358753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.37358753
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.441118619
Short name T472
Test name
Test status
Simulation time 57586897 ps
CPU time 2.17 seconds
Started Aug 16 05:54:35 PM PDT 24
Finished Aug 16 05:54:37 PM PDT 24
Peak memory 216448 kb
Host smart-63a7c3d2-b12c-419f-bcb7-8c45c86dd9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441118619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.441118619
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3914277469
Short name T659
Test name
Test status
Simulation time 73132776 ps
CPU time 2.64 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:09 PM PDT 24
Peak memory 208780 kb
Host smart-c6e108b2-d296-49c2-a36b-996a8229b706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914277469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3914277469
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3861885617
Short name T650
Test name
Test status
Simulation time 603845868 ps
CPU time 5.07 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 209568 kb
Host smart-d4b0bddd-2518-4675-9065-a8590b1cc9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861885617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3861885617
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2604934681
Short name T359
Test name
Test status
Simulation time 184613662 ps
CPU time 1.68 seconds
Started Aug 16 05:54:44 PM PDT 24
Finished Aug 16 05:54:46 PM PDT 24
Peak memory 210404 kb
Host smart-4b19b246-66eb-44bd-8633-875d24c39f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604934681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2604934681
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1127799910
Short name T440
Test name
Test status
Simulation time 17961747 ps
CPU time 0.73 seconds
Started Aug 16 05:54:07 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 206400 kb
Host smart-deb33abd-3bc1-47a7-a56c-9d94280bed75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127799910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1127799910
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2037887964
Short name T671
Test name
Test status
Simulation time 386422794 ps
CPU time 3.74 seconds
Started Aug 16 05:55:02 PM PDT 24
Finished Aug 16 05:55:06 PM PDT 24
Peak memory 208396 kb
Host smart-111910df-4c7a-4925-8744-03846e096827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037887964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2037887964
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3470347195
Short name T60
Test name
Test status
Simulation time 121707415 ps
CPU time 5.59 seconds
Started Aug 16 05:54:41 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 214756 kb
Host smart-0f000a8e-7d3c-4e49-b88d-f6da260d5133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470347195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3470347195
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.4245488656
Short name T616
Test name
Test status
Simulation time 99915370 ps
CPU time 3.39 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 214616 kb
Host smart-cfcba825-7357-49f4-9825-1817eb5058bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245488656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.4245488656
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3787781275
Short name T184
Test name
Test status
Simulation time 120334114 ps
CPU time 3.98 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:11 PM PDT 24
Peak memory 210424 kb
Host smart-9efb43e0-48be-4f71-b8d0-30fe3307e3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787781275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3787781275
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.774377998
Short name T228
Test name
Test status
Simulation time 6220191425 ps
CPU time 42.17 seconds
Started Aug 16 05:54:44 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 210448 kb
Host smart-8aacd761-073a-4a18-80c2-4ca4ee0449a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774377998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.774377998
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1135762076
Short name T660
Test name
Test status
Simulation time 371761377 ps
CPU time 4.81 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 208680 kb
Host smart-e639eff4-5d78-4c41-ac46-257771061017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135762076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1135762076
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.613774683
Short name T506
Test name
Test status
Simulation time 191292467 ps
CPU time 4.57 seconds
Started Aug 16 05:54:34 PM PDT 24
Finished Aug 16 05:54:38 PM PDT 24
Peak memory 208912 kb
Host smart-42cf68ff-68c2-41d6-8cad-864bf1d8b7da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613774683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.613774683
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.483230875
Short name T627
Test name
Test status
Simulation time 61796078 ps
CPU time 3 seconds
Started Aug 16 05:54:30 PM PDT 24
Finished Aug 16 05:54:33 PM PDT 24
Peak memory 207348 kb
Host smart-76892015-4a87-4a19-b745-e7749a6cd615
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483230875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.483230875
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.568323364
Short name T226
Test name
Test status
Simulation time 201980580 ps
CPU time 3.49 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:54:27 PM PDT 24
Peak memory 209264 kb
Host smart-847c0bfc-421a-4d2d-9e4d-1254990b7c6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568323364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.568323364
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4177184240
Short name T666
Test name
Test status
Simulation time 1409387356 ps
CPU time 14.63 seconds
Started Aug 16 05:54:07 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 222900 kb
Host smart-0be351f5-c675-40b8-9761-7f55945c8690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177184240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4177184240
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1443879761
Short name T420
Test name
Test status
Simulation time 112616733 ps
CPU time 2.73 seconds
Started Aug 16 05:54:36 PM PDT 24
Finished Aug 16 05:54:39 PM PDT 24
Peak memory 208760 kb
Host smart-7244694d-27d7-4ec2-90e0-387ad11a63af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443879761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1443879761
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2466894237
Short name T485
Test name
Test status
Simulation time 235811107 ps
CPU time 6.75 seconds
Started Aug 16 05:54:44 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 220396 kb
Host smart-3adebff8-df1f-4a9e-a938-64da4382fb8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466894237 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2466894237
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1778353331
Short name T816
Test name
Test status
Simulation time 1592472667 ps
CPU time 5.74 seconds
Started Aug 16 05:54:07 PM PDT 24
Finished Aug 16 05:54:13 PM PDT 24
Peak memory 208588 kb
Host smart-3303cfb9-0f0a-49f3-a3a3-d36d90632c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778353331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1778353331
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.718256201
Short name T457
Test name
Test status
Simulation time 34571042 ps
CPU time 1.68 seconds
Started Aug 16 05:54:07 PM PDT 24
Finished Aug 16 05:54:09 PM PDT 24
Peak memory 210324 kb
Host smart-c415b5f2-ca78-475c-abfb-01066beea62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718256201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.718256201
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2752019911
Short name T702
Test name
Test status
Simulation time 14910441 ps
CPU time 0.88 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:07 PM PDT 24
Peak memory 206336 kb
Host smart-4a55f0c9-533a-4148-baaf-66419830bedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752019911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2752019911
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2976411317
Short name T225
Test name
Test status
Simulation time 176090062 ps
CPU time 9.61 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 215756 kb
Host smart-264b3eb7-8cce-431e-837f-80404b9a1244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2976411317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2976411317
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2887638093
Short name T747
Test name
Test status
Simulation time 109277900 ps
CPU time 2.07 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:46 PM PDT 24
Peak memory 218524 kb
Host smart-a9cd2762-3a0c-4e3e-b753-27d903193552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887638093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2887638093
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1010536555
Short name T248
Test name
Test status
Simulation time 231666626 ps
CPU time 3.21 seconds
Started Aug 16 05:54:05 PM PDT 24
Finished Aug 16 05:54:08 PM PDT 24
Peak memory 209836 kb
Host smart-3082dbf6-716c-47c9-9635-811da28dd1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010536555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1010536555
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.499876053
Short name T342
Test name
Test status
Simulation time 133179767 ps
CPU time 2.41 seconds
Started Aug 16 05:54:46 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 214648 kb
Host smart-6572e901-2905-470c-a419-e940169f00e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499876053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.499876053
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.866102547
Short name T185
Test name
Test status
Simulation time 45081507 ps
CPU time 3.15 seconds
Started Aug 16 05:54:10 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 209424 kb
Host smart-c1ba7c03-be9b-4401-97dd-f443e1426a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866102547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.866102547
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.4277602978
Short name T288
Test name
Test status
Simulation time 213614928 ps
CPU time 5.66 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:17 PM PDT 24
Peak memory 208772 kb
Host smart-f645dcd4-6a07-4c79-b1e0-dd7c95251be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277602978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.4277602978
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3286616291
Short name T553
Test name
Test status
Simulation time 21162455 ps
CPU time 1.74 seconds
Started Aug 16 05:54:25 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 207328 kb
Host smart-7c437212-3025-4cfa-a7f6-edbcc6ed4046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286616291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3286616291
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3797352199
Short name T464
Test name
Test status
Simulation time 287257863 ps
CPU time 6.78 seconds
Started Aug 16 05:54:31 PM PDT 24
Finished Aug 16 05:54:38 PM PDT 24
Peak memory 208572 kb
Host smart-810f2efa-fd09-4ed7-a059-8efb228abbef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797352199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3797352199
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1238595262
Short name T628
Test name
Test status
Simulation time 150143000 ps
CPU time 3.69 seconds
Started Aug 16 05:54:12 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 209032 kb
Host smart-6447cde5-58b4-45ae-a5ff-2983f123ef34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238595262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1238595262
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.4197944481
Short name T182
Test name
Test status
Simulation time 157156057 ps
CPU time 5 seconds
Started Aug 16 05:54:15 PM PDT 24
Finished Aug 16 05:54:20 PM PDT 24
Peak memory 208448 kb
Host smart-32e2bf94-5928-4624-aac8-2b105a927587
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197944481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.4197944481
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.702808059
Short name T422
Test name
Test status
Simulation time 132592494 ps
CPU time 5.19 seconds
Started Aug 16 05:54:08 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 210260 kb
Host smart-f4852024-03e6-4ba3-adf1-adb783620968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702808059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.702808059
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1985903179
Short name T872
Test name
Test status
Simulation time 1022903127 ps
CPU time 3.06 seconds
Started Aug 16 05:54:06 PM PDT 24
Finished Aug 16 05:54:09 PM PDT 24
Peak memory 207256 kb
Host smart-7a4ac764-acd1-4901-8eb8-4ce4905e6927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985903179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1985903179
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4030545256
Short name T469
Test name
Test status
Simulation time 3473277754 ps
CPU time 19.88 seconds
Started Aug 16 05:54:30 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 209284 kb
Host smart-cc97a08f-5c5a-4c99-8bfa-4d3b797bcd40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030545256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4030545256
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1365230947
Short name T885
Test name
Test status
Simulation time 303303875 ps
CPU time 4.12 seconds
Started Aug 16 05:54:44 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 209464 kb
Host smart-b78d4a43-b043-4f6f-96fe-d14aa8863f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365230947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1365230947
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1615291254
Short name T635
Test name
Test status
Simulation time 235450734 ps
CPU time 2.54 seconds
Started Aug 16 05:54:07 PM PDT 24
Finished Aug 16 05:54:09 PM PDT 24
Peak memory 210664 kb
Host smart-9812a927-9944-4d88-af7e-bc320400ae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615291254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1615291254
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.39786595
Short name T561
Test name
Test status
Simulation time 22895465 ps
CPU time 1.03 seconds
Started Aug 16 05:54:40 PM PDT 24
Finished Aug 16 05:54:41 PM PDT 24
Peak memory 206668 kb
Host smart-e6b75395-f6f3-4db5-87ab-460bea68c0d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39786595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.39786595
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1987487192
Short name T378
Test name
Test status
Simulation time 62669232 ps
CPU time 2.85 seconds
Started Aug 16 05:54:48 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 214848 kb
Host smart-b1572fa1-6302-415a-bef7-ff99355c42f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987487192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1987487192
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.4143597620
Short name T764
Test name
Test status
Simulation time 1967667899 ps
CPU time 4.65 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 210208 kb
Host smart-c145d618-5e42-433c-ae11-87b85bc5332e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143597620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4143597620
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3461369342
Short name T865
Test name
Test status
Simulation time 66040890 ps
CPU time 2.94 seconds
Started Aug 16 05:54:08 PM PDT 24
Finished Aug 16 05:54:11 PM PDT 24
Peak memory 209272 kb
Host smart-dc00acbe-9ebb-495e-aa04-0d162a850212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461369342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3461369342
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1380565955
Short name T599
Test name
Test status
Simulation time 66000301 ps
CPU time 3 seconds
Started Aug 16 05:54:12 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 214724 kb
Host smart-c502fea7-55f2-4391-b59e-52555b177c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380565955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1380565955
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.297730822
Short name T326
Test name
Test status
Simulation time 314879529 ps
CPU time 6.45 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 222828 kb
Host smart-3f4b7090-50e9-4a13-bfff-89cffd26fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297730822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.297730822
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_random.1059326882
Short name T591
Test name
Test status
Simulation time 79769732 ps
CPU time 4.11 seconds
Started Aug 16 05:54:33 PM PDT 24
Finished Aug 16 05:54:37 PM PDT 24
Peak memory 218632 kb
Host smart-018bb32f-5c98-4a89-ab6c-6600d4c71d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059326882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1059326882
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2204687155
Short name T874
Test name
Test status
Simulation time 57407961 ps
CPU time 2.23 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 207340 kb
Host smart-29f0ac7c-8d0c-4615-83f8-bcb15725804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204687155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2204687155
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1774853276
Short name T487
Test name
Test status
Simulation time 243738390 ps
CPU time 2.99 seconds
Started Aug 16 05:54:15 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 209020 kb
Host smart-643cd77a-cea8-4c2d-a1ea-0f45fecec648
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774853276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1774853276
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3845525278
Short name T565
Test name
Test status
Simulation time 257434936 ps
CPU time 3.73 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 207220 kb
Host smart-3a5de5df-4ced-4083-8be8-64dd6bb30b74
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845525278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3845525278
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2522558323
Short name T738
Test name
Test status
Simulation time 121504452 ps
CPU time 3.86 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:54:36 PM PDT 24
Peak memory 209076 kb
Host smart-ff4f87a5-3dfa-467d-9cf2-086851ea53e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522558323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2522558323
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1063424330
Short name T331
Test name
Test status
Simulation time 72858334 ps
CPU time 2.4 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 209668 kb
Host smart-a9c0bf75-c526-4195-a4ef-b7ebe6bfe3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063424330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1063424330
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1966988120
Short name T563
Test name
Test status
Simulation time 213326025 ps
CPU time 2.17 seconds
Started Aug 16 05:54:48 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 207316 kb
Host smart-f6df9fd5-38d9-49d7-b0f1-f63c117f5748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966988120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1966988120
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2449746813
Short name T836
Test name
Test status
Simulation time 19880801156 ps
CPU time 50.25 seconds
Started Aug 16 05:54:41 PM PDT 24
Finished Aug 16 05:55:37 PM PDT 24
Peak memory 215860 kb
Host smart-92b15c2d-e3c2-424b-86a9-78d797bdc8b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449746813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2449746813
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2729930011
Short name T905
Test name
Test status
Simulation time 168387631 ps
CPU time 4.61 seconds
Started Aug 16 05:54:12 PM PDT 24
Finished Aug 16 05:54:17 PM PDT 24
Peak memory 209388 kb
Host smart-500c962a-b31c-4135-b1f8-f7a80e94d4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729930011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2729930011
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.469888533
Short name T752
Test name
Test status
Simulation time 69960946 ps
CPU time 2.19 seconds
Started Aug 16 05:54:37 PM PDT 24
Finished Aug 16 05:54:40 PM PDT 24
Peak memory 211008 kb
Host smart-977f98ab-54f3-475b-85f7-da460eaa4801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469888533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.469888533
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3519364321
Short name T727
Test name
Test status
Simulation time 48825101 ps
CPU time 0.93 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 206568 kb
Host smart-259e8a92-8b35-43e8-b5af-b8fd98bbfc01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519364321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3519364321
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.725929001
Short name T317
Test name
Test status
Simulation time 198475356 ps
CPU time 9.88 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 214760 kb
Host smart-d2c270bd-5a58-4259-9920-8a92d1e1d8ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725929001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.725929001
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.4029505798
Short name T887
Test name
Test status
Simulation time 65296211 ps
CPU time 2.85 seconds
Started Aug 16 05:54:14 PM PDT 24
Finished Aug 16 05:54:17 PM PDT 24
Peak memory 222800 kb
Host smart-9b36dcc7-5f96-40bf-aab3-01d52656d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029505798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.4029505798
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2177518497
Short name T133
Test name
Test status
Simulation time 367855212 ps
CPU time 8.6 seconds
Started Aug 16 05:54:37 PM PDT 24
Finished Aug 16 05:54:46 PM PDT 24
Peak memory 209336 kb
Host smart-8fc75609-5b1c-4a82-b16e-0bf59a59dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177518497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2177518497
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2606912468
Short name T507
Test name
Test status
Simulation time 55265145 ps
CPU time 2 seconds
Started Aug 16 05:54:14 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 214760 kb
Host smart-66022ecf-ad72-483d-baa5-a742f9a0d7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606912468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2606912468
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1081087283
Short name T235
Test name
Test status
Simulation time 104746396 ps
CPU time 3.62 seconds
Started Aug 16 05:54:48 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 214724 kb
Host smart-778b9c56-9529-4555-b262-1eae5f8054cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081087283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1081087283
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3465789034
Short name T130
Test name
Test status
Simulation time 222559757 ps
CPU time 3.43 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 220412 kb
Host smart-ebc51c94-4d10-4ffe-b8cf-d34c28e8da6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465789034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3465789034
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1816297657
Short name T291
Test name
Test status
Simulation time 86567300 ps
CPU time 3.94 seconds
Started Aug 16 05:54:45 PM PDT 24
Finished Aug 16 05:54:49 PM PDT 24
Peak memory 207940 kb
Host smart-2e5253ad-1d6f-48d2-b57f-991f2b5cd838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816297657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1816297657
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3049333649
Short name T774
Test name
Test status
Simulation time 725422784 ps
CPU time 10.51 seconds
Started Aug 16 05:54:15 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 209464 kb
Host smart-8372ac97-7f96-4a65-8aab-0e51ad0d43fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049333649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3049333649
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.775406147
Short name T771
Test name
Test status
Simulation time 276256240 ps
CPU time 3.12 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 207260 kb
Host smart-f8b511f4-e5db-4651-8e61-4d63d898d221
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775406147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.775406147
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.774782891
Short name T748
Test name
Test status
Simulation time 1186734100 ps
CPU time 8.17 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 208408 kb
Host smart-cf9fad35-ba40-497c-97bc-536cc52f5c95
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774782891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.774782891
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2996144625
Short name T458
Test name
Test status
Simulation time 30887031 ps
CPU time 2.18 seconds
Started Aug 16 05:54:46 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 209508 kb
Host smart-4a78965f-ba13-4a34-a3de-cdc0c0926b51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996144625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2996144625
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2337387617
Short name T820
Test name
Test status
Simulation time 94745782 ps
CPU time 1.92 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:15 PM PDT 24
Peak memory 216428 kb
Host smart-af8645c5-2433-4999-bf2a-3675dab32526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337387617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2337387617
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2284673584
Short name T594
Test name
Test status
Simulation time 479086106 ps
CPU time 10.69 seconds
Started Aug 16 05:54:38 PM PDT 24
Finished Aug 16 05:54:49 PM PDT 24
Peak memory 208280 kb
Host smart-947ac085-a013-495d-8b12-9d246b906442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284673584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2284673584
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1952564012
Short name T218
Test name
Test status
Simulation time 228330991 ps
CPU time 7.63 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 222888 kb
Host smart-bd2e003b-3089-41a0-9085-aa57caa28001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952564012 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1952564012
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2337787719
Short name T765
Test name
Test status
Simulation time 114624551 ps
CPU time 5.77 seconds
Started Aug 16 05:54:16 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 209960 kb
Host smart-a67dd21e-8398-477f-ac27-7f5ce2d3acc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337787719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2337787719
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1775994900
Short name T421
Test name
Test status
Simulation time 64928270 ps
CPU time 2.43 seconds
Started Aug 16 05:54:15 PM PDT 24
Finished Aug 16 05:54:17 PM PDT 24
Peak memory 210884 kb
Host smart-0dd08adf-bdc1-4cf2-97e2-2da272e41044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775994900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1775994900
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1843001672
Short name T173
Test name
Test status
Simulation time 13037526 ps
CPU time 0.71 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 206260 kb
Host smart-6dac584f-aea8-4262-a400-3a79d367b86a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843001672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1843001672
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3028181809
Short name T756
Test name
Test status
Simulation time 1231977279 ps
CPU time 10.43 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:29 PM PDT 24
Peak memory 214792 kb
Host smart-93204b3e-fd60-4d9f-af72-5a2bf9d00de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028181809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3028181809
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2333126351
Short name T849
Test name
Test status
Simulation time 83552000 ps
CPU time 3.73 seconds
Started Aug 16 05:54:40 PM PDT 24
Finished Aug 16 05:54:44 PM PDT 24
Peak memory 209740 kb
Host smart-27d20922-2763-4f98-81af-7f3e1d4e2648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333126351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2333126351
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2715647040
Short name T417
Test name
Test status
Simulation time 439958025 ps
CPU time 2.5 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 207892 kb
Host smart-7da383d7-6e43-49b8-a3e5-d3ccf094cc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715647040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2715647040
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2517222353
Short name T20
Test name
Test status
Simulation time 104757008 ps
CPU time 2.33 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:54:49 PM PDT 24
Peak memory 214640 kb
Host smart-b5002e9f-7f1a-4f88-b4a5-5f861c268809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517222353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2517222353
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3897901620
Short name T341
Test name
Test status
Simulation time 393533034 ps
CPU time 5.09 seconds
Started Aug 16 05:54:29 PM PDT 24
Finished Aug 16 05:54:35 PM PDT 24
Peak memory 222076 kb
Host smart-118f01e6-e5cc-49c5-8f6e-f7ee468b0ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897901620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3897901620
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1611634764
Short name T867
Test name
Test status
Simulation time 76482524 ps
CPU time 3.72 seconds
Started Aug 16 05:54:14 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 210148 kb
Host smart-8fb4b85e-633f-40f0-a6f6-7cc1ff8d256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611634764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1611634764
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.4235618010
Short name T470
Test name
Test status
Simulation time 123167501 ps
CPU time 3.15 seconds
Started Aug 16 05:54:30 PM PDT 24
Finished Aug 16 05:54:33 PM PDT 24
Peak memory 209780 kb
Host smart-635fe3d0-031d-47dd-90dd-5b175fcdeb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235618010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.4235618010
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1960496008
Short name T712
Test name
Test status
Simulation time 185441657 ps
CPU time 6.55 seconds
Started Aug 16 05:54:49 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 208528 kb
Host smart-a5618ce8-0f8d-4d62-8453-34910e16b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960496008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1960496008
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2770543010
Short name T670
Test name
Test status
Simulation time 510919429 ps
CPU time 5.92 seconds
Started Aug 16 05:54:14 PM PDT 24
Finished Aug 16 05:54:20 PM PDT 24
Peak memory 209620 kb
Host smart-7fd61432-2f4f-4cc2-9ccc-360d322ef6ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770543010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2770543010
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1491311390
Short name T723
Test name
Test status
Simulation time 171354751 ps
CPU time 4.42 seconds
Started Aug 16 05:54:48 PM PDT 24
Finished Aug 16 05:54:52 PM PDT 24
Peak memory 209264 kb
Host smart-1c923d96-6e1a-4cb8-a758-576d0addafcd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491311390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1491311390
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.821994525
Short name T446
Test name
Test status
Simulation time 260626324 ps
CPU time 3.19 seconds
Started Aug 16 05:54:15 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 209096 kb
Host smart-54f6a072-2e7c-4365-b671-2513a609f72c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821994525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.821994525
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2833743438
Short name T541
Test name
Test status
Simulation time 1779123571 ps
CPU time 7.11 seconds
Started Aug 16 05:54:16 PM PDT 24
Finished Aug 16 05:54:23 PM PDT 24
Peak memory 209484 kb
Host smart-1bac7d8e-834f-4c7e-be89-10ce275c7c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833743438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2833743438
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.834523263
Short name T676
Test name
Test status
Simulation time 166084516 ps
CPU time 2.44 seconds
Started Aug 16 05:54:42 PM PDT 24
Finished Aug 16 05:54:45 PM PDT 24
Peak memory 207680 kb
Host smart-1a2a16f3-20a7-474b-a648-d285fde29450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834523263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.834523263
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2515175027
Short name T863
Test name
Test status
Simulation time 411259123 ps
CPU time 21.3 seconds
Started Aug 16 05:55:07 PM PDT 24
Finished Aug 16 05:55:34 PM PDT 24
Peak memory 216400 kb
Host smart-6867a019-dc0e-4601-8dec-fcd5f19c1bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515175027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2515175027
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1835809966
Short name T171
Test name
Test status
Simulation time 340240124 ps
CPU time 12.42 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:56 PM PDT 24
Peak memory 221904 kb
Host smart-3d8d121a-1e79-4b0e-8610-9b0a38133961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835809966 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1835809966
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.924776650
Short name T547
Test name
Test status
Simulation time 470586948 ps
CPU time 11.31 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:29 PM PDT 24
Peak memory 208432 kb
Host smart-3753b88c-2721-466c-8317-26a050a6064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924776650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.924776650
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3959692794
Short name T686
Test name
Test status
Simulation time 10772609 ps
CPU time 0.83 seconds
Started Aug 16 05:54:56 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 206284 kb
Host smart-50bb6486-7611-4dc1-bc7f-c413c0f0a92f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959692794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3959692794
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2013307627
Short name T33
Test name
Test status
Simulation time 102144561 ps
CPU time 1.94 seconds
Started Aug 16 05:54:56 PM PDT 24
Finished Aug 16 05:54:58 PM PDT 24
Peak memory 216140 kb
Host smart-ebc69894-80f0-4a48-a37d-bc63a1fe8fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013307627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2013307627
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3449326556
Short name T898
Test name
Test status
Simulation time 76071379 ps
CPU time 2.04 seconds
Started Aug 16 05:54:42 PM PDT 24
Finished Aug 16 05:54:49 PM PDT 24
Peak memory 207660 kb
Host smart-3360cb69-b771-4f4d-923b-e999d83333e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449326556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3449326556
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3386569577
Short name T673
Test name
Test status
Simulation time 88787961 ps
CPU time 2.51 seconds
Started Aug 16 05:54:44 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 214660 kb
Host smart-0491f45e-1ad3-495c-ac7a-139000f73f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386569577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3386569577
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.142556678
Short name T262
Test name
Test status
Simulation time 363877457 ps
CPU time 4.07 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 207460 kb
Host smart-5468190f-ccfc-4f3d-8035-53b5602a5368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142556678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.142556678
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2229442860
Short name T749
Test name
Test status
Simulation time 434965119 ps
CPU time 3.29 seconds
Started Aug 16 05:54:42 PM PDT 24
Finished Aug 16 05:54:46 PM PDT 24
Peak memory 214772 kb
Host smart-8a00bf83-3b3f-4f6a-832c-d281410e4bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229442860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2229442860
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.882170291
Short name T539
Test name
Test status
Simulation time 1439397633 ps
CPU time 4.56 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 208448 kb
Host smart-75e7ba02-de1c-4d66-9873-881ba5ba56f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882170291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.882170291
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3478024454
Short name T316
Test name
Test status
Simulation time 66043561 ps
CPU time 3.41 seconds
Started Aug 16 05:54:15 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 208876 kb
Host smart-9e905d63-8aa9-4a39-baf8-2ae24dd5b370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478024454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3478024454
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2966046095
Short name T345
Test name
Test status
Simulation time 991851563 ps
CPU time 12.15 seconds
Started Aug 16 05:54:44 PM PDT 24
Finished Aug 16 05:54:56 PM PDT 24
Peak memory 208860 kb
Host smart-b7f4992e-ea98-4766-8835-f80afef8b593
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966046095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2966046095
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3473617008
Short name T701
Test name
Test status
Simulation time 68424496 ps
CPU time 2.62 seconds
Started Aug 16 05:54:13 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 209420 kb
Host smart-126c2b03-f0d6-4233-aa7d-5cf176559211
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473617008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3473617008
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3893579932
Short name T792
Test name
Test status
Simulation time 997210681 ps
CPU time 8.22 seconds
Started Aug 16 05:54:17 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 208660 kb
Host smart-fa1dcf3f-7917-4f7e-a819-48f303f2dc96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893579932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3893579932
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4204649297
Short name T403
Test name
Test status
Simulation time 186268351 ps
CPU time 1.97 seconds
Started Aug 16 05:54:16 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 208192 kb
Host smart-8ad1c48a-774a-4f3e-92f8-a7833f857132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204649297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4204649297
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1082126293
Short name T667
Test name
Test status
Simulation time 452969437 ps
CPU time 5.38 seconds
Started Aug 16 05:54:10 PM PDT 24
Finished Aug 16 05:54:16 PM PDT 24
Peak memory 207548 kb
Host smart-5a117baa-6886-417e-a2be-d4ab67a88278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082126293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1082126293
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.406861808
Short name T192
Test name
Test status
Simulation time 519777883 ps
CPU time 15.64 seconds
Started Aug 16 05:54:11 PM PDT 24
Finished Aug 16 05:54:27 PM PDT 24
Peak memory 221844 kb
Host smart-b27d7fb9-5ade-48eb-9b2b-cbcc41357069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406861808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.406861808
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1434493102
Short name T664
Test name
Test status
Simulation time 509312125 ps
CPU time 5.59 seconds
Started Aug 16 05:54:16 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 218856 kb
Host smart-3c1ecfcc-3652-4db3-a40c-662eab150660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434493102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1434493102
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2997008288
Short name T528
Test name
Test status
Simulation time 12622763 ps
CPU time 0.87 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 206424 kb
Host smart-f54944e5-62e8-474e-ae9f-e26667f5f8a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997008288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2997008288
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1523866687
Short name T798
Test name
Test status
Simulation time 4136065826 ps
CPU time 106.42 seconds
Started Aug 16 05:54:45 PM PDT 24
Finished Aug 16 05:56:31 PM PDT 24
Peak memory 218140 kb
Host smart-df9d1bc8-46ce-447d-b5d1-867dd818465d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523866687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1523866687
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2401956621
Short name T73
Test name
Test status
Simulation time 229184441 ps
CPU time 4.82 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:23 PM PDT 24
Peak memory 214776 kb
Host smart-dbc40853-7a77-4a52-a74e-79a18a0913be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401956621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2401956621
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1425806456
Short name T707
Test name
Test status
Simulation time 177103973 ps
CPU time 2.27 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 214896 kb
Host smart-539b0805-2f0f-453c-8391-a47e54d75ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425806456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1425806456
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1193455442
Short name T299
Test name
Test status
Simulation time 81488499 ps
CPU time 2.35 seconds
Started Aug 16 05:54:46 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 214640 kb
Host smart-d56b5935-3149-4c87-804c-049cdc74c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193455442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1193455442
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1473110463
Short name T540
Test name
Test status
Simulation time 85038669 ps
CPU time 3.08 seconds
Started Aug 16 05:54:46 PM PDT 24
Finished Aug 16 05:54:49 PM PDT 24
Peak memory 209728 kb
Host smart-4fa75684-474d-4cf4-bd39-547134165bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473110463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1473110463
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.4034843574
Short name T180
Test name
Test status
Simulation time 353625875 ps
CPU time 4.5 seconds
Started Aug 16 05:54:25 PM PDT 24
Finished Aug 16 05:54:30 PM PDT 24
Peak memory 207752 kb
Host smart-7079147a-9306-4222-9a96-587f74fb4bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034843574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.4034843574
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.303964280
Short name T290
Test name
Test status
Simulation time 108443843 ps
CPU time 2.3 seconds
Started Aug 16 05:54:45 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 207788 kb
Host smart-ef704f43-b7f1-406c-8e68-8470178b4e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303964280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.303964280
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1912407096
Short name T459
Test name
Test status
Simulation time 125324180 ps
CPU time 3.06 seconds
Started Aug 16 05:54:16 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 207444 kb
Host smart-81ac8b84-757f-43fd-9726-dcf3c8e63616
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912407096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1912407096
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.762950348
Short name T294
Test name
Test status
Simulation time 2072251704 ps
CPU time 11.8 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:17 PM PDT 24
Peak memory 208440 kb
Host smart-646682fe-aea6-4aac-8af9-5db3101697f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762950348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.762950348
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2384067494
Short name T690
Test name
Test status
Simulation time 139546098 ps
CPU time 3.74 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:54:58 PM PDT 24
Peak memory 207308 kb
Host smart-0a8e360b-93b8-4e4a-b00e-f3bc3c37b68e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384067494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2384067494
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1904364944
Short name T241
Test name
Test status
Simulation time 39935970 ps
CPU time 1.94 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:23 PM PDT 24
Peak memory 218780 kb
Host smart-8ba3e24a-4bac-4bc4-a58a-922bd7f96ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904364944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1904364944
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2253863150
Short name T622
Test name
Test status
Simulation time 366009422 ps
CPU time 4.87 seconds
Started Aug 16 05:54:17 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 208804 kb
Host smart-ccd18bd3-dbab-44d4-aba5-bb966d9b87be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253863150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2253863150
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2370957529
Short name T861
Test name
Test status
Simulation time 186916229 ps
CPU time 4.5 seconds
Started Aug 16 05:55:00 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 217180 kb
Host smart-d2d22280-4ce6-46ef-9769-79dbf9b69c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370957529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2370957529
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.717648868
Short name T258
Test name
Test status
Simulation time 277674128 ps
CPU time 18.3 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:37 PM PDT 24
Peak memory 224040 kb
Host smart-7a52ed25-e5b8-4541-837d-28e66cf8a6fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717648868 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.717648868
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1450292650
Short name T582
Test name
Test status
Simulation time 1562384947 ps
CPU time 28.22 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 209000 kb
Host smart-0f79ebff-70b2-4b6f-adbc-4f39723bce77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450292650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1450292650
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.156375833
Short name T889
Test name
Test status
Simulation time 81248084 ps
CPU time 2.26 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 210468 kb
Host smart-01cff849-ec64-4631-953d-6cadbbe95740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156375833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.156375833
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1589238208
Short name T703
Test name
Test status
Simulation time 40331562 ps
CPU time 0.71 seconds
Started Aug 16 05:54:56 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 206312 kb
Host smart-677f0183-f038-4f43-a336-d6b1914b30b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589238208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1589238208
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2193760654
Short name T394
Test name
Test status
Simulation time 256055027 ps
CPU time 12.58 seconds
Started Aug 16 05:54:22 PM PDT 24
Finished Aug 16 05:54:35 PM PDT 24
Peak memory 222844 kb
Host smart-452e9e21-e025-4450-8b56-8e823934f5b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193760654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2193760654
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3054066593
Short name T41
Test name
Test status
Simulation time 51435585 ps
CPU time 2.88 seconds
Started Aug 16 05:54:26 PM PDT 24
Finished Aug 16 05:54:29 PM PDT 24
Peak memory 214772 kb
Host smart-6491f0d5-ba97-4e8a-a408-d5c63f441d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054066593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3054066593
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2328831897
Short name T847
Test name
Test status
Simulation time 529638866 ps
CPU time 8.7 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:28 PM PDT 24
Peak memory 210020 kb
Host smart-cb99944e-1c0b-4316-a9f2-c85e96e6028a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328831897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2328831897
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.973218375
Short name T55
Test name
Test status
Simulation time 256749017 ps
CPU time 3.84 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:54:58 PM PDT 24
Peak memory 209940 kb
Host smart-1ea45ff6-bb6b-4261-b9e7-dca7fbeee0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973218375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.973218375
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2091997953
Short name T232
Test name
Test status
Simulation time 461527821 ps
CPU time 3.33 seconds
Started Aug 16 05:54:57 PM PDT 24
Finished Aug 16 05:55:01 PM PDT 24
Peak memory 214764 kb
Host smart-6d20fed7-d87f-47b7-a51b-9a2f22744521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091997953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2091997953
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1024540558
Short name T461
Test name
Test status
Simulation time 437879560 ps
CPU time 3.84 seconds
Started Aug 16 05:54:46 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 220772 kb
Host smart-7943c786-bdf8-4354-afe0-b7ad44467994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024540558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1024540558
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.919958401
Short name T268
Test name
Test status
Simulation time 347279598 ps
CPU time 7 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 210544 kb
Host smart-a029e27e-4a39-4d7b-ace7-209052925ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919958401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.919958401
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1309626929
Short name T551
Test name
Test status
Simulation time 46242200 ps
CPU time 1.92 seconds
Started Aug 16 05:54:22 PM PDT 24
Finished Aug 16 05:54:24 PM PDT 24
Peak memory 208804 kb
Host smart-16558980-3cb7-4463-857a-e7094f7be602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309626929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1309626929
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2282891733
Short name T426
Test name
Test status
Simulation time 73016664 ps
CPU time 2.69 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 207432 kb
Host smart-32ce48cd-fa4f-4fb6-a640-e92982075178
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282891733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2282891733
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3194770747
Short name T854
Test name
Test status
Simulation time 616590673 ps
CPU time 4.71 seconds
Started Aug 16 05:54:43 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 209368 kb
Host smart-37ce07fd-d1b0-45db-a6d0-3c0f60084040
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194770747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3194770747
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.486346835
Short name T640
Test name
Test status
Simulation time 1910731260 ps
CPU time 18.71 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:39 PM PDT 24
Peak memory 207888 kb
Host smart-f6e53e9b-7975-4f6c-9b9c-8cb978da8f1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486346835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.486346835
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3495730098
Short name T895
Test name
Test status
Simulation time 361044688 ps
CPU time 6.09 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 208448 kb
Host smart-19d4f200-dd6a-4e16-abfc-ecac0631d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495730098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3495730098
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1312287329
Short name T564
Test name
Test status
Simulation time 287061090 ps
CPU time 3.95 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 208896 kb
Host smart-7aa068fb-f522-4900-8038-36a60a679a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312287329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1312287329
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4207295908
Short name T766
Test name
Test status
Simulation time 2870074026 ps
CPU time 21.75 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:54:45 PM PDT 24
Peak memory 217016 kb
Host smart-8fab70dd-6804-4204-a2d2-d8a0218faa4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207295908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4207295908
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2202520660
Short name T168
Test name
Test status
Simulation time 731273850 ps
CPU time 7.08 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 223016 kb
Host smart-b896ee6e-138f-424d-a67e-09d9f279b2c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202520660 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2202520660
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3333835509
Short name T779
Test name
Test status
Simulation time 342665120 ps
CPU time 4.08 seconds
Started Aug 16 05:54:17 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 207436 kb
Host smart-0c417ab3-8daa-49a2-b92b-ed8ea888d0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333835509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3333835509
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3795025478
Short name T439
Test name
Test status
Simulation time 41215084 ps
CPU time 2.5 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:55:17 PM PDT 24
Peak memory 210824 kb
Host smart-f35d1af6-6944-4138-be07-79f88460e790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795025478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3795025478
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4159245133
Short name T498
Test name
Test status
Simulation time 23410681 ps
CPU time 0.83 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:55:09 PM PDT 24
Peak memory 206400 kb
Host smart-8ba982c8-33fe-4b73-a71f-072e55d37b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159245133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4159245133
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.258663198
Short name T381
Test name
Test status
Simulation time 73482054 ps
CPU time 5.11 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:24 PM PDT 24
Peak memory 215768 kb
Host smart-40497e48-8ead-4ae5-a284-db4dfeb3de20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258663198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.258663198
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3164060950
Short name T30
Test name
Test status
Simulation time 57142483 ps
CPU time 2.4 seconds
Started Aug 16 05:54:18 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 214856 kb
Host smart-4ea2a68f-140a-4cc0-bd35-138822f0316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164060950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3164060950
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.780807951
Short name T211
Test name
Test status
Simulation time 1786684360 ps
CPU time 15.88 seconds
Started Aug 16 05:54:17 PM PDT 24
Finished Aug 16 05:54:33 PM PDT 24
Peak memory 214756 kb
Host smart-559c3277-300c-4f90-b3a5-70edb0b2b3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780807951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.780807951
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.823511117
Short name T58
Test name
Test status
Simulation time 4557679768 ps
CPU time 32.27 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:55:20 PM PDT 24
Peak memory 214688 kb
Host smart-2bad5c40-fa8a-43e1-bffb-f6dd10cdbf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823511117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.823511117
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2841439943
Short name T51
Test name
Test status
Simulation time 118867003 ps
CPU time 3.9 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:24 PM PDT 24
Peak memory 222528 kb
Host smart-aeb4145b-bf07-4e0b-b930-fa80a0e75069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841439943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2841439943
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1005221496
Short name T705
Test name
Test status
Simulation time 66527335 ps
CPU time 3.04 seconds
Started Aug 16 05:54:44 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 220772 kb
Host smart-7e9e76b9-3dae-44c1-ad39-8c8aa523e909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005221496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1005221496
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3132105624
Short name T909
Test name
Test status
Simulation time 216790478 ps
CPU time 3.71 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 222932 kb
Host smart-9c9717e6-c00f-4349-bfb2-d7d6c2c27978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132105624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3132105624
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.4283858439
Short name T352
Test name
Test status
Simulation time 199758270 ps
CPU time 2.78 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 207368 kb
Host smart-804252e6-ebb7-47ec-919e-3c3b2a75cd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283858439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.4283858439
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4176392741
Short name T490
Test name
Test status
Simulation time 232092078 ps
CPU time 3.24 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 207172 kb
Host smart-eda3046d-530b-4de0-b80b-0c2bf78a73b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176392741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4176392741
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.167221661
Short name T286
Test name
Test status
Simulation time 1902229227 ps
CPU time 18.24 seconds
Started Aug 16 05:54:42 PM PDT 24
Finished Aug 16 05:55:00 PM PDT 24
Peak memory 209144 kb
Host smart-92ed9c28-dd9b-49df-8205-efa192a86428
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167221661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.167221661
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.987889521
Short name T465
Test name
Test status
Simulation time 432742286 ps
CPU time 3.23 seconds
Started Aug 16 05:55:06 PM PDT 24
Finished Aug 16 05:55:09 PM PDT 24
Peak memory 207256 kb
Host smart-4e0560d2-1cc5-4b32-a628-d0cd080f0637
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987889521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.987889521
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2269534757
Short name T746
Test name
Test status
Simulation time 269317570 ps
CPU time 6 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:55:01 PM PDT 24
Peak memory 209536 kb
Host smart-f3e9f213-c2e5-432f-bba6-7dc4a0e41672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269534757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2269534757
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.391767599
Short name T813
Test name
Test status
Simulation time 48770485 ps
CPU time 2.51 seconds
Started Aug 16 05:55:00 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 207220 kb
Host smart-52c85b9b-f632-435f-8e40-22b0dc3b0681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391767599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.391767599
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1956951807
Short name T292
Test name
Test status
Simulation time 605755688 ps
CPU time 9 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:55:16 PM PDT 24
Peak memory 216876 kb
Host smart-b7b8977f-14bc-4386-9c77-e489926184e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956951807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1956951807
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1381671574
Short name T245
Test name
Test status
Simulation time 124672028 ps
CPU time 6.15 seconds
Started Aug 16 05:54:21 PM PDT 24
Finished Aug 16 05:54:27 PM PDT 24
Peak memory 210428 kb
Host smart-6ef3f163-8e54-49c1-b52f-f4c04d64ea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381671574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1381671574
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1492459756
Short name T102
Test name
Test status
Simulation time 127240937 ps
CPU time 1.96 seconds
Started Aug 16 05:55:00 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 210604 kb
Host smart-b1990926-99aa-4efc-b614-2ef6b42bebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492459756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1492459756
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4142092740
Short name T409
Test name
Test status
Simulation time 93908812 ps
CPU time 0.77 seconds
Started Aug 16 05:52:33 PM PDT 24
Finished Aug 16 05:52:34 PM PDT 24
Peak memory 206372 kb
Host smart-ca8aedbd-4e40-411a-809f-3e82a727d0ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142092740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4142092740
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1790172887
Short name T109
Test name
Test status
Simulation time 208787216 ps
CPU time 10.13 seconds
Started Aug 16 05:53:13 PM PDT 24
Finished Aug 16 05:53:24 PM PDT 24
Peak memory 215796 kb
Host smart-256b92f8-e283-4f91-85ed-215526d9a0f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790172887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1790172887
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1379044697
Short name T28
Test name
Test status
Simulation time 200357957 ps
CPU time 2.04 seconds
Started Aug 16 05:52:38 PM PDT 24
Finished Aug 16 05:52:40 PM PDT 24
Peak memory 222032 kb
Host smart-05334eb3-1798-4d0f-9ce2-97ac4927ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379044697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1379044697
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3005369421
Short name T537
Test name
Test status
Simulation time 102329268 ps
CPU time 1.36 seconds
Started Aug 16 05:53:35 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 207912 kb
Host smart-d784c939-3975-44ff-b588-7a65b4c40769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005369421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3005369421
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1751701741
Short name T52
Test name
Test status
Simulation time 155691354 ps
CPU time 3.24 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:12 PM PDT 24
Peak memory 214976 kb
Host smart-26497930-5bef-432f-866a-fc508c94bae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751701741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1751701741
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3660625121
Short name T231
Test name
Test status
Simulation time 579353249 ps
CPU time 2.17 seconds
Started Aug 16 05:53:00 PM PDT 24
Finished Aug 16 05:53:03 PM PDT 24
Peak memory 222728 kb
Host smart-1f8c8ffa-ae75-4e41-8446-050c566a2bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660625121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3660625121
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4089049187
Short name T306
Test name
Test status
Simulation time 367788484 ps
CPU time 5.76 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:16 PM PDT 24
Peak memory 222896 kb
Host smart-60561306-a453-48f7-aed2-ca51722e6c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089049187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4089049187
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2177430088
Short name T318
Test name
Test status
Simulation time 76794592 ps
CPU time 3.54 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:15 PM PDT 24
Peak memory 209324 kb
Host smart-ba8e145a-f7a8-4c2b-a63b-4320760f90a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177430088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2177430088
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2127540993
Short name T332
Test name
Test status
Simulation time 282380732 ps
CPU time 3.45 seconds
Started Aug 16 05:52:41 PM PDT 24
Finished Aug 16 05:52:45 PM PDT 24
Peak memory 209208 kb
Host smart-9533445c-3ab6-4cfe-a712-ef85cb1f3d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127540993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2127540993
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2920062252
Short name T619
Test name
Test status
Simulation time 122237567 ps
CPU time 3.81 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:14 PM PDT 24
Peak memory 207320 kb
Host smart-87477866-0437-4816-9fdf-9901d091eaad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920062252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2920062252
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1578483926
Short name T560
Test name
Test status
Simulation time 154372388 ps
CPU time 2.5 seconds
Started Aug 16 05:52:37 PM PDT 24
Finished Aug 16 05:52:40 PM PDT 24
Peak memory 207364 kb
Host smart-29c1edb3-7dcb-4b16-844a-764e9e8e04f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578483926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1578483926
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1972314783
Short name T334
Test name
Test status
Simulation time 5083134025 ps
CPU time 15.36 seconds
Started Aug 16 05:52:41 PM PDT 24
Finished Aug 16 05:52:57 PM PDT 24
Peak memory 208420 kb
Host smart-f0944fb7-cd39-452b-b375-ab6b387fa8f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972314783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1972314783
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1661814421
Short name T600
Test name
Test status
Simulation time 2425797901 ps
CPU time 13.17 seconds
Started Aug 16 05:52:38 PM PDT 24
Finished Aug 16 05:52:51 PM PDT 24
Peak memory 218788 kb
Host smart-ad2872ea-8a34-496d-8721-0e6a3f445489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661814421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1661814421
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2684003828
Short name T826
Test name
Test status
Simulation time 21316081 ps
CPU time 1.66 seconds
Started Aug 16 05:53:18 PM PDT 24
Finished Aug 16 05:53:20 PM PDT 24
Peak memory 207552 kb
Host smart-9fade67e-c478-4ed1-ba33-39597e6ddde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684003828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2684003828
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1541077222
Short name T550
Test name
Test status
Simulation time 778461396 ps
CPU time 7.89 seconds
Started Aug 16 05:53:08 PM PDT 24
Finished Aug 16 05:53:16 PM PDT 24
Peak memory 222408 kb
Host smart-d08f5ba6-919a-4f94-8e50-10f25180a5b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541077222 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1541077222
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3465338647
Short name T853
Test name
Test status
Simulation time 1323934742 ps
CPU time 9.06 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:18 PM PDT 24
Peak memory 214744 kb
Host smart-2a58d37d-ffe8-468f-a64b-a708bc3c80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465338647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3465338647
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2861005289
Short name T519
Test name
Test status
Simulation time 39517009 ps
CPU time 1.76 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 210252 kb
Host smart-be27eff8-7416-4c92-bd8e-b6a6d51ea05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861005289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2861005289
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2724549254
Short name T611
Test name
Test status
Simulation time 25643770 ps
CPU time 0.78 seconds
Started Aug 16 05:53:14 PM PDT 24
Finished Aug 16 05:53:14 PM PDT 24
Peak memory 206372 kb
Host smart-533c7a9b-e7a3-47cb-a866-ffe8a3de3f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724549254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2724549254
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2652373618
Short name T313
Test name
Test status
Simulation time 216871728 ps
CPU time 4.24 seconds
Started Aug 16 05:53:14 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 222916 kb
Host smart-b20dddd4-fcfe-4651-9a1b-249abc82c346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652373618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2652373618
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.4082169828
Short name T34
Test name
Test status
Simulation time 63762041 ps
CPU time 2.72 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 215020 kb
Host smart-ea5e5eb0-a704-4ad1-9652-8f2abc773206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082169828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4082169828
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3738675833
Short name T430
Test name
Test status
Simulation time 68267464 ps
CPU time 3.02 seconds
Started Aug 16 05:52:42 PM PDT 24
Finished Aug 16 05:52:46 PM PDT 24
Peak memory 214756 kb
Host smart-3ccfabc0-1f1b-44eb-8414-1e32f48b1329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738675833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3738675833
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2666146666
Short name T795
Test name
Test status
Simulation time 122714611 ps
CPU time 3.2 seconds
Started Aug 16 05:52:45 PM PDT 24
Finished Aug 16 05:52:49 PM PDT 24
Peak memory 215100 kb
Host smart-eed93b0c-d168-49c0-a9c0-8111c70d369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666146666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2666146666
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1715163562
Short name T370
Test name
Test status
Simulation time 72879595 ps
CPU time 1.64 seconds
Started Aug 16 05:52:48 PM PDT 24
Finished Aug 16 05:52:49 PM PDT 24
Peak memory 214680 kb
Host smart-f50be238-3b1a-44f0-bd0a-c4a4114763a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715163562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1715163562
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.850381435
Short name T189
Test name
Test status
Simulation time 59697595 ps
CPU time 2.21 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:12 PM PDT 24
Peak memory 214656 kb
Host smart-ddd85dfa-05aa-4a86-85f6-fc708fac8bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850381435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.850381435
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.4141205263
Short name T805
Test name
Test status
Simulation time 270768980 ps
CPU time 7.37 seconds
Started Aug 16 05:53:21 PM PDT 24
Finished Aug 16 05:53:28 PM PDT 24
Peak memory 209676 kb
Host smart-14fa34e8-ea01-40fc-bb7e-76585aeb39c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141205263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.4141205263
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2960783219
Short name T693
Test name
Test status
Simulation time 271518693 ps
CPU time 3.51 seconds
Started Aug 16 05:52:41 PM PDT 24
Finished Aug 16 05:52:45 PM PDT 24
Peak memory 209204 kb
Host smart-a22076e9-82e1-444a-be06-eaf42f063809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960783219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2960783219
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2346184104
Short name T845
Test name
Test status
Simulation time 111052219 ps
CPU time 2.34 seconds
Started Aug 16 05:53:16 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 208048 kb
Host smart-16cb04f9-4ef2-405d-b3dd-65fd1067f9bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346184104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2346184104
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.751201878
Short name T309
Test name
Test status
Simulation time 428343467 ps
CPU time 6.31 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 209132 kb
Host smart-2c978215-62de-47af-8841-f2d5ad245652
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751201878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.751201878
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3915498926
Short name T683
Test name
Test status
Simulation time 176333233 ps
CPU time 4.56 seconds
Started Aug 16 05:53:13 PM PDT 24
Finished Aug 16 05:53:18 PM PDT 24
Peak memory 207356 kb
Host smart-e5c5f1a1-1956-4b22-9261-c43d07913a9a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915498926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3915498926
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3160739785
Short name T605
Test name
Test status
Simulation time 25290431 ps
CPU time 2.01 seconds
Started Aug 16 05:53:22 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 208152 kb
Host smart-cf5d8822-4a98-41f6-987c-ff3789c5f7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160739785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3160739785
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1584562563
Short name T398
Test name
Test status
Simulation time 120958208 ps
CPU time 1.85 seconds
Started Aug 16 05:52:37 PM PDT 24
Finished Aug 16 05:52:39 PM PDT 24
Peak memory 207752 kb
Host smart-3e8485cd-7321-482c-a4aa-7b2fafa3a433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584562563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1584562563
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1171431376
Short name T138
Test name
Test status
Simulation time 3770302381 ps
CPU time 26.02 seconds
Started Aug 16 05:53:21 PM PDT 24
Finished Aug 16 05:53:48 PM PDT 24
Peak memory 223124 kb
Host smart-a4aa7299-3173-4569-841f-3f9ca95ad9d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171431376 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1171431376
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2261971578
Short name T145
Test name
Test status
Simulation time 708747462 ps
CPU time 13.96 seconds
Started Aug 16 05:52:49 PM PDT 24
Finished Aug 16 05:53:03 PM PDT 24
Peak memory 209936 kb
Host smart-6f05dcdd-9c68-488d-b7a5-121e9a777256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261971578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2261971578
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1960536318
Short name T496
Test name
Test status
Simulation time 79360613 ps
CPU time 1.98 seconds
Started Aug 16 05:53:06 PM PDT 24
Finished Aug 16 05:53:08 PM PDT 24
Peak memory 210260 kb
Host smart-33cc7df9-789e-4fd8-8b68-d7ddb4f74141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960536318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1960536318
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.4130544919
Short name T429
Test name
Test status
Simulation time 14312955 ps
CPU time 0.81 seconds
Started Aug 16 05:53:33 PM PDT 24
Finished Aug 16 05:53:34 PM PDT 24
Peak memory 206376 kb
Host smart-f7217991-4d21-444b-99b0-58b268a1bc36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130544919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4130544919
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2158772790
Short name T367
Test name
Test status
Simulation time 175538657 ps
CPU time 3.48 seconds
Started Aug 16 05:53:24 PM PDT 24
Finished Aug 16 05:53:38 PM PDT 24
Peak memory 214708 kb
Host smart-49d71fe0-9203-4ce2-8dca-6fb87cd69bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158772790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2158772790
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.293265636
Short name T754
Test name
Test status
Simulation time 106206858 ps
CPU time 2.95 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 209368 kb
Host smart-8032a37e-de31-4102-8fb9-1766fa94a7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293265636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.293265636
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1839007528
Short name T858
Test name
Test status
Simulation time 132570149 ps
CPU time 2.77 seconds
Started Aug 16 05:52:41 PM PDT 24
Finished Aug 16 05:52:44 PM PDT 24
Peak memory 214760 kb
Host smart-ed1347de-a79c-4434-902b-6360bd442ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839007528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1839007528
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1469440375
Short name T344
Test name
Test status
Simulation time 88340731 ps
CPU time 2.31 seconds
Started Aug 16 05:52:42 PM PDT 24
Finished Aug 16 05:52:44 PM PDT 24
Peak memory 214716 kb
Host smart-b4af6b8d-2047-47a1-99ff-3b6330091c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469440375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1469440375
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3904538819
Short name T791
Test name
Test status
Simulation time 219295245 ps
CPU time 4.28 seconds
Started Aug 16 05:53:13 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 207280 kb
Host smart-dcfd76fc-d5d7-47b3-b0d4-39a92814b31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904538819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3904538819
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2355142445
Short name T871
Test name
Test status
Simulation time 283360538 ps
CPU time 6.64 seconds
Started Aug 16 05:52:43 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 214784 kb
Host smart-47143710-2f65-4bd1-b739-c4d9eb217ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355142445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2355142445
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3723788816
Short name T741
Test name
Test status
Simulation time 284052891 ps
CPU time 4.92 seconds
Started Aug 16 05:52:43 PM PDT 24
Finished Aug 16 05:52:48 PM PDT 24
Peak memory 209012 kb
Host smart-1db7fc63-2195-4241-976e-319f90deeac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723788816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3723788816
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3869920538
Short name T523
Test name
Test status
Simulation time 933087614 ps
CPU time 12.55 seconds
Started Aug 16 05:53:12 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 208968 kb
Host smart-ec69e363-dd17-475b-99fb-7698843ec79e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869920538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3869920538
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.4181381071
Short name T888
Test name
Test status
Simulation time 77166669 ps
CPU time 2.81 seconds
Started Aug 16 05:52:49 PM PDT 24
Finished Aug 16 05:52:52 PM PDT 24
Peak memory 208984 kb
Host smart-c4f26e05-834e-41fe-b8c5-028a9d692a32
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181381071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.4181381071
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.173572212
Short name T321
Test name
Test status
Simulation time 1550470157 ps
CPU time 6.84 seconds
Started Aug 16 05:52:43 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 208448 kb
Host smart-47b6c509-0db1-446f-9b3f-5bb3d4a841e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173572212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.173572212
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3232831588
Short name T570
Test name
Test status
Simulation time 103736021 ps
CPU time 1.63 seconds
Started Aug 16 05:53:27 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 214768 kb
Host smart-479b8424-7ce9-4ac5-92c1-c30e4bc1fd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232831588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3232831588
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3539642235
Short name T626
Test name
Test status
Simulation time 210270140 ps
CPU time 2.33 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:09 PM PDT 24
Peak memory 207144 kb
Host smart-a85d3b8c-c3e8-4d79-a4b1-33947001c916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539642235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3539642235
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.202358000
Short name T856
Test name
Test status
Simulation time 358153256 ps
CPU time 12.41 seconds
Started Aug 16 05:53:26 PM PDT 24
Finished Aug 16 05:53:39 PM PDT 24
Peak memory 222780 kb
Host smart-a312a8ee-01a9-47e1-bcf7-0bbcc193be63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202358000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.202358000
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2724933774
Short name T91
Test name
Test status
Simulation time 973283991 ps
CPU time 9.97 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:57 PM PDT 24
Peak memory 218720 kb
Host smart-44f5b372-248f-4d29-8540-b32ad515f94c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724933774 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2724933774
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2009434686
Short name T471
Test name
Test status
Simulation time 535848903 ps
CPU time 12.23 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:53:00 PM PDT 24
Peak memory 214712 kb
Host smart-47b8a976-2601-4530-948f-17335fd7cebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009434686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2009434686
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2574106865
Short name T814
Test name
Test status
Simulation time 662266332 ps
CPU time 4.15 seconds
Started Aug 16 05:53:06 PM PDT 24
Finished Aug 16 05:53:10 PM PDT 24
Peak memory 211104 kb
Host smart-536194b9-c84b-433f-8eda-ba8b16358eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574106865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2574106865
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3245710839
Short name T825
Test name
Test status
Simulation time 20088820 ps
CPU time 0.75 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 206316 kb
Host smart-86fc7a99-cf45-4a6e-85ac-6ebdcfc4a445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245710839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3245710839
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3319820982
Short name T387
Test name
Test status
Simulation time 125431610 ps
CPU time 2.93 seconds
Started Aug 16 05:53:18 PM PDT 24
Finished Aug 16 05:53:21 PM PDT 24
Peak memory 214800 kb
Host smart-cb8c75f9-c929-46f4-b921-d2b807150c85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319820982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3319820982
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2935755556
Short name T32
Test name
Test status
Simulation time 1376684151 ps
CPU time 5.05 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:52 PM PDT 24
Peak memory 209136 kb
Host smart-1d653902-288c-4c87-b0a1-921cf5ec7236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935755556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2935755556
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3942907477
Short name T127
Test name
Test status
Simulation time 484502830 ps
CPU time 3.78 seconds
Started Aug 16 05:52:50 PM PDT 24
Finished Aug 16 05:52:54 PM PDT 24
Peak memory 210084 kb
Host smart-b8ed24fb-9910-4677-a181-eccb99036afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942907477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3942907477
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2149035028
Short name T554
Test name
Test status
Simulation time 426595054 ps
CPU time 2.13 seconds
Started Aug 16 05:53:09 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 214724 kb
Host smart-c5184605-2ea6-497e-aff2-d414f62f6748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149035028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2149035028
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1664158257
Short name T851
Test name
Test status
Simulation time 73733016 ps
CPU time 3 seconds
Started Aug 16 05:52:46 PM PDT 24
Finished Aug 16 05:52:49 PM PDT 24
Peak memory 222900 kb
Host smart-6bb0dfd1-7178-4a0b-8d0a-9f1ae3c2226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664158257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1664158257
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1002360362
Short name T68
Test name
Test status
Simulation time 1513376851 ps
CPU time 15.43 seconds
Started Aug 16 05:52:48 PM PDT 24
Finished Aug 16 05:53:04 PM PDT 24
Peak memory 210808 kb
Host smart-c0cd52df-6e4d-49d3-821c-f57bb61a907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002360362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1002360362
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2782301398
Short name T840
Test name
Test status
Simulation time 419692778 ps
CPU time 4.92 seconds
Started Aug 16 05:52:45 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 210036 kb
Host smart-c4a9189d-15e8-4ac1-8979-bd5c84ea5e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782301398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2782301398
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1765636892
Short name T587
Test name
Test status
Simulation time 87977044 ps
CPU time 3.82 seconds
Started Aug 16 05:52:50 PM PDT 24
Finished Aug 16 05:52:54 PM PDT 24
Peak memory 208988 kb
Host smart-1f650c61-ce06-4c6a-883f-363f4b248282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765636892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1765636892
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2287583446
Short name T728
Test name
Test status
Simulation time 115650251 ps
CPU time 3.07 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 209352 kb
Host smart-b5e64861-68fe-4d4f-8336-2e2f9cae2641
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287583446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2287583446
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2596767600
Short name T427
Test name
Test status
Simulation time 1359088953 ps
CPU time 5.15 seconds
Started Aug 16 05:53:27 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 209060 kb
Host smart-ec7c2bc2-8523-4220-9a9d-0890f9971194
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596767600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2596767600
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3404389802
Short name T416
Test name
Test status
Simulation time 672432643 ps
CPU time 23.31 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:30 PM PDT 24
Peak memory 208408 kb
Host smart-1a56fb19-effa-49fd-a195-a7e7ab7c3a74
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404389802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3404389802
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3003933190
Short name T543
Test name
Test status
Simulation time 66330787 ps
CPU time 2.79 seconds
Started Aug 16 05:53:10 PM PDT 24
Finished Aug 16 05:53:13 PM PDT 24
Peak memory 209896 kb
Host smart-f93f31e9-c3ce-4946-96c5-4b32a38d0b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003933190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3003933190
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2178978074
Short name T732
Test name
Test status
Simulation time 56013767 ps
CPU time 2.44 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:10 PM PDT 24
Peak memory 207152 kb
Host smart-8e42571e-48e0-439a-9592-51f817e3c134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178978074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2178978074
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3034861399
Short name T877
Test name
Test status
Simulation time 226269009 ps
CPU time 9.2 seconds
Started Aug 16 05:52:46 PM PDT 24
Finished Aug 16 05:52:56 PM PDT 24
Peak memory 223092 kb
Host smart-a2383403-0c23-49c8-b8b1-9fa8c6737f54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034861399 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3034861399
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3077686384
Short name T869
Test name
Test status
Simulation time 277198399 ps
CPU time 7.13 seconds
Started Aug 16 05:52:50 PM PDT 24
Finished Aug 16 05:52:57 PM PDT 24
Peak memory 218992 kb
Host smart-d3110fea-f650-44a5-9802-2383a2301dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077686384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3077686384
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2963443569
Short name T753
Test name
Test status
Simulation time 176774965 ps
CPU time 2.16 seconds
Started Aug 16 05:53:31 PM PDT 24
Finished Aug 16 05:53:33 PM PDT 24
Peak memory 210560 kb
Host smart-9270dd0d-89bd-4849-b7dd-de2a58c6777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963443569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2963443569
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1648787196
Short name T689
Test name
Test status
Simulation time 11676663 ps
CPU time 0.75 seconds
Started Aug 16 05:52:51 PM PDT 24
Finished Aug 16 05:52:52 PM PDT 24
Peak memory 206352 kb
Host smart-d13c708a-de32-4d6e-9338-e3c989075d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648787196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1648787196
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.4253139551
Short name T848
Test name
Test status
Simulation time 58555985 ps
CPU time 3.77 seconds
Started Aug 16 05:52:46 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 214736 kb
Host smart-ea25b884-46c6-4bbc-8494-e27940b3cc6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253139551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4253139551
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1762951187
Short name T907
Test name
Test status
Simulation time 1882469221 ps
CPU time 17.15 seconds
Started Aug 16 05:53:11 PM PDT 24
Finished Aug 16 05:53:28 PM PDT 24
Peak memory 209396 kb
Host smart-eb786938-4f93-4abb-8da9-137909716436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762951187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1762951187
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2577198099
Short name T641
Test name
Test status
Simulation time 85445970 ps
CPU time 2.67 seconds
Started Aug 16 05:52:48 PM PDT 24
Finished Aug 16 05:52:51 PM PDT 24
Peak memory 214760 kb
Host smart-06e82cec-23ba-45fd-8670-a6685cf335ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577198099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2577198099
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1259411511
Short name T74
Test name
Test status
Simulation time 248723813 ps
CPU time 3.2 seconds
Started Aug 16 05:52:49 PM PDT 24
Finished Aug 16 05:52:52 PM PDT 24
Peak memory 214720 kb
Host smart-f41dbf6c-0dfa-4ad3-b46e-ebc3c8850875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259411511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1259411511
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2173870678
Short name T194
Test name
Test status
Simulation time 1035514951 ps
CPU time 10.93 seconds
Started Aug 16 05:52:46 PM PDT 24
Finished Aug 16 05:52:57 PM PDT 24
Peak memory 214776 kb
Host smart-94bd46ac-dc80-40fb-b42f-91e7eed3fa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173870678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2173870678
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3426366630
Short name T850
Test name
Test status
Simulation time 55153109 ps
CPU time 2.98 seconds
Started Aug 16 05:53:08 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 207424 kb
Host smart-721ec8e5-aabe-4a29-8a77-da1fdb1701f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426366630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3426366630
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.968913389
Short name T663
Test name
Test status
Simulation time 129818731 ps
CPU time 3.54 seconds
Started Aug 16 05:53:23 PM PDT 24
Finished Aug 16 05:53:27 PM PDT 24
Peak memory 208924 kb
Host smart-e1973c1b-ae28-447f-a026-b7089fa1ade9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968913389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.968913389
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2375477001
Short name T174
Test name
Test status
Simulation time 130896645 ps
CPU time 5.03 seconds
Started Aug 16 05:52:46 PM PDT 24
Finished Aug 16 05:52:51 PM PDT 24
Peak memory 209136 kb
Host smart-fc80d6e0-e6a9-4271-8636-a3e6837d700c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375477001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2375477001
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.376215540
Short name T691
Test name
Test status
Simulation time 201662443 ps
CPU time 4.84 seconds
Started Aug 16 05:53:32 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 208996 kb
Host smart-0b436101-7630-48a9-8340-15172eedd583
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376215540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.376215540
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1985357255
Short name T280
Test name
Test status
Simulation time 190288837 ps
CPU time 5.94 seconds
Started Aug 16 05:53:13 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 209640 kb
Host smart-e64a951e-e701-49bc-af0c-351418c382f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985357255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1985357255
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1750526631
Short name T516
Test name
Test status
Simulation time 390056656 ps
CPU time 2.42 seconds
Started Aug 16 05:52:48 PM PDT 24
Finished Aug 16 05:52:51 PM PDT 24
Peak memory 216688 kb
Host smart-e3616fa0-2204-48bd-b93f-ab8063ecf65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750526631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1750526631
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.299189463
Short name T740
Test name
Test status
Simulation time 40025187 ps
CPU time 2.37 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:49 PM PDT 24
Peak memory 208852 kb
Host smart-30f210f9-e812-41ca-b3a4-0c16c17e6354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299189463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.299189463
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.508809433
Short name T656
Test name
Test status
Simulation time 778489819 ps
CPU time 4.85 seconds
Started Aug 16 05:52:49 PM PDT 24
Finished Aug 16 05:52:54 PM PDT 24
Peak memory 209400 kb
Host smart-45daa56b-1b1c-4911-ba29-48d85d2752c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508809433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.508809433
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4227609722
Short name T162
Test name
Test status
Simulation time 610544565 ps
CPU time 2.01 seconds
Started Aug 16 05:52:48 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 210824 kb
Host smart-af01df81-65bc-4bfc-8e11-da54df1515a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227609722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4227609722
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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