Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	51	1			T97	1		T101	1		T6	1
auto[OpGenId]	13	1			T59	1		T135	1		T174	1
auto[OpGenSwOut]	19	1			T6	1		T105	1		T130	1
auto[OpGenHwOut]	26	1			T3	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1633	1			T12	6		T36	3		T6	1
auto[StInit]	83	1			T3	1		T15	1		T97	1
auto[StCreatorRootKey]	60	1			T4	1		T12	1		T36	2
auto[StOwnerIntKey]	43	1			T1	1		T16	1		T59	1
auto[StOwnerKey]	47	1			T12	1		T73	1		T55	1
auto[StDisabled]	489	1			T3	4		T12	2		T36	5
auto[StInvalid]	49	1			T23	1		T45	1		T128	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3370

1

T1

2

T2

1

T3

5

auto[1]

109

1

T3

1

T97

1

T101

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1623	1			T12	6		T36	3		T6	1
auto[StReset]	auto[1]	10	1			T202	1		T175	1		T203	1
auto[StInit]	auto[0]	45	1			T15	1		T32	1		T127	1
auto[StInit]	auto[1]	38	1			T3	1		T97	1		T6	1
auto[StCreatorRootKey]	auto[0]	37	1			T4	1		T12	1		T36	2
auto[StCreatorRootKey]	auto[1]	23	1			T60	1		T130	1		T7	1
auto[StOwnerIntKey]	auto[0]	32	1			T1	1		T16	1		T59	1
auto[StOwnerIntKey]	auto[1]	11	1			T204	1		T205	1		T206	1
auto[StOwnerKey]	auto[0]	32	1			T12	1		T73	1		T55	1
auto[StOwnerKey]	auto[1]	15	1			T59	1		T60	1		T105	1
auto[StDisabled]	auto[0]	477	1			T3	4		T12	2		T36	5
auto[StDisabled]	auto[1]	12	1			T101	1		T6	2		T207	1
auto[StInvalid]	auto[0]	49	1			T23	1		T45	1		T128	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[StDisabled]]	[auto[OpGenId]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	8	1			T202	1		T175	1		T30	1
auto[StReset]	auto[OpGenId]	1	1			T208	1		-	-		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T203	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	18	1			T97	1		T117	1		T112	1
auto[StInit]	auto[OpGenId]	5	1			T89	1		T209	1		T210	1
auto[StInit]	auto[OpGenSwOut]	6	1			T114	1		T211	1		T210	1
auto[StInit]	auto[OpGenHwOut]	9	1			T3	1		T6	1		T212	1
auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T60	1		T175	1		T213	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T88	1		T214	1		T215	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T130	1		T205	1		T216	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	6	1			T7	1		T211	1		T217	1
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T218	1		T177	1		T219	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T205	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T204	1		T220	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T206	1		T221	1		T222	1
auto[StOwnerKey]	auto[OpAdvance]	4	1			T60	1		T223	1		T224	1
auto[StOwnerKey]	auto[OpGenId]	3	1			T59	1		T135	1		T174	1
auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T105	1		T225	1		T226	1
auto[StOwnerKey]	auto[OpGenHwOut]	4	1			T33	1		T227	1		T228	1
auto[StDisabled]	auto[OpAdvance]	5	1			T101	1		T6	1		T229	1
auto[StDisabled]	auto[OpGenSwOut]	4	1			T6	1		T207	1		T230	1
auto[StDisabled]	auto[OpGenHwOut]	3	1			T231	1		T232	1		T178	1