Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4965

1

T1

1

T3

21

T5

2

auto[1]

546

1

T3

4

T5

1

T36

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4965

1

T1

1

T3

21

T5

2

auto[1]

546

1

T3

4

T5

1

T36

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4922

1

T1

1

T3

18

T5

3

auto[1]

589

1

T3

7

T93

4

T36

4

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4922

1

T1

1

T3

18

T5

3

auto[1]

589

1

T3

7

T93

4

T36

4

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	446	1			T3	5		T11	1		T12	1
auto[OpGenId]	1145	1			T3	4		T5	3		T11	3
auto[OpGenSwOut]	1240	1			T1	1		T3	8		T11	2
auto[OpGenHwOut]	2599	1			T3	7		T11	2		T12	1
auto[OpDisable]	81	1			T3	1		T71	1		T194	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	446	1			T3	5		T11	1		T12	1
auto[OpGenId]	1145	1			T3	4		T5	3		T11	3
auto[OpGenSwOut]	1240	1			T1	1		T3	8		T11	2
auto[OpGenHwOut]	2599	1			T3	7		T11	2		T12	1
auto[OpDisable]	81	1			T3	1		T71	1		T194	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4984

1

T3

24

T5

3

T11

7

auto[1]

527

1

T1

1

T3

1

T11

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4984

1

T3

24

T5

3

T11

7

auto[1]

527

1

T1

1

T3

1

T11

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5273

1

T1

1

T3

25

T5

3

auto[1]

238

1

T79

1

T102

4

T113

8

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1855	1			T1	1		T3	9		T5	1
auto[1]	759	1			T3	5		T11	3		T70	1
auto[2]	714	1			T3	4		T5	1		T70	1
auto[3]	743	1			T3	3		T5	1		T12	2
auto[4]	345	1			T3	2		T11	2		T13	1
auto[5]	363	1			T3	1		T11	2		T70	5
auto[6]	350	1			T71	1		T58	1		T131	1
auto[7]	382	1			T3	1		T70	1		T71	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1440	1			T3	4		T11	4		T13	1
clear_one[1]	759	1			T3	5		T11	3		T70	1
clear_one[2]	714	1			T3	4		T5	1		T70	1
clear_one[3]	743	1			T3	3		T5	1		T12	2
clear_none	1855	1			T1	1		T3	9		T5	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1011	1			T3	7		T11	2		T12	2
auto[StInit]	692	1			T3	1		T5	1		T11	1
auto[StCreatorRootKey]	594	1			T1	1		T3	3		T11	1
auto[StOwnerIntKey]	562	1			T11	1		T12	1		T70	1
auto[StOwnerKey]	467	1			T3	3		T5	1		T11	1
auto[StDisabled]	1895	1			T3	11		T5	1		T11	2
auto[StInvalid]	290	1			T23	5		T44	6		T40	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1011	1			T3	7		T11	2		T12	2
auto[StInit]	692	1			T3	1		T5	1		T11	1
auto[StCreatorRootKey]	594	1			T1	1		T3	3		T11	1
auto[StOwnerIntKey]	562	1			T11	1		T12	1		T70	1
auto[StOwnerKey]	467	1			T3	3		T5	1		T11	1
auto[StDisabled]	1895	1			T3	11		T5	1		T11	2
auto[StInvalid]	290	1			T23	5		T44	6		T40	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T233	1		T234	1		T235	1
auto[0]	auto[StReset]	auto[OpGenId]	160	1			T11	1		T12	1		T36	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	163	1			T3	4		T38	1		T36	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	257	1			T3	1		T70	1		T71	1
auto[0]	auto[StInit]	auto[OpAdvance]	41	1			T13	1		T16	1		T201	1
auto[0]	auto[StInit]	auto[OpGenId]	98	1			T5	1		T36	1		T134	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	95	1			T36	2		T196	1		T193	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	182	1			T93	1		T126	1		T20	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T12	1		T59	2		T134	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	65	1			T14	1		T36	1		T183	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	47	1			T1	1		T60	1		T190	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	75	1			T3	1		T52	1		T196	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T105	1		T236	1		T223	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	38	1			T52	1		T167	1		T46	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	39	1			T6	1		T59	2		T60	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T36	1		T200	1		T237	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T58	1		T6	1		T134	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	18	1			T207	3		T238	1		T210	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T130	1		T239	1		T240	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T12	1		T100	1		T200	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	26	1			T79	1		T101	1		T6	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T3	1		T6	1		T59	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T3	2		T58	1		T199	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T93	1		T79	1		T195	1
auto[0]	auto[StDisabled]	auto[OpDisable]	25	1			T59	1		T134	1		T241	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T242	1		T243	1		T244	1
auto[0]	auto[StInvalid]	auto[OpGenId]	29	1			T44	1		T42	1		T41	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T23	1		T45	1		T41	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	18	1			T40	1		T42	1		T245	1
auto[1]	auto[StReset]	auto[OpGenId]	16	1			T11	1		T42	1		T246	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	18	1			T3	1		T59	1		T60	2
auto[1]	auto[StReset]	auto[OpGenHwOut]	51	1			T237	1		T181	1		T185	1
auto[1]	auto[StInit]	auto[OpAdvance]	6	1			T3	1		T113	1		T207	1
auto[1]	auto[StInit]	auto[OpGenId]	15	1			T130	1		T247	1		T240	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	10	1			T71	1		T130	1		T21	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	21	1			T195	1		T113	1		T60	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T197	1		T113	1		T247	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T3	1		T174	1		T140	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T16	1		T113	1		T174	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	46	1			T101	1		T113	1		T185	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T247	2		T248	1		T249	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T183	1		T134	2		T205	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T247	1		T250	1		T207	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T185	1		T168	1		T251	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T3	1		T252	1		T229	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	27	1			T52	1		T193	1		T113	2
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T197	1		T59	1		T60	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T11	1		T70	1		T113	2
auto[1]	auto[StDisabled]	auto[OpAdvance]	29	1			T3	1		T11	1		T58	1
auto[1]	auto[StDisabled]	auto[OpGenId]	54	1			T58	1		T6	1		T60	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	77	1			T36	1		T59	2		T72	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T93	1		T79	1		T237	2
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T130	1		T137	1		T253	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	8	1			T45	1		T254	1		T255	1
auto[1]	auto[StInvalid]	auto[OpGenId]	8	1			T23	1		T47	1		T256	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T43	1		T245	2		T257	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T23	1		T40	1		T42	1
auto[2]	auto[StReset]	auto[OpGenId]	12	1			T258	1		T259	1		T231	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	25	1			T36	1		T40	1		T32	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	47	1			T44	2		T181	2		T185	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T205	1		T178	1		T219	1
auto[2]	auto[StInit]	auto[OpGenId]	15	1			T36	1		T260	1		T174	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	14	1			T261	1		T21	1		T206	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	22	1			T130	1		T205	1		T262	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T60	1		T263	1		T264	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T130	1		T207	1		T175	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T72	1		T130	1		T265	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T3	1		T6	1		T171	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T60	1		T261	1		T266	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T267	1		T87	1		T268	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T6	1		T60	1		T134	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	32	1			T93	1		T269	1		T270	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T250	1		T66	1		T240	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	19	1			T5	1		T271	1		T272	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T236	1		T130	1		T175	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T60	1		T269	1		T273	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	33	1			T3	1		T79	1		T103	2
auto[2]	auto[StDisabled]	auto[OpGenId]	42	1			T193	1		T6	1		T103	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	64	1			T3	1		T6	2		T199	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	161	1			T70	1		T100	1		T196	1
auto[2]	auto[StDisabled]	auto[OpDisable]	13	1			T3	1		T71	1		T194	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T254	1		T274	1		T275	1
auto[2]	auto[StInvalid]	auto[OpGenId]	12	1			T44	1		T40	1		T41	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T23	1		T257	1		T276	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T257	1		T277	1		T254	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T278	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T12	1		T59	1		T130	2
auto[3]	auto[StReset]	auto[OpGenSwOut]	25	1			T97	1		T130	1		T207	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	43	1			T58	1		T59	1		T279	1
auto[3]	auto[StInit]	auto[OpAdvance]	9	1			T280	4		T61	1		T28	1
auto[3]	auto[StInit]	auto[OpGenId]	11	1			T182	1		T207	1		T22	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	16	1			T38	1		T20	1		T60	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	29	1			T70	1		T134	1		T7	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T102	2		T207	1		T175	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T20	1		T102	1		T136	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T212	1		T281	1		T282	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T93	1		T181	1		T261	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T130	1		T134	1		T207	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	22	1			T12	1		T36	1		T195	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T199	1		T283	1		T284	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T102	1		T181	1		T285	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T3	1		T280	2		T205	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T6	1		T174	1		T211	2
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T59	1		T286	1		T211	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T93	1		T187	1		T287	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	19	1			T52	1		T196	1		T59	1
auto[3]	auto[StDisabled]	auto[OpGenId]	63	1			T5	1		T36	1		T193	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T36	1		T183	1		T60	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T3	2		T70	2		T36	1
auto[3]	auto[StDisabled]	auto[OpDisable]	17	1			T59	1		T60	1		T130	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	8	1			T288	2		T289	1		T290	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T44	1		T41	1		T291	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T23	1		T254	1		T292	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T293	1		T243	1		T294	1
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T40	1		T134	1		T295	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	14	1			T36	1		T130	1		T234	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	15	1			T174	1		T296	1		T90	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T219	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T134	1		T22	1		T214	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T36	1		T297	1		T298	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T20	1		T299	1		T300	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T301	1		T53	1		T302	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T131	1		T201	1		T272	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T13	1		T60	3		T134	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	12	1			T237	1		T299	1		T303	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T304	1		T305	1		T306	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T33	1		T303	1		T307	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T260	1		T308	1		T309	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T11	1		T310	1		T286	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T210	1		T306	1		T311	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T3	1		T211	1		T312	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T130	1		T304	1		T205	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T237	1		T60	1		T212	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	17	1			T103	1		T313	1		T273	1
auto[4]	auto[StDisabled]	auto[OpGenId]	20	1			T3	1		T134	1		T212	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T11	1		T6	1		T60	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T93	1		T200	2		T6	1
auto[4]	auto[StDisabled]	auto[OpDisable]	2	1			T314	1		T125	1		-	-
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T41	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T315	1		T316	1		T317	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T257	1		T318	1		T319	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T42	1		T320	1		T321	1
auto[5]	auto[StReset]	auto[OpGenId]	5	1			T258	1		T89	1		T306	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T128	1		T293	1		T205	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	30	1			T70	3		T185	1		T279	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T20	1		T90	1		T322	1
auto[5]	auto[StInit]	auto[OpGenId]	9	1			T11	1		T198	1		T323	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T324	1		T248	1		T90	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	16	1			T237	1		T60	1		T279	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T134	1		T204	1		T137	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T212	1		T325	1		T326	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T11	1		T6	1		T207	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T70	1		T285	1		T310	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T174	1		T327	1		T328	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	2	1			T122	1		T329	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T6	1		T59	1		T90	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T70	1		T201	1		T130	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	2	1			T190	1		T324	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T205	1		T137	2		T211	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T330	1		T299	1		T331	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	14	1			T332	1		T273	1		T205	1
auto[5]	auto[StDisabled]	auto[OpGenId]	23	1			T126	1		T205	1		T175	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T199	1		T59	1		T134	2
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T3	1		T100	1		T6	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T333	1		T141	1		T334	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	3	1			T335	1		T336	1		T337	1
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T42	1		T242	1		T320	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T44	2		T128	1		T320	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T44	1		T242	1		T320	1
auto[6]	auto[StReset]	auto[OpGenId]	12	1			T338	1		T205	1		T321	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T99	1		T6	1		T59	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T181	1		T171	1		T130	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T280	1		T339	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T137	1		T211	1		T340	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	11	1			T168	1		T22	1		T259	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T185	1		T171	1		T137	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T341	1		T89	1		T342	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T60	1		T168	1		T215	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T271	1		T333	1		T48	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T58	1		T100	1		T187	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T99	1		T61	1		T343	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T6	1		T60	1		T233	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T60	1		T273	1		T240	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T131	1		T100	1		T193	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T344	3		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T60	1		T345	1		T207	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T233	1		T137	1		T89	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T270	1		T33	1		T346	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T6	1		T304	1		T67	1
auto[6]	auto[StDisabled]	auto[OpGenId]	24	1			T6	1		T170	1		T261	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T195	1		T72	1		T134	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T71	1		T100	1		T187	1
auto[6]	auto[StDisabled]	auto[OpDisable]	9	1			T347	1		T175	1		T88	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T169	1		T43	1		T348	1
auto[6]	auto[StInvalid]	auto[OpGenId]	1	1			T169	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T169	1		T321	2		T349	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T245	1		T318	1		T243	1
auto[7]	auto[StReset]	auto[OpGenId]	13	1			T168	1		T248	1		T234	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	8	1			T197	1		T7	1		T350	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T3	1		T71	1		T6	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T134	1		T351	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T130	1		T207	1		T53	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T101	1		T170	1		T352	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T20	1		T181	1		T285	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T103	1		T340	1		T230	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T71	1		T193	1		T309	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T229	1		T174	1		T90	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T200	1		T79	1		T105	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T103	1		T325	1		T353	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T205	1		T312	1		T140	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T196	1		T6	1		T354	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T279	1		T187	1		T171	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T79	1		T90	1		T306	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T355	1		T356	1		T357	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T130	2		T358	1		T210	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T279	1		T285	1		T359	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T137	1		T360	1		T357	1
auto[7]	auto[StDisabled]	auto[OpGenId]	23	1			T361	1		T247	1		T137	3
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T103	1		T167	1		T361	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	95	1			T70	1		T93	1		T52	1
auto[7]	auto[StDisabled]	auto[OpDisable]	2	1			T207	1		T306	1		-	-
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T318	1		T256	1		T321	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T255	1		T291	1		T362	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T318	1		T289	1		T276	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T40	1		T169	1		T289	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1440

1

T3

4

T11

4

T13

1

clear_one[1]

auto[0]

auto[0]

auto[0]

444

1

T3

2

T11

2

T71

1

clear_one[1]

auto[0]

auto[0]

auto[1]

123

1

T11

1

T70

1

T52

1

clear_one[1]

auto[0]

auto[1]

auto[0]

149

1

T3

3

T93

1

T36

1

clear_one[1]

auto[0]

auto[1]

auto[1]

43

1

T6

1

T59

1

T113

1

clear_one[2]

auto[0]

auto[0]

auto[0]

430

1

T3

3

T5

1

T71

1

clear_one[2]

auto[0]

auto[0]

auto[1]

115

1

T3

1

T70

1

T79

1

clear_one[2]

auto[1]

auto[0]

auto[0]

127

1

T100

1

T193

1

T6

3

clear_one[2]

auto[1]

auto[0]

auto[1]

42

1

T6

2

T166

1

T236

1

clear_one[3]

auto[0]

auto[0]

auto[0]

455

1

T3

1

T12

2

T70

3

clear_one[3]

auto[0]

auto[1]

auto[0]

121

1

T3

1

T93

2

T36

1

clear_one[3]

auto[1]

auto[0]

auto[0]

127

1

T5

1

T20

1

T100

1

clear_one[3]

auto[1]

auto[1]

auto[0]

40

1

T3

1

T36

1

T59

1

clear_none

auto[0]

auto[0]

auto[0]

1344

1

T3

6

T5

1

T11

1

clear_none

auto[0]

auto[0]

auto[1]

114

1

T1

1

T52

2

T200

2

clear_none

auto[0]

auto[1]

auto[0]

151

1

T93

1

T36

1

T79

1

clear_none

auto[0]

auto[1]

auto[1]

36

1

T79

1

T6

1

T59

1

clear_none

auto[1]

auto[0]

auto[0]

125

1

T3

1

T100

1

T6

3

clear_none

auto[1]

auto[0]

auto[1]

36

1

T6

4

T59

1

T313

1

clear_none

auto[1]

auto[1]

auto[0]

31

1

T3

2

T195

1

T59

1

clear_none

auto[1]

auto[1]

auto[1]

18

1

T58

1

T130

1

T301

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1379	1			T3	4		T11	4		T13	1
clear_all	auto[1]	61	1			T103	2		T342	1		T360	1
clear_one[1]	auto[0]	701	1			T3	5		T11	3		T70	1
clear_one[1]	auto[1]	58	1			T113	8		T247	10		T302	1
clear_one[2]	auto[0]	685	1			T3	4		T5	1		T70	1
clear_one[2]	auto[1]	29	1			T103	3		T280	1		T250	2
clear_one[3]	auto[0]	697	1			T3	3		T5	1		T12	2
clear_one[3]	auto[1]	46	1			T102	3		T280	6		T302	2
clear_none	auto[0]	1811	1			T1	1		T3	9		T5	1
clear_none	auto[1]	44	1			T79	1		T102	1		T103	1