Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11272

1

T1

4

T3

62

T4

7

auto[Attestation]

8002

1

T1

4

T3

46

T4

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2792	1			T3	12		T4	1		T5	2
auto[Aes]	3380	1			T1	2		T3	17		T4	2
auto[Kmac]	3629	1			T1	1		T3	20		T5	2
auto[Otbn]	3418	1			T1	3		T3	23		T4	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7850	1			T1	3		T3	35		T4	2
auto[OpGenId]	6055	1			T1	2		T3	36		T4	4
auto[OpGenSwOut]	6113	1			T1	3		T3	31		T4	4
auto[OpGenHwOut]	7106	1			T1	3		T3	41		T4	1
auto[OpDisable]	173	1			T3	1		T5	1		T71	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10925

1

T1

7

T3

50

T4

4

auto[OpDoneFail]

16372

1

T1

4

T3

94

T4

7

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6695	1			T1	1		T3	35		T4	7
auto[StInit]	3914	1			T1	5		T3	16		T4	2
auto[StCreatorRootKey]	3278	1			T1	5		T3	20		T4	2
auto[StOwnerIntKey]	2867	1			T3	7		T5	4		T11	2
auto[StOwnerKey]	2480	1			T3	12		T5	4		T11	2
auto[StDisabled]	8063	1			T3	54		T5	3		T11	5

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	341	1			T3	1		T11	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	111	1			T12	1		T20	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	91	1			T3	1		T11	1		T92	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T5	1		T193	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T73	1		T6	1		T60	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	219	1			T36	1		T194	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	318	1			T3	2		T4	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	113	1			T38	1		T36	2		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	95	1			T1	1		T13	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T16	1		T196	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	66	1			T3	1		T14	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	184	1			T3	1		T11	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	347	1			T3	4		T11	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	114	1			T3	1		T6	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T16	1		T98	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T12	1		T14	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	72	1			T12	1		T101	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	216	1			T3	1		T36	2		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	298	1			T3	3		T4	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	89	1			T20	1		T73	1		T127	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T1	1		T5	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T5	1		T14	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	47	1			T3	1		T98	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	235	1			T3	2		T12	1		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	96	1			T3	2		T36	3		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	107	1			T12	2		T36	2		T126	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	80	1			T4	1		T13	1		T99	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T197	1		T6	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T92	1		T193	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	223	1			T3	2		T12	1		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	95	1			T3	1		T12	1		T36	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	98	1			T3	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	90	1			T11	1		T12	1		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	63	1			T98	1		T59	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	71	1			T36	1		T52	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	215	1			T3	2		T11	1		T36	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	84	1			T12	1		T36	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	117	1			T71	1		T36	3		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T5	1		T11	1		T12	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T3	1		T31	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	66	1			T12	1		T98	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	246	1			T3	1		T12	2		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	98	1			T12	3		T36	2		T59	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	105	1			T1	1		T3	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	103	1			T14	1		T71	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T196	1		T6	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	69	1			T6	1		T130	2		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	216	1			T3	2		T31	1		T36	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	291	1			T3	3		T15	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T38	1		T20	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	72	1			T3	1		T5	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	65	1			T131	1		T197	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	46	1			T196	1		T59	1		T60	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	178	1			T79	1		T193	1		T6	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	448	1			T3	1		T11	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	119	1			T1	1		T58	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	106	1			T20	1		T6	2		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	98	1			T3	1		T100	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	92	1			T14	2		T100	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	279	1			T5	1		T58	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	535	1			T3	2		T11	2		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	121	1			T93	1		T36	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T3	3		T38	2		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T11	1		T99	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	81	1			T3	1		T55	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	285	1			T3	2		T93	2		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	457	1			T3	2		T4	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	120	1			T3	1		T20	1		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	120	1			T3	1		T38	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T70	1		T99	2		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	89	1			T12	1		T14	2		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	296	1			T3	5		T70	2		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T36	2		T59	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	88	1			T6	3		T103	1		T130	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T3	2		T12	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T14	1		T131	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T14	1		T73	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	170	1			T196	1		T193	1		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	62	1			T36	1		T6	3		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	113	1			T3	1		T36	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T3	1		T13	1		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	101	1			T14	1		T60	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	87	1			T3	1		T201	1		T167	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	288	1			T3	4		T5	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	71	1			T6	2		T59	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	117	1			T1	1		T3	1		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T13	1		T6	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	81	1			T93	1		T36	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	92	1			T5	1		T93	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	318	1			T3	3		T93	2		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T36	1		T6	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T3	1		T70	1		T73	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	91	1			T1	1		T13	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	115	1			T3	1		T99	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T11	1		T12	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	285	1			T3	3		T70	2		T36	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	199	1			T3	1		T5	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	690	1			T3	1		T11	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	219	1			T1	1		T3	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	629	1			T3	3		T4	1		T11	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	229	1			T12	2		T14	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	692	1			T3	6		T11	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	195	1			T1	1		T3	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	638	1			T3	5		T4	1		T11	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	201	1			T4	1		T13	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	434	1			T3	4		T12	3		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	206	1			T11	1		T12	1		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	426	1			T3	4		T4	1		T11	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	227	1			T3	1		T5	1		T11	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	462	1			T3	1		T12	3		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	229	1			T14	1		T71	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	437	1			T1	1		T3	3		T12	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	162	1			T3	1		T5	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	596	1			T3	3		T15	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	281	1			T3	1		T14	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	861	1			T1	1		T3	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T3	4		T11	1		T38	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	960	1			T3	4		T11	2		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	276	1			T3	1		T14	2		T70	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	887	1			T3	8		T4	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	179	1			T3	2		T12	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	331	1			T36	2		T52	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	269	1			T3	2		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	489	1			T3	5		T5	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	271	1			T5	1		T13	1		T93	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	520	1			T1	1		T3	4		T93	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	275	1			T1	1		T3	1		T11	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	481	1			T3	4		T12	1		T70	3