Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33460

1

T1

12

T3

157

T4

12

auto[1]

184

1

T79

2

T102

4

T113

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33469	1			T1	12		T3	157		T4	12
auto[134217728:268435455]	4	1			T102	1		T322	1		T388	1
auto[268435456:402653183]	6	1			T389	1		T322	1		T390	1
auto[402653184:536870911]	2	1			T391	1		T235	1		-	-
auto[536870912:671088639]	5	1			T280	1		T247	1		T392	1
auto[671088640:805306367]	2	1			T377	1		T344	1		-	-
auto[805306368:939524095]	6	1			T247	1		T391	1		T389	1
auto[939524096:1073741823]	3	1			T102	1		T280	1		T393	1
auto[1073741824:1207959551]	9	1			T389	2		T388	1		T394	2
auto[1207959552:1342177279]	6	1			T389	1		T395	1		T378	1
auto[1342177280:1476395007]	3	1			T280	1		T247	2		-	-
auto[1476395008:1610612735]	11	1			T280	2		T247	1		T302	1
auto[1610612736:1744830463]	7	1			T302	1		T392	1		T389	1
auto[1744830464:1879048191]	7	1			T273	1		T234	1		T322	1
auto[1879048192:2013265919]	3	1			T280	1		T236	1		T356	1
auto[2013265920:2147483647]	5	1			T302	1		T322	1		T390	1
auto[2147483648:2281701375]	4	1			T250	1		T389	1		T278	1
auto[2281701376:2415919103]	5	1			T102	1		T396	1		T389	1
auto[2415919104:2550136831]	7	1			T247	1		T360	1		T388	1
auto[2550136832:2684354559]	8	1			T113	1		T247	1		T377	1
auto[2684354560:2818572287]	4	1			T391	1		T395	2		T397	1
auto[2818572288:2952790015]	3	1			T113	1		T302	1		T388	1
auto[2952790016:3087007743]	11	1			T247	1		T356	1		T342	1
auto[3087007744:3221225471]	4	1			T102	1		T247	1		T395	2
auto[3221225472:3355443199]	6	1			T236	1		T247	1		T389	1
auto[3355443200:3489660927]	5	1			T280	1		T394	1		T344	1
auto[3489660928:3623878655]	5	1			T103	1		T391	1		T322	3
auto[3623878656:3758096383]	6	1			T280	1		T395	2		T344	1
auto[3758096384:3892314111]	4	1			T113	1		T302	1		T398	2
auto[3892314112:4026531839]	7	1			T396	1		T235	2		T344	1
auto[4026531840:4160749567]	5	1			T79	1		T233	1		T389	1
auto[4160749568:4294967295]	12	1			T113	1		T280	1		T236	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33460	1			T1	12		T3	157		T4	12
auto[0:134217727]	auto[1]	9	1			T79	1		T113	1		T103	1
auto[134217728:268435455]	auto[1]	4	1			T102	1		T322	1		T388	1
auto[268435456:402653183]	auto[1]	6	1			T389	1		T322	1		T390	1
auto[402653184:536870911]	auto[1]	2	1			T391	1		T235	1		-	-
auto[536870912:671088639]	auto[1]	5	1			T280	1		T247	1		T392	1
auto[671088640:805306367]	auto[1]	2	1			T377	1		T344	1		-	-
auto[805306368:939524095]	auto[1]	6	1			T247	1		T391	1		T389	1
auto[939524096:1073741823]	auto[1]	3	1			T102	1		T280	1		T393	1
auto[1073741824:1207959551]	auto[1]	9	1			T389	2		T388	1		T394	2
auto[1207959552:1342177279]	auto[1]	6	1			T389	1		T395	1		T378	1
auto[1342177280:1476395007]	auto[1]	3	1			T280	1		T247	2		-	-
auto[1476395008:1610612735]	auto[1]	11	1			T280	2		T247	1		T302	1
auto[1610612736:1744830463]	auto[1]	7	1			T302	1		T392	1		T389	1
auto[1744830464:1879048191]	auto[1]	7	1			T273	1		T234	1		T322	1
auto[1879048192:2013265919]	auto[1]	3	1			T280	1		T236	1		T356	1
auto[2013265920:2147483647]	auto[1]	5	1			T302	1		T322	1		T390	1
auto[2147483648:2281701375]	auto[1]	4	1			T250	1		T389	1		T278	1
auto[2281701376:2415919103]	auto[1]	5	1			T102	1		T396	1		T389	1
auto[2415919104:2550136831]	auto[1]	7	1			T247	1		T360	1		T388	1
auto[2550136832:2684354559]	auto[1]	8	1			T113	1		T247	1		T377	1
auto[2684354560:2818572287]	auto[1]	4	1			T391	1		T395	2		T397	1
auto[2818572288:2952790015]	auto[1]	3	1			T113	1		T302	1		T388	1
auto[2952790016:3087007743]	auto[1]	11	1			T247	1		T356	1		T342	1
auto[3087007744:3221225471]	auto[1]	4	1			T102	1		T247	1		T395	2
auto[3221225472:3355443199]	auto[1]	6	1			T236	1		T247	1		T389	1
auto[3355443200:3489660927]	auto[1]	5	1			T280	1		T394	1		T344	1
auto[3489660928:3623878655]	auto[1]	5	1			T103	1		T391	1		T322	3
auto[3623878656:3758096383]	auto[1]	6	1			T280	1		T395	2		T344	1
auto[3758096384:3892314111]	auto[1]	4	1			T113	1		T302	1		T398	2
auto[3892314112:4026531839]	auto[1]	7	1			T396	1		T235	2		T344	1
auto[4026531840:4160749567]	auto[1]	5	1			T79	1		T233	1		T389	1
auto[4160749568:4294967295]	auto[1]	12	1			T113	1		T280	1		T236	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1619

1

T1

1

T3

15

T12

2

auto[1]

1851

1

T1

2

T3

17

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	121	1			T12	2		T36	1		T58	1
auto[134217728:268435455]	102	1			T3	1		T13	1		T58	1
auto[268435456:402653183]	101	1			T3	2		T36	1		T101	1
auto[402653184:536870911]	104	1			T71	1		T36	1		T44	1
auto[536870912:671088639]	121	1			T12	1		T44	1		T40	2
auto[671088640:805306367]	111	1			T36	1		T45	1		T131	1
auto[805306368:939524095]	103	1			T1	1		T3	2		T12	1
auto[939524096:1073741823]	116	1			T3	3		T11	1		T44	1
auto[1073741824:1207959551]	111	1			T71	1		T6	1		T59	1
auto[1207959552:1342177279]	108	1			T3	1		T20	1		T97	1
auto[1342177280:1476395007]	115	1			T40	1		T42	1		T6	2
auto[1476395008:1610612735]	118	1			T5	1		T11	1		T52	1
auto[1610612736:1744830463]	109	1			T3	2		T45	1		T20	1
auto[1744830464:1879048191]	110	1			T36	2		T44	1		T20	1
auto[1879048192:2013265919]	104	1			T3	1		T36	1		T58	1
auto[2013265920:2147483647]	93	1			T3	1		T127	1		T6	1
auto[2147483648:2281701375]	110	1			T3	3		T36	1		T40	1
auto[2281701376:2415919103]	107	1			T1	1		T3	1		T12	1
auto[2415919104:2550136831]	109	1			T3	1		T71	1		T16	1
auto[2550136832:2684354559]	109	1			T3	1		T14	1		T36	1
auto[2684354560:2818572287]	120	1			T44	1		T58	1		T45	1
auto[2818572288:2952790015]	105	1			T3	1		T14	1		T32	1
auto[2952790016:3087007743]	99	1			T3	2		T126	1		T16	1
auto[3087007744:3221225471]	111	1			T3	1		T14	1		T38	1
auto[3221225472:3355443199]	97	1			T3	1		T127	1		T42	1
auto[3355443200:3489660927]	96	1			T3	2		T38	1		T196	1
auto[3489660928:3623878655]	103	1			T3	1		T79	1		T6	1
auto[3623878656:3758096383]	106	1			T1	1		T3	1		T12	1
auto[3758096384:3892314111]	116	1			T3	2		T71	1		T40	1
auto[3892314112:4026531839]	111	1			T16	1		T6	4		T59	2
auto[4026531840:4160749567]	105	1			T38	1		T131	1		T193	1
auto[4160749568:4294967295]	119	1			T3	2		T11	1		T23	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T59	1		T60	1		T399	1
auto[0:134217727]	auto[1]	65	1			T12	2		T36	1		T58	1
auto[134217728:268435455]	auto[0]	49	1			T6	1		T128	1		T134	1
auto[134217728:268435455]	auto[1]	53	1			T3	1		T13	1		T58	1
auto[268435456:402653183]	auto[0]	54	1			T3	1		T36	1		T101	1
auto[268435456:402653183]	auto[1]	47	1			T3	1		T102	1		T59	1
auto[402653184:536870911]	auto[0]	43	1			T71	1		T44	1		T101	1
auto[402653184:536870911]	auto[1]	61	1			T36	1		T6	1		T59	3
auto[536870912:671088639]	auto[0]	68	1			T44	1		T40	2		T45	1
auto[536870912:671088639]	auto[1]	53	1			T12	1		T32	1		T6	2
auto[671088640:805306367]	auto[0]	38	1			T6	1		T399	1		T105	1
auto[671088640:805306367]	auto[1]	73	1			T36	1		T45	1		T131	1
auto[805306368:939524095]	auto[0]	52	1			T12	1		T36	1		T97	1
auto[805306368:939524095]	auto[1]	51	1			T1	1		T3	2		T101	1
auto[939524096:1073741823]	auto[0]	50	1			T44	1		T134	2		T43	1
auto[939524096:1073741823]	auto[1]	66	1			T3	3		T11	1		T99	1
auto[1073741824:1207959551]	auto[0]	58	1			T71	1		T60	1		T134	1
auto[1073741824:1207959551]	auto[1]	53	1			T6	1		T59	1		T182	1
auto[1207959552:1342177279]	auto[0]	48	1			T3	1		T20	1		T97	1
auto[1207959552:1342177279]	auto[1]	60	1			T193	1		T59	1		T60	1
auto[1342177280:1476395007]	auto[0]	50	1			T42	1		T6	1		T59	1
auto[1342177280:1476395007]	auto[1]	65	1			T40	1		T6	1		T59	1
auto[1476395008:1610612735]	auto[0]	59	1			T194	1		T60	2		T130	1
auto[1476395008:1610612735]	auto[1]	59	1			T5	1		T11	1		T52	1
auto[1610612736:1744830463]	auto[0]	40	1			T3	1		T45	1		T20	1
auto[1610612736:1744830463]	auto[1]	69	1			T3	1		T6	2		T59	2
auto[1744830464:1879048191]	auto[0]	46	1			T36	2		T44	1		T127	1
auto[1744830464:1879048191]	auto[1]	64	1			T20	1		T6	1		T261	1
auto[1879048192:2013265919]	auto[0]	54	1			T3	1		T36	1		T58	1
auto[1879048192:2013265919]	auto[1]	50	1			T42	1		T6	1		T102	1
auto[2013265920:2147483647]	auto[0]	46	1			T3	1		T127	1		T399	1
auto[2013265920:2147483647]	auto[1]	47	1			T6	1		T59	3		T167	1
auto[2147483648:2281701375]	auto[0]	38	1			T3	2		T36	1		T40	1
auto[2147483648:2281701375]	auto[1]	72	1			T3	1		T196	1		T113	1
auto[2281701376:2415919103]	auto[0]	49	1			T12	1		T38	1		T45	1
auto[2281701376:2415919103]	auto[1]	58	1			T1	1		T3	1		T6	1
auto[2415919104:2550136831]	auto[0]	48	1			T71	1		T59	1		T130	4
auto[2415919104:2550136831]	auto[1]	61	1			T3	1		T16	1		T79	1
auto[2550136832:2684354559]	auto[0]	47	1			T14	1		T36	1		T40	1
auto[2550136832:2684354559]	auto[1]	62	1			T3	1		T128	1		T60	2
auto[2684354560:2818572287]	auto[0]	61	1			T44	1		T58	1		T45	1
auto[2684354560:2818572287]	auto[1]	59	1			T52	3		T194	1		T197	1
auto[2818572288:2952790015]	auto[0]	54	1			T3	1		T32	1		T42	2
auto[2818572288:2952790015]	auto[1]	51	1			T14	1		T103	1		T361	1
auto[2952790016:3087007743]	auto[0]	42	1			T3	1		T16	1		T6	1
auto[2952790016:3087007743]	auto[1]	57	1			T3	1		T126	1		T6	1
auto[3087007744:3221225471]	auto[0]	60	1			T38	1		T97	1		T193	1
auto[3087007744:3221225471]	auto[1]	51	1			T3	1		T14	1		T16	1
auto[3221225472:3355443199]	auto[0]	48	1			T3	1		T127	1		T42	1
auto[3221225472:3355443199]	auto[1]	49	1			T59	1		T361	1		T77	1
auto[3355443200:3489660927]	auto[0]	53	1			T3	1		T38	1		T212	1
auto[3355443200:3489660927]	auto[1]	43	1			T3	1		T196	1		T193	1
auto[3489660928:3623878655]	auto[0]	46	1			T3	1		T59	1		T169	1
auto[3489660928:3623878655]	auto[1]	57	1			T79	1		T6	1		T313	1
auto[3623878656:3758096383]	auto[0]	60	1			T1	1		T3	1		T38	1
auto[3623878656:3758096383]	auto[1]	46	1			T12	1		T16	1		T99	1
auto[3758096384:3892314111]	auto[0]	50	1			T3	1		T71	1		T40	1
auto[3758096384:3892314111]	auto[1]	66	1			T3	1		T59	1		T60	2
auto[3892314112:4026531839]	auto[0]	56	1			T6	2		T60	3		T130	1
auto[3892314112:4026531839]	auto[1]	55	1			T16	1		T6	2		T59	2
auto[4026531840:4160749567]	auto[0]	43	1			T131	1		T193	1		T6	2
auto[4026531840:4160749567]	auto[1]	62	1			T38	1		T59	1		T261	1
auto[4160749568:4294967295]	auto[0]	53	1			T3	1		T45	1		T127	1
auto[4160749568:4294967295]	auto[1]	66	1			T3	1		T11	1		T23	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1630

1

T3

17

T11

1

T12

3

auto[1]

1842

1

T1

3

T3

15

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T3	3		T12	1		T13	1
auto[134217728:268435455]	117	1			T1	1		T11	1		T71	1
auto[268435456:402653183]	99	1			T12	1		T36	1		T44	1
auto[402653184:536870911]	104	1			T38	1		T36	1		T20	1
auto[536870912:671088639]	109	1			T23	1		T40	1		T20	1
auto[671088640:805306367]	114	1			T3	3		T71	1		T16	1
auto[805306368:939524095]	110	1			T3	1		T40	1		T97	1
auto[939524096:1073741823]	91	1			T59	1		T183	1		T261	1
auto[1073741824:1207959551]	118	1			T3	4		T40	1		T45	1
auto[1207959552:1342177279]	98	1			T38	1		T59	1		T60	1
auto[1342177280:1476395007]	107	1			T3	1		T58	1		T20	1
auto[1476395008:1610612735]	98	1			T3	2		T11	1		T127	1
auto[1610612736:1744830463]	115	1			T38	1		T36	1		T97	1
auto[1744830464:1879048191]	110	1			T12	1		T97	1		T193	1
auto[1879048192:2013265919]	112	1			T3	3		T12	1		T36	1
auto[2013265920:2147483647]	122	1			T3	1		T14	1		T58	2
auto[2147483648:2281701375]	119	1			T3	2		T12	1		T45	1
auto[2281701376:2415919103]	111	1			T3	2		T71	1		T79	1
auto[2415919104:2550136831]	94	1			T14	1		T79	1		T194	1
auto[2550136832:2684354559]	104	1			T3	1		T40	1		T32	1
auto[2684354560:2818572287]	101	1			T71	1		T36	1		T6	5
auto[2818572288:2952790015]	130	1			T12	1		T38	1		T58	1
auto[2952790016:3087007743]	105	1			T99	1		T101	1		T6	1
auto[3087007744:3221225471]	115	1			T1	1		T3	2		T36	1
auto[3221225472:3355443199]	132	1			T5	1		T126	1		T16	1
auto[3355443200:3489660927]	113	1			T44	1		T97	1		T101	1
auto[3489660928:3623878655]	105	1			T6	1		T60	1		T167	1
auto[3623878656:3758096383]	92	1			T3	2		T14	1		T36	1
auto[3758096384:3892314111]	101	1			T3	1		T45	2		T99	1
auto[3892314112:4026531839]	108	1			T3	2		T38	1		T36	1
auto[4026531840:4160749567]	124	1			T1	1		T3	1		T11	1
auto[4160749568:4294967295]	88	1			T3	1		T44	1		T40	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T3	1		T36	1		T44	1
auto[0:134217727]	auto[1]	56	1			T3	2		T12	1		T13	1
auto[134217728:268435455]	auto[0]	55	1			T44	1		T58	1		T117	1
auto[134217728:268435455]	auto[1]	62	1			T1	1		T11	1		T71	1
auto[268435456:402653183]	auto[0]	53	1			T12	1		T36	1		T44	1
auto[268435456:402653183]	auto[1]	46	1			T6	1		T59	1		T60	1
auto[402653184:536870911]	auto[0]	57	1			T38	1		T36	1		T20	1
auto[402653184:536870911]	auto[1]	47	1			T32	1		T261	1		T130	1
auto[536870912:671088639]	auto[0]	55	1			T20	1		T101	1		T42	1
auto[536870912:671088639]	auto[1]	54	1			T23	1		T40	1		T52	1
auto[671088640:805306367]	auto[0]	48	1			T3	2		T71	1		T16	1
auto[671088640:805306367]	auto[1]	66	1			T3	1		T99	1		T52	1
auto[805306368:939524095]	auto[0]	49	1			T3	1		T40	1		T6	2
auto[805306368:939524095]	auto[1]	61	1			T97	1		T6	1		T59	1
auto[939524096:1073741823]	auto[0]	47	1			T236	1		T130	2		T400	1
auto[939524096:1073741823]	auto[1]	44	1			T59	1		T183	1		T261	1
auto[1073741824:1207959551]	auto[0]	54	1			T3	3		T40	1		T45	1
auto[1073741824:1207959551]	auto[1]	64	1			T3	1		T16	1		T59	1
auto[1207959552:1342177279]	auto[0]	50	1			T60	1		T134	2		T345	1
auto[1207959552:1342177279]	auto[1]	48	1			T38	1		T59	1		T166	1
auto[1342177280:1476395007]	auto[0]	53	1			T3	1		T101	1		T6	1
auto[1342177280:1476395007]	auto[1]	54	1			T58	1		T20	1		T131	1
auto[1476395008:1610612735]	auto[0]	45	1			T11	1		T127	1		T41	1
auto[1476395008:1610612735]	auto[1]	53	1			T3	2		T194	1		T60	2
auto[1610612736:1744830463]	auto[0]	54	1			T38	1		T97	1		T127	1
auto[1610612736:1744830463]	auto[1]	61	1			T36	1		T79	1		T59	1
auto[1744830464:1879048191]	auto[0]	57	1			T97	1		T42	1		T59	2
auto[1744830464:1879048191]	auto[1]	53	1			T12	1		T193	1		T60	1
auto[1879048192:2013265919]	auto[0]	46	1			T3	2		T36	1		T20	1
auto[1879048192:2013265919]	auto[1]	66	1			T3	1		T12	1		T16	2
auto[2013265920:2147483647]	auto[0]	41	1			T58	1		T127	1		T60	1
auto[2013265920:2147483647]	auto[1]	81	1			T3	1		T14	1		T58	1
auto[2147483648:2281701375]	auto[0]	61	1			T3	2		T12	1		T45	1
auto[2147483648:2281701375]	auto[1]	58	1			T127	1		T59	1		T105	2
auto[2281701376:2415919103]	auto[0]	51	1			T3	1		T71	1		T59	1
auto[2281701376:2415919103]	auto[1]	60	1			T3	1		T79	1		T6	1
auto[2415919104:2550136831]	auto[0]	39	1			T14	1		T105	1		T134	1
auto[2415919104:2550136831]	auto[1]	55	1			T79	1		T194	1		T6	1
auto[2550136832:2684354559]	auto[0]	47	1			T3	1		T40	1		T32	1
auto[2550136832:2684354559]	auto[1]	57	1			T102	1		T59	1		T103	1
auto[2684354560:2818572287]	auto[0]	42	1			T71	1		T36	1		T6	2
auto[2684354560:2818572287]	auto[1]	59	1			T6	3		T59	1		T60	1
auto[2818572288:2952790015]	auto[0]	55	1			T12	1		T38	1		T97	1
auto[2818572288:2952790015]	auto[1]	75	1			T58	1		T16	1		T52	2
auto[2952790016:3087007743]	auto[0]	52	1			T24	1		T283	1		T130	1
auto[2952790016:3087007743]	auto[1]	53	1			T99	1		T101	1		T6	1
auto[3087007744:3221225471]	auto[0]	48	1			T3	1		T36	1		T45	1
auto[3087007744:3221225471]	auto[1]	67	1			T1	1		T3	1		T131	1
auto[3221225472:3355443199]	auto[0]	62	1			T126	1		T16	1		T59	1
auto[3221225472:3355443199]	auto[1]	70	1			T5	1		T79	1		T6	2
auto[3355443200:3489660927]	auto[0]	59	1			T44	1		T97	1		T101	1
auto[3355443200:3489660927]	auto[1]	54	1			T59	1		T113	1		T60	1
auto[3489660928:3623878655]	auto[0]	56	1			T6	1		T167	1		T77	1
auto[3489660928:3623878655]	auto[1]	49	1			T60	1		T169	1		T361	1
auto[3623878656:3758096383]	auto[0]	38	1			T3	1		T14	1		T36	1
auto[3623878656:3758096383]	auto[1]	54	1			T3	1		T59	1		T60	1
auto[3758096384:3892314111]	auto[0]	55	1			T45	2		T6	2		T60	1
auto[3758096384:3892314111]	auto[1]	46	1			T3	1		T99	1		T196	1
auto[3892314112:4026531839]	auto[0]	51	1			T3	1		T38	1		T36	1
auto[3892314112:4026531839]	auto[1]	57	1			T3	1		T102	1		T59	1
auto[4026531840:4160749567]	auto[0]	51	1			T45	1		T60	1		T399	1
auto[4026531840:4160749567]	auto[1]	73	1			T1	1		T3	1		T11	1
auto[4160749568:4294967295]	auto[0]	49	1			T40	1		T6	1		T190	1
auto[4160749568:4294967295]	auto[1]	39	1			T3	1		T44	1		T102	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1619

1

T1

1

T3

16

T11

1

auto[1]

1852

1

T1

2

T3

16

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T3	2		T44	1		T58	1
auto[134217728:268435455]	100	1			T44	1		T58	1		T99	1
auto[268435456:402653183]	122	1			T1	2		T3	3		T12	1
auto[402653184:536870911]	98	1			T3	1		T38	1		T6	2
auto[536870912:671088639]	101	1			T3	1		T101	1		T41	1
auto[671088640:805306367]	89	1			T3	1		T71	1		T38	1
auto[805306368:939524095]	121	1			T3	1		T16	1		T79	1
auto[939524096:1073741823]	101	1			T3	1		T36	1		T6	1
auto[1073741824:1207959551]	112	1			T3	2		T36	2		T97	2
auto[1207959552:1342177279]	108	1			T12	1		T71	1		T38	1
auto[1342177280:1476395007]	108	1			T3	2		T20	1		T16	1
auto[1476395008:1610612735]	117	1			T3	2		T11	1		T36	1
auto[1610612736:1744830463]	89	1			T14	1		T38	1		T99	1
auto[1744830464:1879048191]	91	1			T20	1		T16	1		T127	1
auto[1879048192:2013265919]	112	1			T3	1		T12	1		T71	1
auto[2013265920:2147483647]	100	1			T3	1		T40	1		T131	1
auto[2147483648:2281701375]	115	1			T3	1		T36	1		T131	1
auto[2281701376:2415919103]	103	1			T11	1		T12	1		T40	1
auto[2415919104:2550136831]	113	1			T3	1		T197	1		T6	1
auto[2550136832:2684354559]	105	1			T3	1		T12	1		T36	1
auto[2684354560:2818572287]	119	1			T3	2		T13	1		T71	1
auto[2818572288:2952790015]	123	1			T3	1		T127	1		T193	1
auto[2952790016:3087007743]	106	1			T3	1		T5	1		T12	1
auto[3087007744:3221225471]	117	1			T3	2		T16	1		T59	1
auto[3221225472:3355443199]	110	1			T3	1		T36	2		T20	1
auto[3355443200:3489660927]	132	1			T3	1		T45	1		T6	1
auto[3489660928:3623878655]	98	1			T3	1		T38	1		T40	1
auto[3623878656:3758096383]	103	1			T1	1		T14	1		T44	1
auto[3758096384:3892314111]	104	1			T3	1		T6	2		T59	1
auto[3892314112:4026531839]	106	1			T131	1		T32	1		T193	1
auto[4026531840:4160749567]	119	1			T11	1		T14	1		T40	1
auto[4160749568:4294967295]	109	1			T3	1		T40	1		T6	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T3	1		T44	1		T58	1
auto[0:134217727]	auto[1]	61	1			T3	1		T196	1		T6	1
auto[134217728:268435455]	auto[0]	45	1			T44	1		T127	1		T6	2
auto[134217728:268435455]	auto[1]	55	1			T58	1		T99	1		T52	1
auto[268435456:402653183]	auto[0]	53	1			T12	1		T36	1		T45	1
auto[268435456:402653183]	auto[1]	69	1			T1	2		T3	3		T101	1
auto[402653184:536870911]	auto[0]	44	1			T3	1		T38	1		T59	1
auto[402653184:536870911]	auto[1]	54	1			T6	2		T60	1		T283	1
auto[536870912:671088639]	auto[0]	46	1			T3	1		T101	1		T130	1
auto[536870912:671088639]	auto[1]	55	1			T41	1		T59	2		T60	3
auto[671088640:805306367]	auto[0]	45	1			T3	1		T71	1		T44	1
auto[671088640:805306367]	auto[1]	44	1			T38	1		T16	1		T196	1
auto[805306368:939524095]	auto[0]	53	1			T399	1		T313	2		T198	1
auto[805306368:939524095]	auto[1]	68	1			T3	1		T16	1		T79	1
auto[939524096:1073741823]	auto[0]	45	1			T3	1		T36	1		T201	1
auto[939524096:1073741823]	auto[1]	56	1			T6	1		T60	1		T105	1
auto[1073741824:1207959551]	auto[0]	53	1			T97	2		T101	2		T169	1
auto[1073741824:1207959551]	auto[1]	59	1			T3	2		T36	2		T60	1
auto[1207959552:1342177279]	auto[0]	45	1			T12	1		T71	1		T38	1
auto[1207959552:1342177279]	auto[1]	63	1			T58	1		T126	1		T32	1
auto[1342177280:1476395007]	auto[0]	57	1			T3	1		T20	1		T16	1
auto[1342177280:1476395007]	auto[1]	51	1			T3	1		T102	1		T59	2
auto[1476395008:1610612735]	auto[0]	57	1			T3	2		T36	1		T183	1
auto[1476395008:1610612735]	auto[1]	60	1			T11	1		T79	1		T127	1
auto[1610612736:1744830463]	auto[0]	43	1			T38	1		T167	1		T169	1
auto[1610612736:1744830463]	auto[1]	46	1			T14	1		T99	1		T6	1
auto[1744830464:1879048191]	auto[0]	43	1			T127	1		T261	1		T130	1
auto[1744830464:1879048191]	auto[1]	48	1			T20	1		T16	1		T59	2
auto[1879048192:2013265919]	auto[0]	44	1			T3	1		T36	1		T40	1
auto[1879048192:2013265919]	auto[1]	68	1			T12	1		T71	1		T23	1
auto[2013265920:2147483647]	auto[0]	51	1			T3	1		T40	1		T42	1
auto[2013265920:2147483647]	auto[1]	49	1			T131	1		T52	1		T6	2
auto[2147483648:2281701375]	auto[0]	47	1			T3	1		T36	1		T42	1
auto[2147483648:2281701375]	auto[1]	68	1			T131	1		T247	1		T304	1
auto[2281701376:2415919103]	auto[0]	57	1			T12	1		T40	1		T45	1
auto[2281701376:2415919103]	auto[1]	46	1			T11	1		T16	1		T117	1
auto[2415919104:2550136831]	auto[0]	55	1			T3	1		T6	1		T59	3
auto[2415919104:2550136831]	auto[1]	58	1			T197	1		T113	1		T60	1
auto[2550136832:2684354559]	auto[0]	58	1			T12	1		T36	1		T45	2
auto[2550136832:2684354559]	auto[1]	47	1			T3	1		T52	1		T6	1
auto[2684354560:2818572287]	auto[0]	53	1			T3	1		T71	1		T20	1
auto[2684354560:2818572287]	auto[1]	66	1			T3	1		T13	1		T99	1
auto[2818572288:2952790015]	auto[0]	57	1			T127	1		T193	1		T6	1
auto[2818572288:2952790015]	auto[1]	66	1			T3	1		T6	2		T59	1
auto[2952790016:3087007743]	auto[0]	46	1			T44	1		T97	1		T127	1
auto[2952790016:3087007743]	auto[1]	60	1			T3	1		T5	1		T12	1
auto[3087007744:3221225471]	auto[0]	45	1			T16	1		T130	3		T134	1
auto[3087007744:3221225471]	auto[1]	72	1			T3	2		T59	1		T182	1
auto[3221225472:3355443199]	auto[0]	53	1			T3	1		T36	2		T20	1
auto[3221225472:3355443199]	auto[1]	57	1			T102	1		T60	2		T77	1
auto[3355443200:3489660927]	auto[0]	56	1			T45	1		T166	1		T169	1
auto[3355443200:3489660927]	auto[1]	76	1			T3	1		T6	1		T59	1
auto[3489660928:3623878655]	auto[0]	48	1			T3	1		T38	1		T42	1
auto[3489660928:3623878655]	auto[1]	50	1			T40	1		T52	1		T59	1
auto[3623878656:3758096383]	auto[0]	54	1			T1	1		T44	1		T6	1
auto[3623878656:3758096383]	auto[1]	49	1			T14	1		T58	1		T59	1
auto[3758096384:3892314111]	auto[0]	44	1			T6	1		T60	1		T166	1
auto[3758096384:3892314111]	auto[1]	60	1			T3	1		T6	1		T59	1
auto[3892314112:4026531839]	auto[0]	47	1			T131	1		T193	1		T6	1
auto[3892314112:4026531839]	auto[1]	59	1			T32	1		T102	1		T130	1
auto[4026531840:4160749567]	auto[0]	58	1			T11	1		T14	1		T40	1
auto[4026531840:4160749567]	auto[1]	61	1			T79	1		T193	1		T6	1
auto[4160749568:4294967295]	auto[0]	58	1			T3	1		T40	1		T59	1
auto[4160749568:4294967295]	auto[1]	51	1			T6	2		T102	1		T60	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1609

1

T1

1

T3

14

T12

3

auto[1]

1862

1

T1

2

T3

18

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T3	1		T40	1		T193	1
auto[134217728:268435455]	100	1			T3	2		T38	1		T97	1
auto[268435456:402653183]	114	1			T5	1		T42	1		T6	3
auto[402653184:536870911]	124	1			T3	3		T44	1		T45	1
auto[536870912:671088639]	122	1			T11	1		T14	1		T36	1
auto[671088640:805306367]	105	1			T3	3		T16	1		T52	1
auto[805306368:939524095]	90	1			T3	2		T131	1		T16	1
auto[939524096:1073741823]	100	1			T3	1		T12	1		T36	1
auto[1073741824:1207959551]	91	1			T1	1		T193	1		T101	1
auto[1207959552:1342177279]	130	1			T36	1		T58	1		T97	1
auto[1342177280:1476395007]	108	1			T14	1		T40	1		T16	1
auto[1476395008:1610612735]	102	1			T3	1		T11	1		T36	1
auto[1610612736:1744830463]	131	1			T3	2		T38	1		T58	1
auto[1744830464:1879048191]	110	1			T3	2		T12	1		T38	1
auto[1879048192:2013265919]	102	1			T3	3		T261	1		T130	1
auto[2013265920:2147483647]	94	1			T38	1		T36	1		T6	1
auto[2147483648:2281701375]	106	1			T13	1		T14	1		T58	1
auto[2281701376:2415919103]	101	1			T44	1		T40	1		T45	1
auto[2415919104:2550136831]	103	1			T3	1		T12	1		T6	2
auto[2550136832:2684354559]	93	1			T12	2		T71	1		T36	1
auto[2684354560:2818572287]	128	1			T3	3		T38	1		T36	1
auto[2818572288:2952790015]	109	1			T71	1		T20	1		T131	1
auto[2952790016:3087007743]	101	1			T3	1		T79	2		T101	2
auto[3087007744:3221225471]	111	1			T71	1		T40	1		T45	1
auto[3221225472:3355443199]	113	1			T3	1		T45	1		T97	1
auto[3355443200:3489660927]	107	1			T36	1		T6	1		T102	1
auto[3489660928:3623878655]	123	1			T71	1		T36	2		T44	2
auto[3623878656:3758096383]	94	1			T12	1		T126	1		T194	1
auto[3758096384:3892314111]	114	1			T3	2		T58	1		T16	1
auto[3892314112:4026531839]	118	1			T3	1		T131	1		T52	1
auto[4026531840:4160749567]	106	1			T1	1		T3	3		T11	1
auto[4160749568:4294967295]	106	1			T1	1		T42	1		T60	1